Macros
#define	CLEAR_BIT(x, bit) x =bit

#define	SOFTWARE_RESET 0x8000

#define	CMD_OPCODE 0x0f00

#define	CMD_CHANNEL 0x00f0

#define	CMD_FLAG 0x0001

#define	INIT_RXTX_PARAMS 0x0000

#define	INIT_RX_PARAMS 0x0100

#define	INIT_TX_PARAMS 0x0200

#define	ENTER_HUNT_MODE 0x0300

#define	STOP_TX 0x0400

#define	GR_STOP_TX 0x0500

#define	RESTART_TX 0x0600

#define	CLOSE_RX_BD 0x0700

#define	SET_ENET_GROUP 0x0800

#define	RESET_ENET_GROUP 0x0900

#define	STOP_TX_32 0x0e00 /add chan# bits 2-6 /

#define	ENTER_HUNT_MODE_32 0x1e00

#define	GOV 0x01

#define	GUN 0x02

#define	GINT 0x04

#define	IQOV 0x08

#define	SET_TIMER 0x0800

#define	INTR_VALID 0x8000 /* Valid interrupt entry */

#define	INTR_WRAP 0x4000 /* Wrap bit in the interrupt entry table */

#define	INTR_CH_NU 0x07c0 /* Channel Num in interrupt table */

#define	INTR_MASK_BITS 0x383f

#define	MODE_HDLC 0x0

#define	MODE_APPLE_TALK 0x2

#define	MODE_SS7 0x3

#define	MODE_UART 0x4

#define	MODE_PROFIBUS 0x5

#define	MODE_ASYNC_HDLC 0x6

#define	MODE_V14 0x7

#define	MODE_BISYNC 0x8

#define	MODE_DDCMP 0x9

#define	MODE_MULTI_CHANNEL 0xa

#define	MODE_ETHERNET 0xc

#define	DIAG_NORMAL 0x0

#define	DIAG_LOCAL_LPB 0x1

#define	DIAG_AUTO_ECHO 0x2

#define	DIAG_LBP_ECHO 0x3

#define	ENC_NRZ 0x0

#define	ENC_NRZI 0x1

#define	ENC_FM0 0x2

#define	ENC_MANCH 0x4

#define	ENC_DIFF_MANC 0x6

#define	CLOCK_RATE_1 0x0

#define	CLOCK_RATE_8 0x1

#define	CLOCK_RATE_16 0x2

#define	CLOCK_RATE_32 0x3

#define	TPP_00 0x0

#define	TPP_10 0x1

#define	TPP_01 0x2

#define	TPP_11 0x3

#define	TPL_NO 0x0

#define	TPL_8 0x1

#define	TPL_16 0x2

#define	TPL_32 0x3

#define	TPL_48 0x4

#define	TPL_64 0x5

#define	TPL_128 0x6

#define	TSNC_INFINITE 0x0

#define	TSNC_14_65 0x1

#define	TSNC_4_15 0x2

#define	TSNC_3_1 0x3

#define	EDGE_BOTH 0x0

#define	EDGE_POS 0x1

#define	EDGE_NEG 0x2

#define	EDGE_NO 0x3

#define	SYNL_NO 0x0

#define	SYNL_4 0x1

#define	SYNL_8 0x2

#define	SYNL_16 0x3

#define	TCRC_CCITT16 0x0

#define	TCRC_CRC16 0x1

#define	TCRC_CCITT32 0x2

#define	TODR_TOD 0x8000 /* Transmit on demand */

#define	CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */

#define	CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */

#define	CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */

#define	CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */

#define	CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */

#define	CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */

#define	CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */

#define	CICR_SPS ((uint)0x00000001) /* SCC Spread */

#define	INTR_PIO_PC0 0x80000000 /* parallel I/O C bit 0 */

#define	INTR_SCC1 0x40000000 /* SCC port 1 */

#define	INTR_SCC2 0x20000000 /* SCC port 2 */

#define	INTR_SCC3 0x10000000 /* SCC port 3 */

#define	INTR_SCC4 0x08000000 /* SCC port 4 */

#define	INTR_PIO_PC1 0x04000000 /* parallel i/o C bit 1 */

#define	INTR_TIMER1 0x02000000 /* timer 1 */

#define	INTR_PIO_PC2 0x01000000 /* parallel i/o C bit 2 */

#define	INTR_PIO_PC3 0x00800000 /* parallel i/o C bit 3 */

#define	INTR_SDMA_BERR 0x00400000 /* SDMA channel bus error */

#define	INTR_DMA1 0x00200000 /* idma 1 */

#define	INTR_DMA2 0x00100000 /* idma 2 */

#define	INTR_TIMER2 0x00040000 /* timer 2 */

#define	INTR_CP_TIMER 0x00020000 /* CP timer */

#define	INTR_PIP_STATUS 0x00010000 /* PIP status */

#define	INTR_PIO_PC4 0x00008000 /* parallel i/o C bit 4 */

#define	INTR_PIO_PC5 0x00004000 /* parallel i/o C bit 5 */

#define	INTR_TIMER3 0x00001000 /* timer 3 */

#define	INTR_PIO_PC6 0x00000800 /* parallel i/o C bit 6 */

#define	INTR_PIO_PC7 0x00000400 /* parallel i/o C bit 7 */

#define	INTR_PIO_PC8 0x00000200 /* parallel i/o C bit 8 */

#define	INTR_TIMER4 0x00000080 /* timer 4 */

#define	INTR_PIO_PC9 0x00000040 /* parallel i/o C bit 9 */

#define	INTR_SCP 0x00000020 /* SCP */

#define	INTR_SMC1 0x00000010 /* SMC 1 */

#define	INTR_SMC2 0x00000008 /* SMC 2 */

#define	INTR_PIO_PC10 0x00000004 /* parallel i/o C bit 10 */

#define	INTR_PIO_PC11 0x00000002 /* parallel i/o C bit 11 */

#define	INTR_ERR 0x00000001 /* error */

#define	CPMVEC_NR 32

#define	CPMVEC_PIO_PC0 0x1f

#define	CPMVEC_SCC1 0x1e

#define	CPMVEC_SCC2 0x1d

#define	CPMVEC_SCC3 0x1c

#define	CPMVEC_SCC4 0x1b

#define	CPMVEC_PIO_PC1 0x1a

#define	CPMVEC_TIMER1 0x19

#define	CPMVEC_PIO_PC2 0x18

#define	CPMVEC_PIO_PC3 0x17

#define	CPMVEC_SDMA_CB_ERR 0x16

#define	CPMVEC_IDMA1 0x15

#define	CPMVEC_IDMA2 0x14

#define	CPMVEC_RESERVED3 0x13

#define	CPMVEC_TIMER2 0x12

#define	CPMVEC_RISCTIMER 0x11

#define	CPMVEC_RESERVED2 0x10

#define	CPMVEC_PIO_PC4 0x0f

#define	CPMVEC_PIO_PC5 0x0e

#define	CPMVEC_TIMER3 0x0c

#define	CPMVEC_PIO_PC6 0x0b

#define	CPMVEC_PIO_PC7 0x0a

#define	CPMVEC_PIO_PC8 0x09

#define	CPMVEC_RESERVED1 0x08

#define	CPMVEC_TIMER4 0x07

#define	CPMVEC_PIO_PC9 0x06

#define	CPMVEC_SPI 0x05

#define	CPMVEC_SMC1 0x04

#define	CPMVEC_SMC2 0x03

#define	CPMVEC_PIO_PC10 0x02

#define	CPMVEC_PIO_PC11 0x01

#define	CPMVEC_ERROR 0x00

#define	PA_RXD1 ((ushort)0x0001)

#define	PA_TXD1 ((ushort)0x0002)

#define	PA_RXD2 ((ushort)0x0004)

#define	PA_TXD2 ((ushort)0x0008)

#define	PA_RXD3 ((ushort)0x0010)

#define	PA_TXD3 ((ushort)0x0020)

#define	PA_RXD4 ((ushort)0x0040)

#define	PA_TXD4 ((ushort)0x0080)

#define	PA_CLK1 ((ushort)0x0100)

#define	PA_CLK2 ((ushort)0x0200)

#define	PA_CLK3 ((ushort)0x0400)

#define	PA_CLK4 ((ushort)0x0800)

#define	PA_CLK5 ((ushort)0x1000)

#define	PA_CLK6 ((ushort)0x2000)

#define	PA_CLK7 ((ushort)0x4000)

#define	PA_CLK8 ((ushort)0x8000)

#define	PC_RTS1 ((ushort)0x0001)

#define	PC_RTS2 ((ushort)0x0002)

#define	PC__RTS3 ((ushort)0x0004) /* !RTS3 */

#define	PC__RTS4 ((ushort)0x0008) /* !RTS4 */

#define	PC_CTS1 ((ushort)0x0010)

#define	PC_CD1 ((ushort)0x0020)

#define	PC_CTS2 ((ushort)0x0040)

#define	PC_CD2 ((ushort)0x0080)

#define	PC_CTS3 ((ushort)0x0100)

#define	PC_CD3 ((ushort)0x0200)

#define	PC_CTS4 ((ushort)0x0400)

#define	PC_CD4 ((ushort)0x0800)

#define	DTACK 0xe000

#define	ADR_MASK 0x1ffc

#define	RDWR_MASK 0x0002

#define	FC_MASK 0x0001

#define	TBD_ADDR(quicc, pram)

#define	RBD_ADDR(quicc, pram)

#define	TBD_CUR_ADDR(quicc, pram)

#define	RBD_CUR_ADDR(quicc, pram)

#define	TBD_SET_CUR_ADDR(bd, quicc, pram)

#define	RBD_SET_CUR_ADDR(bd, quicc, pram)

#define	INCREASE_TBD(bd, quicc, pram)

#define	DECREASE_TBD(bd, quicc, pram)

#define	INCREASE_RBD(bd, quicc, pram)

#define	DECREASE_RBD(bd, quicc, pram)

#define	QMC_BASE(quicc, page) (struct global_multi_pram *)(&quicc->pram[page])

#define	MCBASE(quicc, page) (unsigned long)(quicc->pram[page].m.mcbase)

#define	CHANNEL_PRAM_BASE(quicc, channel)

#define	TBD_32_ADDR(quicc, page, channel)

#define	RBD_32_ADDR(quicc, page, channel)

#define	TBD_32_CUR_ADDR(quicc, page, channel)

#define	RBD_32_CUR_ADDR(quicc, page, channel)

#define	TBD_32_SET_CUR_ADDR(bd, quicc, page, channel)

#define	RBD_32_SET_CUR_ADDR(bd, quicc, page, channel)

#define	INCREASE_TBD_32(bd, quicc, page, channel)

#define	DECREASE_TBD_32(bd, quicc, page, channel)

#define	INCREASE_RBD_32(bd, quicc, page, channel)

#define	DECREASE_RBD_32(bd, quicc, page, channel)

Macro Definition Documentation

#define ADR_MASK 0x1ffc

Definition at line 313 of file m68360_regs.h.

#define CHANNEL_PRAM_BASE	(	quicc,
		channel
	)

Value:

((struct quicc32_pram *) \

(&(quicc->ch_or_u.ch_pram_tbl[channel])))

Definition at line 364 of file m68360_regs.h.

#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */

Definition at line 142 of file m68360_regs.h.

#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */

Definition at line 141 of file m68360_regs.h.

#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */

Definition at line 136 of file m68360_regs.h.

#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */

Definition at line 137 of file m68360_regs.h.

#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */

Definition at line 138 of file m68360_regs.h.

#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */

Definition at line 139 of file m68360_regs.h.

#define CICR_SPS ((uint)0x00000001) /* SCC Spread */

Definition at line 144 of file m68360_regs.h.

#define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */

Definition at line 143 of file m68360_regs.h.

#define CLEAR_BIT	(	x,
		bit
	)	x =bit

Definition at line 13 of file m68360_regs.h.

#define CLOCK_RATE_1 0x0

Definition at line 86 of file m68360_regs.h.

#define CLOCK_RATE_16 0x2

Definition at line 88 of file m68360_regs.h.

#define CLOCK_RATE_32 0x3

Definition at line 89 of file m68360_regs.h.

#define CLOCK_RATE_8 0x1

Definition at line 87 of file m68360_regs.h.

#define CLOSE_RX_BD 0x0700

Definition at line 33 of file m68360_regs.h.

#define CMD_CHANNEL 0x00f0

Definition at line 22 of file m68360_regs.h.

#define CMD_FLAG 0x0001

Definition at line 23 of file m68360_regs.h.

#define CMD_OPCODE 0x0f00

Definition at line 21 of file m68360_regs.h.

#define CPMVEC_ERROR 0x00

Definition at line 217 of file m68360_regs.h.

#define CPMVEC_IDMA1 0x15

Definition at line 197 of file m68360_regs.h.

#define CPMVEC_IDMA2 0x14

Definition at line 198 of file m68360_regs.h.

#define CPMVEC_NR 32

Definition at line 186 of file m68360_regs.h.

#define CPMVEC_PIO_PC0 0x1f

Definition at line 187 of file m68360_regs.h.

#define CPMVEC_PIO_PC1 0x1a

Definition at line 192 of file m68360_regs.h.

#define CPMVEC_PIO_PC10 0x02

Definition at line 215 of file m68360_regs.h.

#define CPMVEC_PIO_PC11 0x01

Definition at line 216 of file m68360_regs.h.

#define CPMVEC_PIO_PC2 0x18

Definition at line 194 of file m68360_regs.h.

#define CPMVEC_PIO_PC3 0x17

Definition at line 195 of file m68360_regs.h.

#define CPMVEC_PIO_PC4 0x0f

Definition at line 203 of file m68360_regs.h.

#define CPMVEC_PIO_PC5 0x0e

Definition at line 204 of file m68360_regs.h.

#define CPMVEC_PIO_PC6 0x0b

Definition at line 206 of file m68360_regs.h.

#define CPMVEC_PIO_PC7 0x0a

Definition at line 207 of file m68360_regs.h.

#define CPMVEC_PIO_PC8 0x09

Definition at line 208 of file m68360_regs.h.

#define CPMVEC_PIO_PC9 0x06

Definition at line 211 of file m68360_regs.h.

#define CPMVEC_RESERVED1 0x08

Definition at line 209 of file m68360_regs.h.

#define CPMVEC_RESERVED2 0x10

Definition at line 202 of file m68360_regs.h.

#define CPMVEC_RESERVED3 0x13

Definition at line 199 of file m68360_regs.h.

#define CPMVEC_RISCTIMER 0x11

Definition at line 201 of file m68360_regs.h.

#define CPMVEC_SCC1 0x1e

Definition at line 188 of file m68360_regs.h.

#define CPMVEC_SCC2 0x1d

Definition at line 189 of file m68360_regs.h.

#define CPMVEC_SCC3 0x1c

Definition at line 190 of file m68360_regs.h.

#define CPMVEC_SCC4 0x1b

Definition at line 191 of file m68360_regs.h.

#define CPMVEC_SDMA_CB_ERR 0x16

Definition at line 196 of file m68360_regs.h.

#define CPMVEC_SMC1 0x04

Definition at line 213 of file m68360_regs.h.

#define CPMVEC_SMC2 0x03

Definition at line 214 of file m68360_regs.h.

#define CPMVEC_SPI 0x05

Definition at line 212 of file m68360_regs.h.

#define CPMVEC_TIMER1 0x19

Definition at line 193 of file m68360_regs.h.

#define CPMVEC_TIMER2 0x12

Definition at line 200 of file m68360_regs.h.

#define CPMVEC_TIMER3 0x0c

Definition at line 205 of file m68360_regs.h.

#define CPMVEC_TIMER4 0x07

Definition at line 210 of file m68360_regs.h.

#define DECREASE_RBD	(	bd,
		quicc,
		pram
	)

Value:

{  \
    if ((bd) == RBD_ADDR(quicc, pram)) \
        while (!((bd)->status & T_W))  \
            (bd)++;                    \
    else                               \
        (bd)--;                        \
}

Definition at line 351 of file m68360_regs.h.

#define DECREASE_RBD_32	(	bd,
		quicc,
		page,
		channel
	)

Value:

{  \
    if ((bd) == RBD_32_ADDR(quicc, page,channel)) \
        while (!((bd)->status & T_W))             \
            (bd)++;                               \
    else                                          \
        (bd)--;                                   \
}

Definition at line 400 of file m68360_regs.h.

#define DECREASE_TBD	(	bd,
		quicc,
		pram
	)

Value:

{  \
    if ((bd) == TBD_ADDR(quicc, pram)) \
        while (!((bd)->status & T_W))  \
            (bd)++;                    \
    else                               \
        (bd)--;                        \
}

Definition at line 338 of file m68360_regs.h.

#define DECREASE_TBD_32	(	bd,
		quicc,
		page,
		channel
	)

Value:

{  \
    if ((bd) == TBD_32_ADDR(quicc, page,channel)) \
        while (!((bd)->status & T_W))             \
            (bd)++;                               \
    else                                          \
        (bd)--;                                   \
}

Definition at line 387 of file m68360_regs.h.

#define DIAG_AUTO_ECHO 0x2

Definition at line 75 of file m68360_regs.h.

#define DIAG_LBP_ECHO 0x3

Definition at line 76 of file m68360_regs.h.

#define DIAG_LOCAL_LPB 0x1

Definition at line 74 of file m68360_regs.h.

#define DIAG_NORMAL 0x0

Definition at line 73 of file m68360_regs.h.

#define DTACK 0xe000

Definition at line 312 of file m68360_regs.h.

#define EDGE_BOTH 0x0

Definition at line 109 of file m68360_regs.h.

#define EDGE_NEG 0x2

Definition at line 111 of file m68360_regs.h.

#define EDGE_NO 0x3

Definition at line 112 of file m68360_regs.h.

#define EDGE_POS 0x1

Definition at line 110 of file m68360_regs.h.

#define ENC_DIFF_MANC 0x6

Definition at line 83 of file m68360_regs.h.

#define ENC_FM0 0x2

Definition at line 81 of file m68360_regs.h.

#define ENC_MANCH 0x4

Definition at line 82 of file m68360_regs.h.

#define ENC_NRZ 0x0

Definition at line 79 of file m68360_regs.h.

#define ENC_NRZI 0x1

Definition at line 80 of file m68360_regs.h.

#define ENTER_HUNT_MODE 0x0300

Definition at line 29 of file m68360_regs.h.

#define ENTER_HUNT_MODE_32 0x1e00

Definition at line 39 of file m68360_regs.h.

#define FC_MASK 0x0001

Definition at line 315 of file m68360_regs.h.

#define GINT 0x04

Definition at line 44 of file m68360_regs.h.

#define GOV 0x01

Definition at line 42 of file m68360_regs.h.

#define GR_STOP_TX 0x0500

Definition at line 31 of file m68360_regs.h.

#define GUN 0x02

Definition at line 43 of file m68360_regs.h.

#define INCREASE_RBD	(	bd,
		quicc,
		pram
	)

Value:

{  \
    if((bd)->status & R_W)             \
        (bd) = RBD_ADDR(quicc,pram);   \
    else                               \
        (bd)++;                        \
}

Definition at line 345 of file m68360_regs.h.

#define INCREASE_RBD_32	(	bd,
		quicc,
		page,
		channel
	)

Value:

{  \
    if((bd)->status & R_W)                        \
        (bd) = RBD_32_ADDR(quicc,page,channel);   \
    else                                          \
        (bd)++;                                   \
}

Definition at line 394 of file m68360_regs.h.

#define INCREASE_TBD	(	bd,
		quicc,
		pram
	)

Value:

{  \
    if((bd)->status & T_W)             \
        (bd) = TBD_ADDR(quicc,pram);   \
    else                               \
        (bd)++;                        \
}

Definition at line 332 of file m68360_regs.h.

#define INCREASE_TBD_32	(	bd,
		quicc,
		page,
		channel
	)

Value:

{  \
    if((bd)->status & T_W)                        \
        (bd) = TBD_32_ADDR(quicc,page,channel);   \
    else                                          \
        (bd)++;                                   \
}

Definition at line 381 of file m68360_regs.h.

#define INIT_RX_PARAMS 0x0100

Definition at line 27 of file m68360_regs.h.

#define INIT_RXTX_PARAMS 0x0000

Definition at line 26 of file m68360_regs.h.

#define INIT_TX_PARAMS 0x0200

Definition at line 28 of file m68360_regs.h.

#define INTR_CH_NU 0x07c0 /* Channel Num in interrupt table */

Definition at line 54 of file m68360_regs.h.

#define INTR_CP_TIMER 0x00020000 /* CP timer */

Definition at line 164 of file m68360_regs.h.

#define INTR_DMA1 0x00200000 /* idma 1 */

Definition at line 161 of file m68360_regs.h.

#define INTR_DMA2 0x00100000 /* idma 2 */

Definition at line 162 of file m68360_regs.h.

#define INTR_ERR 0x00000001 /* error */

Definition at line 179 of file m68360_regs.h.

#define INTR_MASK_BITS 0x383f

Definition at line 55 of file m68360_regs.h.

#define INTR_PIO_PC0 0x80000000 /* parallel I/O C bit 0 */

Definition at line 151 of file m68360_regs.h.

#define INTR_PIO_PC1 0x04000000 /* parallel i/o C bit 1 */

Definition at line 156 of file m68360_regs.h.

#define INTR_PIO_PC10 0x00000004 /* parallel i/o C bit 10 */

Definition at line 177 of file m68360_regs.h.

#define INTR_PIO_PC11 0x00000002 /* parallel i/o C bit 11 */

Definition at line 178 of file m68360_regs.h.

#define INTR_PIO_PC2 0x01000000 /* parallel i/o C bit 2 */

Definition at line 158 of file m68360_regs.h.

#define INTR_PIO_PC3 0x00800000 /* parallel i/o C bit 3 */

Definition at line 159 of file m68360_regs.h.

#define INTR_PIO_PC4 0x00008000 /* parallel i/o C bit 4 */

Definition at line 166 of file m68360_regs.h.

#define INTR_PIO_PC5 0x00004000 /* parallel i/o C bit 5 */

Definition at line 167 of file m68360_regs.h.

#define INTR_PIO_PC6 0x00000800 /* parallel i/o C bit 6 */

Definition at line 169 of file m68360_regs.h.

#define INTR_PIO_PC7 0x00000400 /* parallel i/o C bit 7 */

Definition at line 170 of file m68360_regs.h.

#define INTR_PIO_PC8 0x00000200 /* parallel i/o C bit 8 */

Definition at line 171 of file m68360_regs.h.

#define INTR_PIO_PC9 0x00000040 /* parallel i/o C bit 9 */

Definition at line 173 of file m68360_regs.h.

#define INTR_PIP_STATUS 0x00010000 /* PIP status */

Definition at line 165 of file m68360_regs.h.

#define INTR_SCC1 0x40000000 /* SCC port 1 */

Definition at line 152 of file m68360_regs.h.

#define INTR_SCC2 0x20000000 /* SCC port 2 */

Definition at line 153 of file m68360_regs.h.

#define INTR_SCC3 0x10000000 /* SCC port 3 */

Definition at line 154 of file m68360_regs.h.

#define INTR_SCC4 0x08000000 /* SCC port 4 */

Definition at line 155 of file m68360_regs.h.

#define INTR_SCP 0x00000020 /* SCP */

Definition at line 174 of file m68360_regs.h.

#define INTR_SDMA_BERR 0x00400000 /* SDMA channel bus error */

Definition at line 160 of file m68360_regs.h.

#define INTR_SMC1 0x00000010 /* SMC 1 */

Definition at line 175 of file m68360_regs.h.

#define INTR_SMC2 0x00000008 /* SMC 2 */

Definition at line 176 of file m68360_regs.h.

#define INTR_TIMER1 0x02000000 /* timer 1 */

Definition at line 157 of file m68360_regs.h.

#define INTR_TIMER2 0x00040000 /* timer 2 */

Definition at line 163 of file m68360_regs.h.

#define INTR_TIMER3 0x00001000 /* timer 3 */

Definition at line 168 of file m68360_regs.h.

#define INTR_TIMER4 0x00000080 /* timer 4 */

Definition at line 172 of file m68360_regs.h.

#define INTR_VALID 0x8000 /* Valid interrupt entry */

Definition at line 52 of file m68360_regs.h.

#define INTR_WRAP 0x4000 /* Wrap bit in the interrupt entry table */

Definition at line 53 of file m68360_regs.h.

#define IQOV 0x08

Definition at line 45 of file m68360_regs.h.

#define MCBASE	(	quicc,
		page
	)	(unsigned long)(quicc->pram[page].m.mcbase)

Definition at line 363 of file m68360_regs.h.

#define MODE_APPLE_TALK 0x2

Definition at line 62 of file m68360_regs.h.

#define MODE_ASYNC_HDLC 0x6

Definition at line 66 of file m68360_regs.h.

#define MODE_BISYNC 0x8

Definition at line 68 of file m68360_regs.h.

#define MODE_DDCMP 0x9

Definition at line 69 of file m68360_regs.h.

#define MODE_ETHERNET 0xc

Definition at line 71 of file m68360_regs.h.

#define MODE_HDLC 0x0

Definition at line 61 of file m68360_regs.h.

#define MODE_MULTI_CHANNEL 0xa

Definition at line 70 of file m68360_regs.h.

#define MODE_PROFIBUS 0x5

Definition at line 65 of file m68360_regs.h.

#define MODE_SS7 0x3

Definition at line 63 of file m68360_regs.h.

#define MODE_UART 0x4

Definition at line 64 of file m68360_regs.h.

#define MODE_V14 0x7

Definition at line 67 of file m68360_regs.h.

#define PA_CLK1 ((ushort)0x0100)

Definition at line 276 of file m68360_regs.h.

#define PA_CLK2 ((ushort)0x0200)

Definition at line 277 of file m68360_regs.h.

#define PA_CLK3 ((ushort)0x0400)

Definition at line 278 of file m68360_regs.h.

#define PA_CLK4 ((ushort)0x0800)

Definition at line 279 of file m68360_regs.h.

#define PA_CLK5 ((ushort)0x1000)

Definition at line 280 of file m68360_regs.h.

#define PA_CLK6 ((ushort)0x2000)

Definition at line 281 of file m68360_regs.h.

#define PA_CLK7 ((ushort)0x4000)

Definition at line 282 of file m68360_regs.h.

#define PA_CLK8 ((ushort)0x8000)

Definition at line 283 of file m68360_regs.h.

#define PA_RXD1 ((ushort)0x0001)

Definition at line 267 of file m68360_regs.h.

#define PA_RXD2 ((ushort)0x0004)

Definition at line 269 of file m68360_regs.h.

#define PA_RXD3 ((ushort)0x0010)

Definition at line 271 of file m68360_regs.h.

#define PA_RXD4 ((ushort)0x0040)

Definition at line 273 of file m68360_regs.h.

#define PA_TXD1 ((ushort)0x0002)

Definition at line 268 of file m68360_regs.h.

#define PA_TXD2 ((ushort)0x0008)

Definition at line 270 of file m68360_regs.h.

#define PA_TXD3 ((ushort)0x0020)

Definition at line 272 of file m68360_regs.h.

#define PA_TXD4 ((ushort)0x0080)

Definition at line 274 of file m68360_regs.h.

#define PC__RTS3 ((ushort)0x0004) /* !RTS3 */

Definition at line 295 of file m68360_regs.h.

#define PC__RTS4 ((ushort)0x0008) /* !RTS4 */

Definition at line 296 of file m68360_regs.h.

#define PC_CD1 ((ushort)0x0020)

Definition at line 299 of file m68360_regs.h.

#define PC_CD2 ((ushort)0x0080)

Definition at line 301 of file m68360_regs.h.

#define PC_CD3 ((ushort)0x0200)

Definition at line 303 of file m68360_regs.h.

#define PC_CD4 ((ushort)0x0800)

Definition at line 305 of file m68360_regs.h.

#define PC_CTS1 ((ushort)0x0010)

Definition at line 298 of file m68360_regs.h.

#define PC_CTS2 ((ushort)0x0040)

Definition at line 300 of file m68360_regs.h.

#define PC_CTS3 ((ushort)0x0100)

Definition at line 302 of file m68360_regs.h.

#define PC_CTS4 ((ushort)0x0400)

Definition at line 304 of file m68360_regs.h.

#define PC_RTS1 ((ushort)0x0001)

Definition at line 293 of file m68360_regs.h.

#define PC_RTS2 ((ushort)0x0002)

Definition at line 294 of file m68360_regs.h.

#define QMC_BASE	(	quicc,
		page
	)	(struct global_multi_pram *)(&quicc->pram[page])

Definition at line 362 of file m68360_regs.h.

#define RBD_32_ADDR	(	quicc,
		page,
		channel
	)

Value:

((struct quicc_bd *) \

(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbase)))

Definition at line 368 of file m68360_regs.h.

#define RBD_32_CUR_ADDR	(	quicc,
		page,
		channel
	)

Value:

((struct quicc_bd *) \

(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbptr)))

Definition at line 372 of file m68360_regs.h.

#define RBD_32_SET_CUR_ADDR	(	bd,
		quicc,
		page,
		channel
	)

Value:

CHANNEL_PRAM_BASE(quicc,channel)->rbptr = \

((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))

Definition at line 377 of file m68360_regs.h.

#define RBD_ADDR	(	quicc,
		pram
	)

Value:

((struct quicc_bd *) \

(quicc->ch_or_u.u.udata_bd_ucode + pram->rbase))

Definition at line 322 of file m68360_regs.h.

#define RBD_CUR_ADDR	(	quicc,
		pram
	)

Value:

((struct quicc_bd *) \

(quicc->ch_or_u.u.udata_bd_ucode + pram->rbptr))

Definition at line 326 of file m68360_regs.h.

#define RBD_SET_CUR_ADDR	(	bd,
		quicc,
		pram
	)

Value:

pram->rbptr = \

((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))

Definition at line 330 of file m68360_regs.h.

#define RDWR_MASK 0x0002

Definition at line 314 of file m68360_regs.h.

#define RESET_ENET_GROUP 0x0900

Definition at line 35 of file m68360_regs.h.

#define RESTART_TX 0x0600

Definition at line 32 of file m68360_regs.h.

#define SET_ENET_GROUP 0x0800

Definition at line 34 of file m68360_regs.h.

#define SET_TIMER 0x0800

Definition at line 49 of file m68360_regs.h.

#define SOFTWARE_RESET 0x8000

Definition at line 20 of file m68360_regs.h.

#define STOP_TX 0x0400

Definition at line 30 of file m68360_regs.h.

#define STOP_TX_32 0x0e00 /*add chan# bits 2-6 */

Definition at line 38 of file m68360_regs.h.

#define SYNL_16 0x3

Definition at line 117 of file m68360_regs.h.

#define SYNL_4 0x1

Definition at line 115 of file m68360_regs.h.

#define SYNL_8 0x2

Definition at line 116 of file m68360_regs.h.

#define SYNL_NO 0x0

Definition at line 114 of file m68360_regs.h.

#define TBD_32_ADDR	(	quicc,
		page,
		channel
	)

Value:

((struct quicc_bd *) \

(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbase)))

Definition at line 366 of file m68360_regs.h.

#define TBD_32_CUR_ADDR	(	quicc,
		page,
		channel
	)

Value:

((struct quicc_bd *) \

(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbptr)))

Definition at line 370 of file m68360_regs.h.

#define TBD_32_SET_CUR_ADDR	(	bd,
		quicc,
		page,
		channel
	)

Value:

CHANNEL_PRAM_BASE(quicc,channel)->tbptr = \

((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))

Definition at line 374 of file m68360_regs.h.

#define TBD_ADDR	(	quicc,
		pram
	)

Value:

((struct quicc_bd *) \

(quicc->ch_or_u.u.udata_bd_ucode + pram->tbase))

Definition at line 320 of file m68360_regs.h.

#define TBD_CUR_ADDR	(	quicc,
		pram
	)

Value:

((struct quicc_bd *) \

(quicc->ch_or_u.u.udata_bd_ucode + pram->tbptr))

Definition at line 324 of file m68360_regs.h.

#define TBD_SET_CUR_ADDR	(	bd,
		quicc,
		pram
	)

Value:

pram->tbptr = \

((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))

Definition at line 328 of file m68360_regs.h.

#define TCRC_CCITT16 0x0

Definition at line 119 of file m68360_regs.h.

#define TCRC_CCITT32 0x2

Definition at line 121 of file m68360_regs.h.

#define TCRC_CRC16 0x1

Definition at line 120 of file m68360_regs.h.

#define TODR_TOD 0x8000 /* Transmit on demand */

Definition at line 127 of file m68360_regs.h.

#define TPL_128 0x6

Definition at line 102 of file m68360_regs.h.

#define TPL_16 0x2

Definition at line 98 of file m68360_regs.h.

#define TPL_32 0x3

Definition at line 99 of file m68360_regs.h.

#define TPL_48 0x4

Definition at line 100 of file m68360_regs.h.

#define TPL_64 0x5

Definition at line 101 of file m68360_regs.h.

#define TPL_8 0x1

Definition at line 97 of file m68360_regs.h.

#define TPL_NO 0x0

Definition at line 96 of file m68360_regs.h.

#define TPP_00 0x0

Definition at line 91 of file m68360_regs.h.

#define TPP_01 0x2

Definition at line 93 of file m68360_regs.h.

#define TPP_10 0x1

Definition at line 92 of file m68360_regs.h.

#define TPP_11 0x3

Definition at line 94 of file m68360_regs.h.

#define TSNC_14_65 0x1

Definition at line 105 of file m68360_regs.h.

#define TSNC_3_1 0x3

Definition at line 107 of file m68360_regs.h.

#define TSNC_4_15 0x2

Definition at line 106 of file m68360_regs.h.

#define TSNC_INFINITE 0x0

Definition at line 104 of file m68360_regs.h.

Macros

Macro Definition Documentation