Data Structures
struct	reg_gio_r_pa_din

struct	reg_gio_rw_pa_dout

struct	reg_gio_rw_pa_oe

struct	reg_gio_rw_pa_byte0_dout

struct	reg_gio_rw_pa_byte0_oe

struct	reg_gio_rw_pa_byte1_dout

struct	reg_gio_rw_pa_byte1_oe

struct	reg_gio_rw_pa_byte2_dout

struct	reg_gio_rw_pa_byte2_oe

struct	reg_gio_rw_pa_byte3_dout

struct	reg_gio_rw_pa_byte3_oe

struct	reg_gio_r_pb_din

struct	reg_gio_rw_pb_dout

struct	reg_gio_rw_pb_oe

struct	reg_gio_rw_pb_byte0_dout

struct	reg_gio_rw_pb_byte0_oe

struct	reg_gio_rw_pb_byte1_dout

struct	reg_gio_rw_pb_byte1_oe

struct	reg_gio_rw_pb_byte2_dout

struct	reg_gio_rw_pb_byte2_oe

struct	reg_gio_rw_pb_byte3_dout

struct	reg_gio_rw_pb_byte3_oe

struct	reg_gio_r_pc_din

struct	reg_gio_rw_pc_dout

struct	reg_gio_rw_pc_oe

struct	reg_gio_rw_pc_byte0_dout

struct	reg_gio_rw_pc_byte0_oe

struct	reg_gio_rw_pc_byte1_dout

struct	reg_gio_rw_pc_byte1_oe

struct	reg_gio_r_pd_din

struct	reg_gio_rw_intr_cfg

struct	reg_gio_rw_intr_pins

struct	reg_gio_rw_intr_mask

struct	reg_gio_rw_ack_intr

struct	reg_gio_r_intr

struct	reg_gio_r_masked_intr

struct	reg_gio_rw_i2c0_start

struct	reg_gio_rw_i2c0_cfg

struct	reg_gio_rw_i2c0_ctrl

struct	reg_gio_rw_i2c0_data

struct	reg_gio_rw_i2c0_data2

struct	reg_gio_rw_i2c1_start

struct	reg_gio_rw_i2c1_cfg

struct	reg_gio_rw_i2c1_ctrl

struct	reg_gio_rw_i2c1_data

struct	reg_gio_rw_i2c1_data2

struct	reg_gio_r_ppwm_stat

struct	reg_gio_rw_ppwm_data

struct	reg_gio_rw_pwm0_ctrl

struct	reg_gio_rw_pwm0_var

struct	reg_gio_rw_pwm0_data

struct	reg_gio_rw_pwm1_ctrl

struct	reg_gio_rw_pwm1_var

struct	reg_gio_rw_pwm1_data

struct	reg_gio_rw_pwm2_ctrl

struct	reg_gio_rw_pwm2_var

struct	reg_gio_rw_pwm2_data

struct	reg_gio_rw_pwm_in_cfg

struct	reg_gio_r_pwm_in_lo

struct	reg_gio_r_pwm_in_hi

struct	reg_gio_r_pwm_in_cnt

Macros
#define	REG_RD(scope, inst, reg)

#define	REG_WR(scope, inst, reg, val)

#define	REG_RD_VECT(scope, inst, reg, index)

#define	REG_WR_VECT(scope, inst, reg, index, val)

#define	REG_RD_INT(scope, inst, reg) REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

#define	REG_WR_INT(scope, inst, reg, val) REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

#define	REG_RD_INT_VECT(scope, inst, reg, index)

#define	REG_WR_INT_VECT(scope, inst, reg, index, val)

#define	REG_TYPE_CONV(type, orgtype, val) ( { union { orgtype o; type n; } r; r.o = val; r.n; } )

#define	reg_page_size 8192

#define	REG_ADDR(scope, inst, reg) ( (inst) + REG_RD_ADDR_##scope##_##reg )

#define	REG_ADDR_VECT(scope, inst, reg, index)

#define	REG_RD_ADDR_gio_r_pa_din 0

#define	REG_RD_ADDR_gio_rw_pa_dout 4

#define	REG_WR_ADDR_gio_rw_pa_dout 4

#define	REG_RD_ADDR_gio_rw_pa_oe 8

#define	REG_WR_ADDR_gio_rw_pa_oe 8

#define	REG_RD_ADDR_gio_rw_pa_byte0_dout 12

#define	REG_WR_ADDR_gio_rw_pa_byte0_dout 12

#define	REG_RD_ADDR_gio_rw_pa_byte0_oe 16

#define	REG_WR_ADDR_gio_rw_pa_byte0_oe 16

#define	REG_RD_ADDR_gio_rw_pa_byte1_dout 20

#define	REG_WR_ADDR_gio_rw_pa_byte1_dout 20

#define	REG_RD_ADDR_gio_rw_pa_byte1_oe 24

#define	REG_WR_ADDR_gio_rw_pa_byte1_oe 24

#define	REG_RD_ADDR_gio_rw_pa_byte2_dout 28

#define	REG_WR_ADDR_gio_rw_pa_byte2_dout 28

#define	REG_RD_ADDR_gio_rw_pa_byte2_oe 32

#define	REG_WR_ADDR_gio_rw_pa_byte2_oe 32

#define	REG_RD_ADDR_gio_rw_pa_byte3_dout 36

#define	REG_WR_ADDR_gio_rw_pa_byte3_dout 36

#define	REG_RD_ADDR_gio_rw_pa_byte3_oe 40

#define	REG_WR_ADDR_gio_rw_pa_byte3_oe 40

#define	REG_RD_ADDR_gio_r_pb_din 44

#define	REG_RD_ADDR_gio_rw_pb_dout 48

#define	REG_WR_ADDR_gio_rw_pb_dout 48

#define	REG_RD_ADDR_gio_rw_pb_oe 52

#define	REG_WR_ADDR_gio_rw_pb_oe 52

#define	REG_RD_ADDR_gio_rw_pb_byte0_dout 56

#define	REG_WR_ADDR_gio_rw_pb_byte0_dout 56

#define	REG_RD_ADDR_gio_rw_pb_byte0_oe 60

#define	REG_WR_ADDR_gio_rw_pb_byte0_oe 60

#define	REG_RD_ADDR_gio_rw_pb_byte1_dout 64

#define	REG_WR_ADDR_gio_rw_pb_byte1_dout 64

#define	REG_RD_ADDR_gio_rw_pb_byte1_oe 68

#define	REG_WR_ADDR_gio_rw_pb_byte1_oe 68

#define	REG_RD_ADDR_gio_rw_pb_byte2_dout 72

#define	REG_WR_ADDR_gio_rw_pb_byte2_dout 72

#define	REG_RD_ADDR_gio_rw_pb_byte2_oe 76

#define	REG_WR_ADDR_gio_rw_pb_byte2_oe 76

#define	REG_RD_ADDR_gio_rw_pb_byte3_dout 80

#define	REG_WR_ADDR_gio_rw_pb_byte3_dout 80

#define	REG_RD_ADDR_gio_rw_pb_byte3_oe 84

#define	REG_WR_ADDR_gio_rw_pb_byte3_oe 84

#define	REG_RD_ADDR_gio_r_pc_din 88

#define	REG_RD_ADDR_gio_rw_pc_dout 92

#define	REG_WR_ADDR_gio_rw_pc_dout 92

#define	REG_RD_ADDR_gio_rw_pc_oe 96

#define	REG_WR_ADDR_gio_rw_pc_oe 96

#define	REG_RD_ADDR_gio_rw_pc_byte0_dout 100

#define	REG_WR_ADDR_gio_rw_pc_byte0_dout 100

#define	REG_RD_ADDR_gio_rw_pc_byte0_oe 104

#define	REG_WR_ADDR_gio_rw_pc_byte0_oe 104

#define	REG_RD_ADDR_gio_rw_pc_byte1_dout 108

#define	REG_WR_ADDR_gio_rw_pc_byte1_dout 108

#define	REG_RD_ADDR_gio_rw_pc_byte1_oe 112

#define	REG_WR_ADDR_gio_rw_pc_byte1_oe 112

#define	REG_RD_ADDR_gio_r_pd_din 116

#define	REG_RD_ADDR_gio_rw_intr_cfg 120

#define	REG_WR_ADDR_gio_rw_intr_cfg 120

#define	REG_RD_ADDR_gio_rw_intr_pins 124

#define	REG_WR_ADDR_gio_rw_intr_pins 124

#define	REG_RD_ADDR_gio_rw_intr_mask 128

#define	REG_WR_ADDR_gio_rw_intr_mask 128

#define	REG_RD_ADDR_gio_rw_ack_intr 132

#define	REG_WR_ADDR_gio_rw_ack_intr 132

#define	REG_RD_ADDR_gio_r_intr 136

#define	REG_RD_ADDR_gio_r_masked_intr 140

#define	REG_RD_ADDR_gio_rw_i2c0_start 144

#define	REG_WR_ADDR_gio_rw_i2c0_start 144

#define	REG_RD_ADDR_gio_rw_i2c0_cfg 148

#define	REG_WR_ADDR_gio_rw_i2c0_cfg 148

#define	REG_RD_ADDR_gio_rw_i2c0_ctrl 152

#define	REG_WR_ADDR_gio_rw_i2c0_ctrl 152

#define	REG_RD_ADDR_gio_rw_i2c0_data 156

#define	REG_WR_ADDR_gio_rw_i2c0_data 156

#define	REG_RD_ADDR_gio_rw_i2c0_data2 160

#define	REG_WR_ADDR_gio_rw_i2c0_data2 160

#define	REG_RD_ADDR_gio_rw_i2c1_start 164

#define	REG_WR_ADDR_gio_rw_i2c1_start 164

#define	REG_RD_ADDR_gio_rw_i2c1_cfg 168

#define	REG_WR_ADDR_gio_rw_i2c1_cfg 168

#define	REG_RD_ADDR_gio_rw_i2c1_ctrl 172

#define	REG_WR_ADDR_gio_rw_i2c1_ctrl 172

#define	REG_RD_ADDR_gio_rw_i2c1_data 176

#define	REG_WR_ADDR_gio_rw_i2c1_data 176

#define	REG_RD_ADDR_gio_rw_i2c1_data2 180

#define	REG_WR_ADDR_gio_rw_i2c1_data2 180

#define	REG_RD_ADDR_gio_r_ppwm_stat 184

#define	REG_RD_ADDR_gio_rw_ppwm_data 188

#define	REG_WR_ADDR_gio_rw_ppwm_data 188

#define	REG_RD_ADDR_gio_rw_pwm0_ctrl 192

#define	REG_WR_ADDR_gio_rw_pwm0_ctrl 192

#define	REG_RD_ADDR_gio_rw_pwm0_var 196

#define	REG_WR_ADDR_gio_rw_pwm0_var 196

#define	REG_RD_ADDR_gio_rw_pwm0_data 200

#define	REG_WR_ADDR_gio_rw_pwm0_data 200

#define	REG_RD_ADDR_gio_rw_pwm1_ctrl 204

#define	REG_WR_ADDR_gio_rw_pwm1_ctrl 204

#define	REG_RD_ADDR_gio_rw_pwm1_var 208

#define	REG_WR_ADDR_gio_rw_pwm1_var 208

#define	REG_RD_ADDR_gio_rw_pwm1_data 212

#define	REG_WR_ADDR_gio_rw_pwm1_data 212

#define	REG_RD_ADDR_gio_rw_pwm2_ctrl 216

#define	REG_WR_ADDR_gio_rw_pwm2_ctrl 216

#define	REG_RD_ADDR_gio_rw_pwm2_var 220

#define	REG_WR_ADDR_gio_rw_pwm2_var 220

#define	REG_RD_ADDR_gio_rw_pwm2_data 224

#define	REG_WR_ADDR_gio_rw_pwm2_data 224

#define	REG_RD_ADDR_gio_rw_pwm_in_cfg 228

#define	REG_WR_ADDR_gio_rw_pwm_in_cfg 228

#define	REG_RD_ADDR_gio_r_pwm_in_lo 232

#define	REG_RD_ADDR_gio_r_pwm_in_hi 236

#define	REG_RD_ADDR_gio_r_pwm_in_cnt 240

Enumerations
enum	{ regk_gio_anyedge = 0x00000007, regk_gio_f100k = 0x00000000, regk_gio_f1562 = 0x00000000, regk_gio_f195 = 0x00000003, regk_gio_f1m = 0x00000002, regk_gio_f390 = 0x00000002, regk_gio_f400k = 0x00000001, regk_gio_f5m = 0x00000003, regk_gio_f781 = 0x00000001, regk_gio_hi = 0x00000001, regk_gio_in = 0x00000000, regk_gio_intr_pa0 = 0x00000000, regk_gio_intr_pa1 = 0x00000000, regk_gio_intr_pa10 = 0x00000001, regk_gio_intr_pa11 = 0x00000001, regk_gio_intr_pa12 = 0x00000001, regk_gio_intr_pa13 = 0x00000001, regk_gio_intr_pa14 = 0x00000001, regk_gio_intr_pa15 = 0x00000001, regk_gio_intr_pa16 = 0x00000002, regk_gio_intr_pa17 = 0x00000002, regk_gio_intr_pa18 = 0x00000002, regk_gio_intr_pa19 = 0x00000002, regk_gio_intr_pa2 = 0x00000000, regk_gio_intr_pa20 = 0x00000002, regk_gio_intr_pa21 = 0x00000002, regk_gio_intr_pa22 = 0x00000002, regk_gio_intr_pa23 = 0x00000002, regk_gio_intr_pa24 = 0x00000003, regk_gio_intr_pa25 = 0x00000003, regk_gio_intr_pa26 = 0x00000003, regk_gio_intr_pa27 = 0x00000003, regk_gio_intr_pa28 = 0x00000003, regk_gio_intr_pa29 = 0x00000003, regk_gio_intr_pa3 = 0x00000000, regk_gio_intr_pa30 = 0x00000003, regk_gio_intr_pa31 = 0x00000003, regk_gio_intr_pa4 = 0x00000000, regk_gio_intr_pa5 = 0x00000000, regk_gio_intr_pa6 = 0x00000000, regk_gio_intr_pa7 = 0x00000000, regk_gio_intr_pa8 = 0x00000001, regk_gio_intr_pa9 = 0x00000001, regk_gio_intr_pb0 = 0x00000004, regk_gio_intr_pb1 = 0x00000004, regk_gio_intr_pb10 = 0x00000005, regk_gio_intr_pb11 = 0x00000005, regk_gio_intr_pb12 = 0x00000005, regk_gio_intr_pb13 = 0x00000005, regk_gio_intr_pb14 = 0x00000005, regk_gio_intr_pb15 = 0x00000005, regk_gio_intr_pb16 = 0x00000006, regk_gio_intr_pb17 = 0x00000006, regk_gio_intr_pb18 = 0x00000006, regk_gio_intr_pb19 = 0x00000006, regk_gio_intr_pb2 = 0x00000004, regk_gio_intr_pb20 = 0x00000006, regk_gio_intr_pb21 = 0x00000006, regk_gio_intr_pb22 = 0x00000006, regk_gio_intr_pb23 = 0x00000006, regk_gio_intr_pb24 = 0x00000007, regk_gio_intr_pb25 = 0x00000007, regk_gio_intr_pb26 = 0x00000007, regk_gio_intr_pb27 = 0x00000007, regk_gio_intr_pb28 = 0x00000007, regk_gio_intr_pb29 = 0x00000007, regk_gio_intr_pb3 = 0x00000004, regk_gio_intr_pb30 = 0x00000007, regk_gio_intr_pb31 = 0x00000007, regk_gio_intr_pb4 = 0x00000004, regk_gio_intr_pb5 = 0x00000004, regk_gio_intr_pb6 = 0x00000004, regk_gio_intr_pb7 = 0x00000004, regk_gio_intr_pb8 = 0x00000005, regk_gio_intr_pb9 = 0x00000005, regk_gio_intr_pc0 = 0x00000008, regk_gio_intr_pc1 = 0x00000008, regk_gio_intr_pc10 = 0x00000009, regk_gio_intr_pc11 = 0x00000009, regk_gio_intr_pc12 = 0x00000009, regk_gio_intr_pc13 = 0x00000009, regk_gio_intr_pc14 = 0x00000009, regk_gio_intr_pc15 = 0x00000009, regk_gio_intr_pc2 = 0x00000008, regk_gio_intr_pc3 = 0x00000008, regk_gio_intr_pc4 = 0x00000008, regk_gio_intr_pc5 = 0x00000008, regk_gio_intr_pc6 = 0x00000008, regk_gio_intr_pc7 = 0x00000008, regk_gio_intr_pc8 = 0x00000009, regk_gio_intr_pc9 = 0x00000009, regk_gio_intr_pd0 = 0x0000000c, regk_gio_intr_pd1 = 0x0000000c, regk_gio_intr_pd10 = 0x0000000d, regk_gio_intr_pd11 = 0x0000000d, regk_gio_intr_pd12 = 0x0000000d, regk_gio_intr_pd13 = 0x0000000d, regk_gio_intr_pd14 = 0x0000000d, regk_gio_intr_pd15 = 0x0000000d, regk_gio_intr_pd16 = 0x0000000e, regk_gio_intr_pd17 = 0x0000000e, regk_gio_intr_pd18 = 0x0000000e, regk_gio_intr_pd19 = 0x0000000e, regk_gio_intr_pd2 = 0x0000000c, regk_gio_intr_pd20 = 0x0000000e, regk_gio_intr_pd21 = 0x0000000e, regk_gio_intr_pd22 = 0x0000000e, regk_gio_intr_pd23 = 0x0000000e, regk_gio_intr_pd24 = 0x0000000f, regk_gio_intr_pd25 = 0x0000000f, regk_gio_intr_pd26 = 0x0000000f, regk_gio_intr_pd27 = 0x0000000f, regk_gio_intr_pd28 = 0x0000000f, regk_gio_intr_pd29 = 0x0000000f, regk_gio_intr_pd3 = 0x0000000c, regk_gio_intr_pd30 = 0x0000000f, regk_gio_intr_pd31 = 0x0000000f, regk_gio_intr_pd4 = 0x0000000c, regk_gio_intr_pd5 = 0x0000000c, regk_gio_intr_pd6 = 0x0000000c, regk_gio_intr_pd7 = 0x0000000c, regk_gio_intr_pd8 = 0x0000000d, regk_gio_intr_pd9 = 0x0000000d, regk_gio_lo = 0x00000002, regk_gio_lsb = 0x00000000, regk_gio_msb = 0x00000001, regk_gio_negedge = 0x00000006, regk_gio_no = 0x00000000, regk_gio_no_switch = 0x0000003f, regk_gio_none = 0x00000007, regk_gio_off = 0x00000000, regk_gio_opendrain = 0x00000000, regk_gio_out = 0x00000001, regk_gio_posedge = 0x00000005, regk_gio_pwm_hfp = 0x00000002, regk_gio_pwm_pa0 = 0x00000001, regk_gio_pwm_pa19 = 0x00000004, regk_gio_pwm_pa6 = 0x00000002, regk_gio_pwm_pa7 = 0x00000003, regk_gio_pwm_pb26 = 0x00000005, regk_gio_pwm_pd23 = 0x00000006, regk_gio_pwm_pd31 = 0x00000007, regk_gio_pwm_std = 0x00000001, regk_gio_pwm_var = 0x00000003, regk_gio_rw_i2c0_cfg_default = 0x00000020, regk_gio_rw_i2c0_ctrl_default = 0x00010000, regk_gio_rw_i2c0_start_default = 0x00000000, regk_gio_rw_i2c1_cfg_default = 0x00000aa0, regk_gio_rw_i2c1_ctrl_default = 0x00010000, regk_gio_rw_i2c1_start_default = 0x00000000, regk_gio_rw_intr_cfg_default = 0x00000000, regk_gio_rw_intr_mask_default = 0x00000000, regk_gio_rw_pa_oe_default = 0x00000000, regk_gio_rw_pb_oe_default = 0x00000000, regk_gio_rw_pc_oe_default = 0x00000000, regk_gio_rw_ppwm_data_default = 0x00000000, regk_gio_rw_pwm0_ctrl_default = 0x00000000, regk_gio_rw_pwm1_ctrl_default = 0x00000000, regk_gio_rw_pwm2_ctrl_default = 0x00000000, regk_gio_rw_pwm_in_cfg_default = 0x00000000, regk_gio_sda0 = 0x00000000, regk_gio_sda1 = 0x00000001, regk_gio_sda2 = 0x00000002, regk_gio_sda3 = 0x00000003, regk_gio_sen = 0x00000000, regk_gio_set = 0x00000003, regk_gio_yes = 0x00000001 }

Macro Definition Documentation

#define REG_ADDR	(	scope,
		inst,
		reg
	)	( (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 72 of file gio_defs.h.

#define REG_ADDR_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

( (inst) + REG_RD_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg )

Definition at line 77 of file gio_defs.h.

#define reg_page_size 8192

Definition at line 68 of file gio_defs.h.

#define REG_RD	(	scope,
		inst,
		reg
	)

Value:

REG_READ( reg_##scope##_##reg, \

(inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 15 of file gio_defs.h.

#define REG_RD_ADDR_gio_r_intr 136

Definition at line 390 of file gio_defs.h.

#define REG_RD_ADDR_gio_r_masked_intr 140

Definition at line 406 of file gio_defs.h.

#define REG_RD_ADDR_gio_r_pa_din 0

Definition at line 88 of file gio_defs.h.

#define REG_RD_ADDR_gio_r_pb_din 44

Definition at line 172 of file gio_defs.h.

#define REG_RD_ADDR_gio_r_pc_din 88

Definition at line 257 of file gio_defs.h.

#define REG_RD_ADDR_gio_r_pd_din 116

Definition at line 311 of file gio_defs.h.

#define REG_RD_ADDR_gio_r_ppwm_stat 184

Definition at line 549 of file gio_defs.h.

#define REG_RD_ADDR_gio_r_pwm_in_cnt 240

Definition at line 664 of file gio_defs.h.

#define REG_RD_ADDR_gio_r_pwm_in_hi 236

Definition at line 658 of file gio_defs.h.

#define REG_RD_ADDR_gio_r_pwm_in_lo 232

Definition at line 652 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_ack_intr 132

Definition at line 373 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_i2c0_cfg 148

Definition at line 426 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152

Definition at line 447 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_i2c0_data 156

Definition at line 457 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_i2c0_data2 160

Definition at line 468 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_i2c0_start 144

Definition at line 413 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_i2c1_cfg 168

Definition at line 499 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172

Definition at line 520 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_i2c1_data 176

Definition at line 530 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_i2c1_data2 180

Definition at line 541 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_i2c1_start 164

Definition at line 476 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_intr_cfg 120

Definition at line 325 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_intr_mask 128

Definition at line 356 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_intr_pins 124

Definition at line 339 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12

Definition at line 109 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16

Definition at line 117 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20

Definition at line 125 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24

Definition at line 133 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28

Definition at line 141 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32

Definition at line 149 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36

Definition at line 157 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40

Definition at line 165 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pa_dout 4

Definition at line 94 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pa_oe 8

Definition at line 101 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56

Definition at line 193 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60

Definition at line 201 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64

Definition at line 209 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68

Definition at line 217 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72

Definition at line 225 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76

Definition at line 233 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80

Definition at line 241 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84

Definition at line 249 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pb_dout 48

Definition at line 178 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pb_oe 52

Definition at line 185 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100

Definition at line 280 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104

Definition at line 288 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108

Definition at line 296 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112

Definition at line 304 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pc_dout 92

Definition at line 264 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pc_oe 96

Definition at line 272 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_ppwm_data 188

Definition at line 556 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192

Definition at line 566 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pwm0_data 200

Definition at line 583 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pwm0_var 196

Definition at line 575 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204

Definition at line 593 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pwm1_data 212

Definition at line 610 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pwm1_var 208

Definition at line 602 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216

Definition at line 620 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pwm2_data 224

Definition at line 637 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pwm2_var 220

Definition at line 629 of file gio_defs.h.

#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228

Definition at line 645 of file gio_defs.h.

#define REG_RD_INT	(	scope,
		inst,
		reg
	)	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 41 of file gio_defs.h.

#define REG_RD_INT_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg )

Definition at line 51 of file gio_defs.h.

#define REG_RD_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 27 of file gio_defs.h.

#define REG_TYPE_CONV	(	type,
		orgtype,
		val
	)	( { union { orgtype o; type n; } r; r.o = val; r.n; } )

Definition at line 63 of file gio_defs.h.

#define REG_WR	(	scope,
		inst,
		reg,
		val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \

(inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 21 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_ack_intr 132

Definition at line 374 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_i2c0_cfg 148

Definition at line 427 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152

Definition at line 448 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_i2c0_data 156

Definition at line 458 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_i2c0_data2 160

Definition at line 469 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_i2c0_start 144

Definition at line 414 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_i2c1_cfg 168

Definition at line 500 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172

Definition at line 521 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_i2c1_data 176

Definition at line 531 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_i2c1_data2 180

Definition at line 542 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_i2c1_start 164

Definition at line 477 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_intr_cfg 120

Definition at line 326 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_intr_mask 128

Definition at line 357 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_intr_pins 124

Definition at line 340 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12

Definition at line 110 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16

Definition at line 118 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20

Definition at line 126 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24

Definition at line 134 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28

Definition at line 142 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32

Definition at line 150 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36

Definition at line 158 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40

Definition at line 166 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pa_dout 4

Definition at line 95 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pa_oe 8

Definition at line 102 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56

Definition at line 194 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60

Definition at line 202 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64

Definition at line 210 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68

Definition at line 218 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72

Definition at line 226 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76

Definition at line 234 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80

Definition at line 242 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84

Definition at line 250 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pb_dout 48

Definition at line 179 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pb_oe 52

Definition at line 186 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100

Definition at line 281 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104

Definition at line 289 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108

Definition at line 297 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112

Definition at line 305 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pc_dout 92

Definition at line 265 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pc_oe 96

Definition at line 273 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_ppwm_data 188

Definition at line 557 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192

Definition at line 567 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pwm0_data 200

Definition at line 584 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pwm0_var 196

Definition at line 576 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204

Definition at line 594 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pwm1_data 212

Definition at line 611 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pwm1_var 208

Definition at line 603 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216

Definition at line 621 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pwm2_data 224

Definition at line 638 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pwm2_var 220

Definition at line 630 of file gio_defs.h.

#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228

Definition at line 646 of file gio_defs.h.

#define REG_WR_INT	(	scope,
		inst,
		reg,
		val
	)	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 46 of file gio_defs.h.

#define REG_WR_INT_VECT	(	scope,
		inst,
		reg,
		index,
		val
	)

Value:

REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg, (val) )

Definition at line 57 of file gio_defs.h.

#define REG_WR_VECT	(	scope,
		inst,
		reg,
		index,
		val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 34 of file gio_defs.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

regk_gio_anyedge
regk_gio_f100k
regk_gio_f1562
regk_gio_f195
regk_gio_f1m
regk_gio_f390
regk_gio_f400k
regk_gio_f5m
regk_gio_f781
regk_gio_hi
regk_gio_in
regk_gio_intr_pa0
regk_gio_intr_pa1
regk_gio_intr_pa10
regk_gio_intr_pa11
regk_gio_intr_pa12
regk_gio_intr_pa13
regk_gio_intr_pa14
regk_gio_intr_pa15
regk_gio_intr_pa16
regk_gio_intr_pa17
regk_gio_intr_pa18
regk_gio_intr_pa19
regk_gio_intr_pa2
regk_gio_intr_pa20
regk_gio_intr_pa21
regk_gio_intr_pa22
regk_gio_intr_pa23
regk_gio_intr_pa24
regk_gio_intr_pa25
regk_gio_intr_pa26
regk_gio_intr_pa27
regk_gio_intr_pa28
regk_gio_intr_pa29
regk_gio_intr_pa3
regk_gio_intr_pa30
regk_gio_intr_pa31
regk_gio_intr_pa4
regk_gio_intr_pa5
regk_gio_intr_pa6
regk_gio_intr_pa7
regk_gio_intr_pa8
regk_gio_intr_pa9
regk_gio_intr_pb0
regk_gio_intr_pb1
regk_gio_intr_pb10
regk_gio_intr_pb11
regk_gio_intr_pb12
regk_gio_intr_pb13
regk_gio_intr_pb14
regk_gio_intr_pb15
regk_gio_intr_pb16
regk_gio_intr_pb17
regk_gio_intr_pb18
regk_gio_intr_pb19
regk_gio_intr_pb2
regk_gio_intr_pb20
regk_gio_intr_pb21
regk_gio_intr_pb22
regk_gio_intr_pb23
regk_gio_intr_pb24
regk_gio_intr_pb25
regk_gio_intr_pb26
regk_gio_intr_pb27
regk_gio_intr_pb28
regk_gio_intr_pb29
regk_gio_intr_pb3
regk_gio_intr_pb30
regk_gio_intr_pb31
regk_gio_intr_pb4
regk_gio_intr_pb5
regk_gio_intr_pb6
regk_gio_intr_pb7
regk_gio_intr_pb8
regk_gio_intr_pb9
regk_gio_intr_pc0
regk_gio_intr_pc1
regk_gio_intr_pc10
regk_gio_intr_pc11
regk_gio_intr_pc12
regk_gio_intr_pc13
regk_gio_intr_pc14
regk_gio_intr_pc15
regk_gio_intr_pc2
regk_gio_intr_pc3
regk_gio_intr_pc4
regk_gio_intr_pc5
regk_gio_intr_pc6
regk_gio_intr_pc7
regk_gio_intr_pc8
regk_gio_intr_pc9
regk_gio_intr_pd0
regk_gio_intr_pd1
regk_gio_intr_pd10
regk_gio_intr_pd11
regk_gio_intr_pd12
regk_gio_intr_pd13
regk_gio_intr_pd14
regk_gio_intr_pd15
regk_gio_intr_pd16
regk_gio_intr_pd17
regk_gio_intr_pd18
regk_gio_intr_pd19
regk_gio_intr_pd2
regk_gio_intr_pd20
regk_gio_intr_pd21
regk_gio_intr_pd22
regk_gio_intr_pd23
regk_gio_intr_pd24
regk_gio_intr_pd25
regk_gio_intr_pd26
regk_gio_intr_pd27
regk_gio_intr_pd28
regk_gio_intr_pd29
regk_gio_intr_pd3
regk_gio_intr_pd30
regk_gio_intr_pd31
regk_gio_intr_pd4
regk_gio_intr_pd5
regk_gio_intr_pd6
regk_gio_intr_pd7
regk_gio_intr_pd8
regk_gio_intr_pd9
regk_gio_lo
regk_gio_lsb
regk_gio_msb
regk_gio_negedge
regk_gio_no
regk_gio_no_switch
regk_gio_none
regk_gio_off
regk_gio_opendrain
regk_gio_out
regk_gio_posedge
regk_gio_pwm_hfp
regk_gio_pwm_pa0
regk_gio_pwm_pa19
regk_gio_pwm_pa6
regk_gio_pwm_pa7
regk_gio_pwm_pb26
regk_gio_pwm_pd23
regk_gio_pwm_pd31
regk_gio_pwm_std
regk_gio_pwm_var
regk_gio_rw_i2c0_cfg_default
regk_gio_rw_i2c0_ctrl_default
regk_gio_rw_i2c0_start_default
regk_gio_rw_i2c1_cfg_default
regk_gio_rw_i2c1_ctrl_default
regk_gio_rw_i2c1_start_default
regk_gio_rw_intr_cfg_default
regk_gio_rw_intr_mask_default
regk_gio_rw_pa_oe_default
regk_gio_rw_pb_oe_default
regk_gio_rw_pc_oe_default
regk_gio_rw_ppwm_data_default
regk_gio_rw_pwm0_ctrl_default
regk_gio_rw_pwm1_ctrl_default
regk_gio_rw_pwm2_ctrl_default
regk_gio_rw_pwm_in_cfg_default
regk_gio_sda0
regk_gio_sda1
regk_gio_sda2
regk_gio_sda3
regk_gio_sen
regk_gio_set
regk_gio_yes

Definition at line 668 of file gio_defs.h.

Data Structures

Macros

Enumerations

Macro Definition Documentation

Enumeration Type Documentation