Data Structures
struct	reg_iop_sw_cfg_rw_crc_par_owner

struct	reg_iop_sw_cfg_rw_dmc_in_owner

struct	reg_iop_sw_cfg_rw_dmc_out_owner

struct	reg_iop_sw_cfg_rw_fifo_in_owner

struct	reg_iop_sw_cfg_rw_fifo_in_extra_owner

struct	reg_iop_sw_cfg_rw_fifo_out_owner

struct	reg_iop_sw_cfg_rw_fifo_out_extra_owner

struct	reg_iop_sw_cfg_rw_sap_in_owner

struct	reg_iop_sw_cfg_rw_sap_out_owner

struct	reg_iop_sw_cfg_rw_scrc_in_owner

struct	reg_iop_sw_cfg_rw_scrc_out_owner

struct	reg_iop_sw_cfg_rw_spu_owner

struct	reg_iop_sw_cfg_rw_timer_grp0_owner

struct	reg_iop_sw_cfg_rw_timer_grp1_owner

struct	reg_iop_sw_cfg_rw_trigger_grp0_owner

struct	reg_iop_sw_cfg_rw_trigger_grp1_owner

struct	reg_iop_sw_cfg_rw_trigger_grp2_owner

struct	reg_iop_sw_cfg_rw_trigger_grp3_owner

struct	reg_iop_sw_cfg_rw_trigger_grp4_owner

struct	reg_iop_sw_cfg_rw_trigger_grp5_owner

struct	reg_iop_sw_cfg_rw_trigger_grp6_owner

struct	reg_iop_sw_cfg_rw_trigger_grp7_owner

struct	reg_iop_sw_cfg_rw_bus_mask

struct	reg_iop_sw_cfg_rw_bus_oe_mask

struct	reg_iop_sw_cfg_rw_gio_mask

struct	reg_iop_sw_cfg_rw_gio_oe_mask

struct	reg_iop_sw_cfg_rw_pinmapping

struct	reg_iop_sw_cfg_rw_bus_out_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp0_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp1_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp2_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp3_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp4_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp5_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp6_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp7_cfg

struct	reg_iop_sw_cfg_rw_spu_cfg

struct	reg_iop_sw_cfg_rw_timer_grp0_cfg

struct	reg_iop_sw_cfg_rw_timer_grp1_cfg

struct	reg_iop_sw_cfg_rw_trigger_grps_cfg

struct	reg_iop_sw_cfg_rw_pdp_cfg

struct	reg_iop_sw_cfg_rw_sdp_cfg

Macros
#define	REG_RD(scope, inst, reg)

#define	REG_WR(scope, inst, reg, val)

#define	REG_RD_VECT(scope, inst, reg, index)

#define	REG_WR_VECT(scope, inst, reg, index, val)

#define	REG_RD_INT(scope, inst, reg) REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

#define	REG_WR_INT(scope, inst, reg, val) REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

#define	REG_RD_INT_VECT(scope, inst, reg, index)

#define	REG_WR_INT_VECT(scope, inst, reg, index, val)

#define	REG_TYPE_CONV(type, orgtype, val) ( { union { orgtype o; type n; } r; r.o = val; r.n; } )

#define	reg_page_size 8192

#define	REG_ADDR(scope, inst, reg) ( (inst) + REG_RD_ADDR_##scope##_##reg )

#define	REG_ADDR_VECT(scope, inst, reg, index)

#define	REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0

#define	REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0

#define	REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4

#define	REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4

#define	REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8

#define	REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24

#define	REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28

#define	REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28

#define	REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32

#define	REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32

#define	REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36

#define	REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36

#define	REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40

#define	REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40

#define	REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44

#define	REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84

#define	REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88

#define	REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88

#define	REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92

#define	REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100

#define	REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104

#define	REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104

#define	REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108

#define	REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140

#define	REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144

#define	REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156

#define	REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160

#define	REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160

#define	REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164

#define	REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164

Enumerations
enum	{ regk_iop_sw_cfg_a = 0x00000001, regk_iop_sw_cfg_b = 0x00000002, regk_iop_sw_cfg_bus = 0x00000000, regk_iop_sw_cfg_bus_rot16 = 0x00000002, regk_iop_sw_cfg_bus_rot24 = 0x00000003, regk_iop_sw_cfg_bus_rot8 = 0x00000001, regk_iop_sw_cfg_clk12 = 0x00000000, regk_iop_sw_cfg_cpu = 0x00000000, regk_iop_sw_cfg_gated_clk0 = 0x0000000e, regk_iop_sw_cfg_gated_clk1 = 0x0000000f, regk_iop_sw_cfg_gio0 = 0x00000004, regk_iop_sw_cfg_gio1 = 0x00000001, regk_iop_sw_cfg_gio2 = 0x00000005, regk_iop_sw_cfg_gio3 = 0x00000002, regk_iop_sw_cfg_gio4 = 0x00000006, regk_iop_sw_cfg_gio5 = 0x00000003, regk_iop_sw_cfg_gio6 = 0x00000007, regk_iop_sw_cfg_gio7 = 0x00000004, regk_iop_sw_cfg_gio_in18 = 0x00000002, regk_iop_sw_cfg_gio_in19 = 0x00000003, regk_iop_sw_cfg_gio_in20 = 0x00000004, regk_iop_sw_cfg_gio_in21 = 0x00000005, regk_iop_sw_cfg_gio_in26 = 0x00000006, regk_iop_sw_cfg_gio_in27 = 0x00000007, regk_iop_sw_cfg_gio_in4 = 0x00000000, regk_iop_sw_cfg_gio_in5 = 0x00000001, regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, regk_iop_sw_cfg_mpu = 0x00000001, regk_iop_sw_cfg_none = 0x00000000, regk_iop_sw_cfg_pdp_out = 0x00000001, regk_iop_sw_cfg_pdp_out_hi = 0x00000001, regk_iop_sw_cfg_pdp_out_lo = 0x00000000, regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, regk_iop_sw_cfg_sdp_out = 0x00000004, regk_iop_sw_cfg_size16 = 0x00000002, regk_iop_sw_cfg_size24 = 0x00000003, regk_iop_sw_cfg_size32 = 0x00000004, regk_iop_sw_cfg_size8 = 0x00000001, regk_iop_sw_cfg_spu = 0x00000002, regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, regk_iop_sw_cfg_spu_g0 = 0x00000007, regk_iop_sw_cfg_spu_g1 = 0x00000007, regk_iop_sw_cfg_spu_g2 = 0x00000007, regk_iop_sw_cfg_spu_g3 = 0x00000007, regk_iop_sw_cfg_spu_g4 = 0x00000007, regk_iop_sw_cfg_spu_g5 = 0x00000007, regk_iop_sw_cfg_spu_g6 = 0x00000007, regk_iop_sw_cfg_spu_g7 = 0x00000007, regk_iop_sw_cfg_spu_gio0 = 0x00000000, regk_iop_sw_cfg_spu_gio1 = 0x00000001, regk_iop_sw_cfg_spu_gio5 = 0x00000005, regk_iop_sw_cfg_spu_gio6 = 0x00000006, regk_iop_sw_cfg_spu_gio7 = 0x00000007, regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, regk_iop_sw_cfg_spu_gioout0 = 0x00000000, regk_iop_sw_cfg_spu_gioout1 = 0x00000000, regk_iop_sw_cfg_spu_gioout10 = 0x00000007, regk_iop_sw_cfg_spu_gioout11 = 0x00000007, regk_iop_sw_cfg_spu_gioout12 = 0x00000007, regk_iop_sw_cfg_spu_gioout13 = 0x00000007, regk_iop_sw_cfg_spu_gioout14 = 0x00000007, regk_iop_sw_cfg_spu_gioout15 = 0x00000007, regk_iop_sw_cfg_spu_gioout16 = 0x00000007, regk_iop_sw_cfg_spu_gioout17 = 0x00000007, regk_iop_sw_cfg_spu_gioout18 = 0x00000007, regk_iop_sw_cfg_spu_gioout19 = 0x00000007, regk_iop_sw_cfg_spu_gioout2 = 0x00000001, regk_iop_sw_cfg_spu_gioout20 = 0x00000007, regk_iop_sw_cfg_spu_gioout21 = 0x00000007, regk_iop_sw_cfg_spu_gioout22 = 0x00000007, regk_iop_sw_cfg_spu_gioout23 = 0x00000007, regk_iop_sw_cfg_spu_gioout24 = 0x00000007, regk_iop_sw_cfg_spu_gioout25 = 0x00000007, regk_iop_sw_cfg_spu_gioout26 = 0x00000007, regk_iop_sw_cfg_spu_gioout27 = 0x00000007, regk_iop_sw_cfg_spu_gioout28 = 0x00000007, regk_iop_sw_cfg_spu_gioout29 = 0x00000007, regk_iop_sw_cfg_spu_gioout3 = 0x00000001, regk_iop_sw_cfg_spu_gioout30 = 0x00000007, regk_iop_sw_cfg_spu_gioout31 = 0x00000007, regk_iop_sw_cfg_spu_gioout4 = 0x00000002, regk_iop_sw_cfg_spu_gioout5 = 0x00000002, regk_iop_sw_cfg_spu_gioout6 = 0x00000003, regk_iop_sw_cfg_spu_gioout7 = 0x00000003, regk_iop_sw_cfg_spu_gioout8 = 0x00000007, regk_iop_sw_cfg_spu_gioout9 = 0x00000007, regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, regk_iop_sw_cfg_timer_grp0 = 0x00000000, regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, regk_iop_sw_cfg_timer_grp1 = 0x00000000, regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, regk_iop_sw_cfg_trig0_0 = 0x00000000, regk_iop_sw_cfg_trig0_1 = 0x00000000, regk_iop_sw_cfg_trig0_2 = 0x00000000, regk_iop_sw_cfg_trig0_3 = 0x00000000, regk_iop_sw_cfg_trig1_0 = 0x00000000, regk_iop_sw_cfg_trig1_1 = 0x00000000, regk_iop_sw_cfg_trig1_2 = 0x00000000, regk_iop_sw_cfg_trig1_3 = 0x00000000, regk_iop_sw_cfg_trig2_0 = 0x00000001, regk_iop_sw_cfg_trig2_1 = 0x00000001, regk_iop_sw_cfg_trig2_2 = 0x00000001, regk_iop_sw_cfg_trig2_3 = 0x00000001, regk_iop_sw_cfg_trig3_0 = 0x00000001, regk_iop_sw_cfg_trig3_1 = 0x00000001, regk_iop_sw_cfg_trig3_2 = 0x00000001, regk_iop_sw_cfg_trig3_3 = 0x00000001, regk_iop_sw_cfg_trig4_0 = 0x00000002, regk_iop_sw_cfg_trig4_1 = 0x00000002, regk_iop_sw_cfg_trig4_2 = 0x00000002, regk_iop_sw_cfg_trig4_3 = 0x00000002, regk_iop_sw_cfg_trig5_0 = 0x00000002, regk_iop_sw_cfg_trig5_1 = 0x00000002, regk_iop_sw_cfg_trig5_2 = 0x00000002, regk_iop_sw_cfg_trig5_3 = 0x00000002, regk_iop_sw_cfg_trig6_0 = 0x00000003, regk_iop_sw_cfg_trig6_1 = 0x00000003, regk_iop_sw_cfg_trig6_2 = 0x00000003, regk_iop_sw_cfg_trig6_3 = 0x00000003, regk_iop_sw_cfg_trig7_0 = 0x00000003, regk_iop_sw_cfg_trig7_1 = 0x00000003, regk_iop_sw_cfg_trig7_2 = 0x00000003, regk_iop_sw_cfg_trig7_3 = 0x00000003 }

Macro Definition Documentation

#define REG_ADDR	(	scope,
		inst,
		reg
	)	( (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 72 of file iop_sw_cfg_defs.h.

#define REG_ADDR_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

( (inst) + REG_RD_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg )

Definition at line 77 of file iop_sw_cfg_defs.h.

#define reg_page_size 8192

Definition at line 68 of file iop_sw_cfg_defs.h.

#define REG_RD	(	scope,
		inst,
		reg
	)

Value:

REG_READ( reg_##scope##_##reg, \

(inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 15 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88

Definition at line 267 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92

Definition at line 278 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108

Definition at line 322 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0

Definition at line 89 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4

Definition at line 97 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8

Definition at line 105 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16

Definition at line 121 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12

Definition at line 113 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24

Definition at line 137 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20

Definition at line 129 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96

Definition at line 285 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100

Definition at line 292 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112

Definition at line 337 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116

Definition at line 352 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120

Definition at line 367 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124

Definition at line 382 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128

Definition at line 397 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132

Definition at line 412 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136

Definition at line 427 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140

Definition at line 442 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160

Definition at line 518 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104

Definition at line 311 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28

Definition at line 145 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32

Definition at line 153 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36

Definition at line 161 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40

Definition at line 169 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164

Definition at line 529 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144

Definition at line 451 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44

Definition at line 177 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148

Definition at line 467 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48

Definition at line 185 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152

Definition at line 483 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52

Definition at line 193 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56

Definition at line 201 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60

Definition at line 209 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64

Definition at line 217 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68

Definition at line 225 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72

Definition at line 233 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76

Definition at line 241 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80

Definition at line 249 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84

Definition at line 257 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156

Definition at line 506 of file iop_sw_cfg_defs.h.

#define REG_RD_INT	(	scope,
		inst,
		reg
	)	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 41 of file iop_sw_cfg_defs.h.

#define REG_RD_INT_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg )

Definition at line 51 of file iop_sw_cfg_defs.h.

#define REG_RD_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 27 of file iop_sw_cfg_defs.h.

#define REG_TYPE_CONV	(	type,
		orgtype,
		val
	)	( { union { orgtype o; type n; } r; r.o = val; r.n; } )

Definition at line 63 of file iop_sw_cfg_defs.h.

#define REG_WR	(	scope,
		inst,
		reg,
		val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \

(inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 21 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88

Definition at line 268 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92

Definition at line 279 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108

Definition at line 323 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0

Definition at line 90 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4

Definition at line 98 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8

Definition at line 106 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16

Definition at line 122 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12

Definition at line 114 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24

Definition at line 138 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20

Definition at line 130 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96

Definition at line 286 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100

Definition at line 293 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112

Definition at line 338 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116

Definition at line 353 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120

Definition at line 368 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124

Definition at line 383 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128

Definition at line 398 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132

Definition at line 413 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136

Definition at line 428 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140

Definition at line 443 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160

Definition at line 519 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104

Definition at line 312 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28

Definition at line 146 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32

Definition at line 154 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36

Definition at line 162 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40

Definition at line 170 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164

Definition at line 530 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144

Definition at line 452 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44

Definition at line 178 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148

Definition at line 468 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48

Definition at line 186 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152

Definition at line 484 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52

Definition at line 194 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56

Definition at line 202 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60

Definition at line 210 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64

Definition at line 218 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68

Definition at line 226 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72

Definition at line 234 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76

Definition at line 242 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80

Definition at line 250 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84

Definition at line 258 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156

Definition at line 507 of file iop_sw_cfg_defs.h.

#define REG_WR_INT	(	scope,
		inst,
		reg,
		val
	)	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 46 of file iop_sw_cfg_defs.h.

#define REG_WR_INT_VECT	(	scope,
		inst,
		reg,
		index,
		val
	)

Value:

REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg, (val) )

Definition at line 57 of file iop_sw_cfg_defs.h.

#define REG_WR_VECT	(	scope,
		inst,
		reg,
		index,
		val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 34 of file iop_sw_cfg_defs.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

regk_iop_sw_cfg_a
regk_iop_sw_cfg_b
regk_iop_sw_cfg_bus
regk_iop_sw_cfg_bus_rot16
regk_iop_sw_cfg_bus_rot24
regk_iop_sw_cfg_bus_rot8
regk_iop_sw_cfg_clk12
regk_iop_sw_cfg_cpu
regk_iop_sw_cfg_gated_clk0
regk_iop_sw_cfg_gated_clk1
regk_iop_sw_cfg_gio0
regk_iop_sw_cfg_gio1
regk_iop_sw_cfg_gio2
regk_iop_sw_cfg_gio3
regk_iop_sw_cfg_gio4
regk_iop_sw_cfg_gio5
regk_iop_sw_cfg_gio6
regk_iop_sw_cfg_gio7
regk_iop_sw_cfg_gio_in18
regk_iop_sw_cfg_gio_in19
regk_iop_sw_cfg_gio_in20
regk_iop_sw_cfg_gio_in21
regk_iop_sw_cfg_gio_in26
regk_iop_sw_cfg_gio_in27
regk_iop_sw_cfg_gio_in4
regk_iop_sw_cfg_gio_in5
regk_iop_sw_cfg_last_timer_grp0_tmr2
regk_iop_sw_cfg_last_timer_grp1_tmr2
regk_iop_sw_cfg_last_timer_grp1_tmr3
regk_iop_sw_cfg_mpu
regk_iop_sw_cfg_none
regk_iop_sw_cfg_pdp_out
regk_iop_sw_cfg_pdp_out_hi
regk_iop_sw_cfg_pdp_out_lo
regk_iop_sw_cfg_rw_bus_mask_default
regk_iop_sw_cfg_rw_bus_oe_mask_default
regk_iop_sw_cfg_rw_bus_out_cfg_default
regk_iop_sw_cfg_rw_crc_par_owner_default
regk_iop_sw_cfg_rw_dmc_in_owner_default
regk_iop_sw_cfg_rw_dmc_out_owner_default
regk_iop_sw_cfg_rw_fifo_in_extra_owner_default
regk_iop_sw_cfg_rw_fifo_in_owner_default
regk_iop_sw_cfg_rw_fifo_out_extra_owner_default
regk_iop_sw_cfg_rw_fifo_out_owner_default
regk_iop_sw_cfg_rw_gio_mask_default
regk_iop_sw_cfg_rw_gio_oe_mask_default
regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default
regk_iop_sw_cfg_rw_pdp_cfg_default
regk_iop_sw_cfg_rw_pinmapping_default
regk_iop_sw_cfg_rw_sap_in_owner_default
regk_iop_sw_cfg_rw_sap_out_owner_default
regk_iop_sw_cfg_rw_scrc_in_owner_default
regk_iop_sw_cfg_rw_scrc_out_owner_default
regk_iop_sw_cfg_rw_sdp_cfg_default
regk_iop_sw_cfg_rw_spu_cfg_default
regk_iop_sw_cfg_rw_spu_owner_default
regk_iop_sw_cfg_rw_timer_grp0_cfg_default
regk_iop_sw_cfg_rw_timer_grp0_owner_default
regk_iop_sw_cfg_rw_timer_grp1_cfg_default
regk_iop_sw_cfg_rw_timer_grp1_owner_default
regk_iop_sw_cfg_rw_trigger_grp0_owner_default
regk_iop_sw_cfg_rw_trigger_grp1_owner_default
regk_iop_sw_cfg_rw_trigger_grp2_owner_default
regk_iop_sw_cfg_rw_trigger_grp3_owner_default
regk_iop_sw_cfg_rw_trigger_grp4_owner_default
regk_iop_sw_cfg_rw_trigger_grp5_owner_default
regk_iop_sw_cfg_rw_trigger_grp6_owner_default
regk_iop_sw_cfg_rw_trigger_grp7_owner_default
regk_iop_sw_cfg_rw_trigger_grps_cfg_default
regk_iop_sw_cfg_sdp_out
regk_iop_sw_cfg_size16
regk_iop_sw_cfg_size24
regk_iop_sw_cfg_size32
regk_iop_sw_cfg_size8
regk_iop_sw_cfg_spu
regk_iop_sw_cfg_spu_bus_out0_hi
regk_iop_sw_cfg_spu_bus_out0_lo
regk_iop_sw_cfg_spu_bus_out1_hi
regk_iop_sw_cfg_spu_bus_out1_lo
regk_iop_sw_cfg_spu_g0
regk_iop_sw_cfg_spu_g1
regk_iop_sw_cfg_spu_g2
regk_iop_sw_cfg_spu_g3
regk_iop_sw_cfg_spu_g4
regk_iop_sw_cfg_spu_g5
regk_iop_sw_cfg_spu_g6
regk_iop_sw_cfg_spu_g7
regk_iop_sw_cfg_spu_gio0
regk_iop_sw_cfg_spu_gio1
regk_iop_sw_cfg_spu_gio5
regk_iop_sw_cfg_spu_gio6
regk_iop_sw_cfg_spu_gio7
regk_iop_sw_cfg_spu_gio_out0
regk_iop_sw_cfg_spu_gio_out1
regk_iop_sw_cfg_spu_gio_out2
regk_iop_sw_cfg_spu_gio_out3
regk_iop_sw_cfg_spu_gio_out4
regk_iop_sw_cfg_spu_gio_out5
regk_iop_sw_cfg_spu_gio_out6
regk_iop_sw_cfg_spu_gio_out7
regk_iop_sw_cfg_spu_gioout0
regk_iop_sw_cfg_spu_gioout1
regk_iop_sw_cfg_spu_gioout10
regk_iop_sw_cfg_spu_gioout11
regk_iop_sw_cfg_spu_gioout12
regk_iop_sw_cfg_spu_gioout13
regk_iop_sw_cfg_spu_gioout14
regk_iop_sw_cfg_spu_gioout15
regk_iop_sw_cfg_spu_gioout16
regk_iop_sw_cfg_spu_gioout17
regk_iop_sw_cfg_spu_gioout18
regk_iop_sw_cfg_spu_gioout19
regk_iop_sw_cfg_spu_gioout2
regk_iop_sw_cfg_spu_gioout20
regk_iop_sw_cfg_spu_gioout21
regk_iop_sw_cfg_spu_gioout22
regk_iop_sw_cfg_spu_gioout23
regk_iop_sw_cfg_spu_gioout24
regk_iop_sw_cfg_spu_gioout25
regk_iop_sw_cfg_spu_gioout26
regk_iop_sw_cfg_spu_gioout27
regk_iop_sw_cfg_spu_gioout28
regk_iop_sw_cfg_spu_gioout29
regk_iop_sw_cfg_spu_gioout3
regk_iop_sw_cfg_spu_gioout30
regk_iop_sw_cfg_spu_gioout31
regk_iop_sw_cfg_spu_gioout4
regk_iop_sw_cfg_spu_gioout5
regk_iop_sw_cfg_spu_gioout6
regk_iop_sw_cfg_spu_gioout7
regk_iop_sw_cfg_spu_gioout8
regk_iop_sw_cfg_spu_gioout9
regk_iop_sw_cfg_strb_timer_grp0_tmr0
regk_iop_sw_cfg_strb_timer_grp0_tmr1
regk_iop_sw_cfg_strb_timer_grp1_tmr0
regk_iop_sw_cfg_strb_timer_grp1_tmr1
regk_iop_sw_cfg_timer_grp0
regk_iop_sw_cfg_timer_grp0_rot
regk_iop_sw_cfg_timer_grp0_strb0
regk_iop_sw_cfg_timer_grp0_strb1
regk_iop_sw_cfg_timer_grp0_strb2
regk_iop_sw_cfg_timer_grp0_strb3
regk_iop_sw_cfg_timer_grp0_tmr0
regk_iop_sw_cfg_timer_grp1
regk_iop_sw_cfg_timer_grp1_rot
regk_iop_sw_cfg_timer_grp1_strb0
regk_iop_sw_cfg_timer_grp1_strb1
regk_iop_sw_cfg_timer_grp1_strb2
regk_iop_sw_cfg_timer_grp1_strb3
regk_iop_sw_cfg_timer_grp1_tmr0
regk_iop_sw_cfg_trig0_0
regk_iop_sw_cfg_trig0_1
regk_iop_sw_cfg_trig0_2
regk_iop_sw_cfg_trig0_3
regk_iop_sw_cfg_trig1_0
regk_iop_sw_cfg_trig1_1
regk_iop_sw_cfg_trig1_2
regk_iop_sw_cfg_trig1_3
regk_iop_sw_cfg_trig2_0
regk_iop_sw_cfg_trig2_1
regk_iop_sw_cfg_trig2_2
regk_iop_sw_cfg_trig2_3
regk_iop_sw_cfg_trig3_0
regk_iop_sw_cfg_trig3_1
regk_iop_sw_cfg_trig3_2
regk_iop_sw_cfg_trig3_3
regk_iop_sw_cfg_trig4_0
regk_iop_sw_cfg_trig4_1
regk_iop_sw_cfg_trig4_2
regk_iop_sw_cfg_trig4_3
regk_iop_sw_cfg_trig5_0
regk_iop_sw_cfg_trig5_1
regk_iop_sw_cfg_trig5_2
regk_iop_sw_cfg_trig5_3
regk_iop_sw_cfg_trig6_0
regk_iop_sw_cfg_trig6_1
regk_iop_sw_cfg_trig6_2
regk_iop_sw_cfg_trig6_3
regk_iop_sw_cfg_trig7_0
regk_iop_sw_cfg_trig7_1
regk_iop_sw_cfg_trig7_2
regk_iop_sw_cfg_trig7_3

Definition at line 534 of file iop_sw_cfg_defs.h.

Data Structures

Macros

Enumerations

Macro Definition Documentation

Enumeration Type Documentation