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arch
mips
include
asm
mach-ip27
dma-coherence.h
Go to the documentation of this file.
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Ralf Baechle <
[email protected]
>
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*
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*/
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#ifndef __ASM_MACH_IP27_DMA_COHERENCE_H
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#define __ASM_MACH_IP27_DMA_COHERENCE_H
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#include <
asm/pci/bridge.h
>
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#define pdev_to_baddr(pdev, addr) \
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(BRIDGE_CONTROLLER(pdev->bus)->baddr + (addr))
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#define dev_to_baddr(dev, addr) \
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pdev_to_baddr(to_pci_dev(dev), (addr))
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struct
device
;
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static
inline
dma_addr_t
plat_map_dma_mem(
struct
device
*
dev
,
void
*
addr
,
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size_t
size
)
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{
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dma_addr_t
pa =
dev_to_baddr
(dev,
virt_to_phys
(addr));
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return
pa;
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}
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static
inline
dma_addr_t
plat_map_dma_mem_page(
struct
device
*dev,
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struct
page
*
page
)
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{
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dma_addr_t
pa =
dev_to_baddr
(dev,
page_to_phys
(page));
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return
pa;
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}
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static
inline
unsigned
long
plat_dma_addr_to_phys(
struct
device
*dev,
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dma_addr_t
dma_addr
)
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{
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return
dma_addr & ~(0xff
UL
<< 56);
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}
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static
inline
void
plat_unmap_dma_mem(
struct
device
*dev,
dma_addr_t
dma_addr
,
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size_t
size,
enum
dma_data_direction
direction
)
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{
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}
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static
inline
int
plat_dma_supported(
struct
device
*dev,
u64
mask
)
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{
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/*
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* we fall back to GFP_DMA when the mask isn't all 1s,
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* so we can't guarantee allocations that must be
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* within a tighter range than GFP_DMA..
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*/
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if
(mask <
DMA_BIT_MASK
(24))
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return
0;
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return
1;
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}
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static
inline
void
plat_extra_sync_for_device(
struct
device
*dev)
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{
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}
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static
inline
int
plat_dma_mapping_error(
struct
device
*dev,
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dma_addr_t
dma_addr
)
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{
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return
0;
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}
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static
inline
int
plat_device_is_coherent(
struct
device
*dev)
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{
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return
1;
/* IP27 non-cohernet mode is unsupported */
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}
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#endif
/* __ASM_MACH_IP27_DMA_COHERENCE_H */
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