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mach-qt2410.c
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1 /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
2  *
3  * Copyright (C) 2006 by OpenMoko, Inc.
4  * Author: Harald Welte <[email protected]>
5  * All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  *
22  */
23 
24 #include <linux/kernel.h>
25 #include <linux/types.h>
26 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/timer.h>
29 #include <linux/init.h>
30 #include <linux/gpio.h>
31 #include <linux/device.h>
32 #include <linux/platform_device.h>
33 #include <linux/serial_core.h>
34 #include <linux/spi/spi.h>
35 #include <linux/spi/spi_gpio.h>
36 #include <linux/io.h>
37 #include <linux/mtd/mtd.h>
38 #include <linux/mtd/nand.h>
39 #include <linux/mtd/nand_ecc.h>
40 #include <linux/mtd/partitions.h>
41 
42 #include <asm/mach/arch.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/irq.h>
45 
46 #include <mach/hardware.h>
47 #include <asm/irq.h>
48 #include <asm/mach-types.h>
49 
51 #include <mach/regs-lcd.h>
52 #include <plat/regs-serial.h>
53 #include <mach/fb.h>
57 
58 #include <plat/common-smdk.h>
59 #include <plat/gpio-cfg.h>
60 #include <plat/devs.h>
61 #include <plat/cpu.h>
62 #include <plat/pm.h>
63 
64 #include "common.h"
65 
66 static struct map_desc qt2410_iodesc[] __initdata = {
67  { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
68 };
69 
70 #define UCON S3C2410_UCON_DEFAULT
71 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
72 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
73 
74 static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
75  [0] = {
76  .hwport = 0,
77  .flags = 0,
78  .ucon = UCON,
79  .ulcon = ULCON,
80  .ufcon = UFCON,
81  },
82  [1] = {
83  .hwport = 1,
84  .flags = 0,
85  .ucon = UCON,
86  .ulcon = ULCON,
87  .ufcon = UFCON,
88  },
89  [2] = {
90  .hwport = 2,
91  .flags = 0,
92  .ucon = UCON,
93  .ulcon = ULCON,
94  .ufcon = UFCON,
95  }
96 };
97 
98 /* LCD driver info */
99 
100 static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
101  {
102  /* Configuration for 640x480 SHARP LQ080V3DG01 */
103  .lcdcon5 = S3C2410_LCDCON5_FRM565 |
108 
109  .type = S3C2410_LCDCON1_TFT,
110  .width = 640,
111  .height = 480,
112 
113  .pixclock = 40000, /* HCLK/4 */
114  .xres = 640,
115  .yres = 480,
116  .bpp = 16,
117  .left_margin = 44,
118  .right_margin = 116,
119  .hsync_len = 96,
120  .upper_margin = 19,
121  .lower_margin = 11,
122  .vsync_len = 15,
123  },
124  {
125  /* Configuration for 480x640 toppoly TD028TTEC1 */
126  .lcdcon5 = S3C2410_LCDCON5_FRM565 |
131 
132  .type = S3C2410_LCDCON1_TFT,
133  .width = 480,
134  .height = 640,
135  .pixclock = 40000, /* HCLK/4 */
136  .xres = 480,
137  .yres = 640,
138  .bpp = 16,
139  .left_margin = 8,
140  .right_margin = 24,
141  .hsync_len = 8,
142  .upper_margin = 2,
143  .lower_margin = 4,
144  .vsync_len = 2,
145  },
146  {
147  /* Config for 240x320 LCD */
148  .lcdcon5 = S3C2410_LCDCON5_FRM565 |
153 
154  .type = S3C2410_LCDCON1_TFT,
155  .width = 240,
156  .height = 320,
157  .pixclock = 100000, /* HCLK/10 */
158  .xres = 240,
159  .yres = 320,
160  .bpp = 16,
161  .left_margin = 13,
162  .right_margin = 8,
163  .hsync_len = 4,
164  .upper_margin = 2,
165  .lower_margin = 7,
166  .vsync_len = 4,
167  },
168 };
169 
170 
171 static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
172  .displays = qt2410_lcd_cfg,
173  .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
174  .default_display = 0,
175 
176  .lpcsel = ((0xCE6) & ~7) | 1<<4,
177 };
178 
179 /* CS8900 */
180 
181 static struct resource qt2410_cs89x0_resources[] = {
182  [0] = DEFINE_RES_MEM(0x19000000, 17),
183  [1] = DEFINE_RES_IRQ(IRQ_EINT9),
184 };
185 
186 static struct platform_device qt2410_cs89x0 = {
187  .name = "cirrus-cs89x0",
188  .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
189  .resource = qt2410_cs89x0_resources,
190 };
191 
192 /* LED */
193 
194 static struct s3c24xx_led_platdata qt2410_pdata_led = {
195  .gpio = S3C2410_GPB(0),
197  .name = "led",
198  .def_trigger = "timer",
199 };
200 
201 static struct platform_device qt2410_led = {
202  .name = "s3c24xx_led",
203  .id = 0,
204  .dev = {
205  .platform_data = &qt2410_pdata_led,
206  },
207 };
208 
209 /* SPI */
210 
211 static struct spi_gpio_platform_data spi_gpio_cfg = {
212  .sck = S3C2410_GPG(7),
213  .mosi = S3C2410_GPG(6),
214  .miso = S3C2410_GPG(5),
215 };
216 
217 static struct platform_device qt2410_spi = {
218  .name = "spi-gpio",
219  .id = 1,
220  .dev.platform_data = &spi_gpio_cfg,
221 };
222 
223 /* Board devices */
224 
225 static struct platform_device *qt2410_devices[] __initdata = {
233  &qt2410_spi,
234  &qt2410_cs89x0,
235  &qt2410_led,
236 };
237 
238 static struct mtd_partition __initdata qt2410_nand_part[] = {
239  [0] = {
240  .name = "U-Boot",
241  .size = 0x30000,
242  .offset = 0,
243  },
244  [1] = {
245  .name = "U-Boot environment",
246  .offset = 0x30000,
247  .size = 0x4000,
248  },
249  [2] = {
250  .name = "kernel",
251  .offset = 0x34000,
252  .size = SZ_2M,
253  },
254  [3] = {
255  .name = "initrd",
256  .offset = 0x234000,
257  .size = SZ_4M,
258  },
259  [4] = {
260  .name = "jffs2",
261  .offset = 0x634000,
262  .size = 0x39cc000,
263  },
264 };
265 
266 static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
267  [0] = {
268  .name = "NAND",
269  .nr_chips = 1,
270  .nr_partitions = ARRAY_SIZE(qt2410_nand_part),
271  .partitions = qt2410_nand_part,
272  },
273 };
274 
275 /* choose a set of timings which should suit most 512Mbit
276  * chips and beyond.
277  */
278 
279 static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
280  .tacls = 20,
281  .twrph0 = 60,
282  .twrph1 = 20,
283  .nr_sets = ARRAY_SIZE(qt2410_nand_sets),
284  .sets = qt2410_nand_sets,
285 };
286 
287 /* UDC */
288 
289 static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
290 };
291 
292 static char tft_type = 's';
293 
294 static int __init qt2410_tft_setup(char *str)
295 {
296  tft_type = str[0];
297  return 1;
298 }
299 
300 __setup("tft=", qt2410_tft_setup);
301 
302 static void __init qt2410_map_io(void)
303 {
304  s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
305  s3c24xx_init_clocks(12*1000*1000);
306  s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
307 }
308 
309 static void __init qt2410_machine_init(void)
310 {
311  s3c_nand_set_platdata(&qt2410_nand_info);
312 
313  switch (tft_type) {
314  case 'p': /* production */
315  qt2410_fb_info.default_display = 1;
316  break;
317  case 'b': /* big */
318  qt2410_fb_info.default_display = 0;
319  break;
320  case 's': /* small */
321  default:
322  qt2410_fb_info.default_display = 2;
323  break;
324  }
325  s3c24xx_fb_set_platdata(&qt2410_fb_info);
326 
327  /* set initial state of the LED GPIO */
330 
331  s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
333 
334  WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
336 
337  platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
338  s3c_pm_init();
339 }
340 
341 MACHINE_START(QT2410, "QT2410")
342  .atag_offset = 0x100,
343  .map_io = qt2410_map_io,
344  .init_irq = s3c24xx_init_irq,
345  .init_machine = qt2410_machine_init,
346  .timer = &s3c24xx_timer,
347  .restart = s3c2410_restart,