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marvell.c
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1 /*
2  * drivers/net/phy/marvell.c
3  *
4  * Driver for Marvell PHYs
5  *
6  * Author: Andy Fleming
7  *
8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License as published by the
12  * Free Software Foundation; either version 2 of the License, or (at your
13  * option) any later version.
14  *
15  */
16 #include <linux/kernel.h>
17 #include <linux/string.h>
18 #include <linux/errno.h>
19 #include <linux/unistd.h>
20 #include <linux/interrupt.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/skbuff.h>
26 #include <linux/spinlock.h>
27 #include <linux/mm.h>
28 #include <linux/module.h>
29 #include <linux/mii.h>
30 #include <linux/ethtool.h>
31 #include <linux/phy.h>
32 #include <linux/marvell_phy.h>
33 #include <linux/of.h>
34 
35 #include <asm/io.h>
36 #include <asm/irq.h>
37 #include <asm/uaccess.h>
38 
39 #define MII_MARVELL_PHY_PAGE 22
40 
41 #define MII_M1011_IEVENT 0x13
42 #define MII_M1011_IEVENT_CLEAR 0x0000
43 
44 #define MII_M1011_IMASK 0x12
45 #define MII_M1011_IMASK_INIT 0x6400
46 #define MII_M1011_IMASK_CLEAR 0x0000
47 
48 #define MII_M1011_PHY_SCR 0x10
49 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
50 
51 #define MII_M1145_PHY_EXT_CR 0x14
52 #define MII_M1145_RGMII_RX_DELAY 0x0080
53 #define MII_M1145_RGMII_TX_DELAY 0x0002
54 
55 #define MII_M1111_PHY_LED_CONTROL 0x18
56 #define MII_M1111_PHY_LED_DIRECT 0x4100
57 #define MII_M1111_PHY_LED_COMBINE 0x411c
58 #define MII_M1111_PHY_EXT_CR 0x14
59 #define MII_M1111_RX_DELAY 0x80
60 #define MII_M1111_TX_DELAY 0x2
61 #define MII_M1111_PHY_EXT_SR 0x1b
62 
63 #define MII_M1111_HWCFG_MODE_MASK 0xf
64 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
65 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
66 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
67 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
68 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
69 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
70 
71 #define MII_M1111_COPPER 0
72 #define MII_M1111_FIBER 1
73 
74 #define MII_88E1121_PHY_MSCR_PAGE 2
75 #define MII_88E1121_PHY_MSCR_REG 21
76 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
77 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
78 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
79 
80 #define MII_88E1318S_PHY_MSCR1_REG 16
81 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
82 
83 #define MII_88E1121_PHY_LED_CTRL 16
84 #define MII_88E1121_PHY_LED_PAGE 3
85 #define MII_88E1121_PHY_LED_DEF 0x0030
86 
87 #define MII_M1011_PHY_STATUS 0x11
88 #define MII_M1011_PHY_STATUS_1000 0x8000
89 #define MII_M1011_PHY_STATUS_100 0x4000
90 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
91 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
92 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
93 #define MII_M1011_PHY_STATUS_LINK 0x0400
94 
95 
96 MODULE_DESCRIPTION("Marvell PHY driver");
97 MODULE_AUTHOR("Andy Fleming");
98 MODULE_LICENSE("GPL");
99 
100 static int marvell_ack_interrupt(struct phy_device *phydev)
101 {
102  int err;
103 
104  /* Clear the interrupts by reading the reg */
105  err = phy_read(phydev, MII_M1011_IEVENT);
106 
107  if (err < 0)
108  return err;
109 
110  return 0;
111 }
112 
113 static int marvell_config_intr(struct phy_device *phydev)
114 {
115  int err;
116 
117  if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
118  err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
119  else
120  err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
121 
122  return err;
123 }
124 
125 static int marvell_config_aneg(struct phy_device *phydev)
126 {
127  int err;
128 
129  /* The Marvell PHY has an errata which requires
130  * that certain registers get written in order
131  * to restart autonegotiation */
132  err = phy_write(phydev, MII_BMCR, BMCR_RESET);
133 
134  if (err < 0)
135  return err;
136 
137  err = phy_write(phydev, 0x1d, 0x1f);
138  if (err < 0)
139  return err;
140 
141  err = phy_write(phydev, 0x1e, 0x200c);
142  if (err < 0)
143  return err;
144 
145  err = phy_write(phydev, 0x1d, 0x5);
146  if (err < 0)
147  return err;
148 
149  err = phy_write(phydev, 0x1e, 0);
150  if (err < 0)
151  return err;
152 
153  err = phy_write(phydev, 0x1e, 0x100);
154  if (err < 0)
155  return err;
156 
157  err = phy_write(phydev, MII_M1011_PHY_SCR,
158  MII_M1011_PHY_SCR_AUTO_CROSS);
159  if (err < 0)
160  return err;
161 
162  err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
163  MII_M1111_PHY_LED_DIRECT);
164  if (err < 0)
165  return err;
166 
167  err = genphy_config_aneg(phydev);
168  if (err < 0)
169  return err;
170 
171  if (phydev->autoneg != AUTONEG_ENABLE) {
172  int bmcr;
173 
174  /*
175  * A write to speed/duplex bits (that is performed by
176  * genphy_config_aneg() call above) must be followed by
177  * a software reset. Otherwise, the write has no effect.
178  */
179  bmcr = phy_read(phydev, MII_BMCR);
180  if (bmcr < 0)
181  return bmcr;
182 
183  err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
184  if (err < 0)
185  return err;
186  }
187 
188  return 0;
189 }
190 
191 #ifdef CONFIG_OF_MDIO
192 /*
193  * Set and/or override some configuration registers based on the
194  * marvell,reg-init property stored in the of_node for the phydev.
195  *
196  * marvell,reg-init = <reg-page reg mask value>,...;
197  *
198  * There may be one or more sets of <reg-page reg mask value>:
199  *
200  * reg-page: which register bank to use.
201  * reg: the register.
202  * mask: if non-zero, ANDed with existing register value.
203  * value: ORed with the masked value and written to the regiser.
204  *
205  */
206 static int marvell_of_reg_init(struct phy_device *phydev)
207 {
208  const __be32 *paddr;
209  int len, i, saved_page, current_page, page_changed, ret;
210 
211  if (!phydev->dev.of_node)
212  return 0;
213 
214  paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
215  if (!paddr || len < (4 * sizeof(*paddr)))
216  return 0;
217 
218  saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
219  if (saved_page < 0)
220  return saved_page;
221  page_changed = 0;
222  current_page = saved_page;
223 
224  ret = 0;
225  len /= sizeof(*paddr);
226  for (i = 0; i < len - 3; i += 4) {
227  u16 reg_page = be32_to_cpup(paddr + i);
228  u16 reg = be32_to_cpup(paddr + i + 1);
229  u16 mask = be32_to_cpup(paddr + i + 2);
230  u16 val_bits = be32_to_cpup(paddr + i + 3);
231  int val;
232 
233  if (reg_page != current_page) {
234  current_page = reg_page;
235  page_changed = 1;
236  ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
237  if (ret < 0)
238  goto err;
239  }
240 
241  val = 0;
242  if (mask) {
243  val = phy_read(phydev, reg);
244  if (val < 0) {
245  ret = val;
246  goto err;
247  }
248  val &= mask;
249  }
250  val |= val_bits;
251 
252  ret = phy_write(phydev, reg, val);
253  if (ret < 0)
254  goto err;
255 
256  }
257 err:
258  if (page_changed) {
259  i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
260  if (ret == 0)
261  ret = i;
262  }
263  return ret;
264 }
265 #else
266 static int marvell_of_reg_init(struct phy_device *phydev)
267 {
268  return 0;
269 }
270 #endif /* CONFIG_OF_MDIO */
271 
272 static int m88e1121_config_aneg(struct phy_device *phydev)
273 {
274  int err, oldpage, mscr;
275 
276  oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
277 
278  err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
279  MII_88E1121_PHY_MSCR_PAGE);
280  if (err < 0)
281  return err;
282 
283  if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
284  (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
285  (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
286  (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
287 
288  mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
289  MII_88E1121_PHY_MSCR_DELAY_MASK;
290 
291  if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
292  mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
293  MII_88E1121_PHY_MSCR_TX_DELAY);
294  else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
295  mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
296  else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
297  mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
298 
299  err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
300  if (err < 0)
301  return err;
302  }
303 
304  phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
305 
306  err = phy_write(phydev, MII_BMCR, BMCR_RESET);
307  if (err < 0)
308  return err;
309 
310  err = phy_write(phydev, MII_M1011_PHY_SCR,
311  MII_M1011_PHY_SCR_AUTO_CROSS);
312  if (err < 0)
313  return err;
314 
315  oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
316 
317  phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
318  phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
319  phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
320 
321  err = genphy_config_aneg(phydev);
322 
323  return err;
324 }
325 
326 static int m88e1318_config_aneg(struct phy_device *phydev)
327 {
328  int err, oldpage, mscr;
329 
330  oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
331 
332  err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
333  MII_88E1121_PHY_MSCR_PAGE);
334  if (err < 0)
335  return err;
336 
337  mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
338  mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
339 
340  err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
341  if (err < 0)
342  return err;
343 
344  err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
345  if (err < 0)
346  return err;
347 
348  return m88e1121_config_aneg(phydev);
349 }
350 
351 static int m88e1111_config_init(struct phy_device *phydev)
352 {
353  int err;
354  int temp;
355 
356  /* Enable Fiber/Copper auto selection */
357  temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
358  temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
359  phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
360 
361  temp = phy_read(phydev, MII_BMCR);
362  temp |= BMCR_RESET;
363  phy_write(phydev, MII_BMCR, temp);
364 
365  if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
366  (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
367  (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
368  (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
369 
370  temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
371  if (temp < 0)
372  return temp;
373 
374  if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
375  temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
376  } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
377  temp &= ~MII_M1111_TX_DELAY;
378  temp |= MII_M1111_RX_DELAY;
379  } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
380  temp &= ~MII_M1111_RX_DELAY;
381  temp |= MII_M1111_TX_DELAY;
382  }
383 
384  err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
385  if (err < 0)
386  return err;
387 
388  temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
389  if (temp < 0)
390  return temp;
391 
392  temp &= ~(MII_M1111_HWCFG_MODE_MASK);
393 
394  if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
395  temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
396  else
397  temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
398 
399  err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
400  if (err < 0)
401  return err;
402  }
403 
404  if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
405  temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
406  if (temp < 0)
407  return temp;
408 
409  temp &= ~(MII_M1111_HWCFG_MODE_MASK);
410  temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
411  temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
412 
413  err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
414  if (err < 0)
415  return err;
416  }
417 
418  if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
419  temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
420  if (temp < 0)
421  return temp;
422  temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
423  err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
424  if (err < 0)
425  return err;
426 
427  temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
428  if (temp < 0)
429  return temp;
430  temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
431  temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
432  err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
433  if (err < 0)
434  return err;
435 
436  /* soft reset */
437  err = phy_write(phydev, MII_BMCR, BMCR_RESET);
438  if (err < 0)
439  return err;
440  do
441  temp = phy_read(phydev, MII_BMCR);
442  while (temp & BMCR_RESET);
443 
444  temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
445  if (temp < 0)
446  return temp;
447  temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
448  temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
449  err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
450  if (err < 0)
451  return err;
452  }
453 
454  err = marvell_of_reg_init(phydev);
455  if (err < 0)
456  return err;
457 
458  return phy_write(phydev, MII_BMCR, BMCR_RESET);
459 }
460 
461 static int m88e1118_config_aneg(struct phy_device *phydev)
462 {
463  int err;
464 
465  err = phy_write(phydev, MII_BMCR, BMCR_RESET);
466  if (err < 0)
467  return err;
468 
469  err = phy_write(phydev, MII_M1011_PHY_SCR,
470  MII_M1011_PHY_SCR_AUTO_CROSS);
471  if (err < 0)
472  return err;
473 
474  err = genphy_config_aneg(phydev);
475  return 0;
476 }
477 
478 static int m88e1118_config_init(struct phy_device *phydev)
479 {
480  int err;
481 
482  /* Change address */
483  err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
484  if (err < 0)
485  return err;
486 
487  /* Enable 1000 Mbit */
488  err = phy_write(phydev, 0x15, 0x1070);
489  if (err < 0)
490  return err;
491 
492  /* Change address */
493  err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
494  if (err < 0)
495  return err;
496 
497  /* Adjust LED Control */
498  if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
499  err = phy_write(phydev, 0x10, 0x1100);
500  else
501  err = phy_write(phydev, 0x10, 0x021e);
502  if (err < 0)
503  return err;
504 
505  err = marvell_of_reg_init(phydev);
506  if (err < 0)
507  return err;
508 
509  /* Reset address */
510  err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
511  if (err < 0)
512  return err;
513 
514  return phy_write(phydev, MII_BMCR, BMCR_RESET);
515 }
516 
517 static int m88e1149_config_init(struct phy_device *phydev)
518 {
519  int err;
520 
521  /* Change address */
522  err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
523  if (err < 0)
524  return err;
525 
526  /* Enable 1000 Mbit */
527  err = phy_write(phydev, 0x15, 0x1048);
528  if (err < 0)
529  return err;
530 
531  err = marvell_of_reg_init(phydev);
532  if (err < 0)
533  return err;
534 
535  /* Reset address */
536  err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
537  if (err < 0)
538  return err;
539 
540  return phy_write(phydev, MII_BMCR, BMCR_RESET);
541 }
542 
543 static int m88e1145_config_init(struct phy_device *phydev)
544 {
545  int err;
546 
547  /* Take care of errata E0 & E1 */
548  err = phy_write(phydev, 0x1d, 0x001b);
549  if (err < 0)
550  return err;
551 
552  err = phy_write(phydev, 0x1e, 0x418f);
553  if (err < 0)
554  return err;
555 
556  err = phy_write(phydev, 0x1d, 0x0016);
557  if (err < 0)
558  return err;
559 
560  err = phy_write(phydev, 0x1e, 0xa2da);
561  if (err < 0)
562  return err;
563 
564  if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
565  int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
566  if (temp < 0)
567  return temp;
568 
569  temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
570 
571  err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
572  if (err < 0)
573  return err;
574 
575  if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
576  err = phy_write(phydev, 0x1d, 0x0012);
577  if (err < 0)
578  return err;
579 
580  temp = phy_read(phydev, 0x1e);
581  if (temp < 0)
582  return temp;
583 
584  temp &= 0xf03f;
585  temp |= 2 << 9; /* 36 ohm */
586  temp |= 2 << 6; /* 39 ohm */
587 
588  err = phy_write(phydev, 0x1e, temp);
589  if (err < 0)
590  return err;
591 
592  err = phy_write(phydev, 0x1d, 0x3);
593  if (err < 0)
594  return err;
595 
596  err = phy_write(phydev, 0x1e, 0x8000);
597  if (err < 0)
598  return err;
599  }
600  }
601 
602  err = marvell_of_reg_init(phydev);
603  if (err < 0)
604  return err;
605 
606  return 0;
607 }
608 
609 /* marvell_read_status
610  *
611  * Generic status code does not detect Fiber correctly!
612  * Description:
613  * Check the link, then figure out the current state
614  * by comparing what we advertise with what the link partner
615  * advertises. Start by checking the gigabit possibilities,
616  * then move on to 10/100.
617  */
618 static int marvell_read_status(struct phy_device *phydev)
619 {
620  int adv;
621  int err;
622  int lpa;
623  int status = 0;
624 
625  /* Update the link, but return if there
626  * was an error */
627  err = genphy_update_link(phydev);
628  if (err)
629  return err;
630 
631  if (AUTONEG_ENABLE == phydev->autoneg) {
632  status = phy_read(phydev, MII_M1011_PHY_STATUS);
633  if (status < 0)
634  return status;
635 
636  lpa = phy_read(phydev, MII_LPA);
637  if (lpa < 0)
638  return lpa;
639 
640  adv = phy_read(phydev, MII_ADVERTISE);
641  if (adv < 0)
642  return adv;
643 
644  lpa &= adv;
645 
646  if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
647  phydev->duplex = DUPLEX_FULL;
648  else
649  phydev->duplex = DUPLEX_HALF;
650 
651  status = status & MII_M1011_PHY_STATUS_SPD_MASK;
652  phydev->pause = phydev->asym_pause = 0;
653 
654  switch (status) {
655  case MII_M1011_PHY_STATUS_1000:
656  phydev->speed = SPEED_1000;
657  break;
658 
659  case MII_M1011_PHY_STATUS_100:
660  phydev->speed = SPEED_100;
661  break;
662 
663  default:
664  phydev->speed = SPEED_10;
665  break;
666  }
667 
668  if (phydev->duplex == DUPLEX_FULL) {
669  phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
670  phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
671  }
672  } else {
673  int bmcr = phy_read(phydev, MII_BMCR);
674 
675  if (bmcr < 0)
676  return bmcr;
677 
678  if (bmcr & BMCR_FULLDPLX)
679  phydev->duplex = DUPLEX_FULL;
680  else
681  phydev->duplex = DUPLEX_HALF;
682 
683  if (bmcr & BMCR_SPEED1000)
684  phydev->speed = SPEED_1000;
685  else if (bmcr & BMCR_SPEED100)
686  phydev->speed = SPEED_100;
687  else
688  phydev->speed = SPEED_10;
689 
690  phydev->pause = phydev->asym_pause = 0;
691  }
692 
693  return 0;
694 }
695 
696 static int m88e1121_did_interrupt(struct phy_device *phydev)
697 {
698  int imask;
699 
700  imask = phy_read(phydev, MII_M1011_IEVENT);
701 
702  if (imask & MII_M1011_IMASK_INIT)
703  return 1;
704 
705  return 0;
706 }
707 
708 static struct phy_driver marvell_drivers[] = {
709  {
710  .phy_id = MARVELL_PHY_ID_88E1101,
711  .phy_id_mask = MARVELL_PHY_ID_MASK,
712  .name = "Marvell 88E1101",
713  .features = PHY_GBIT_FEATURES,
714  .flags = PHY_HAS_INTERRUPT,
715  .config_aneg = &marvell_config_aneg,
716  .read_status = &genphy_read_status,
717  .ack_interrupt = &marvell_ack_interrupt,
718  .config_intr = &marvell_config_intr,
719  .driver = { .owner = THIS_MODULE },
720  },
721  {
722  .phy_id = MARVELL_PHY_ID_88E1112,
723  .phy_id_mask = MARVELL_PHY_ID_MASK,
724  .name = "Marvell 88E1112",
725  .features = PHY_GBIT_FEATURES,
726  .flags = PHY_HAS_INTERRUPT,
727  .config_init = &m88e1111_config_init,
728  .config_aneg = &marvell_config_aneg,
729  .read_status = &genphy_read_status,
730  .ack_interrupt = &marvell_ack_interrupt,
731  .config_intr = &marvell_config_intr,
732  .driver = { .owner = THIS_MODULE },
733  },
734  {
735  .phy_id = MARVELL_PHY_ID_88E1111,
736  .phy_id_mask = MARVELL_PHY_ID_MASK,
737  .name = "Marvell 88E1111",
738  .features = PHY_GBIT_FEATURES,
739  .flags = PHY_HAS_INTERRUPT,
740  .config_init = &m88e1111_config_init,
741  .config_aneg = &marvell_config_aneg,
742  .read_status = &marvell_read_status,
743  .ack_interrupt = &marvell_ack_interrupt,
744  .config_intr = &marvell_config_intr,
745  .driver = { .owner = THIS_MODULE },
746  },
747  {
748  .phy_id = MARVELL_PHY_ID_88E1118,
749  .phy_id_mask = MARVELL_PHY_ID_MASK,
750  .name = "Marvell 88E1118",
751  .features = PHY_GBIT_FEATURES,
752  .flags = PHY_HAS_INTERRUPT,
753  .config_init = &m88e1118_config_init,
754  .config_aneg = &m88e1118_config_aneg,
755  .read_status = &genphy_read_status,
756  .ack_interrupt = &marvell_ack_interrupt,
757  .config_intr = &marvell_config_intr,
758  .driver = {.owner = THIS_MODULE,},
759  },
760  {
761  .phy_id = MARVELL_PHY_ID_88E1121R,
762  .phy_id_mask = MARVELL_PHY_ID_MASK,
763  .name = "Marvell 88E1121R",
764  .features = PHY_GBIT_FEATURES,
765  .flags = PHY_HAS_INTERRUPT,
766  .config_aneg = &m88e1121_config_aneg,
767  .read_status = &marvell_read_status,
768  .ack_interrupt = &marvell_ack_interrupt,
769  .config_intr = &marvell_config_intr,
770  .did_interrupt = &m88e1121_did_interrupt,
771  .driver = { .owner = THIS_MODULE },
772  },
773  {
774  .phy_id = MARVELL_PHY_ID_88E1318S,
775  .phy_id_mask = MARVELL_PHY_ID_MASK,
776  .name = "Marvell 88E1318S",
777  .features = PHY_GBIT_FEATURES,
778  .flags = PHY_HAS_INTERRUPT,
779  .config_aneg = &m88e1318_config_aneg,
780  .read_status = &marvell_read_status,
781  .ack_interrupt = &marvell_ack_interrupt,
782  .config_intr = &marvell_config_intr,
783  .did_interrupt = &m88e1121_did_interrupt,
784  .driver = { .owner = THIS_MODULE },
785  },
786  {
787  .phy_id = MARVELL_PHY_ID_88E1145,
788  .phy_id_mask = MARVELL_PHY_ID_MASK,
789  .name = "Marvell 88E1145",
790  .features = PHY_GBIT_FEATURES,
791  .flags = PHY_HAS_INTERRUPT,
792  .config_init = &m88e1145_config_init,
793  .config_aneg = &marvell_config_aneg,
794  .read_status = &genphy_read_status,
795  .ack_interrupt = &marvell_ack_interrupt,
796  .config_intr = &marvell_config_intr,
797  .driver = { .owner = THIS_MODULE },
798  },
799  {
800  .phy_id = MARVELL_PHY_ID_88E1149R,
801  .phy_id_mask = MARVELL_PHY_ID_MASK,
802  .name = "Marvell 88E1149R",
803  .features = PHY_GBIT_FEATURES,
804  .flags = PHY_HAS_INTERRUPT,
805  .config_init = &m88e1149_config_init,
806  .config_aneg = &m88e1118_config_aneg,
807  .read_status = &genphy_read_status,
808  .ack_interrupt = &marvell_ack_interrupt,
809  .config_intr = &marvell_config_intr,
810  .driver = { .owner = THIS_MODULE },
811  },
812  {
813  .phy_id = MARVELL_PHY_ID_88E1240,
814  .phy_id_mask = MARVELL_PHY_ID_MASK,
815  .name = "Marvell 88E1240",
816  .features = PHY_GBIT_FEATURES,
817  .flags = PHY_HAS_INTERRUPT,
818  .config_init = &m88e1111_config_init,
819  .config_aneg = &marvell_config_aneg,
820  .read_status = &genphy_read_status,
821  .ack_interrupt = &marvell_ack_interrupt,
822  .config_intr = &marvell_config_intr,
823  .driver = { .owner = THIS_MODULE },
824  },
825 };
826 
827 static int __init marvell_init(void)
828 {
829  return phy_drivers_register(marvell_drivers,
830  ARRAY_SIZE(marvell_drivers));
831 }
832 
833 static void __exit marvell_exit(void)
834 {
835  phy_drivers_unregister(marvell_drivers,
836  ARRAY_SIZE(marvell_drivers));
837 }
838 
839 module_init(marvell_init);
840 module_exit(marvell_exit);
841 
842 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
843  { 0x01410c60, 0xfffffff0 },
844  { 0x01410c90, 0xfffffff0 },
845  { 0x01410cc0, 0xfffffff0 },
846  { 0x01410e10, 0xfffffff0 },
847  { 0x01410cb0, 0xfffffff0 },
848  { 0x01410cd0, 0xfffffff0 },
849  { 0x01410e50, 0xfffffff0 },
850  { 0x01410e30, 0xfffffff0 },
851  { 0x01410e90, 0xfffffff0 },
852  { }
853 };
854 
855 MODULE_DEVICE_TABLE(mdio, marvell_tbl);
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