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mc13892-regulator.c
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1 /*
2  * Regulator Driver for Freescale MC13892 PMIC
3  *
4  * Copyright 2010 Yong Shen <[email protected]>
5  *
6  * Based on draft driver from Arnaud Patard <[email protected]>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/mfd/mc13892.h>
14 #include <linux/regulator/machine.h>
15 #include <linux/regulator/driver.h>
16 #include <linux/platform_device.h>
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/module.h>
22 #include "mc13xxx.h"
23 
24 #define MC13892_REVISION 7
25 
26 #define MC13892_POWERCTL0 13
27 #define MC13892_POWERCTL0_USEROFFSPI 3
28 #define MC13892_POWERCTL0_VCOINCELLVSEL 20
29 #define MC13892_POWERCTL0_VCOINCELLVSEL_M (7<<20)
30 #define MC13892_POWERCTL0_VCOINCELLEN (1<<23)
31 
32 #define MC13892_SWITCHERS0_SWxHI (1<<23)
33 
34 #define MC13892_SWITCHERS0 24
35 #define MC13892_SWITCHERS0_SW1VSEL 0
36 #define MC13892_SWITCHERS0_SW1VSEL_M (0x1f<<0)
37 #define MC13892_SWITCHERS0_SW1HI (1<<23)
38 #define MC13892_SWITCHERS0_SW1EN 0
39 
40 #define MC13892_SWITCHERS1 25
41 #define MC13892_SWITCHERS1_SW2VSEL 0
42 #define MC13892_SWITCHERS1_SW2VSEL_M (0x1f<<0)
43 #define MC13892_SWITCHERS1_SW2HI (1<<23)
44 #define MC13892_SWITCHERS1_SW2EN 0
45 
46 #define MC13892_SWITCHERS2 26
47 #define MC13892_SWITCHERS2_SW3VSEL 0
48 #define MC13892_SWITCHERS2_SW3VSEL_M (0x1f<<0)
49 #define MC13892_SWITCHERS2_SW3HI (1<<23)
50 #define MC13892_SWITCHERS2_SW3EN 0
51 
52 #define MC13892_SWITCHERS3 27
53 #define MC13892_SWITCHERS3_SW4VSEL 0
54 #define MC13892_SWITCHERS3_SW4VSEL_M (0x1f<<0)
55 #define MC13892_SWITCHERS3_SW4HI (1<<23)
56 #define MC13892_SWITCHERS3_SW4EN 0
57 
58 #define MC13892_SWITCHERS4 28
59 #define MC13892_SWITCHERS4_SW1MODE 0
60 #define MC13892_SWITCHERS4_SW1MODE_AUTO (8<<0)
61 #define MC13892_SWITCHERS4_SW1MODE_M (0xf<<0)
62 #define MC13892_SWITCHERS4_SW2MODE 10
63 #define MC13892_SWITCHERS4_SW2MODE_AUTO (8<<10)
64 #define MC13892_SWITCHERS4_SW2MODE_M (0xf<<10)
65 
66 #define MC13892_SWITCHERS5 29
67 #define MC13892_SWITCHERS5_SW3MODE 0
68 #define MC13892_SWITCHERS5_SW3MODE_AUTO (8<<0)
69 #define MC13892_SWITCHERS5_SW3MODE_M (0xf<<0)
70 #define MC13892_SWITCHERS5_SW4MODE 8
71 #define MC13892_SWITCHERS5_SW4MODE_AUTO (8<<8)
72 #define MC13892_SWITCHERS5_SW4MODE_M (0xf<<8)
73 #define MC13892_SWITCHERS5_SWBSTEN (1<<20)
74 
75 #define MC13892_REGULATORSETTING0 30
76 #define MC13892_REGULATORSETTING0_VGEN1VSEL 0
77 #define MC13892_REGULATORSETTING0_VDIGVSEL 4
78 #define MC13892_REGULATORSETTING0_VGEN2VSEL 6
79 #define MC13892_REGULATORSETTING0_VPLLVSEL 9
80 #define MC13892_REGULATORSETTING0_VUSB2VSEL 11
81 #define MC13892_REGULATORSETTING0_VGEN3VSEL 14
82 #define MC13892_REGULATORSETTING0_VCAMVSEL 16
83 
84 #define MC13892_REGULATORSETTING0_VGEN1VSEL_M (3<<0)
85 #define MC13892_REGULATORSETTING0_VDIGVSEL_M (3<<4)
86 #define MC13892_REGULATORSETTING0_VGEN2VSEL_M (7<<6)
87 #define MC13892_REGULATORSETTING0_VPLLVSEL_M (3<<9)
88 #define MC13892_REGULATORSETTING0_VUSB2VSEL_M (3<<11)
89 #define MC13892_REGULATORSETTING0_VGEN3VSEL_M (1<<14)
90 #define MC13892_REGULATORSETTING0_VCAMVSEL_M (3<<16)
91 
92 #define MC13892_REGULATORSETTING1 31
93 #define MC13892_REGULATORSETTING1_VVIDEOVSEL 2
94 #define MC13892_REGULATORSETTING1_VAUDIOVSEL 4
95 #define MC13892_REGULATORSETTING1_VSDVSEL 6
96 
97 #define MC13892_REGULATORSETTING1_VVIDEOVSEL_M (3<<2)
98 #define MC13892_REGULATORSETTING1_VAUDIOVSEL_M (3<<4)
99 #define MC13892_REGULATORSETTING1_VSDVSEL_M (7<<6)
100 
101 #define MC13892_REGULATORMODE0 32
102 #define MC13892_REGULATORMODE0_VGEN1EN (1<<0)
103 #define MC13892_REGULATORMODE0_VGEN1STDBY (1<<1)
104 #define MC13892_REGULATORMODE0_VGEN1MODE (1<<2)
105 #define MC13892_REGULATORMODE0_VIOHIEN (1<<3)
106 #define MC13892_REGULATORMODE0_VIOHISTDBY (1<<4)
107 #define MC13892_REGULATORMODE0_VIOHIMODE (1<<5)
108 #define MC13892_REGULATORMODE0_VDIGEN (1<<9)
109 #define MC13892_REGULATORMODE0_VDIGSTDBY (1<<10)
110 #define MC13892_REGULATORMODE0_VDIGMODE (1<<11)
111 #define MC13892_REGULATORMODE0_VGEN2EN (1<<12)
112 #define MC13892_REGULATORMODE0_VGEN2STDBY (1<<13)
113 #define MC13892_REGULATORMODE0_VGEN2MODE (1<<14)
114 #define MC13892_REGULATORMODE0_VPLLEN (1<<15)
115 #define MC13892_REGULATORMODE0_VPLLSTDBY (1<<16)
116 #define MC13892_REGULATORMODE0_VPLLMODE (1<<17)
117 #define MC13892_REGULATORMODE0_VUSB2EN (1<<18)
118 #define MC13892_REGULATORMODE0_VUSB2STDBY (1<<19)
119 #define MC13892_REGULATORMODE0_VUSB2MODE (1<<20)
120 
121 #define MC13892_REGULATORMODE1 33
122 #define MC13892_REGULATORMODE1_VGEN3EN (1<<0)
123 #define MC13892_REGULATORMODE1_VGEN3STDBY (1<<1)
124 #define MC13892_REGULATORMODE1_VGEN3MODE (1<<2)
125 #define MC13892_REGULATORMODE1_VCAMEN (1<<6)
126 #define MC13892_REGULATORMODE1_VCAMSTDBY (1<<7)
127 #define MC13892_REGULATORMODE1_VCAMMODE (1<<8)
128 #define MC13892_REGULATORMODE1_VCAMCONFIGEN (1<<9)
129 #define MC13892_REGULATORMODE1_VVIDEOEN (1<<12)
130 #define MC13892_REGULATORMODE1_VVIDEOSTDBY (1<<13)
131 #define MC13892_REGULATORMODE1_VVIDEOMODE (1<<14)
132 #define MC13892_REGULATORMODE1_VAUDIOEN (1<<15)
133 #define MC13892_REGULATORMODE1_VAUDIOSTDBY (1<<16)
134 #define MC13892_REGULATORMODE1_VAUDIOMODE (1<<17)
135 #define MC13892_REGULATORMODE1_VSDEN (1<<18)
136 #define MC13892_REGULATORMODE1_VSDSTDBY (1<<19)
137 #define MC13892_REGULATORMODE1_VSDMODE (1<<20)
138 
139 #define MC13892_POWERMISC 34
140 #define MC13892_POWERMISC_GPO1EN (1<<6)
141 #define MC13892_POWERMISC_GPO2EN (1<<8)
142 #define MC13892_POWERMISC_GPO3EN (1<<10)
143 #define MC13892_POWERMISC_GPO4EN (1<<12)
144 #define MC13892_POWERMISC_PWGT1SPIEN (1<<15)
145 #define MC13892_POWERMISC_PWGT2SPIEN (1<<16)
146 #define MC13892_POWERMISC_GPO4ADINEN (1<<21)
147 
148 #define MC13892_POWERMISC_PWGTSPI_M (3 << 15)
149 
150 #define MC13892_USB1 50
151 #define MC13892_USB1_VUSBEN (1<<3)
152 
153 static const unsigned int mc13892_vcoincell[] = {
154  2500000, 2700000, 2800000, 2900000, 3000000, 3100000,
155  3200000, 3300000,
156 };
157 
158 static const unsigned int mc13892_sw1[] = {
159  600000, 625000, 650000, 675000, 700000, 725000,
160  750000, 775000, 800000, 825000, 850000, 875000,
161  900000, 925000, 950000, 975000, 1000000, 1025000,
162  1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
163  1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
164  1350000, 1375000
165 };
166 
167 static const unsigned int mc13892_sw[] = {
168  600000, 625000, 650000, 675000, 700000, 725000,
169  750000, 775000, 800000, 825000, 850000, 875000,
170  900000, 925000, 950000, 975000, 1000000, 1025000,
171  1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
172  1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
173  1350000, 1375000, 1400000, 1425000, 1450000, 1475000,
174  1500000, 1525000, 1550000, 1575000, 1600000, 1625000,
175  1650000, 1675000, 1700000, 1725000, 1750000, 1775000,
176  1800000, 1825000, 1850000, 1875000
177 };
178 
179 static const unsigned int mc13892_swbst[] = {
180  5000000,
181 };
182 
183 static const unsigned int mc13892_viohi[] = {
184  2775000,
185 };
186 
187 static const unsigned int mc13892_vpll[] = {
188  1050000, 1250000, 1650000, 1800000,
189 };
190 
191 static const unsigned int mc13892_vdig[] = {
192  1050000, 1250000, 1650000, 1800000,
193 };
194 
195 static const unsigned int mc13892_vsd[] = {
196  1800000, 2000000, 2600000, 2700000,
197  2800000, 2900000, 3000000, 3150000,
198 };
199 
200 static const unsigned int mc13892_vusb2[] = {
201  2400000, 2600000, 2700000, 2775000,
202 };
203 
204 static const unsigned int mc13892_vvideo[] = {
205  2700000, 2775000, 2500000, 2600000,
206 };
207 
208 static const unsigned int mc13892_vaudio[] = {
209  2300000, 2500000, 2775000, 3000000,
210 };
211 
212 static const unsigned int mc13892_vcam[] = {
213  2500000, 2600000, 2750000, 3000000,
214 };
215 
216 static const unsigned int mc13892_vgen1[] = {
217  1200000, 1500000, 2775000, 3150000,
218 };
219 
220 static const unsigned int mc13892_vgen2[] = {
221  1200000, 1500000, 1600000, 1800000,
222  2700000, 2800000, 3000000, 3150000,
223 };
224 
225 static const unsigned int mc13892_vgen3[] = {
226  1800000, 2900000,
227 };
228 
229 static const unsigned int mc13892_vusb[] = {
230  3300000,
231 };
232 
233 static const unsigned int mc13892_gpo[] = {
234  2750000,
235 };
236 
237 static const unsigned int mc13892_pwgtdrv[] = {
238  5000000,
239 };
240 
241 static struct regulator_ops mc13892_gpo_regulator_ops;
242 /* sw regulators need special care due to the "hi bit" */
243 static struct regulator_ops mc13892_sw_regulator_ops;
244 
245 
246 #define MC13892_FIXED_DEFINE(name, reg, voltages) \
247  MC13xxx_FIXED_DEFINE(MC13892_, name, reg, voltages, \
248  mc13xxx_fixed_regulator_ops)
249 
250 #define MC13892_GPO_DEFINE(name, reg, voltages) \
251  MC13xxx_GPO_DEFINE(MC13892_, name, reg, voltages, \
252  mc13892_gpo_regulator_ops)
253 
254 #define MC13892_SW_DEFINE(name, reg, vsel_reg, voltages) \
255  MC13xxx_DEFINE(MC13892_, name, reg, vsel_reg, voltages, \
256  mc13892_sw_regulator_ops)
257 
258 #define MC13892_DEFINE_REGU(name, reg, vsel_reg, voltages) \
259  MC13xxx_DEFINE(MC13892_, name, reg, vsel_reg, voltages, \
260  mc13xxx_regulator_ops)
261 
262 static struct mc13xxx_regulator mc13892_regulators[] = {
263  MC13892_DEFINE_REGU(VCOINCELL, POWERCTL0, POWERCTL0, mc13892_vcoincell),
264  MC13892_SW_DEFINE(SW1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
265  MC13892_SW_DEFINE(SW2, SWITCHERS1, SWITCHERS1, mc13892_sw),
266  MC13892_SW_DEFINE(SW3, SWITCHERS2, SWITCHERS2, mc13892_sw),
267  MC13892_SW_DEFINE(SW4, SWITCHERS3, SWITCHERS3, mc13892_sw),
268  MC13892_FIXED_DEFINE(SWBST, SWITCHERS5, mc13892_swbst),
269  MC13892_FIXED_DEFINE(VIOHI, REGULATORMODE0, mc13892_viohi),
270  MC13892_DEFINE_REGU(VPLL, REGULATORMODE0, REGULATORSETTING0, \
271  mc13892_vpll),
272  MC13892_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0, \
273  mc13892_vdig),
274  MC13892_DEFINE_REGU(VSD, REGULATORMODE1, REGULATORSETTING1, \
275  mc13892_vsd),
276  MC13892_DEFINE_REGU(VUSB2, REGULATORMODE0, REGULATORSETTING0, \
277  mc13892_vusb2),
278  MC13892_DEFINE_REGU(VVIDEO, REGULATORMODE1, REGULATORSETTING1, \
279  mc13892_vvideo),
280  MC13892_DEFINE_REGU(VAUDIO, REGULATORMODE1, REGULATORSETTING1, \
281  mc13892_vaudio),
282  MC13892_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0, \
283  mc13892_vcam),
284  MC13892_DEFINE_REGU(VGEN1, REGULATORMODE0, REGULATORSETTING0, \
285  mc13892_vgen1),
286  MC13892_DEFINE_REGU(VGEN2, REGULATORMODE0, REGULATORSETTING0, \
287  mc13892_vgen2),
288  MC13892_DEFINE_REGU(VGEN3, REGULATORMODE1, REGULATORSETTING0, \
289  mc13892_vgen3),
290  MC13892_FIXED_DEFINE(VUSB, USB1, mc13892_vusb),
291  MC13892_GPO_DEFINE(GPO1, POWERMISC, mc13892_gpo),
292  MC13892_GPO_DEFINE(GPO2, POWERMISC, mc13892_gpo),
293  MC13892_GPO_DEFINE(GPO3, POWERMISC, mc13892_gpo),
294  MC13892_GPO_DEFINE(GPO4, POWERMISC, mc13892_gpo),
295  MC13892_GPO_DEFINE(PWGT1SPI, POWERMISC, mc13892_pwgtdrv),
296  MC13892_GPO_DEFINE(PWGT2SPI, POWERMISC, mc13892_pwgtdrv),
297 };
298 
299 static int mc13892_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
300  u32 val)
301 {
302  struct mc13xxx *mc13892 = priv->mc13xxx;
303  int ret;
304  u32 valread;
305 
306  BUG_ON(val & ~mask);
307 
308  mc13xxx_lock(priv->mc13xxx);
309  ret = mc13xxx_reg_read(mc13892, MC13892_POWERMISC, &valread);
310  if (ret)
311  goto out;
312 
313  /* Update the stored state for Power Gates. */
314  priv->powermisc_pwgt_state =
315  (priv->powermisc_pwgt_state & ~mask) | val;
316  priv->powermisc_pwgt_state &= MC13892_POWERMISC_PWGTSPI_M;
317 
318  /* Construct the new register value */
319  valread = (valread & ~mask) | val;
320  /* Overwrite the PWGTxEN with the stored version */
321  valread = (valread & ~MC13892_POWERMISC_PWGTSPI_M) |
322  priv->powermisc_pwgt_state;
323 
324  ret = mc13xxx_reg_write(mc13892, MC13892_POWERMISC, valread);
325 out:
326  mc13xxx_unlock(priv->mc13xxx);
327  return ret;
328 }
329 
330 static int mc13892_gpo_regulator_enable(struct regulator_dev *rdev)
331 {
332  struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
333  int id = rdev_get_id(rdev);
334  u32 en_val = mc13892_regulators[id].enable_bit;
335  u32 mask = mc13892_regulators[id].enable_bit;
336 
337  dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
338 
339  /* Power Gate enable value is 0 */
340  if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
341  en_val = 0;
342 
343  if (id == MC13892_GPO4)
344  mask |= MC13892_POWERMISC_GPO4ADINEN;
345 
346  return mc13892_powermisc_rmw(priv, mask, en_val);
347 }
348 
349 static int mc13892_gpo_regulator_disable(struct regulator_dev *rdev)
350 {
351  struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
352  int id = rdev_get_id(rdev);
353  u32 dis_val = 0;
354 
355  dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
356 
357  /* Power Gate disable value is 1 */
358  if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
359  dis_val = mc13892_regulators[id].enable_bit;
360 
361  return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit,
362  dis_val);
363 }
364 
365 static int mc13892_gpo_regulator_is_enabled(struct regulator_dev *rdev)
366 {
367  struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
368  int ret, id = rdev_get_id(rdev);
369  unsigned int val;
370 
371  mc13xxx_lock(priv->mc13xxx);
372  ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
373  mc13xxx_unlock(priv->mc13xxx);
374 
375  if (ret)
376  return ret;
377 
378  /* Power Gates state is stored in powermisc_pwgt_state
379  * where the meaning of bits is negated */
380  val = (val & ~MC13892_POWERMISC_PWGTSPI_M) |
381  (priv->powermisc_pwgt_state ^ MC13892_POWERMISC_PWGTSPI_M);
382 
383  return (val & mc13892_regulators[id].enable_bit) != 0;
384 }
385 
386 
387 static struct regulator_ops mc13892_gpo_regulator_ops = {
388  .enable = mc13892_gpo_regulator_enable,
389  .disable = mc13892_gpo_regulator_disable,
390  .is_enabled = mc13892_gpo_regulator_is_enabled,
391  .list_voltage = regulator_list_voltage_table,
392  .set_voltage = mc13xxx_fixed_regulator_set_voltage,
393 };
394 
395 static int mc13892_sw_regulator_get_voltage_sel(struct regulator_dev *rdev)
396 {
397  struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
398  int ret, id = rdev_get_id(rdev);
399  unsigned int val;
400 
401  dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
402 
403  mc13xxx_lock(priv->mc13xxx);
404  ret = mc13xxx_reg_read(priv->mc13xxx,
405  mc13892_regulators[id].vsel_reg, &val);
406  mc13xxx_unlock(priv->mc13xxx);
407  if (ret)
408  return ret;
409 
410  val = (val & mc13892_regulators[id].vsel_mask)
411  >> mc13892_regulators[id].vsel_shift;
412 
413  dev_dbg(rdev_get_dev(rdev), "%s id: %d val: %d\n", __func__, id, val);
414 
415  return val;
416 }
417 
418 static int mc13892_sw_regulator_set_voltage_sel(struct regulator_dev *rdev,
419  unsigned selector)
420 {
421  struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
422  int volt, mask, id = rdev_get_id(rdev);
423  u32 reg_value;
424  int ret;
425 
426  volt = rdev->desc->volt_table[selector];
427  mask = mc13892_regulators[id].vsel_mask;
428  reg_value = selector << mc13892_regulators[id].vsel_shift;
429 
430  if (volt > 1375000) {
431  mask |= MC13892_SWITCHERS0_SWxHI;
432  reg_value |= MC13892_SWITCHERS0_SWxHI;
433  } else if (volt < 1100000) {
434  mask |= MC13892_SWITCHERS0_SWxHI;
435  reg_value &= ~MC13892_SWITCHERS0_SWxHI;
436  }
437 
438  mc13xxx_lock(priv->mc13xxx);
439  ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].reg, mask,
440  reg_value);
441  mc13xxx_unlock(priv->mc13xxx);
442 
443  return ret;
444 }
445 
446 static struct regulator_ops mc13892_sw_regulator_ops = {
447  .list_voltage = regulator_list_voltage_table,
448  .set_voltage_sel = mc13892_sw_regulator_set_voltage_sel,
449  .get_voltage_sel = mc13892_sw_regulator_get_voltage_sel,
450 };
451 
452 static int mc13892_vcam_set_mode(struct regulator_dev *rdev, unsigned int mode)
453 {
454  unsigned int en_val = 0;
455  struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
456  int ret, id = rdev_get_id(rdev);
457 
458  if (mode == REGULATOR_MODE_FAST)
459  en_val = MC13892_REGULATORMODE1_VCAMCONFIGEN;
460 
461  mc13xxx_lock(priv->mc13xxx);
462  ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].reg,
463  MC13892_REGULATORMODE1_VCAMCONFIGEN, en_val);
464  mc13xxx_unlock(priv->mc13xxx);
465 
466  return ret;
467 }
468 
469 static unsigned int mc13892_vcam_get_mode(struct regulator_dev *rdev)
470 {
471  struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
472  int ret, id = rdev_get_id(rdev);
473  unsigned int val;
474 
475  mc13xxx_lock(priv->mc13xxx);
476  ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
477  mc13xxx_unlock(priv->mc13xxx);
478 
479  if (ret)
480  return ret;
481 
482  if (val & MC13892_REGULATORMODE1_VCAMCONFIGEN)
483  return REGULATOR_MODE_FAST;
484 
485  return REGULATOR_MODE_NORMAL;
486 }
487 
488 
489 static int __devinit mc13892_regulator_probe(struct platform_device *pdev)
490 {
491  struct mc13xxx_regulator_priv *priv;
492  struct mc13xxx *mc13892 = dev_get_drvdata(pdev->dev.parent);
493  struct mc13xxx_regulator_platform_data *pdata =
494  dev_get_platdata(&pdev->dev);
495  struct mc13xxx_regulator_init_data *mc13xxx_data;
496  struct regulator_config config = { };
497  int i, ret;
498  int num_regulators = 0;
499  u32 val;
500 
501  num_regulators = mc13xxx_get_num_regulators_dt(pdev);
502  if (num_regulators <= 0 && pdata)
503  num_regulators = pdata->num_regulators;
504  if (num_regulators <= 0)
505  return -EINVAL;
506 
507  priv = devm_kzalloc(&pdev->dev, sizeof(*priv) +
508  num_regulators * sizeof(priv->regulators[0]),
509  GFP_KERNEL);
510  if (!priv)
511  return -ENOMEM;
512 
513  priv->num_regulators = num_regulators;
514  priv->mc13xxx_regulators = mc13892_regulators;
515  priv->mc13xxx = mc13892;
516  platform_set_drvdata(pdev, priv);
517 
518  mc13xxx_lock(mc13892);
519  ret = mc13xxx_reg_read(mc13892, MC13892_REVISION, &val);
520  if (ret)
521  goto err_unlock;
522 
523  /* enable switch auto mode */
524  if ((val & 0x0000FFFF) == 0x45d0) {
525  ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS4,
526  MC13892_SWITCHERS4_SW1MODE_M |
527  MC13892_SWITCHERS4_SW2MODE_M,
528  MC13892_SWITCHERS4_SW1MODE_AUTO |
529  MC13892_SWITCHERS4_SW2MODE_AUTO);
530  if (ret)
531  goto err_unlock;
532 
533  ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS5,
534  MC13892_SWITCHERS5_SW3MODE_M |
535  MC13892_SWITCHERS5_SW4MODE_M,
536  MC13892_SWITCHERS5_SW3MODE_AUTO |
537  MC13892_SWITCHERS5_SW4MODE_AUTO);
538  if (ret)
539  goto err_unlock;
540  }
541  mc13xxx_unlock(mc13892);
542 
543  mc13892_regulators[MC13892_VCAM].desc.ops->set_mode
544  = mc13892_vcam_set_mode;
545  mc13892_regulators[MC13892_VCAM].desc.ops->get_mode
546  = mc13892_vcam_get_mode;
547 
548  mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13892_regulators,
549  ARRAY_SIZE(mc13892_regulators));
550  for (i = 0; i < num_regulators; i++) {
551  struct regulator_init_data *init_data;
552  struct regulator_desc *desc;
553  struct device_node *node = NULL;
554  int id;
555 
556  if (mc13xxx_data) {
557  id = mc13xxx_data[i].id;
558  init_data = mc13xxx_data[i].init_data;
559  node = mc13xxx_data[i].node;
560  } else {
561  id = pdata->regulators[i].id;
562  init_data = pdata->regulators[i].init_data;
563  }
564  desc = &mc13892_regulators[id].desc;
565 
566  config.dev = &pdev->dev;
567  config.init_data = init_data;
568  config.driver_data = priv;
569  config.of_node = node;
570 
571  priv->regulators[i] = regulator_register(desc, &config);
572  if (IS_ERR(priv->regulators[i])) {
573  dev_err(&pdev->dev, "failed to register regulator %s\n",
574  mc13892_regulators[i].desc.name);
575  ret = PTR_ERR(priv->regulators[i]);
576  goto err;
577  }
578  }
579 
580  return 0;
581 err:
582  while (--i >= 0)
583  regulator_unregister(priv->regulators[i]);
584  return ret;
585 
586 err_unlock:
587  mc13xxx_unlock(mc13892);
588  return ret;
589 }
590 
591 static int __devexit mc13892_regulator_remove(struct platform_device *pdev)
592 {
593  struct mc13xxx_regulator_priv *priv = platform_get_drvdata(pdev);
594  int i;
595 
596  platform_set_drvdata(pdev, NULL);
597 
598  for (i = 0; i < priv->num_regulators; i++)
599  regulator_unregister(priv->regulators[i]);
600 
601  return 0;
602 }
603 
604 static struct platform_driver mc13892_regulator_driver = {
605  .driver = {
606  .name = "mc13892-regulator",
607  .owner = THIS_MODULE,
608  },
609  .remove = __devexit_p(mc13892_regulator_remove),
610  .probe = mc13892_regulator_probe,
611 };
612 
613 static int __init mc13892_regulator_init(void)
614 {
615  return platform_driver_register(&mc13892_regulator_driver);
616 }
617 subsys_initcall(mc13892_regulator_init);
618 
619 static void __exit mc13892_regulator_exit(void)
620 {
621  platform_driver_unregister(&mc13892_regulator_driver);
622 }
623 module_exit(mc13892_regulator_exit);
624 
625 MODULE_LICENSE("GPL v2");
626 MODULE_AUTHOR("Yong Shen <[email protected]>");
627 MODULE_DESCRIPTION("Regulator Driver for Freescale MC13892 PMIC");
628 MODULE_ALIAS("platform:mc13892-regulator");
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