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Data Structures | Macros | Typedefs
mi_pc.h File Reference

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Data Structures

struct  mp_xcptcontext_s
 
struct  mp_load
 

Macros

#define BRI_MEMORY_BASE   0x1f700000
 
#define BRI_MEMORY_SIZE   0x00100000 /* 1MB on the BRI */
 
#define BRI_SHARED_RAM_SIZE   0x00010000 /* 64k shared RAM */
 
#define BRI_RAY_TAYLOR_DSP_CODE_SIZE   0x00020000 /* max 128k DSP-Code (Ray Taylor's code) */
 
#define BRI_ORG_MAX_DSP_CODE_SIZE   0x00050000 /* max 320k DSP-Code (Telindus) */
 
#define BRI_V90D_MAX_DSP_CODE_SIZE   0x00060000 /* max 384k DSP-Code if V.90D included */
 
#define BRI_CACHED_ADDR(x)   (((x) & 0x1fffffffL) | 0x80000000L)
 
#define BRI_UNCACHED_ADDR(x)   (((x) & 0x1fffffffL) | 0xa0000000L)
 
#define ADDR   4
 
#define ADDRH   6
 
#define DATA   0
 
#define RESET   7
 
#define DEFAULT_ADDRESS   0x240
 
#define DEFAULT_IRQ   3
 
#define M_PCI_ADDR   0x04 /* MAESTRA BRI PCI */
 
#define M_PCI_ADDRH   0x0c /* MAESTRA BRI PCI */
 
#define M_PCI_DATA   0x00 /* MAESTRA BRI PCI */
 
#define M_PCI_RESET   0x10 /* MAESTRA BRI PCI */
 
#define MP_IRQ_RESET   0xc18 /* offset of isr in the CONFIG memory bar */
 
#define MP_IRQ_RESET_VAL   0xfe /* value to clear an interrupt */
 
#define MP_MEMORY_SIZE   0x00400000 /* 4MB on standard PRI */
 
#define MP2_MEMORY_SIZE   0x00800000 /* 8MB on PRI Rev. 2 */
 
#define MP_SHARED_RAM_OFFSET   0x00001000 /* offset of shared RAM base in the DRAM memory bar */
 
#define MP_SHARED_RAM_SIZE   0x00010000 /* 64k shared RAM */
 
#define MP_PROTOCOL_OFFSET   (MP_SHARED_RAM_OFFSET + MP_SHARED_RAM_SIZE)
 
#define MP_RAY_TAYLOR_DSP_CODE_SIZE   0x00040000 /* max 256k DSP-Code (Ray Taylor's code) */
 
#define MP_ORG_MAX_DSP_CODE_SIZE   0x00060000 /* max 384k DSP-Code (Telindus) */
 
#define MP_V90D_MAX_DSP_CODE_SIZE   0x00070000 /* max 448k DSP-Code if V.90D included) */
 
#define MP_VOIP_MAX_DSP_CODE_SIZE   0x00090000 /* max 576k DSP-Code if voice over IP included */
 
#define MP_CACHED_ADDR(x)   (((x) & 0x1fffffffL) | 0x80000000L)
 
#define MP_UNCACHED_ADDR(x)   (((x) & 0x1fffffffL) | 0xa0000000L)
 
#define MP_RESET   0x20 /* offset of RESET register in the DEVICES memory bar */
 
#define _MP_S2M_RESET   0x10 /* active lo */
 
#define _MP_LED2   0x08 /* 1 = on */
 
#define _MP_LED1   0x04 /* 1 = on */
 
#define _MP_DSP_RESET   0x02 /* active lo */
 
#define _MP_RISC_RESET   0x81 /* active hi, bit 7 for compatibility with old boards */
 
#define MQ_BOARD_REG_OFFSET   0x800000 /* PC relative On board registers offset */
 
#define MQ_BREG_RISC   0x1200 /* RISC Reset ect */
 
#define MQ_RISC_COLD_RESET_MASK   0x0001 /* RISC Cold reset */
 
#define MQ_RISC_WARM_RESET_MASK   0x0002 /* RISC Warm reset */
 
#define MQ_BREG_IRQ_TEST   0x0608 /* Interrupt request, no CPU interaction */
 
#define MQ_IRQ_REQ_ON   0x1
 
#define MQ_IRQ_REQ_OFF   0x0
 
#define MQ_BOARD_DSP_OFFSET   0xa00000 /* PC relative On board DSP regs offset */
 
#define MQ_DSP1_ADDR_OFFSET   0x0008 /* Addr register offset DSP 1 subboard 1 */
 
#define MQ_DSP2_ADDR_OFFSET   0x0208 /* Addr register offset DSP 2 subboard 1 */
 
#define MQ_DSP1_DATA_OFFSET   0x0000 /* Data register offset DSP 1 subboard 1 */
 
#define MQ_DSP2_DATA_OFFSET   0x0200 /* Data register offset DSP 2 subboard 1 */
 
#define MQ_DSP_JUNK_OFFSET   0x0400 /* DSP Data/Addr regs subboard offset */
 
#define MQ_ISAC_DSP_RESET   0x0028 /* ISAC and DSP reset address offset */
 
#define MQ_BOARD_ISAC_DSP_RESET   0x800028 /* ISAC and DSP reset address offset */
 
#define MQ_INSTANCE_COUNT   4 /* 4BRI consists of four instances */
 
#define MQ_MEMORY_SIZE   0x00400000 /* 4MB on standard 4BRI */
 
#define MQ_CTRL_SIZE   0x00002000 /* 8K memory mapped registers */
 
#define MQ_SHARED_RAM_SIZE   0x00010000 /* 64k shared RAM */
 
#define MQ_ORG_MAX_DSP_CODE_SIZE   0x00050000 /* max 320k DSP-Code (Telindus) */
 
#define MQ_V90D_MAX_DSP_CODE_SIZE   0x00060000 /* max 384K DSP-Code if V.90D included */
 
#define MQ_VOIP_MAX_DSP_CODE_SIZE   0x00028000 /* max 4*160k = 640K DSP-Code if voice over IP included */
 
#define MQ_CACHED_ADDR(x)   (((x) & 0x1fffffffL) | 0x80000000L)
 
#define MQ_UNCACHED_ADDR(x)   (((x) & 0x1fffffffL) | 0xa0000000L)
 
#define MQ2_BREG_RISC   0x0200 /* RISC Reset ect */
 
#define MQ2_BREG_IRQ_TEST   0x0400 /* Interrupt request, no CPU interaction */
 
#define MQ2_BOARD_DSP_OFFSET   0x800000 /* PC relative On board DSP regs offset */
 
#define MQ2_DSP1_DATA_OFFSET   0x1800 /* Data register offset DSP 1 subboard 1 */
 
#define MQ2_DSP1_ADDR_OFFSET   0x1808 /* Addr register offset DSP 1 subboard 1 */
 
#define MQ2_DSP2_DATA_OFFSET   0x1810 /* Data register offset DSP 2 subboard 1 */
 
#define MQ2_DSP2_ADDR_OFFSET   0x1818 /* Addr register offset DSP 2 subboard 1 */
 
#define MQ2_DSP_JUNK_OFFSET   0x1000 /* DSP Data/Addr regs subboard offset */
 
#define MQ2_ISAC_DSP_RESET   0x0000 /* ISAC and DSP reset address offset */
 
#define MQ2_BOARD_ISAC_DSP_RESET   0x800000 /* ISAC and DSP reset address offset */
 
#define MQ2_IPACX_CONFIG   0x0300 /* IPACX Configuration TE(0)/NT(1) */
 
#define MQ2_BOARD_IPACX_CONFIG   0x800300 /* "" */
 
#define MQ2_MEMORY_SIZE   0x01000000 /* 16MB code/data memory */
 
#define MQ2_CTRL_SIZE   0x00008000 /* 32K memory mapped registers */
 
#define BRI2_MEMORY_SIZE   0x00800000 /* 8MB code/data memory */
 
#define BRI2_PROTOCOL_MEMORY_SIZE   (MQ2_MEMORY_SIZE >> 2) /* same as one 4BRI Rev.2 task */
 
#define BRI2_CTRL_SIZE   0x00008000 /* 32K memory mapped registers */
 
#define M_INSTANCE_COUNT   1 /* BRI consists of one instance */
 
#define ID_REG   0x0000 /*Pci reg-contain the Dev&Ven ID of the card*/
 
#define RAS0_BASEREG   0x0010 /*Ras0 register - contain the base addr Ras0*/
 
#define RAS2_BASEREG   0x0014
 
#define CS_BASEREG   0x0018
 
#define BOOT_BASEREG   0x001c
 
#define GTREGS_BASEREG   0x0024 /*GTRegsBase reg-contain the base addr where*/
 
#define LOW_RAS0_DREG   0x0400 /*Ras0 low decode address*/
 
#define HI_RAS0_DREG   0x0404 /*Ras0 high decode address*/
 
#define LOW_RAS1_DREG   0x0408 /*Ras1 low decode address*/
 
#define HI_RAS1_DREG   0x040c /*Ras1 high decode address*/
 
#define LOW_RAS2_DREG   0x0410 /*Ras2 low decode address*/
 
#define HI_RAS2_DREG   0x0414 /*Ras2 high decode address*/
 
#define LOW_RAS3_DREG   0x0418 /*Ras3 low decode address*/
 
#define HI_RAS3_DREG   0x041c /*Ras3 high decode address*/
 
#define LOW_CS0_DREG   0x0420 /* CS0* low decode register */
 
#define HI_CS0_DREG   0x0424 /* CS0* high decode register */
 
#define LOW_CS1_DREG   0x0428 /* CS1* low decode register */
 
#define HI_CS1_DREG   0x042c /* CS1* high decode register */
 
#define LOW_CS2_DREG   0x0430 /* CS2* low decode register */
 
#define HI_CS2_DREG   0x0434 /* CS2* high decode register */
 
#define LOW_CS3_DREG   0x0438 /* CS3* low decode register */
 
#define HI_CS3_DREG   0x043c /* CS3* high decode register */
 
#define LOW_BOOTCS_DREG   0x0440 /* Boot CS low decode register */
 
#define HI_BOOTCS_DREG   0x0444 /* Boot CS High decode register */
 
#define LO_RAS10_GREG   0x0008 /*Ras1..0 group low decode address*/
 
#define HI_RAS10_GREG   0x0010 /*Ras1..0 group high decode address*/
 
#define LO_RAS32_GREG   0x0018 /*Ras3..2 group low decode address */
 
#define HI_RAS32_GREG   0x0020 /*Ras3..2 group high decode address */
 
#define LO_CS20_GREG   0x0028 /* CS2..0 group low decode register */
 
#define HI_CS20_GREG   0x0030 /* CS2..0 group high decode register */
 
#define LO_CS3B_GREG   0x0038 /* CS3 & PROM group low decode register */
 
#define HI_CS3B_GREG   0x0040 /* CS3 & PROM group high decode register */
 
#define PCI_TIMEOUT_RET   0x0c04 /* Time Out and retry register */
 
#define RAS10_BANKSIZE   0x0c08 /* RAS 1..0 group PCI bank size */
 
#define RAS32_BANKSIZE   0x0c0c /* RAS 3..2 group PCI bank size */
 
#define CS20_BANKSIZE   0x0c10 /* CS 2..0 group PCI bank size */
 
#define CS3B_BANKSIZE   0x0c14 /* CS 3 & Boot group PCI bank size */
 
#define DRAM_SIZE   0x0001 /*Dram size in mega bytes*/
 
#define PROM_SIZE   0x08000 /*Prom size in bytes*/
 
#define OFFS_DIVA_INIT_TASK_COUNT   0x68
 
#define OFFS_DSP_CODE_BASE_ADDR   0x6c
 
#define OFFS_XLOG_BUF_ADDR   0x70
 
#define OFFS_XLOG_COUNT_ADDR   0x74
 
#define OFFS_XLOG_OUT_ADDR   0x78
 
#define OFFS_PROTOCOL_END_ADDR   0x7c
 
#define OFFS_PROTOCOL_ID_STRING   0x80
 

Typedefs

typedef struct mp_xcptcontext_s MP_XCPTC
 

Macro Definition Documentation

#define _MP_DSP_RESET   0x02 /* active lo */

Definition at line 66 of file mi_pc.h.

#define _MP_LED1   0x04 /* 1 = on */

Definition at line 65 of file mi_pc.h.

#define _MP_LED2   0x08 /* 1 = on */

Definition at line 64 of file mi_pc.h.

#define _MP_RISC_RESET   0x81 /* active hi, bit 7 for compatibility with old boards */

Definition at line 67 of file mi_pc.h.

#define _MP_S2M_RESET   0x10 /* active lo */

Definition at line 63 of file mi_pc.h.

#define ADDR   4

Definition at line 36 of file mi_pc.h.

#define ADDRH   6

Definition at line 37 of file mi_pc.h.

#define BOOT_BASEREG   0x001c

Definition at line 151 of file mi_pc.h.

#define BRI2_CTRL_SIZE   0x00008000 /* 32K memory mapped registers */

Definition at line 142 of file mi_pc.h.

#define BRI2_MEMORY_SIZE   0x00800000 /* 8MB code/data memory */

Definition at line 140 of file mi_pc.h.

#define BRI2_PROTOCOL_MEMORY_SIZE   (MQ2_MEMORY_SIZE >> 2) /* same as one 4BRI Rev.2 task */

Definition at line 141 of file mi_pc.h.

#define BRI_CACHED_ADDR (   x)    (((x) & 0x1fffffffL) | 0x80000000L)

Definition at line 34 of file mi_pc.h.

#define BRI_MEMORY_BASE   0x1f700000

Definition at line 28 of file mi_pc.h.

#define BRI_MEMORY_SIZE   0x00100000 /* 1MB on the BRI */

Definition at line 29 of file mi_pc.h.

#define BRI_ORG_MAX_DSP_CODE_SIZE   0x00050000 /* max 320k DSP-Code (Telindus) */

Definition at line 32 of file mi_pc.h.

#define BRI_RAY_TAYLOR_DSP_CODE_SIZE   0x00020000 /* max 128k DSP-Code (Ray Taylor's code) */

Definition at line 31 of file mi_pc.h.

#define BRI_SHARED_RAM_SIZE   0x00010000 /* 64k shared RAM */

Definition at line 30 of file mi_pc.h.

#define BRI_UNCACHED_ADDR (   x)    (((x) & 0x1fffffffL) | 0xa0000000L)

Definition at line 35 of file mi_pc.h.

#define BRI_V90D_MAX_DSP_CODE_SIZE   0x00060000 /* max 384k DSP-Code if V.90D included */

Definition at line 33 of file mi_pc.h.

#define CS20_BANKSIZE   0x0c10 /* CS 2..0 group PCI bank size */

Definition at line 192 of file mi_pc.h.

#define CS3B_BANKSIZE   0x0c14 /* CS 3 & Boot group PCI bank size */

Definition at line 193 of file mi_pc.h.

#define CS_BASEREG   0x0018

Definition at line 150 of file mi_pc.h.

#define DATA   0

Definition at line 38 of file mi_pc.h.

#define DEFAULT_ADDRESS   0x240

Definition at line 40 of file mi_pc.h.

#define DEFAULT_IRQ   3

Definition at line 41 of file mi_pc.h.

#define DRAM_SIZE   0x0001 /*Dram size in mega bytes*/

Definition at line 194 of file mi_pc.h.

#define GTREGS_BASEREG   0x0024 /*GTRegsBase reg-contain the base addr where*/

Definition at line 152 of file mi_pc.h.

#define HI_BOOTCS_DREG   0x0444 /* Boot CS High decode register */

Definition at line 177 of file mi_pc.h.

#define HI_CS0_DREG   0x0424 /* CS0* high decode register */

Definition at line 168 of file mi_pc.h.

#define HI_CS1_DREG   0x042c /* CS1* high decode register */

Definition at line 170 of file mi_pc.h.

#define HI_CS20_GREG   0x0030 /* CS2..0 group high decode register */

Definition at line 185 of file mi_pc.h.

#define HI_CS2_DREG   0x0434 /* CS2* high decode register */

Definition at line 172 of file mi_pc.h.

#define HI_CS3_DREG   0x043c /* CS3* high decode register */

Definition at line 174 of file mi_pc.h.

#define HI_CS3B_GREG   0x0040 /* CS3 & PROM group high decode register */

Definition at line 187 of file mi_pc.h.

#define HI_RAS0_DREG   0x0404 /*Ras0 high decode address*/

Definition at line 159 of file mi_pc.h.

#define HI_RAS10_GREG   0x0010 /*Ras1..0 group high decode address*/

Definition at line 180 of file mi_pc.h.

#define HI_RAS1_DREG   0x040c /*Ras1 high decode address*/

Definition at line 161 of file mi_pc.h.

#define HI_RAS2_DREG   0x0414 /*Ras2 high decode address*/

Definition at line 163 of file mi_pc.h.

#define HI_RAS32_GREG   0x0020 /*Ras3..2 group high decode address */

Definition at line 182 of file mi_pc.h.

#define HI_RAS3_DREG   0x041c /*Ras3 high decode address*/

Definition at line 165 of file mi_pc.h.

#define ID_REG   0x0000 /*Pci reg-contain the Dev&Ven ID of the card*/

Definition at line 147 of file mi_pc.h.

#define LO_CS20_GREG   0x0028 /* CS2..0 group low decode register */

Definition at line 184 of file mi_pc.h.

#define LO_CS3B_GREG   0x0038 /* CS3 & PROM group low decode register */

Definition at line 186 of file mi_pc.h.

#define LO_RAS10_GREG   0x0008 /*Ras1..0 group low decode address*/

Definition at line 179 of file mi_pc.h.

#define LO_RAS32_GREG   0x0018 /*Ras3..2 group low decode address */

Definition at line 181 of file mi_pc.h.

#define LOW_BOOTCS_DREG   0x0440 /* Boot CS low decode register */

Definition at line 176 of file mi_pc.h.

#define LOW_CS0_DREG   0x0420 /* CS0* low decode register */

Definition at line 167 of file mi_pc.h.

#define LOW_CS1_DREG   0x0428 /* CS1* low decode register */

Definition at line 169 of file mi_pc.h.

#define LOW_CS2_DREG   0x0430 /* CS2* low decode register */

Definition at line 171 of file mi_pc.h.

#define LOW_CS3_DREG   0x0438 /* CS3* low decode register */

Definition at line 173 of file mi_pc.h.

#define LOW_RAS0_DREG   0x0400 /*Ras0 low decode address*/

Definition at line 158 of file mi_pc.h.

#define LOW_RAS1_DREG   0x0408 /*Ras1 low decode address*/

Definition at line 160 of file mi_pc.h.

#define LOW_RAS2_DREG   0x0410 /*Ras2 low decode address*/

Definition at line 162 of file mi_pc.h.

#define LOW_RAS3_DREG   0x0418 /*Ras3 low decode address*/

Definition at line 164 of file mi_pc.h.

#define M_INSTANCE_COUNT   1 /* BRI consists of one instance */

Definition at line 143 of file mi_pc.h.

#define M_PCI_ADDR   0x04 /* MAESTRA BRI PCI */

Definition at line 42 of file mi_pc.h.

#define M_PCI_ADDRH   0x0c /* MAESTRA BRI PCI */

Definition at line 43 of file mi_pc.h.

#define M_PCI_DATA   0x00 /* MAESTRA BRI PCI */

Definition at line 44 of file mi_pc.h.

#define M_PCI_RESET   0x10 /* MAESTRA BRI PCI */

Definition at line 45 of file mi_pc.h.

#define MP2_MEMORY_SIZE   0x00800000 /* 8MB on PRI Rev. 2 */

Definition at line 51 of file mi_pc.h.

#define MP_CACHED_ADDR (   x)    (((x) & 0x1fffffffL) | 0x80000000L)

Definition at line 59 of file mi_pc.h.

#define MP_IRQ_RESET   0xc18 /* offset of isr in the CONFIG memory bar */

Definition at line 48 of file mi_pc.h.

#define MP_IRQ_RESET_VAL   0xfe /* value to clear an interrupt */

Definition at line 49 of file mi_pc.h.

#define MP_MEMORY_SIZE   0x00400000 /* 4MB on standard PRI */

Definition at line 50 of file mi_pc.h.

#define MP_ORG_MAX_DSP_CODE_SIZE   0x00060000 /* max 384k DSP-Code (Telindus) */

Definition at line 56 of file mi_pc.h.

#define MP_PROTOCOL_OFFSET   (MP_SHARED_RAM_OFFSET + MP_SHARED_RAM_SIZE)

Definition at line 54 of file mi_pc.h.

#define MP_RAY_TAYLOR_DSP_CODE_SIZE   0x00040000 /* max 256k DSP-Code (Ray Taylor's code) */

Definition at line 55 of file mi_pc.h.

#define MP_RESET   0x20 /* offset of RESET register in the DEVICES memory bar */

Definition at line 61 of file mi_pc.h.

#define MP_SHARED_RAM_OFFSET   0x00001000 /* offset of shared RAM base in the DRAM memory bar */

Definition at line 52 of file mi_pc.h.

#define MP_SHARED_RAM_SIZE   0x00010000 /* 64k shared RAM */

Definition at line 53 of file mi_pc.h.

#define MP_UNCACHED_ADDR (   x)    (((x) & 0x1fffffffL) | 0xa0000000L)

Definition at line 60 of file mi_pc.h.

#define MP_V90D_MAX_DSP_CODE_SIZE   0x00070000 /* max 448k DSP-Code if V.90D included) */

Definition at line 57 of file mi_pc.h.

#define MP_VOIP_MAX_DSP_CODE_SIZE   0x00090000 /* max 576k DSP-Code if voice over IP included */

Definition at line 58 of file mi_pc.h.

#define MQ2_BOARD_DSP_OFFSET   0x800000 /* PC relative On board DSP regs offset */

Definition at line 126 of file mi_pc.h.

#define MQ2_BOARD_IPACX_CONFIG   0x800300 /* "" */

Definition at line 135 of file mi_pc.h.

#define MQ2_BOARD_ISAC_DSP_RESET   0x800000 /* ISAC and DSP reset address offset */

Definition at line 133 of file mi_pc.h.

#define MQ2_BREG_IRQ_TEST   0x0400 /* Interrupt request, no CPU interaction */

Definition at line 125 of file mi_pc.h.

#define MQ2_BREG_RISC   0x0200 /* RISC Reset ect */

Definition at line 124 of file mi_pc.h.

#define MQ2_CTRL_SIZE   0x00008000 /* 32K memory mapped registers */

Definition at line 137 of file mi_pc.h.

#define MQ2_DSP1_ADDR_OFFSET   0x1808 /* Addr register offset DSP 1 subboard 1 */

Definition at line 128 of file mi_pc.h.

#define MQ2_DSP1_DATA_OFFSET   0x1800 /* Data register offset DSP 1 subboard 1 */

Definition at line 127 of file mi_pc.h.

#define MQ2_DSP2_ADDR_OFFSET   0x1818 /* Addr register offset DSP 2 subboard 1 */

Definition at line 130 of file mi_pc.h.

#define MQ2_DSP2_DATA_OFFSET   0x1810 /* Data register offset DSP 2 subboard 1 */

Definition at line 129 of file mi_pc.h.

#define MQ2_DSP_JUNK_OFFSET   0x1000 /* DSP Data/Addr regs subboard offset */

Definition at line 131 of file mi_pc.h.

#define MQ2_IPACX_CONFIG   0x0300 /* IPACX Configuration TE(0)/NT(1) */

Definition at line 134 of file mi_pc.h.

#define MQ2_ISAC_DSP_RESET   0x0000 /* ISAC and DSP reset address offset */

Definition at line 132 of file mi_pc.h.

#define MQ2_MEMORY_SIZE   0x01000000 /* 16MB code/data memory */

Definition at line 136 of file mi_pc.h.

#define MQ_BOARD_DSP_OFFSET   0xa00000 /* PC relative On board DSP regs offset */

Definition at line 105 of file mi_pc.h.

#define MQ_BOARD_ISAC_DSP_RESET   0x800028 /* ISAC and DSP reset address offset */

Definition at line 112 of file mi_pc.h.

#define MQ_BOARD_REG_OFFSET   0x800000 /* PC relative On board registers offset */

Definition at line 98 of file mi_pc.h.

#define MQ_BREG_IRQ_TEST   0x0608 /* Interrupt request, no CPU interaction */

Definition at line 102 of file mi_pc.h.

#define MQ_BREG_RISC   0x1200 /* RISC Reset ect */

Definition at line 99 of file mi_pc.h.

#define MQ_CACHED_ADDR (   x)    (((x) & 0x1fffffffL) | 0x80000000L)

Definition at line 120 of file mi_pc.h.

#define MQ_CTRL_SIZE   0x00002000 /* 8K memory mapped registers */

Definition at line 115 of file mi_pc.h.

#define MQ_DSP1_ADDR_OFFSET   0x0008 /* Addr register offset DSP 1 subboard 1 */

Definition at line 106 of file mi_pc.h.

#define MQ_DSP1_DATA_OFFSET   0x0000 /* Data register offset DSP 1 subboard 1 */

Definition at line 108 of file mi_pc.h.

#define MQ_DSP2_ADDR_OFFSET   0x0208 /* Addr register offset DSP 2 subboard 1 */

Definition at line 107 of file mi_pc.h.

#define MQ_DSP2_DATA_OFFSET   0x0200 /* Data register offset DSP 2 subboard 1 */

Definition at line 109 of file mi_pc.h.

#define MQ_DSP_JUNK_OFFSET   0x0400 /* DSP Data/Addr regs subboard offset */

Definition at line 110 of file mi_pc.h.

#define MQ_INSTANCE_COUNT   4 /* 4BRI consists of four instances */

Definition at line 113 of file mi_pc.h.

#define MQ_IRQ_REQ_OFF   0x0

Definition at line 104 of file mi_pc.h.

#define MQ_IRQ_REQ_ON   0x1

Definition at line 103 of file mi_pc.h.

#define MQ_ISAC_DSP_RESET   0x0028 /* ISAC and DSP reset address offset */

Definition at line 111 of file mi_pc.h.

#define MQ_MEMORY_SIZE   0x00400000 /* 4MB on standard 4BRI */

Definition at line 114 of file mi_pc.h.

#define MQ_ORG_MAX_DSP_CODE_SIZE   0x00050000 /* max 320k DSP-Code (Telindus) */

Definition at line 117 of file mi_pc.h.

#define MQ_RISC_COLD_RESET_MASK   0x0001 /* RISC Cold reset */

Definition at line 100 of file mi_pc.h.

#define MQ_RISC_WARM_RESET_MASK   0x0002 /* RISC Warm reset */

Definition at line 101 of file mi_pc.h.

#define MQ_SHARED_RAM_SIZE   0x00010000 /* 64k shared RAM */

Definition at line 116 of file mi_pc.h.

#define MQ_UNCACHED_ADDR (   x)    (((x) & 0x1fffffffL) | 0xa0000000L)

Definition at line 121 of file mi_pc.h.

#define MQ_V90D_MAX_DSP_CODE_SIZE   0x00060000 /* max 384K DSP-Code if V.90D included */

Definition at line 118 of file mi_pc.h.

#define MQ_VOIP_MAX_DSP_CODE_SIZE   0x00028000 /* max 4*160k = 640K DSP-Code if voice over IP included */

Definition at line 119 of file mi_pc.h.

#define OFFS_DIVA_INIT_TASK_COUNT   0x68

Definition at line 197 of file mi_pc.h.

#define OFFS_DSP_CODE_BASE_ADDR   0x6c

Definition at line 198 of file mi_pc.h.

#define OFFS_PROTOCOL_END_ADDR   0x7c

Definition at line 202 of file mi_pc.h.

#define OFFS_PROTOCOL_ID_STRING   0x80

Definition at line 203 of file mi_pc.h.

#define OFFS_XLOG_BUF_ADDR   0x70

Definition at line 199 of file mi_pc.h.

#define OFFS_XLOG_COUNT_ADDR   0x74

Definition at line 200 of file mi_pc.h.

#define OFFS_XLOG_OUT_ADDR   0x78

Definition at line 201 of file mi_pc.h.

#define PCI_TIMEOUT_RET   0x0c04 /* Time Out and retry register */

Definition at line 189 of file mi_pc.h.

#define PROM_SIZE   0x08000 /*Prom size in bytes*/

Definition at line 195 of file mi_pc.h.

#define RAS0_BASEREG   0x0010 /*Ras0 register - contain the base addr Ras0*/

Definition at line 148 of file mi_pc.h.

#define RAS10_BANKSIZE   0x0c08 /* RAS 1..0 group PCI bank size */

Definition at line 190 of file mi_pc.h.

#define RAS2_BASEREG   0x0014

Definition at line 149 of file mi_pc.h.

#define RAS32_BANKSIZE   0x0c0c /* RAS 3..2 group PCI bank size */

Definition at line 191 of file mi_pc.h.

#define RESET   7

Definition at line 39 of file mi_pc.h.

Typedef Documentation

Definition at line 69 of file mi_pc.h.