|
| enum | mite_registers {
MITE_UNKNOWN_DMA_BURST_REG = 0x28,
MITE_IODWBSR = 0xc0,
MITE_IODWBSR_1 = 0xc4,
MITE_IODWCR_1 = 0xf4,
MITE_PCI_CONFIG_OFFSET = 0x300,
MITE_CSIGR = 0x460
} |
| |
| enum | MITE_IODWBSR_bits { WENAB = 0x80
} |
| |
| enum | MITE_UNKNOWN_DMA_BURST_bits { UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
} |
| |
| enum | MITE_MCR_bits { MCRPON = 0
} |
| |
| enum | MITE_DCR_bits { DCR_NORMAL = (1 << 29),
DCRPON = 0
} |
| |
| enum | MITE_CHOR_bits {
CHOR_DMARESET = (1 << 31),
CHOR_SET_SEND_TC = (1 << 11),
CHOR_CLR_SEND_TC = (1 << 10),
CHOR_SET_LPAUSE = (1 << 9),
CHOR_CLR_LPAUSE = (1 << 8),
CHOR_CLRDONE = (1 << 7),
CHOR_CLRRB = (1 << 6),
CHOR_CLRLC = (1 << 5),
CHOR_FRESET = (1 << 4),
CHOR_ABORT = (1 << 3),
CHOR_STOP = (1 << 2),
CHOR_CONT = (1 << 1),
CHOR_START = (1 << 0),
CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE)
} |
| |
| enum | MITE_CHCR_bits {
CHCR_SET_DMA_IE = (1 << 31),
CHCR_CLR_DMA_IE = (1 << 30),
CHCR_SET_LINKP_IE = (1 << 29),
CHCR_CLR_LINKP_IE = (1 << 28),
CHCR_SET_SAR_IE = (1 << 27),
CHCR_CLR_SAR_IE = (1 << 26),
CHCR_SET_DONE_IE = (1 << 25),
CHCR_CLR_DONE_IE = (1 << 24),
CHCR_SET_MRDY_IE = (1 << 23),
CHCR_CLR_MRDY_IE = (1 << 22),
CHCR_SET_DRDY_IE = (1 << 21),
CHCR_CLR_DRDY_IE = (1 << 20),
CHCR_SET_LC_IE = (1 << 19),
CHCR_CLR_LC_IE = (1 << 18),
CHCR_SET_CONT_RB_IE = (1 << 17),
CHCR_CLR_CONT_RB_IE = (1 << 16),
CHCR_FIFODIS = (1 << 15),
CHCR_FIFO_ON = 0,
CHCR_BURSTEN = (1 << 14),
CHCR_NO_BURSTEN = 0,
CHCR_BYTE_SWAP_DEVICE = (1 << 6),
CHCR_BYTE_SWAP_MEMORY = (1 << 4),
CHCR_DIR = (1 << 3),
CHCR_DEV_TO_MEM = CHCR_DIR,
CHCR_MEM_TO_DEV = 0,
CHCR_NORMAL = (0 << 0),
CHCR_CONTINUE = (1 << 0),
CHCR_RINGBUFF = (2 << 0),
CHCR_LINKSHORT = (4 << 0),
CHCR_LINKLONG = (5 << 0),
CHCRPON
} |
| |
| enum | ConfigRegister_bits {
CR_REQS_MASK = 0x7 << 16,
CR_ASEQDONT = 0x0 << 10,
CR_ASEQUP = 0x1 << 10,
CR_ASEQDOWN = 0x2 << 10,
CR_ASEQ_MASK = 0x3 << 10,
CR_PSIZE8 = (1 << 8),
CR_PSIZE16 = (2 << 8),
CR_PSIZE32 = (3 << 8),
CR_PORTCPU = (0 << 6),
CR_PORTIO = (1 << 6),
CR_PORTVXI = (2 << 6),
CR_PORTMXI = (3 << 6),
CR_AMDEVICE = (1 << 0)
} |
| |
| enum | CHSR_bits {
CHSR_INT = (1 << 31),
CHSR_LPAUSES = (1 << 29),
CHSR_SARS = (1 << 27),
CHSR_DONE = (1 << 25),
CHSR_MRDY = (1 << 23),
CHSR_DRDY = (1 << 21),
CHSR_LINKC = (1 << 19),
CHSR_CONTS_RB = (1 << 17),
CHSR_ERROR = (1 << 15),
CHSR_SABORT = (1 << 14),
CHSR_HABORT = (1 << 13),
CHSR_STOPS = (1 << 12),
CHSR_OPERR_mask = (3 << 10),
CHSR_OPERR_NOERROR = (0 << 10),
CHSR_OPERR_FIFOERROR = (1 << 10),
CHSR_OPERR_LINKERROR = (1 << 10),
CHSR_XFERR = (1 << 9),
CHSR_END = (1 << 8),
CHSR_DRQ1 = (1 << 7),
CHSR_DRQ0 = (1 << 6),
CHSR_LxERR_mask = (3 << 4),
CHSR_LBERR = (1 << 4),
CHSR_LRERR = (2 << 4),
CHSR_LOERR = (3 << 4),
CHSR_MxERR_mask = (3 << 2),
CHSR_MBERR = (1 << 2),
CHSR_MRERR = (2 << 2),
CHSR_MOERR = (3 << 2),
CHSR_DxERR_mask = (3 << 0),
CHSR_DBERR = (1 << 0),
CHSR_DRERR = (2 << 0),
CHSR_DOERR = (3 << 0)
} |
| |
1.8.2