#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/dmaengine.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <mach/regs-icu.h>
#include <linux/platform_data/dma-mmp_tdma.h>
#include <linux/of_device.h>
#include "dmaengine.h"

Data Structures
struct	mmp_tdma_desc

struct	mmp_tdma_chan

struct	mmp_tdma_device

Macros
#define	TDBCR 0x00 /* Byte Count */

#define	TDSAR 0x10 /* Src Addr */

#define	TDDAR 0x20 /* Dst Addr */

#define	TDNDPR 0x30 /* Next Desc */

#define	TDCR 0x40 /* Control */

#define	TDCP 0x60 /* Priority*/

#define	TDCDPR 0x70 /* Current Desc */

#define	TDIMR 0x80 /* Int Mask */

#define	TDISR 0xa0 /* Int Status */

#define	TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */

#define	TDCR_SSZ_12_BITS (0x1 << 22)

#define	TDCR_SSZ_16_BITS (0x2 << 22)

#define	TDCR_SSZ_20_BITS (0x3 << 22)

#define	TDCR_SSZ_24_BITS (0x4 << 22)

#define	TDCR_SSZ_32_BITS (0x5 << 22)

#define	TDCR_SSZ_SHIFT (0x1 << 22)

#define	TDCR_SSZ_MASK (0x7 << 22)

#define	TDCR_SSPMOD (0x1 << 21) /* SSP MOD */

#define	TDCR_ABR (0x1 << 20) /* Channel Abort */

#define	TDCR_CDE (0x1 << 17) /* Close Desc Enable */

#define	TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */

#define	TDCR_CHANACT (0x1 << 14) /* Channel Active */

#define	TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */

#define	TDCR_CHANEN (0x1 << 12) /* Channel Enable */

#define	TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */

#define	TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */

#define	TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */

#define	TDCR_BURSTSZ_4B (0x0 << 6)

#define	TDCR_BURSTSZ_8B (0x1 << 6)

#define	TDCR_BURSTSZ_16B (0x3 << 6)

#define	TDCR_BURSTSZ_32B (0x6 << 6)

#define	TDCR_BURSTSZ_64B (0x7 << 6)

#define	TDCR_BURSTSZ_SQU_32B (0x7 << 6)

#define	TDCR_BURSTSZ_128B (0x5 << 6)

#define	TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */

#define	TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */

#define	TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */

#define	TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */

#define	TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */

#define	TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */

#define	TDCR_DSTDESCCONT (0x1 << 1)

#define	TDCR_SRCDESTCONT (0x1 << 0)

#define	TDIMR_COMP (0x1 << 0)

#define	TDISR_COMP (0x1 << 0)

#define	TDMA_ALIGNMENT 3

#define	TDMA_MAX_XFER_BYTES SZ_64K

#define	TDMA_CHANNEL_NUM 2

#define	to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)

Enumerations
enum	mmp_tdma_type { MMP_AUD_TDMA = 0, PXA910_SQU }

Functions
struct mmp_tdma_desc *	mmp_tdma_alloc_descriptor (struct mmp_tdma_chan *tdmac)

	MODULE_DEVICE_TABLE (of, mmp_tdma_dt_ids)

	module_platform_driver (mmp_tdma_driver)

	MODULE_LICENSE ("GPL")

	MODULE_DESCRIPTION ("MMP Two-Channel DMA Driver")

	MODULE_ALIAS ("platform:mmp-tdma")

	MODULE_AUTHOR ("Leo Yan <[email protected]>")

	MODULE_AUTHOR ("Zhangfei Gao <[email protected]>")

Macro Definition Documentation

#define TDBCR 0x00 /* Byte Count */

Definition at line 30 of file mmp_tdma.c.

#define TDCDPR 0x70 /* Current Desc */

Definition at line 36 of file mmp_tdma.c.

#define TDCP 0x60 /* Priority*/

Definition at line 35 of file mmp_tdma.c.

#define TDCR 0x40 /* Control */

Definition at line 34 of file mmp_tdma.c.

#define TDCR_ABR (0x1 << 20) /* Channel Abort */

Definition at line 50 of file mmp_tdma.c.

#define TDCR_BURSTSZ_128B (0x5 << 6)

Definition at line 65 of file mmp_tdma.c.

#define TDCR_BURSTSZ_16B (0x3 << 6)

Definition at line 61 of file mmp_tdma.c.

#define TDCR_BURSTSZ_32B (0x6 << 6)

Definition at line 62 of file mmp_tdma.c.

#define TDCR_BURSTSZ_4B (0x0 << 6)

Definition at line 59 of file mmp_tdma.c.

#define TDCR_BURSTSZ_64B (0x7 << 6)

Definition at line 63 of file mmp_tdma.c.

#define TDCR_BURSTSZ_8B (0x1 << 6)

Definition at line 60 of file mmp_tdma.c.

#define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */

Definition at line 58 of file mmp_tdma.c.

#define TDCR_BURSTSZ_SQU_32B (0x7 << 6)

Definition at line 64 of file mmp_tdma.c.

#define TDCR_CDE (0x1 << 17) /* Close Desc Enable */

Definition at line 51 of file mmp_tdma.c.

#define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */

Definition at line 57 of file mmp_tdma.c.

#define TDCR_CHANACT (0x1 << 14) /* Channel Active */

Definition at line 53 of file mmp_tdma.c.

#define TDCR_CHANEN (0x1 << 12) /* Channel Enable */

Definition at line 55 of file mmp_tdma.c.

#define TDCR_DSTDESCCONT (0x1 << 1)

Definition at line 72 of file mmp_tdma.c.

#define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */

Definition at line 67 of file mmp_tdma.c.

#define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */

Definition at line 68 of file mmp_tdma.c.

#define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */

Definition at line 66 of file mmp_tdma.c.

#define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */

Definition at line 54 of file mmp_tdma.c.

#define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */

Definition at line 56 of file mmp_tdma.c.

#define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */

Definition at line 52 of file mmp_tdma.c.

#define TDCR_SRCDESTCONT (0x1 << 0)

Definition at line 73 of file mmp_tdma.c.

#define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */

Definition at line 70 of file mmp_tdma.c.

#define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */

Definition at line 71 of file mmp_tdma.c.

#define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */

Definition at line 69 of file mmp_tdma.c.

#define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */

Definition at line 49 of file mmp_tdma.c.

#define TDCR_SSZ_12_BITS (0x1 << 22)

Definition at line 42 of file mmp_tdma.c.

#define TDCR_SSZ_16_BITS (0x2 << 22)

Definition at line 43 of file mmp_tdma.c.

#define TDCR_SSZ_20_BITS (0x3 << 22)

Definition at line 44 of file mmp_tdma.c.

#define TDCR_SSZ_24_BITS (0x4 << 22)

Definition at line 45 of file mmp_tdma.c.

#define TDCR_SSZ_32_BITS (0x5 << 22)

Definition at line 46 of file mmp_tdma.c.

#define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */

Definition at line 41 of file mmp_tdma.c.

#define TDCR_SSZ_MASK (0x7 << 22)

Definition at line 48 of file mmp_tdma.c.

#define TDCR_SSZ_SHIFT (0x1 << 22)

Definition at line 47 of file mmp_tdma.c.

#define TDDAR 0x20 /* Dst Addr */

Definition at line 32 of file mmp_tdma.c.

#define TDIMR 0x80 /* Int Mask */

Definition at line 37 of file mmp_tdma.c.

#define TDIMR_COMP (0x1 << 0)

Definition at line 76 of file mmp_tdma.c.

#define TDISR 0xa0 /* Int Status */

Definition at line 38 of file mmp_tdma.c.

#define TDISR_COMP (0x1 << 0)

Definition at line 79 of file mmp_tdma.c.

#define TDMA_ALIGNMENT 3

Definition at line 97 of file mmp_tdma.c.

#define TDMA_CHANNEL_NUM 2

Definition at line 125 of file mmp_tdma.c.

#define TDMA_MAX_XFER_BYTES SZ_64K

Definition at line 98 of file mmp_tdma.c.

#define TDNDPR 0x30 /* Next Desc */

Definition at line 33 of file mmp_tdma.c.

#define TDSAR 0x10 /* Src Addr */

Definition at line 31 of file mmp_tdma.c.

#define to_mmp_tdma_chan ( dchan ) container_of(dchan, struct mmp_tdma_chan, chan)

Definition at line 133 of file mmp_tdma.c.

Enumeration Type Documentation

enum mmp_tdma_type

Enumerator:

MMP_AUD_TDMA
PXA910_SQU

Definition at line 92 of file mmp_tdma.c.

Function Documentation

struct mmp_tdma_desc* mmp_tdma_alloc_descriptor ( struct mmp_tdma_chan * tdmac )

read

Definition at line 339 of file mmp_tdma.c.

MODULE_ALIAS ( "platform:mmp-tdma" )

MODULE_AUTHOR ( "Leo Yan <[email protected]>" )

MODULE_AUTHOR ( "Zhangfei Gao <[email protected]>" )

MODULE_DESCRIPTION ( "MMP Two-Channel DMA Driver" )

MODULE_DEVICE_TABLE	(	of	,
		mmp_tdma_dt_ids
	)

MODULE_LICENSE ( "GPL" )

module_platform_driver ( mmp_tdma_driver )

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation