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#define | MPI2_VERSION_MAJOR (0x02) |
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#define | MPI2_VERSION_MINOR (0x00) |
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#define | MPI2_VERSION_MAJOR_MASK (0xFF00) |
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#define | MPI2_VERSION_MAJOR_SHIFT (8) |
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#define | MPI2_VERSION_MINOR_MASK (0x00FF) |
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#define | MPI2_VERSION_MINOR_SHIFT (0) |
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#define | MPI2_VERSION |
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#define | MPI2_VERSION_02_00 (0x0200) |
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#define | MPI2_HEADER_VERSION_UNIT (0x19) |
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#define | MPI2_HEADER_VERSION_DEV (0x00) |
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#define | MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) |
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#define | MPI2_HEADER_VERSION_UNIT_SHIFT (8) |
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#define | MPI2_HEADER_VERSION_DEV_MASK (0x00FF) |
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#define | MPI2_HEADER_VERSION_DEV_SHIFT (0) |
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#define | MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) |
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#define | MPI2_IOC_STATE_RESET (0x00000000) |
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#define | MPI2_IOC_STATE_READY (0x10000000) |
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#define | MPI2_IOC_STATE_OPERATIONAL (0x20000000) |
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#define | MPI2_IOC_STATE_FAULT (0x40000000) |
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#define | MPI2_IOC_STATE_MASK (0xF0000000) |
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#define | MPI2_IOC_STATE_SHIFT (28) |
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#define | MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) |
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#define | MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) |
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#define | MPI2_DOORBELL_OFFSET (0x00000000) |
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#define | MPI2_DOORBELL_USED (0x08000000) |
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#define | MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) |
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#define | MPI2_DOORBELL_WHO_INIT_SHIFT (24) |
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#define | MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) |
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#define | MPI2_DOORBELL_DATA_MASK (0x0000FFFF) |
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#define | MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) |
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#define | MPI2_DOORBELL_FUNCTION_SHIFT (24) |
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#define | MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) |
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#define | MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) |
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#define | MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) |
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#define | MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) |
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#define | MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) |
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#define | MPI2_WRSEQ_1ST_KEY_VALUE (0xF) |
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#define | MPI2_WRSEQ_2ND_KEY_VALUE (0x4) |
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#define | MPI2_WRSEQ_3RD_KEY_VALUE (0xB) |
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#define | MPI2_WRSEQ_4TH_KEY_VALUE (0x2) |
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#define | MPI2_WRSEQ_5TH_KEY_VALUE (0x7) |
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#define | MPI2_WRSEQ_6TH_KEY_VALUE (0xD) |
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#define | MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) |
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#define | MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) |
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#define | MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) |
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#define | MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) |
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#define | MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) |
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#define | MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) |
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#define | MPI2_DIAG_HCB_MODE (0x00000100) |
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#define | MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) |
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#define | MPI2_DIAG_FLASH_BAD_SIG (0x00000040) |
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#define | MPI2_DIAG_RESET_HISTORY (0x00000020) |
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#define | MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) |
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#define | MPI2_DIAG_RESET_ADAPTER (0x00000004) |
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#define | MPI2_DIAG_HOLD_IOC_RESET (0x00000002) |
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#define | MPI2_DIAG_RW_DATA_OFFSET (0x00000010) |
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#define | MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) |
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#define | MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) |
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#define | MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) |
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#define | MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) |
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#define | MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS |
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#define | MPI2_HIS_RESET_IRQ_STATUS (0x40000000) |
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#define | MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) |
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#define | MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) |
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#define | MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS |
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#define | MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) |
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#define | MPI2_HIM_RESET_IRQ_MASK (0x40000000) |
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#define | MPI2_HIM_REPLY_INT_MASK (0x00000008) |
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#define | MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK |
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#define | MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) |
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#define | MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK |
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#define | MPI2_DCR_DATA_OFFSET (0x00000038) |
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#define | MPI2_DCR_ADDRESS_OFFSET (0x0000003C) |
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#define | MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) |
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#define | MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) |
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#define | MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) |
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#define | MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) |
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#define | MPI2_RPHI_MSIX_INDEX_SHIFT (24) |
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#define | MPI2_HCB_SIZE_OFFSET (0x00000074) |
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#define | MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) |
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#define | MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) |
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#define | MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) |
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#define | MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) |
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#define | MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) |
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#define | MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) |
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#define | MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) |
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#define | MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) |
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#define | MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) |
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#define | MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) |
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#define | MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) |
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#define | MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) |
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#define | MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) |
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#define | MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) |
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#define | MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) |
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#define | MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) |
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#define | MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) |
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#define | MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) |
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#define | MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) |
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#define | MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) |
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#define | MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) |
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#define | MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) |
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#define | MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) |
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#define | MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) |
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#define | MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) |
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#define | MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) |
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#define | MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) |
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#define | MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ |
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#define | MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ |
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#define | MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ |
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#define | MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ |
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#define | MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ |
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#define | MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ |
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#define | MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ |
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#define | MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ |
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#define | MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ |
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#define | MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ |
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#define | MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ |
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#define | MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ |
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#define | MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ |
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#define | MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ |
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#define | MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ |
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#define | MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ |
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#define | MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ |
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#define | MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ |
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#define | MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ |
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#define | MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ |
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#define | MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ |
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#define | MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ |
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#define | MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ |
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#define | MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ |
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#define | MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ |
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#define | MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/ |
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#define | MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) |
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#define | MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) |
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#define | MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) |
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#define | MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) |
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#define | MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) |
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#define | MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) |
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#define | MPI2_FUNCTION_HANDSHAKE (0x42) |
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#define | MPI2_IOCSTATUS_MASK (0x7FFF) |
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#define | MPI2_IOCSTATUS_SUCCESS (0x0000) |
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#define | MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) |
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#define | MPI2_IOCSTATUS_BUSY (0x0002) |
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#define | MPI2_IOCSTATUS_INVALID_SGL (0x0003) |
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#define | MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) |
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#define | MPI2_IOCSTATUS_INVALID_VPID (0x0005) |
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#define | MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) |
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#define | MPI2_IOCSTATUS_INVALID_FIELD (0x0007) |
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#define | MPI2_IOCSTATUS_INVALID_STATE (0x0008) |
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#define | MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) |
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#define | MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) |
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#define | MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) |
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#define | MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) |
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#define | MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) |
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#define | MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) |
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#define | MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) |
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#define | MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) |
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#define | MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) |
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#define | MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) |
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#define | MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) |
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#define | MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) |
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#define | MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) |
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#define | MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) |
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#define | MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) |
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#define | MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) |
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#define | MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) |
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#define | MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) |
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#define | MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) |
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#define | MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) |
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#define | MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) |
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#define | MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) |
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#define | MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) |
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#define | MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) |
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#define | MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) |
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#define | MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) |
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#define | MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) |
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#define | MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) |
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#define | MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) |
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#define | MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) |
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#define | MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) |
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#define | MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) |
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#define | MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) |
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#define | MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) |
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#define | MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) |
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#define | MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) |
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#define | MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) |
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#define | MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) |
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#define | MPI2_IOCLOGINFO_TYPE_SHIFT (28) |
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#define | MPI2_IOCLOGINFO_TYPE_NONE (0x0) |
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#define | MPI2_IOCLOGINFO_TYPE_SCSI (0x1) |
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#define | MPI2_IOCLOGINFO_TYPE_FC (0x2) |
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#define | MPI2_IOCLOGINFO_TYPE_SAS (0x3) |
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#define | MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) |
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#define | MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) |
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#define | MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) |
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#define | MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) |
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#define | MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) |
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#define | MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) |
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#define | MPI2_LUN_LEVEL_1_WORD (0xFF00) |
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#define | MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) |
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#define | MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) |
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#define | MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) |
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#define | MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) |
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#define | MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) |
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#define | MPI2_SGE_FLAGS_DIRECTION (0x04) |
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#define | MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) |
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#define | MPI2_SGE_FLAGS_END_OF_LIST (0x01) |
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#define | MPI2_SGE_FLAGS_SHIFT (24) |
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#define | MPI2_SGE_LENGTH_MASK (0x00FFFFFF) |
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#define | MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) |
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#define | MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) |
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#define | MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) |
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#define | MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) |
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#define | MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) |
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#define | MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) |
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#define | MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) |
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#define | MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) |
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#define | MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) |
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#define | MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) |
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#define | MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) |
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#define | MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) |
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#define | MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) |
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#define | MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) |
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#define | MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) |
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#define | MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) |
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#define | MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) |
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#define | MPI2_SGE_CHAIN_OFFSET_SHIFT (16) |
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#define | MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) |
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#define | MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) |
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#define | MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) |
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#define | MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) |
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#define | MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) |
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#define | MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) |
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#define | MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) |
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#define | MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) |
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#define | MPI2_pSGE_SET_FLAGS(psg, f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) |
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#define | MPI2_pSGE_SET_LENGTH(psg, l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) |
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#define | MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) |
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#define | MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) |
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#define | MPI2_IEEE32_SGE_FLAGS_SHIFT (24) |
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#define | MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) |
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#define | MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) |
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#define | MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) |
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#define | MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) |
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#define | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) |
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#define | MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) |
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#define | MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) |
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#define | MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) |
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#define | MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) |
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#define | MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ |
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#define | MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) |
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#define | MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) |
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#define | MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) |
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#define | MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) |
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#define | MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) |
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#define | MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) |
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#define | MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) |
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#define | MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) |
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#define | MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) |
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#define | MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) |
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#define | MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) |
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#define | MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) |
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#define | MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) |
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#define | MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) |
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#define | MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) |
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#define | MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) |
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#define | MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) |
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#define | MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) |
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