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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Data Structures | |
| struct | msc_irqmap |
Typedefs | |
| typedef struct msc_irqmap | msc_irqmap_t |
Functions | |
| void __init | init_msc_irqs (unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq) |
| void | ll_msc_irq (void) |
| #define MSC01_IC_BASE (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS) |
Definition at line 117 of file msc01_ic.h.
| #define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */ |
Definition at line 32 of file msc01_ic.h.
| #define MSC01_IC_CFG (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS) |
Definition at line 120 of file msc01_ic.h.
| #define MSC01_IC_CFG_DIS_BIT MSC01_IC_CFG_DIS_MSK |
Definition at line 75 of file msc01_ic.h.
| #define MSC01_IC_CFG_DIS_MSK 0x00000001 |
Definition at line 74 of file msc01_ic.h.
| #define MSC01_IC_CFG_DIS_SHF 0 |
Definition at line 73 of file msc01_ic.h.
| #define MSC01_IC_CFG_OFS 0x001c8 /* Configuration register */ |
Definition at line 35 of file msc01_ic.h.
| #define MSC01_IC_CFG_SHFT_MSK 0x00000f00 |
Definition at line 77 of file msc01_ic.h.
| #define MSC01_IC_CFG_SHFT_SHF 8 |
Definition at line 76 of file msc01_ic.h.
| #define MSC01_IC_DIS (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS) |
Definition at line 126 of file msc01_ic.h.
| #define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */ |
Definition at line 41 of file msc01_ic.h.
| #define MSC01_IC_DISH (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS) |
Definition at line 107 of file msc01_ic.h.
| #define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */ |
Definition at line 22 of file msc01_ic.h.
| #define MSC01_IC_DISL (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS) |
Definition at line 106 of file msc01_ic.h.
| #define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */ |
Definition at line 21 of file msc01_ic.h.
| #define MSC01_IC_ENA (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS) |
Definition at line 125 of file msc01_ic.h.
| #define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */ |
Definition at line 40 of file msc01_ic.h.
| #define MSC01_IC_ENAH (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS) |
Definition at line 105 of file msc01_ic.h.
| #define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */ |
Definition at line 20 of file msc01_ic.h.
| #define MSC01_IC_ENAL (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS) |
Definition at line 104 of file msc01_ic.h.
| #define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */ |
Definition at line 19 of file msc01_ic.h.
| #define MSC01_IC_EOI (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS) |
Definition at line 119 of file msc01_ic.h.
| #define MSC01_IC_EOI_OFS 0x001c0 /* Enable lower level ints */ |
Definition at line 34 of file msc01_ic.h.
| #define MSC01_IC_GENA (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS) |
Definition at line 116 of file msc01_ic.h.
| #define MSC01_IC_GENA_GENA_BIT MSC01_IC_GENA_GENA_MSK |
Definition at line 72 of file msc01_ic.h.
| #define MSC01_IC_GENA_GENA_MSK 0x00000001 |
Definition at line 71 of file msc01_ic.h.
| #define MSC01_IC_GENA_GENA_SHF 0 |
Definition at line 70 of file msc01_ic.h.
| #define MSC01_IC_GENA_OFS 0x00198 /* Global HW int enable */ |
Definition at line 31 of file msc01_ic.h.
| #define MSC01_IC_ISA (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS) |
Definition at line 128 of file msc01_ic.h.
| #define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */ |
Definition at line 43 of file msc01_ic.h.
| #define MSC01_IC_ISAH (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS) |
Definition at line 111 of file msc01_ic.h.
| #define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */ |
Definition at line 26 of file msc01_ic.h.
| #define MSC01_IC_ISAL (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS) |
Definition at line 110 of file msc01_ic.h.
| #define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */ |
Definition at line 25 of file msc01_ic.h.
| #define MSC01_IC_ISB (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS) |
Definition at line 127 of file msc01_ic.h.
| #define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */ |
Definition at line 42 of file msc01_ic.h.
| #define MSC01_IC_ISBH (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS) |
Definition at line 109 of file msc01_ic.h.
| #define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */ |
Definition at line 24 of file msc01_ic.h.
| #define MSC01_IC_ISBL (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS) |
Definition at line 108 of file msc01_ic.h.
| #define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */ |
Definition at line 23 of file msc01_ic.h.
| #define MSC01_IC_LVL (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS) |
Definition at line 112 of file msc01_ic.h.
| #define MSC01_IC_LVL_LVL_MSK 0x000000ff |
Definition at line 53 of file msc01_ic.h.
| #define MSC01_IC_LVL_LVL_SHF 0 |
Definition at line 52 of file msc01_ic.h.
| #define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */ |
Definition at line 27 of file msc01_ic.h.
| #define MSC01_IC_LVL_SPUR_BIT MSC01_IC_LVL_SPUR_MSK |
Definition at line 56 of file msc01_ic.h.
| #define MSC01_IC_LVL_SPUR_MSK 0x00010000 |
Definition at line 55 of file msc01_ic.h.
| #define MSC01_IC_LVL_SPUR_SHF 16 |
Definition at line 54 of file msc01_ic.h.
| #define MSC01_IC_OSA (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS) |
Definition at line 115 of file msc01_ic.h.
| #define MSC01_IC_OSA_OFS 0x00190 /* Masked int_out */ |
Definition at line 30 of file msc01_ic.h.
| #define MSC01_IC_OSA_OSA_MSK 0x000000ff |
Definition at line 69 of file msc01_ic.h.
| #define MSC01_IC_OSA_OSA_SHF 0 |
Definition at line 68 of file msc01_ic.h.
| #define MSC01_IC_OSB (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS) |
Definition at line 114 of file msc01_ic.h.
| #define MSC01_IC_OSB_OFS 0x00188 /* Raw int_out */ |
Definition at line 29 of file msc01_ic.h.
| #define MSC01_IC_OSB_OSB_MSK 0x000000ff |
Definition at line 67 of file msc01_ic.h.
| #define MSC01_IC_OSB_OSB_SHF 0 |
Definition at line 66 of file msc01_ic.h.
| #define MSC01_IC_RAMW (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS) |
Definition at line 113 of file msc01_ic.h.
| #define MSC01_IC_RAMW_ADDR_MSK 0x7e000000 |
Definition at line 62 of file msc01_ic.h.
| #define MSC01_IC_RAMW_ADDR_SHF 25 |
Definition at line 61 of file msc01_ic.h.
| #define MSC01_IC_RAMW_DATA_MSK 0x00000fc0 |
Definition at line 60 of file msc01_ic.h.
| #define MSC01_IC_RAMW_DATA_SHF 6 |
Definition at line 59 of file msc01_ic.h.
| #define MSC01_IC_RAMW_OFS 0x00180 /* Shadow set RAM (EI) */ |
Definition at line 28 of file msc01_ic.h.
| #define MSC01_IC_RAMW_READ_BIT MSC01_IC_RAMW_READ_MSK |
Definition at line 65 of file msc01_ic.h.
| #define MSC01_IC_RAMW_READ_MSK 0x80000000 |
Definition at line 64 of file msc01_ic.h.
| #define MSC01_IC_RAMW_READ_SHF 31 |
Definition at line 63 of file msc01_ic.h.
| #define MSC01_IC_RAMW_RIPL_MSK 0x0000003f |
Definition at line 58 of file msc01_ic.h.
| #define MSC01_IC_RAMW_RIPL_SHF 0 |
Definition at line 57 of file msc01_ic.h.
| #define MSC01_IC_RST (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS) |
Definition at line 103 of file msc01_ic.h.
| #define MSC01_IC_RST_OFS 0x00008 /* Software reset */ |
Definition at line 18 of file msc01_ic.h.
| #define MSC01_IC_RST_RST_BIT MSC01_IC_RST_RST_MSK |
Definition at line 51 of file msc01_ic.h.
| #define MSC01_IC_RST_RST_MSK 0x00000001 |
Definition at line 50 of file msc01_ic.h.
| #define MSC01_IC_RST_RST_SHF 0 |
Definition at line 49 of file msc01_ic.h.
| #define MSC01_IC_SUP (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS) |
Definition at line 124 of file msc01_ic.h.
| #define MSC01_IC_SUP_EDGE_BIT MSC01_IC_SUP_EDGE_MSK |
Definition at line 91 of file msc01_ic.h.
| #define MSC01_IC_SUP_EDGE_MSK 0x00000100 |
Definition at line 90 of file msc01_ic.h.
| #define MSC01_IC_SUP_EDGE_SHF 8 |
Definition at line 89 of file msc01_ic.h.
| #define MSC01_IC_SUP_OFS 0x00200 /* Set up int_in line 0 */ |
Definition at line 39 of file msc01_ic.h.
| #define MSC01_IC_SUP_PRI_MSK 0x00000007 |
Definition at line 88 of file msc01_ic.h.
| #define MSC01_IC_SUP_PRI_SHF 0 |
Definition at line 87 of file msc01_ic.h.
| #define MSC01_IC_SUP_STEP 8 |
Definition at line 92 of file msc01_ic.h.
| #define MSC01_IC_TCFG (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS) |
Definition at line 123 of file msc01_ic.h.
| #define MSC01_IC_TCFG_EDGE_BIT MSC01_IC_TCFG_EDGE_MSK |
Definition at line 86 of file msc01_ic.h.
| #define MSC01_IC_TCFG_EDGE_MSK 0x00010000 |
Definition at line 85 of file msc01_ic.h.
| #define MSC01_IC_TCFG_EDGE_SHF 16 |
Definition at line 84 of file msc01_ic.h.
| #define MSC01_IC_TCFG_ENA_BIT MSC01_IC_TCFG_ENA_MSK |
Definition at line 80 of file msc01_ic.h.
| #define MSC01_IC_TCFG_ENA_MSK 0x00000001 |
Definition at line 79 of file msc01_ic.h.
| #define MSC01_IC_TCFG_ENA_SHF 0 |
Definition at line 78 of file msc01_ic.h.
| #define MSC01_IC_TCFG_INT_BIT MSC01_IC_TCFG_INT_MSK |
Definition at line 83 of file msc01_ic.h.
| #define MSC01_IC_TCFG_INT_MSK 0x00000100 |
Definition at line 82 of file msc01_ic.h.
| #define MSC01_IC_TCFG_INT_SHF 8 |
Definition at line 81 of file msc01_ic.h.
| #define MSC01_IC_TCFG_OFS 0x001f0 /* Interval timer config */ |
Definition at line 38 of file msc01_ic.h.
| #define MSC01_IC_TRLD (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS) |
Definition at line 121 of file msc01_ic.h.
| #define MSC01_IC_TRLD_OFS 0x001d0 /* Interval timer reload val */ |
Definition at line 36 of file msc01_ic.h.
| #define MSC01_IC_TVAL (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS) |
Definition at line 122 of file msc01_ic.h.
| #define MSC01_IC_TVAL_OFS 0x001e0 /* Interval timer current val */ |
Definition at line 37 of file msc01_ic.h.
| #define MSC01_IC_VEC (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS) |
Definition at line 118 of file msc01_ic.h.
| #define MSC01_IC_VEC_OFS 0x001b0 /* Active int's vector address */ |
Definition at line 33 of file msc01_ic.h.
| #define MSC01_IRQ_EDGE 1 |
Definition at line 142 of file msc01_ic.h.
| #define MSC01_IRQ_LEVEL 0 |
Definition at line 141 of file msc01_ic.h.
| typedef struct msc_irqmap msc_irqmap_t |
| void __init init_msc_irqs | ( | unsigned long | icubase, |
| unsigned int | base, | ||
| msc_irqmap_t * | imp, | ||
| int | nirq | ||
| ) |
Definition at line 125 of file irq-msc01.c.
Definition at line 87 of file irq-msc01.c.
1.8.2