Macros
#define	MSP_MIPS_INTBASE 0

#define	MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */

#define	MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */

#define	MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */

#define	MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */

#define	MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */

#define	MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */

#define	MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */

#define	MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */

#define	MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8)

#define	MSP_INT_EXT0 (MSP_SLP_INTBASE + 0)

#define	MSP_INT_EXT1 (MSP_SLP_INTBASE + 1)

#define	MSP_INT_EXT2 (MSP_SLP_INTBASE + 2)

#define	MSP_INT_EXT3 (MSP_SLP_INTBASE + 3)

#define	MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8)

#define	MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9)

#define	MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10)

#define	MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11)

#define	MSP_INT_SEC (MSP_SLP_INTBASE + 12)

#define	MSP_INT_PER (MSP_SLP_INTBASE + 13)

#define	MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14)

#define	MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15)

#define	MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16)

#define	MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17)

#define	MSP_INT_BLKCP (MSP_SLP_INTBASE + 18)

#define	MSP_INT_UART0 (MSP_SLP_INTBASE + 19)

#define	MSP_INT_PCI (MSP_SLP_INTBASE + 20)

#define	MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21)

#define	MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22)

#define	MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23)

#define	MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24)

#define	MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25)

#define	MSP_INT_MAC2 (MSP_SLP_INTBASE + 26)

#define	MSP_PER_INTBASE (MSP_SLP_INTBASE + 32)

#define	MSP_INT_UART1 (MSP_PER_INTBASE + 2)

#define	MSP_INT_2WIRE (MSP_PER_INTBASE + 6)

#define	MSP_INT_TM0 (MSP_PER_INTBASE + 7)

#define	MSP_INT_TM1 (MSP_PER_INTBASE + 8)

#define	MSP_INT_SPRX (MSP_PER_INTBASE + 10)

#define	MSP_INT_SPTX (MSP_PER_INTBASE + 11)

#define	MSP_INT_GPIO (MSP_PER_INTBASE + 12)

#define	MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)

Macro Definition Documentation

#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)

Definition at line 124 of file msp_slp_int.h.

#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18)

Definition at line 96 of file msp_slp_int.h.

#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */

Definition at line 48 of file msp_slp_int.h.

#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0)

Definition at line 59 of file msp_slp_int.h.

#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1)

Definition at line 61 of file msp_slp_int.h.

#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2)

Definition at line 63 of file msp_slp_int.h.

#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3)

Definition at line 65 of file msp_slp_int.h.

#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)

Definition at line 135 of file msp_slp_int.h.

#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */

Definition at line 46 of file msp_slp_int.h.

#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */

Definition at line 47 of file msp_slp_int.h.

#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26)

Definition at line 112 of file msp_slp_int.h.

#define MSP_INT_PCI (MSP_SLP_INTBASE + 20)

Definition at line 100 of file msp_slp_int.h.

#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23)

Definition at line 106 of file msp_slp_int.h.

#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24)

Definition at line 108 of file msp_slp_int.h.

#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21)

Definition at line 102 of file msp_slp_int.h.

#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22)

Definition at line 104 of file msp_slp_int.h.

#define MSP_INT_PER (MSP_SLP_INTBASE + 13)

Definition at line 86 of file msp_slp_int.h.

#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)

Definition at line 137 of file msp_slp_int.h.

#define MSP_INT_SEC (MSP_SLP_INTBASE + 12)

Definition at line 84 of file msp_slp_int.h.

#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */

Definition at line 50 of file msp_slp_int.h.

#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25)

Definition at line 110 of file msp_slp_int.h.

#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10)

Definition at line 80 of file msp_slp_int.h.

#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11)

Definition at line 82 of file msp_slp_int.h.

#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9)

Definition at line 78 of file msp_slp_int.h.

#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17)

Definition at line 94 of file msp_slp_int.h.

#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8)

Definition at line 76 of file msp_slp_int.h.

#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)

Definition at line 131 of file msp_slp_int.h.

#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)

Definition at line 133 of file msp_slp_int.h.

#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */

Definition at line 44 of file msp_slp_int.h.

#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */

Definition at line 45 of file msp_slp_int.h.

#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */

Definition at line 51 of file msp_slp_int.h.

#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14)

Definition at line 88 of file msp_slp_int.h.

#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15)

Definition at line 90 of file msp_slp_int.h.

#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16)

Definition at line 92 of file msp_slp_int.h.

#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)

Definition at line 126 of file msp_slp_int.h.

#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)

Definition at line 128 of file msp_slp_int.h.

#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19)

Definition at line 98 of file msp_slp_int.h.

#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)

Definition at line 121 of file msp_slp_int.h.

#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */

Definition at line 49 of file msp_slp_int.h.

#define MSP_MIPS_INTBASE 0

Definition at line 43 of file msp_slp_int.h.

#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32)

Definition at line 119 of file msp_slp_int.h.

#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8)

Definition at line 58 of file msp_slp_int.h.

Macros

Macro Definition Documentation