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Macros
mipsregs.h File Reference
#include <linux/linkage.h>
#include <asm/hazards.h>
#include <asm/war.h>

Go to the source code of this file.

Macros

#define __STR(x)   #x
 
#define STR(x)   __STR(x)
 
#define _ULCAST_   (unsigned long)
 
#define CP0_INDEX   $0
 
#define CP0_RANDOM   $1
 
#define CP0_ENTRYLO0   $2
 
#define CP0_ENTRYLO1   $3
 
#define CP0_CONF   $3
 
#define CP0_CONTEXT   $4
 
#define CP0_PAGEMASK   $5
 
#define CP0_WIRED   $6
 
#define CP0_INFO   $7
 
#define CP0_BADVADDR   $8
 
#define CP0_COUNT   $9
 
#define CP0_ENTRYHI   $10
 
#define CP0_COMPARE   $11
 
#define CP0_STATUS   $12
 
#define CP0_CAUSE   $13
 
#define CP0_EPC   $14
 
#define CP0_PRID   $15
 
#define CP0_CONFIG   $16
 
#define CP0_LLADDR   $17
 
#define CP0_WATCHLO   $18
 
#define CP0_WATCHHI   $19
 
#define CP0_XCONTEXT   $20
 
#define CP0_FRAMEMASK   $21
 
#define CP0_DIAGNOSTIC   $22
 
#define CP0_DEBUG   $23
 
#define CP0_DEPC   $24
 
#define CP0_PERFORMANCE   $25
 
#define CP0_ECC   $26
 
#define CP0_CACHEERR   $27
 
#define CP0_TAGLO   $28
 
#define CP0_TAGHI   $29
 
#define CP0_ERROREPC   $30
 
#define CP0_DESAVE   $31
 
#define CP0_IBASE   $0
 
#define CP0_IBOUND   $1
 
#define CP0_DBASE   $2
 
#define CP0_DBOUND   $3
 
#define CP0_CALG   $17
 
#define CP0_IWATCH   $18
 
#define CP0_DWATCH   $19
 
#define CP0_S1_DERRADDR0   $26
 
#define CP0_S1_DERRADDR1   $27
 
#define CP0_S1_INTCONTROL   $20
 
#define CP0_S2_SRSCTL   $12 /* MIPSR2 */
 
#define CP0_S3_SRSMAP   $12 /* MIPSR2 */
 
#define CP0_TX39_CACHE   $7
 
#define CP1_REVISION   $0
 
#define CP1_STATUS   $31
 
#define FPU_CSR_FLUSH   0x01000000 /* flush denormalised results to 0 */
 
#define FPU_CSR_COND   0x00800000 /* $fcc0 */
 
#define FPU_CSR_COND0   0x00800000 /* $fcc0 */
 
#define FPU_CSR_COND1   0x02000000 /* $fcc1 */
 
#define FPU_CSR_COND2   0x04000000 /* $fcc2 */
 
#define FPU_CSR_COND3   0x08000000 /* $fcc3 */
 
#define FPU_CSR_COND4   0x10000000 /* $fcc4 */
 
#define FPU_CSR_COND5   0x20000000 /* $fcc5 */
 
#define FPU_CSR_COND6   0x40000000 /* $fcc6 */
 
#define FPU_CSR_COND7   0x80000000 /* $fcc7 */
 
#define FPU_CSR_RSVD   0x001c0000
 
#define FPU_CSR_ALL_X   0x0003f000
 
#define FPU_CSR_UNI_X   0x00020000
 
#define FPU_CSR_INV_X   0x00010000
 
#define FPU_CSR_DIV_X   0x00008000
 
#define FPU_CSR_OVF_X   0x00004000
 
#define FPU_CSR_UDF_X   0x00002000
 
#define FPU_CSR_INE_X   0x00001000
 
#define FPU_CSR_ALL_E   0x00000f80
 
#define FPU_CSR_INV_E   0x00000800
 
#define FPU_CSR_DIV_E   0x00000400
 
#define FPU_CSR_OVF_E   0x00000200
 
#define FPU_CSR_UDF_E   0x00000100
 
#define FPU_CSR_INE_E   0x00000080
 
#define FPU_CSR_ALL_S   0x0000007c
 
#define FPU_CSR_INV_S   0x00000040
 
#define FPU_CSR_DIV_S   0x00000020
 
#define FPU_CSR_OVF_S   0x00000010
 
#define FPU_CSR_UDF_S   0x00000008
 
#define FPU_CSR_INE_S   0x00000004
 
#define FPU_CSR_RM   0x00000003
 
#define FPU_CSR_RN   0x0 /* nearest */
 
#define FPU_CSR_RZ   0x1 /* towards zero */
 
#define FPU_CSR_RU   0x2 /* towards +Infinity */
 
#define FPU_CSR_RD   0x3 /* towards -Infinity */
 
#define PM_4K   0x00000000
 
#define PM_8K   0x00002000
 
#define PM_16K   0x00006000
 
#define PM_32K   0x0000e000
 
#define PM_64K   0x0001e000
 
#define PM_128K   0x0003e000
 
#define PM_256K   0x0007e000
 
#define PM_512K   0x000fe000
 
#define PM_1M   0x001fe000
 
#define PM_2M   0x003fe000
 
#define PM_4M   0x007fe000
 
#define PM_8M   0x00ffe000
 
#define PM_16M   0x01ffe000
 
#define PM_32M   0x03ffe000
 
#define PM_64M   0x07ffe000
 
#define PM_256M   0x1fffe000
 
#define PM_1G   0x7fffe000
 
#define PL_4K   12
 
#define PL_16K   14
 
#define PL_64K   16
 
#define PL_256K   18
 
#define PL_1M   20
 
#define PL_4M   22
 
#define PL_16M   24
 
#define PL_64M   26
 
#define PL_256M   28
 
#define PG_RIE   (_ULCAST_(1) << 31)
 
#define PG_XIE   (_ULCAST_(1) << 30)
 
#define PG_ELPA   (_ULCAST_(1) << 29)
 
#define PG_ESP   (_ULCAST_(1) << 28)
 
#define IE_SW0   (_ULCAST_(1) << 8)
 
#define IE_SW1   (_ULCAST_(1) << 9)
 
#define IE_IRQ0   (_ULCAST_(1) << 10)
 
#define IE_IRQ1   (_ULCAST_(1) << 11)
 
#define IE_IRQ2   (_ULCAST_(1) << 12)
 
#define IE_IRQ3   (_ULCAST_(1) << 13)
 
#define IE_IRQ4   (_ULCAST_(1) << 14)
 
#define IE_IRQ5   (_ULCAST_(1) << 15)
 
#define C_SW0   (_ULCAST_(1) << 8)
 
#define C_SW1   (_ULCAST_(1) << 9)
 
#define C_IRQ0   (_ULCAST_(1) << 10)
 
#define C_IRQ1   (_ULCAST_(1) << 11)
 
#define C_IRQ2   (_ULCAST_(1) << 12)
 
#define C_IRQ3   (_ULCAST_(1) << 13)
 
#define C_IRQ4   (_ULCAST_(1) << 14)
 
#define C_IRQ5   (_ULCAST_(1) << 15)
 
#define ST0_IE   0x00000001
 
#define ST0_EXL   0x00000002
 
#define ST0_ERL   0x00000004
 
#define ST0_KSU   0x00000018
 
#define KSU_USER   0x00000010
 
#define KSU_SUPERVISOR   0x00000008
 
#define KSU_KERNEL   0x00000000
 
#define ST0_UX   0x00000020
 
#define ST0_SX   0x00000040
 
#define ST0_KX   0x00000080
 
#define ST0_DE   0x00010000
 
#define ST0_CE   0x00020000
 
#define ST0_CO   0x08000000
 
#define ST0_IEC   0x00000001
 
#define ST0_KUC   0x00000002
 
#define ST0_IEP   0x00000004
 
#define ST0_KUP   0x00000008
 
#define ST0_IEO   0x00000010
 
#define ST0_KUO   0x00000020
 
#define ST0_ISC   0x00010000
 
#define ST0_SWC   0x00020000
 
#define ST0_CM   0x00080000
 
#define ST0_UM   (_ULCAST_(1) << 4)
 
#define ST0_IL   (_ULCAST_(1) << 23)
 
#define ST0_DL   (_ULCAST_(1) << 24)
 
#define ST0_MX   0x01000000
 
#define TX39_CONF_ICS_SHIFT   19
 
#define TX39_CONF_ICS_MASK   0x00380000
 
#define TX39_CONF_ICS_1KB   0x00000000
 
#define TX39_CONF_ICS_2KB   0x00080000
 
#define TX39_CONF_ICS_4KB   0x00100000
 
#define TX39_CONF_ICS_8KB   0x00180000
 
#define TX39_CONF_ICS_16KB   0x00200000
 
#define TX39_CONF_DCS_SHIFT   16
 
#define TX39_CONF_DCS_MASK   0x00070000
 
#define TX39_CONF_DCS_1KB   0x00000000
 
#define TX39_CONF_DCS_2KB   0x00010000
 
#define TX39_CONF_DCS_4KB   0x00020000
 
#define TX39_CONF_DCS_8KB   0x00030000
 
#define TX39_CONF_DCS_16KB   0x00040000
 
#define TX39_CONF_CWFON   0x00004000
 
#define TX39_CONF_WBON   0x00002000
 
#define TX39_CONF_RF_SHIFT   10
 
#define TX39_CONF_RF_MASK   0x00000c00
 
#define TX39_CONF_DOZE   0x00000200
 
#define TX39_CONF_HALT   0x00000100
 
#define TX39_CONF_LOCK   0x00000080
 
#define TX39_CONF_ICE   0x00000020
 
#define TX39_CONF_DCE   0x00000010
 
#define TX39_CONF_IRSIZE_SHIFT   2
 
#define TX39_CONF_IRSIZE_MASK   0x0000000c
 
#define TX39_CONF_DRSIZE_SHIFT   0
 
#define TX39_CONF_DRSIZE_MASK   0x00000003
 
#define ST0_IM   0x0000ff00
 
#define STATUSB_IP0   8
 
#define STATUSF_IP0   (_ULCAST_(1) << 8)
 
#define STATUSB_IP1   9
 
#define STATUSF_IP1   (_ULCAST_(1) << 9)
 
#define STATUSB_IP2   10
 
#define STATUSF_IP2   (_ULCAST_(1) << 10)
 
#define STATUSB_IP3   11
 
#define STATUSF_IP3   (_ULCAST_(1) << 11)
 
#define STATUSB_IP4   12
 
#define STATUSF_IP4   (_ULCAST_(1) << 12)
 
#define STATUSB_IP5   13
 
#define STATUSF_IP5   (_ULCAST_(1) << 13)
 
#define STATUSB_IP6   14
 
#define STATUSF_IP6   (_ULCAST_(1) << 14)
 
#define STATUSB_IP7   15
 
#define STATUSF_IP7   (_ULCAST_(1) << 15)
 
#define STATUSB_IP8   0
 
#define STATUSF_IP8   (_ULCAST_(1) << 0)
 
#define STATUSB_IP9   1
 
#define STATUSF_IP9   (_ULCAST_(1) << 1)
 
#define STATUSB_IP10   2
 
#define STATUSF_IP10   (_ULCAST_(1) << 2)
 
#define STATUSB_IP11   3
 
#define STATUSF_IP11   (_ULCAST_(1) << 3)
 
#define STATUSB_IP12   4
 
#define STATUSF_IP12   (_ULCAST_(1) << 4)
 
#define STATUSB_IP13   5
 
#define STATUSF_IP13   (_ULCAST_(1) << 5)
 
#define STATUSB_IP14   6
 
#define STATUSF_IP14   (_ULCAST_(1) << 6)
 
#define STATUSB_IP15   7
 
#define STATUSF_IP15   (_ULCAST_(1) << 7)
 
#define ST0_CH   0x00040000
 
#define ST0_NMI   0x00080000
 
#define ST0_SR   0x00100000
 
#define ST0_TS   0x00200000
 
#define ST0_BEV   0x00400000
 
#define ST0_RE   0x02000000
 
#define ST0_FR   0x04000000
 
#define ST0_CU   0xf0000000
 
#define ST0_CU0   0x10000000
 
#define ST0_CU1   0x20000000
 
#define ST0_CU2   0x40000000
 
#define ST0_CU3   0x80000000
 
#define ST0_XX   0x80000000 /* MIPS IV naming */
 
#define INTCTLB_IPPCI   26
 
#define INTCTLF_IPPCI   (_ULCAST_(7) << INTCTLB_IPPCI)
 
#define INTCTLB_IPTI   29
 
#define INTCTLF_IPTI   (_ULCAST_(7) << INTCTLB_IPTI)
 
#define CAUSEB_EXCCODE   2
 
#define CAUSEF_EXCCODE   (_ULCAST_(31) << 2)
 
#define CAUSEB_IP   8
 
#define CAUSEF_IP   (_ULCAST_(255) << 8)
 
#define CAUSEB_IP0   8
 
#define CAUSEF_IP0   (_ULCAST_(1) << 8)
 
#define CAUSEB_IP1   9
 
#define CAUSEF_IP1   (_ULCAST_(1) << 9)
 
#define CAUSEB_IP2   10
 
#define CAUSEF_IP2   (_ULCAST_(1) << 10)
 
#define CAUSEB_IP3   11
 
#define CAUSEF_IP3   (_ULCAST_(1) << 11)
 
#define CAUSEB_IP4   12
 
#define CAUSEF_IP4   (_ULCAST_(1) << 12)
 
#define CAUSEB_IP5   13
 
#define CAUSEF_IP5   (_ULCAST_(1) << 13)
 
#define CAUSEB_IP6   14
 
#define CAUSEF_IP6   (_ULCAST_(1) << 14)
 
#define CAUSEB_IP7   15
 
#define CAUSEF_IP7   (_ULCAST_(1) << 15)
 
#define CAUSEB_IV   23
 
#define CAUSEF_IV   (_ULCAST_(1) << 23)
 
#define CAUSEB_PCI   26
 
#define CAUSEF_PCI   (_ULCAST_(1) << 26)
 
#define CAUSEB_CE   28
 
#define CAUSEF_CE   (_ULCAST_(3) << 28)
 
#define CAUSEB_TI   30
 
#define CAUSEF_TI   (_ULCAST_(1) << 30)
 
#define CAUSEB_BD   31
 
#define CAUSEF_BD   (_ULCAST_(1) << 31)
 
#define CONF_CM_CACHABLE_NO_WA   0
 
#define CONF_CM_CACHABLE_WA   1
 
#define CONF_CM_UNCACHED   2
 
#define CONF_CM_CACHABLE_NONCOHERENT   3
 
#define CONF_CM_CACHABLE_CE   4
 
#define CONF_CM_CACHABLE_COW   5
 
#define CONF_CM_CACHABLE_CUW   6
 
#define CONF_CM_CACHABLE_ACCELERATED   7
 
#define CONF_CM_CMASK   7
 
#define CONF_BE   (_ULCAST_(1) << 15)
 
#define CONF_CU   (_ULCAST_(1) << 3)
 
#define CONF_DB   (_ULCAST_(1) << 4)
 
#define CONF_IB   (_ULCAST_(1) << 5)
 
#define CONF_DC   (_ULCAST_(7) << 6)
 
#define CONF_IC   (_ULCAST_(7) << 9)
 
#define CONF_EB   (_ULCAST_(1) << 13)
 
#define CONF_EM   (_ULCAST_(1) << 14)
 
#define CONF_SM   (_ULCAST_(1) << 16)
 
#define CONF_SC   (_ULCAST_(1) << 17)
 
#define CONF_EW   (_ULCAST_(3) << 18)
 
#define CONF_EP   (_ULCAST_(15)<< 24)
 
#define CONF_EC   (_ULCAST_(7) << 28)
 
#define CONF_CM   (_ULCAST_(1) << 31)
 
#define R4K_CONF_SW   (_ULCAST_(1) << 20)
 
#define R4K_CONF_SS   (_ULCAST_(1) << 21)
 
#define R4K_CONF_SB   (_ULCAST_(3) << 22)
 
#define R5K_CONF_SE   (_ULCAST_(1) << 12)
 
#define R5K_CONF_SS   (_ULCAST_(3) << 20)
 
#define RM7K_CONF_SE   (_ULCAST_(1) << 3)
 
#define RM7K_CONF_TE   (_ULCAST_(1) << 12)
 
#define RM7K_CONF_CLK   (_ULCAST_(1) << 16)
 
#define RM7K_CONF_TC   (_ULCAST_(1) << 17)
 
#define RM7K_CONF_SI   (_ULCAST_(3) << 20)
 
#define RM7K_CONF_SC   (_ULCAST_(1) << 31)
 
#define R10K_CONF_DN   (_ULCAST_(3) << 3)
 
#define R10K_CONF_CT   (_ULCAST_(1) << 5)
 
#define R10K_CONF_PE   (_ULCAST_(1) << 6)
 
#define R10K_CONF_PM   (_ULCAST_(3) << 7)
 
#define R10K_CONF_EC   (_ULCAST_(15)<< 9)
 
#define R10K_CONF_SB   (_ULCAST_(1) << 13)
 
#define R10K_CONF_SK   (_ULCAST_(1) << 14)
 
#define R10K_CONF_SS   (_ULCAST_(7) << 16)
 
#define R10K_CONF_SC   (_ULCAST_(7) << 19)
 
#define R10K_CONF_DC   (_ULCAST_(7) << 26)
 
#define R10K_CONF_IC   (_ULCAST_(7) << 29)
 
#define VR41_CONF_CS   (_ULCAST_(1) << 12)
 
#define VR41_CONF_P4K   (_ULCAST_(1) << 13)
 
#define VR41_CONF_BP   (_ULCAST_(1) << 16)
 
#define VR41_CONF_M16   (_ULCAST_(1) << 20)
 
#define VR41_CONF_AD   (_ULCAST_(1) << 23)
 
#define R30XX_CONF_FDM   (_ULCAST_(1) << 19)
 
#define R30XX_CONF_REV   (_ULCAST_(1) << 22)
 
#define R30XX_CONF_AC   (_ULCAST_(1) << 23)
 
#define R30XX_CONF_RF   (_ULCAST_(1) << 24)
 
#define R30XX_CONF_HALT   (_ULCAST_(1) << 25)
 
#define R30XX_CONF_FPINT   (_ULCAST_(7) << 26)
 
#define R30XX_CONF_DBR   (_ULCAST_(1) << 29)
 
#define R30XX_CONF_SB   (_ULCAST_(1) << 30)
 
#define R30XX_CONF_LOCK   (_ULCAST_(1) << 31)
 
#define TX49_CONF_DC   (_ULCAST_(1) << 16)
 
#define TX49_CONF_IC   (_ULCAST_(1) << 17) /* conflict with CONF_SC */
 
#define TX49_CONF_HALT   (_ULCAST_(1) << 18)
 
#define TX49_CONF_CWFON   (_ULCAST_(1) << 27)
 
#define MIPS_CONF_MT   (_ULCAST_(7) << 7)
 
#define MIPS_CONF_AR   (_ULCAST_(7) << 10)
 
#define MIPS_CONF_AT   (_ULCAST_(3) << 13)
 
#define MIPS_CONF_M   (_ULCAST_(1) << 31)
 
#define MIPS_CONF1_FP   (_ULCAST_(1) << 0)
 
#define MIPS_CONF1_EP   (_ULCAST_(1) << 1)
 
#define MIPS_CONF1_CA   (_ULCAST_(1) << 2)
 
#define MIPS_CONF1_WR   (_ULCAST_(1) << 3)
 
#define MIPS_CONF1_PC   (_ULCAST_(1) << 4)
 
#define MIPS_CONF1_MD   (_ULCAST_(1) << 5)
 
#define MIPS_CONF1_C2   (_ULCAST_(1) << 6)
 
#define MIPS_CONF1_DA   (_ULCAST_(7) << 7)
 
#define MIPS_CONF1_DL   (_ULCAST_(7) << 10)
 
#define MIPS_CONF1_DS   (_ULCAST_(7) << 13)
 
#define MIPS_CONF1_IA   (_ULCAST_(7) << 16)
 
#define MIPS_CONF1_IL   (_ULCAST_(7) << 19)
 
#define MIPS_CONF1_IS   (_ULCAST_(7) << 22)
 
#define MIPS_CONF1_TLBS   (_ULCAST_(63)<< 25)
 
#define MIPS_CONF2_SA   (_ULCAST_(15)<< 0)
 
#define MIPS_CONF2_SL   (_ULCAST_(15)<< 4)
 
#define MIPS_CONF2_SS   (_ULCAST_(15)<< 8)
 
#define MIPS_CONF2_SU   (_ULCAST_(15)<< 12)
 
#define MIPS_CONF2_TA   (_ULCAST_(15)<< 16)
 
#define MIPS_CONF2_TL   (_ULCAST_(15)<< 20)
 
#define MIPS_CONF2_TS   (_ULCAST_(15)<< 24)
 
#define MIPS_CONF2_TU   (_ULCAST_(7) << 28)
 
#define MIPS_CONF3_TL   (_ULCAST_(1) << 0)
 
#define MIPS_CONF3_SM   (_ULCAST_(1) << 1)
 
#define MIPS_CONF3_MT   (_ULCAST_(1) << 2)
 
#define MIPS_CONF3_SP   (_ULCAST_(1) << 4)
 
#define MIPS_CONF3_VINT   (_ULCAST_(1) << 5)
 
#define MIPS_CONF3_VEIC   (_ULCAST_(1) << 6)
 
#define MIPS_CONF3_LPA   (_ULCAST_(1) << 7)
 
#define MIPS_CONF3_DSP   (_ULCAST_(1) << 10)
 
#define MIPS_CONF3_DSP2P   (_ULCAST_(1) << 11)
 
#define MIPS_CONF3_RXI   (_ULCAST_(1) << 12)
 
#define MIPS_CONF3_ULRI   (_ULCAST_(1) << 13)
 
#define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 
#define MIPS_CONF4_MMUEXTDEF   (_ULCAST_(3) << 14)
 
#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT   (_ULCAST_(1) << 14)
 
#define MIPS_CONF6_SYND   (_ULCAST_(1) << 13)
 
#define MIPS_CONF7_WII   (_ULCAST_(1) << 31)
 
#define MIPS_CONF7_RPS   (_ULCAST_(1) << 2)
 
#define MIPS_FPIR_S   (_ULCAST_(1) << 16)
 
#define MIPS_FPIR_D   (_ULCAST_(1) << 17)
 
#define MIPS_FPIR_PS   (_ULCAST_(1) << 18)
 
#define MIPS_FPIR_3D   (_ULCAST_(1) << 19)
 
#define MIPS_FPIR_W   (_ULCAST_(1) << 20)
 
#define MIPS_FPIR_L   (_ULCAST_(1) << 21)
 
#define MIPS_FPIR_F64   (_ULCAST_(1) << 22)
 
#define read_r10k_perf_cntr(counter)
 
#define write_r10k_perf_cntr(counter, val)
 
#define read_r10k_perf_event(counter)
 
#define write_r10k_perf_cntl(counter, val)
 
#define __read_32bit_c0_register(source, sel)
 
#define __read_64bit_c0_register(source, sel)
 
#define __write_32bit_c0_register(register, sel, value)
 
#define __write_64bit_c0_register(register, sel, value)
 
#define __read_ulong_c0_register(reg, sel)
 
#define __write_ulong_c0_register(reg, sel, val)
 
#define __read_32bit_c0_ctrl_register(source)
 
#define __write_32bit_c0_ctrl_register(register, value)
 
#define __read_64bit_c0_split(source, sel)
 
#define __write_64bit_c0_split(source, sel, val)
 
#define read_c0_index()   __read_32bit_c0_register($0, 0)
 
#define write_c0_index(val)   __write_32bit_c0_register($0, 0, val)
 
#define read_c0_random()   __read_32bit_c0_register($1, 0)
 
#define write_c0_random(val)   __write_32bit_c0_register($1, 0, val)
 
#define read_c0_entrylo0()   __read_ulong_c0_register($2, 0)
 
#define write_c0_entrylo0(val)   __write_ulong_c0_register($2, 0, val)
 
#define read_c0_entrylo1()   __read_ulong_c0_register($3, 0)
 
#define write_c0_entrylo1(val)   __write_ulong_c0_register($3, 0, val)
 
#define read_c0_conf()   __read_32bit_c0_register($3, 0)
 
#define write_c0_conf(val)   __write_32bit_c0_register($3, 0, val)
 
#define read_c0_context()   __read_ulong_c0_register($4, 0)
 
#define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
 
#define read_c0_userlocal()   __read_ulong_c0_register($4, 2)
 
#define write_c0_userlocal(val)   __write_ulong_c0_register($4, 2, val)
 
#define read_c0_pagemask()   __read_32bit_c0_register($5, 0)
 
#define write_c0_pagemask(val)   __write_32bit_c0_register($5, 0, val)
 
#define read_c0_pagegrain()   __read_32bit_c0_register($5, 1)
 
#define write_c0_pagegrain(val)   __write_32bit_c0_register($5, 1, val)
 
#define read_c0_wired()   __read_32bit_c0_register($6, 0)
 
#define write_c0_wired(val)   __write_32bit_c0_register($6, 0, val)
 
#define read_c0_info()   __read_32bit_c0_register($7, 0)
 
#define read_c0_cache()   __read_32bit_c0_register($7, 0) /* TX39xx */
 
#define write_c0_cache(val)   __write_32bit_c0_register($7, 0, val)
 
#define read_c0_badvaddr()   __read_ulong_c0_register($8, 0)
 
#define write_c0_badvaddr(val)   __write_ulong_c0_register($8, 0, val)
 
#define read_c0_count()   __read_32bit_c0_register($9, 0)
 
#define write_c0_count(val)   __write_32bit_c0_register($9, 0, val)
 
#define read_c0_count2()   __read_32bit_c0_register($9, 6) /* pnx8550 */
 
#define write_c0_count2(val)   __write_32bit_c0_register($9, 6, val)
 
#define read_c0_count3()   __read_32bit_c0_register($9, 7) /* pnx8550 */
 
#define write_c0_count3(val)   __write_32bit_c0_register($9, 7, val)
 
#define read_c0_entryhi()   __read_ulong_c0_register($10, 0)
 
#define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
 
#define read_c0_compare()   __read_32bit_c0_register($11, 0)
 
#define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
 
#define read_c0_compare2()   __read_32bit_c0_register($11, 6) /* pnx8550 */
 
#define write_c0_compare2(val)   __write_32bit_c0_register($11, 6, val)
 
#define read_c0_compare3()   __read_32bit_c0_register($11, 7) /* pnx8550 */
 
#define write_c0_compare3(val)   __write_32bit_c0_register($11, 7, val)
 
#define read_c0_status()   __read_32bit_c0_register($12, 0)
 
#define write_c0_status(val)   __write_32bit_c0_register($12, 0, val)
 
#define read_c0_cause()   __read_32bit_c0_register($13, 0)
 
#define write_c0_cause(val)   __write_32bit_c0_register($13, 0, val)
 
#define read_c0_epc()   __read_ulong_c0_register($14, 0)
 
#define write_c0_epc(val)   __write_ulong_c0_register($14, 0, val)
 
#define read_c0_prid()   __read_32bit_c0_register($15, 0)
 
#define read_c0_config()   __read_32bit_c0_register($16, 0)
 
#define read_c0_config1()   __read_32bit_c0_register($16, 1)
 
#define read_c0_config2()   __read_32bit_c0_register($16, 2)
 
#define read_c0_config3()   __read_32bit_c0_register($16, 3)
 
#define read_c0_config4()   __read_32bit_c0_register($16, 4)
 
#define read_c0_config5()   __read_32bit_c0_register($16, 5)
 
#define read_c0_config6()   __read_32bit_c0_register($16, 6)
 
#define read_c0_config7()   __read_32bit_c0_register($16, 7)
 
#define write_c0_config(val)   __write_32bit_c0_register($16, 0, val)
 
#define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
 
#define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
 
#define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
 
#define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
 
#define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
 
#define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
 
#define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
 
#define read_c0_watchlo0()   __read_ulong_c0_register($18, 0)
 
#define read_c0_watchlo1()   __read_ulong_c0_register($18, 1)
 
#define read_c0_watchlo2()   __read_ulong_c0_register($18, 2)
 
#define read_c0_watchlo3()   __read_ulong_c0_register($18, 3)
 
#define read_c0_watchlo4()   __read_ulong_c0_register($18, 4)
 
#define read_c0_watchlo5()   __read_ulong_c0_register($18, 5)
 
#define read_c0_watchlo6()   __read_ulong_c0_register($18, 6)
 
#define read_c0_watchlo7()   __read_ulong_c0_register($18, 7)
 
#define write_c0_watchlo0(val)   __write_ulong_c0_register($18, 0, val)
 
#define write_c0_watchlo1(val)   __write_ulong_c0_register($18, 1, val)
 
#define write_c0_watchlo2(val)   __write_ulong_c0_register($18, 2, val)
 
#define write_c0_watchlo3(val)   __write_ulong_c0_register($18, 3, val)
 
#define write_c0_watchlo4(val)   __write_ulong_c0_register($18, 4, val)
 
#define write_c0_watchlo5(val)   __write_ulong_c0_register($18, 5, val)
 
#define write_c0_watchlo6(val)   __write_ulong_c0_register($18, 6, val)
 
#define write_c0_watchlo7(val)   __write_ulong_c0_register($18, 7, val)
 
#define read_c0_watchhi0()   __read_32bit_c0_register($19, 0)
 
#define read_c0_watchhi1()   __read_32bit_c0_register($19, 1)
 
#define read_c0_watchhi2()   __read_32bit_c0_register($19, 2)
 
#define read_c0_watchhi3()   __read_32bit_c0_register($19, 3)
 
#define read_c0_watchhi4()   __read_32bit_c0_register($19, 4)
 
#define read_c0_watchhi5()   __read_32bit_c0_register($19, 5)
 
#define read_c0_watchhi6()   __read_32bit_c0_register($19, 6)
 
#define read_c0_watchhi7()   __read_32bit_c0_register($19, 7)
 
#define write_c0_watchhi0(val)   __write_32bit_c0_register($19, 0, val)
 
#define write_c0_watchhi1(val)   __write_32bit_c0_register($19, 1, val)
 
#define write_c0_watchhi2(val)   __write_32bit_c0_register($19, 2, val)
 
#define write_c0_watchhi3(val)   __write_32bit_c0_register($19, 3, val)
 
#define write_c0_watchhi4(val)   __write_32bit_c0_register($19, 4, val)
 
#define write_c0_watchhi5(val)   __write_32bit_c0_register($19, 5, val)
 
#define write_c0_watchhi6(val)   __write_32bit_c0_register($19, 6, val)
 
#define write_c0_watchhi7(val)   __write_32bit_c0_register($19, 7, val)
 
#define read_c0_xcontext()   __read_ulong_c0_register($20, 0)
 
#define write_c0_xcontext(val)   __write_ulong_c0_register($20, 0, val)
 
#define read_c0_intcontrol()   __read_32bit_c0_ctrl_register($20)
 
#define write_c0_intcontrol(val)   __write_32bit_c0_ctrl_register($20, val)
 
#define read_c0_framemask()   __read_32bit_c0_register($21, 0)
 
#define write_c0_framemask(val)   __write_32bit_c0_register($21, 0, val)
 
#define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
 
#define write_c0_perfcontrol(val)   __write_32bit_c0_register($22, 0, val)
 
#define read_c0_diag()   __read_32bit_c0_register($22, 0)
 
#define write_c0_diag(val)   __write_32bit_c0_register($22, 0, val)
 
#define read_c0_diag1()   __read_32bit_c0_register($22, 1)
 
#define write_c0_diag1(val)   __write_32bit_c0_register($22, 1, val)
 
#define read_c0_diag2()   __read_32bit_c0_register($22, 2)
 
#define write_c0_diag2(val)   __write_32bit_c0_register($22, 2, val)
 
#define read_c0_diag3()   __read_32bit_c0_register($22, 3)
 
#define write_c0_diag3(val)   __write_32bit_c0_register($22, 3, val)
 
#define read_c0_diag4()   __read_32bit_c0_register($22, 4)
 
#define write_c0_diag4(val)   __write_32bit_c0_register($22, 4, val)
 
#define read_c0_diag5()   __read_32bit_c0_register($22, 5)
 
#define write_c0_diag5(val)   __write_32bit_c0_register($22, 5, val)
 
#define read_c0_debug()   __read_32bit_c0_register($23, 0)
 
#define write_c0_debug(val)   __write_32bit_c0_register($23, 0, val)
 
#define read_c0_depc()   __read_ulong_c0_register($24, 0)
 
#define write_c0_depc(val)   __write_ulong_c0_register($24, 0, val)
 
#define read_c0_perfctrl0()   __read_32bit_c0_register($25, 0)
 
#define write_c0_perfctrl0(val)   __write_32bit_c0_register($25, 0, val)
 
#define read_c0_perfcntr0()   __read_32bit_c0_register($25, 1)
 
#define write_c0_perfcntr0(val)   __write_32bit_c0_register($25, 1, val)
 
#define read_c0_perfcntr0_64()   __read_64bit_c0_register($25, 1)
 
#define write_c0_perfcntr0_64(val)   __write_64bit_c0_register($25, 1, val)
 
#define read_c0_perfctrl1()   __read_32bit_c0_register($25, 2)
 
#define write_c0_perfctrl1(val)   __write_32bit_c0_register($25, 2, val)
 
#define read_c0_perfcntr1()   __read_32bit_c0_register($25, 3)
 
#define write_c0_perfcntr1(val)   __write_32bit_c0_register($25, 3, val)
 
#define read_c0_perfcntr1_64()   __read_64bit_c0_register($25, 3)
 
#define write_c0_perfcntr1_64(val)   __write_64bit_c0_register($25, 3, val)
 
#define read_c0_perfctrl2()   __read_32bit_c0_register($25, 4)
 
#define write_c0_perfctrl2(val)   __write_32bit_c0_register($25, 4, val)
 
#define read_c0_perfcntr2()   __read_32bit_c0_register($25, 5)
 
#define write_c0_perfcntr2(val)   __write_32bit_c0_register($25, 5, val)
 
#define read_c0_perfcntr2_64()   __read_64bit_c0_register($25, 5)
 
#define write_c0_perfcntr2_64(val)   __write_64bit_c0_register($25, 5, val)
 
#define read_c0_perfctrl3()   __read_32bit_c0_register($25, 6)
 
#define write_c0_perfctrl3(val)   __write_32bit_c0_register($25, 6, val)
 
#define read_c0_perfcntr3()   __read_32bit_c0_register($25, 7)
 
#define write_c0_perfcntr3(val)   __write_32bit_c0_register($25, 7, val)
 
#define read_c0_perfcntr3_64()   __read_64bit_c0_register($25, 7)
 
#define write_c0_perfcntr3_64(val)   __write_64bit_c0_register($25, 7, val)
 
#define read_c0_perfcount()   __read_64bit_c0_register($25, 0)
 
#define write_c0_perfcount(val)   __write_64bit_c0_register($25, 0, val)
 
#define read_c0_ecc()   __read_32bit_c0_register($26, 0)
 
#define write_c0_ecc(val)   __write_32bit_c0_register($26, 0, val)
 
#define read_c0_derraddr0()   __read_ulong_c0_register($26, 1)
 
#define write_c0_derraddr0(val)   __write_ulong_c0_register($26, 1, val)
 
#define read_c0_cacheerr()   __read_32bit_c0_register($27, 0)
 
#define read_c0_derraddr1()   __read_ulong_c0_register($27, 1)
 
#define write_c0_derraddr1(val)   __write_ulong_c0_register($27, 1, val)
 
#define read_c0_taglo()   __read_32bit_c0_register($28, 0)
 
#define write_c0_taglo(val)   __write_32bit_c0_register($28, 0, val)
 
#define read_c0_dtaglo()   __read_32bit_c0_register($28, 2)
 
#define write_c0_dtaglo(val)   __write_32bit_c0_register($28, 2, val)
 
#define read_c0_ddatalo()   __read_32bit_c0_register($28, 3)
 
#define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
 
#define read_c0_staglo()   __read_32bit_c0_register($28, 4)
 
#define write_c0_staglo(val)   __write_32bit_c0_register($28, 4, val)
 
#define read_c0_taghi()   __read_32bit_c0_register($29, 0)
 
#define write_c0_taghi(val)   __write_32bit_c0_register($29, 0, val)
 
#define read_c0_errorepc()   __read_ulong_c0_register($30, 0)
 
#define write_c0_errorepc(val)   __write_ulong_c0_register($30, 0, val)
 
#define read_c0_hwrena()   __read_32bit_c0_register($7, 0)
 
#define write_c0_hwrena(val)   __write_32bit_c0_register($7, 0, val)
 
#define read_c0_intctl()   __read_32bit_c0_register($12, 1)
 
#define write_c0_intctl(val)   __write_32bit_c0_register($12, 1, val)
 
#define read_c0_srsctl()   __read_32bit_c0_register($12, 2)
 
#define write_c0_srsctl(val)   __write_32bit_c0_register($12, 2, val)
 
#define read_c0_srsmap()   __read_32bit_c0_register($12, 3)
 
#define write_c0_srsmap(val)   __write_32bit_c0_register($12, 3, val)
 
#define read_c0_ebase()   __read_32bit_c0_register($15, 1)
 
#define write_c0_ebase(val)   __write_32bit_c0_register($15, 1, val)
 
#define read_c0_cvmcount()   __read_ulong_c0_register($9, 6)
 
#define write_c0_cvmcount(val)   __write_ulong_c0_register($9, 6, val)
 
#define read_c0_cvmctl()   __read_64bit_c0_register($9, 7)
 
#define write_c0_cvmctl(val)   __write_64bit_c0_register($9, 7, val)
 
#define read_c0_cvmmemctl()   __read_64bit_c0_register($11, 7)
 
#define write_c0_cvmmemctl(val)   __write_64bit_c0_register($11, 7, val)
 
#define read_octeon_c0_icacheerr()   __read_64bit_c0_register($27, 0)
 
#define write_octeon_c0_icacheerr(val)   __write_64bit_c0_register($27, 0, val)
 
#define read_octeon_c0_dcacheerr()   __read_64bit_c0_register($27, 1)
 
#define write_octeon_c0_dcacheerr(val)   __write_64bit_c0_register($27, 1, val)
 
#define read_c0_brcm_config_0()   __read_32bit_c0_register($22, 0)
 
#define write_c0_brcm_config_0(val)   __write_32bit_c0_register($22, 0, val)
 
#define read_c0_brcm_bus_pll()   __read_32bit_c0_register($22, 4)
 
#define write_c0_brcm_bus_pll(val)   __write_32bit_c0_register($22, 4, val)
 
#define read_c0_brcm_reset()   __read_32bit_c0_register($22, 5)
 
#define write_c0_brcm_reset(val)   __write_32bit_c0_register($22, 5, val)
 
#define read_c0_brcm_cmt_intr()   __read_32bit_c0_register($22, 1)
 
#define write_c0_brcm_cmt_intr(val)   __write_32bit_c0_register($22, 1, val)
 
#define read_c0_brcm_cmt_ctrl()   __read_32bit_c0_register($22, 2)
 
#define write_c0_brcm_cmt_ctrl(val)   __write_32bit_c0_register($22, 2, val)
 
#define read_c0_brcm_cmt_local()   __read_32bit_c0_register($22, 3)
 
#define write_c0_brcm_cmt_local(val)   __write_32bit_c0_register($22, 3, val)
 
#define read_c0_brcm_config_1()   __read_32bit_c0_register($22, 5)
 
#define write_c0_brcm_config_1(val)   __write_32bit_c0_register($22, 5, val)
 
#define read_c0_brcm_cbr()   __read_32bit_c0_register($22, 6)
 
#define write_c0_brcm_cbr(val)   __write_32bit_c0_register($22, 6, val)
 
#define read_c0_brcm_config()   __read_32bit_c0_register($22, 0)
 
#define write_c0_brcm_config(val)   __write_32bit_c0_register($22, 0, val)
 
#define read_c0_brcm_mode()   __read_32bit_c0_register($22, 1)
 
#define write_c0_brcm_mode(val)   __write_32bit_c0_register($22, 1, val)
 
#define read_c0_brcm_action()   __read_32bit_c0_register($22, 2)
 
#define write_c0_brcm_action(val)   __write_32bit_c0_register($22, 2, val)
 
#define read_c0_brcm_edsp()   __read_32bit_c0_register($22, 3)
 
#define write_c0_brcm_edsp(val)   __write_32bit_c0_register($22, 3, val)
 
#define read_c0_brcm_bootvec()   __read_32bit_c0_register($22, 4)
 
#define write_c0_brcm_bootvec(val)   __write_32bit_c0_register($22, 4, val)
 
#define read_c0_brcm_sleepcount()   __read_32bit_c0_register($22, 7)
 
#define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
 
#define read_32bit_cp1_register(source)
 
#define rddsp(mask)
 
#define wrdsp(val, mask)
 
#define mfhi0()
 
#define mfhi1()
 
#define mfhi2()
 
#define mfhi3()
 
#define mflo0()
 
#define mflo1()
 
#define mflo2()
 
#define mflo3()
 
#define mthi0(x)
 
#define mthi1(x)
 
#define mthi2(x)
 
#define mthi3(x)
 
#define mtlo0(x)
 
#define mtlo1(x)
 
#define mtlo2(x)
 
#define mtlo3(x)
 
#define __BUILD_SET_C0(name)
 

Macro Definition Documentation

#define __BUILD_SET_C0 (   name)

Definition at line 1517 of file mipsregs.h.

#define __read_32bit_c0_ctrl_register (   source)
Value:
({ int __res; \
__asm__ __volatile__( \
"cfc0\t%0, " #source "\n\t" \
: "=r" (__res)); \
__res; \
})

Definition at line 755 of file mipsregs.h.

#define __read_32bit_c0_register (   source,
  sel 
)
Value:
({ int __res; \
if (sel == 0) \
__asm__ __volatile__( \
"mfc0\t%0, " #source "\n\t" \
: "=r" (__res)); \
else \
__asm__ __volatile__( \
".set\tmips32\n\t" \
"mfc0\t%0, " #source ", " #sel "\n\t" \
".set\tmips0\n\t" \
: "=r" (__res)); \
__res; \
})

Definition at line 673 of file mipsregs.h.

#define __read_64bit_c0_register (   source,
  sel 
)
Value:
({ unsigned long long __res; \
if (sizeof(unsigned long) == 4) \
__res = __read_64bit_c0_split(source, sel); \
else if (sel == 0) \
__asm__ __volatile__( \
".set\tmips3\n\t" \
"dmfc0\t%0, " #source "\n\t" \
".set\tmips0" \
: "=r" (__res)); \
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dmfc0\t%0, " #source ", " #sel "\n\t" \
".set\tmips0" \
: "=r" (__res)); \
__res; \
})

Definition at line 688 of file mipsregs.h.

#define __read_64bit_c0_split (   source,
  sel 
)
Value:
({ \
unsigned long long __val; \
unsigned long __flags; \
\
local_irq_save(__flags); \
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dmfc0\t%M0, " #source "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \
"dsra\t%M0, %M0, 32\n\t" \
"dsra\t%L0, %L0, 32\n\t" \
".set\tmips0" \
: "=r" (__val)); \
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dmfc0\t%M0, " #source ", " #sel "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \
"dsra\t%M0, %M0, 32\n\t" \
"dsra\t%L0, %L0, 32\n\t" \
".set\tmips0" \
: "=r" (__val)); \
local_irq_restore(__flags); \
\
__val; \
})

Definition at line 774 of file mipsregs.h.

#define __read_ulong_c0_register (   reg,
  sel 
)
Value:
((sizeof(unsigned long) == 4) ? \
(unsigned long) __read_32bit_c0_register(reg, sel) : \
(unsigned long) __read_64bit_c0_register(reg, sel))

Definition at line 739 of file mipsregs.h.

#define __STR (   x)    #x

Definition at line 25 of file mipsregs.h.

#define __write_32bit_c0_ctrl_register (   register,
  value 
)
Value:
do { \
__asm__ __volatile__( \
"ctc0\t%z0, " #register "\n\t" \
: : "Jr" ((unsigned int)(value))); \
} while (0)

Definition at line 763 of file mipsregs.h.

#define __write_32bit_c0_register (   register,
  sel,
  value 
)
Value:
do { \
if (sel == 0) \
__asm__ __volatile__( \
"mtc0\t%z0, " #register "\n\t" \
: : "Jr" ((unsigned int)(value))); \
else \
__asm__ __volatile__( \
".set\tmips32\n\t" \
"mtc0\t%z0, " #register ", " #sel "\n\t" \
".set\tmips0" \
: : "Jr" ((unsigned int)(value))); \
} while (0)

Definition at line 707 of file mipsregs.h.

#define __write_64bit_c0_register (   register,
  sel,
  value 
)
Value:
do { \
if (sizeof(unsigned long) == 4) \
__write_64bit_c0_split(register, sel, value); \
else if (sel == 0) \
__asm__ __volatile__( \
".set\tmips3\n\t" \
"dmtc0\t%z0, " #register "\n\t" \
".set\tmips0" \
: : "Jr" (value)); \
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dmtc0\t%z0, " #register ", " #sel "\n\t" \
".set\tmips0" \
: : "Jr" (value)); \
} while (0)

Definition at line 721 of file mipsregs.h.

#define __write_64bit_c0_split (   source,
  sel,
  val 
)
Value:
do { \
unsigned long __flags; \
\
local_irq_save(__flags); \
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dsll\t%L0, %L0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
"dsll\t%M0, %M0, 32\n\t" \
"or\t%L0, %L0, %M0\n\t" \
"dmtc0\t%L0, " #source "\n\t" \
".set\tmips0" \
: : "r" (val)); \
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dsll\t%L0, %L0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
"dsll\t%M0, %M0, 32\n\t" \
"or\t%L0, %L0, %M0\n\t" \
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
".set\tmips0" \
: : "r" (val)); \
local_irq_restore(__flags); \
} while (0)

Definition at line 803 of file mipsregs.h.

#define __write_ulong_c0_register (   reg,
  sel,
  val 
)
Value:
do { \
if (sizeof(unsigned long) == 4) \
__write_32bit_c0_register(reg, sel, val); \
else \
__write_64bit_c0_register(reg, sel, val); \
} while (0)

Definition at line 744 of file mipsregs.h.

#define _ULCAST_   (unsigned long)

Definition at line 37 of file mipsregs.h.

#define C_IRQ0   (_ULCAST_(1) << 10)

Definition at line 285 of file mipsregs.h.

#define C_IRQ1   (_ULCAST_(1) << 11)

Definition at line 286 of file mipsregs.h.

#define C_IRQ2   (_ULCAST_(1) << 12)

Definition at line 287 of file mipsregs.h.

#define C_IRQ3   (_ULCAST_(1) << 13)

Definition at line 288 of file mipsregs.h.

#define C_IRQ4   (_ULCAST_(1) << 14)

Definition at line 289 of file mipsregs.h.

#define C_IRQ5   (_ULCAST_(1) << 15)

Definition at line 290 of file mipsregs.h.

#define C_SW0   (_ULCAST_(1) << 8)

Definition at line 283 of file mipsregs.h.

#define C_SW1   (_ULCAST_(1) << 9)

Definition at line 284 of file mipsregs.h.

#define CAUSEB_BD   31

Definition at line 467 of file mipsregs.h.

#define CAUSEB_CE   28

Definition at line 463 of file mipsregs.h.

#define CAUSEB_EXCCODE   2

Definition at line 439 of file mipsregs.h.

#define CAUSEB_IP   8

Definition at line 441 of file mipsregs.h.

#define CAUSEB_IP0   8

Definition at line 443 of file mipsregs.h.

#define CAUSEB_IP1   9

Definition at line 445 of file mipsregs.h.

#define CAUSEB_IP2   10

Definition at line 447 of file mipsregs.h.

#define CAUSEB_IP3   11

Definition at line 449 of file mipsregs.h.

#define CAUSEB_IP4   12

Definition at line 451 of file mipsregs.h.

#define CAUSEB_IP5   13

Definition at line 453 of file mipsregs.h.

#define CAUSEB_IP6   14

Definition at line 455 of file mipsregs.h.

#define CAUSEB_IP7   15

Definition at line 457 of file mipsregs.h.

#define CAUSEB_IV   23

Definition at line 459 of file mipsregs.h.

#define CAUSEB_PCI   26

Definition at line 461 of file mipsregs.h.

#define CAUSEB_TI   30

Definition at line 465 of file mipsregs.h.

#define CAUSEF_BD   (_ULCAST_(1) << 31)

Definition at line 468 of file mipsregs.h.

#define CAUSEF_CE   (_ULCAST_(3) << 28)

Definition at line 464 of file mipsregs.h.

#define CAUSEF_EXCCODE   (_ULCAST_(31) << 2)

Definition at line 440 of file mipsregs.h.

#define CAUSEF_IP   (_ULCAST_(255) << 8)

Definition at line 442 of file mipsregs.h.

#define CAUSEF_IP0   (_ULCAST_(1) << 8)

Definition at line 444 of file mipsregs.h.

#define CAUSEF_IP1   (_ULCAST_(1) << 9)

Definition at line 446 of file mipsregs.h.

#define CAUSEF_IP2   (_ULCAST_(1) << 10)

Definition at line 448 of file mipsregs.h.

#define CAUSEF_IP3   (_ULCAST_(1) << 11)

Definition at line 450 of file mipsregs.h.

#define CAUSEF_IP4   (_ULCAST_(1) << 12)

Definition at line 452 of file mipsregs.h.

#define CAUSEF_IP5   (_ULCAST_(1) << 13)

Definition at line 454 of file mipsregs.h.

#define CAUSEF_IP6   (_ULCAST_(1) << 14)

Definition at line 456 of file mipsregs.h.

#define CAUSEF_IP7   (_ULCAST_(1) << 15)

Definition at line 458 of file mipsregs.h.

#define CAUSEF_IV   (_ULCAST_(1) << 23)

Definition at line 460 of file mipsregs.h.

#define CAUSEF_PCI   (_ULCAST_(1) << 26)

Definition at line 462 of file mipsregs.h.

#define CAUSEF_TI   (_ULCAST_(1) << 30)

Definition at line 466 of file mipsregs.h.

#define CONF_BE   (_ULCAST_(1) << 15)

Definition at line 483 of file mipsregs.h.

#define CONF_CM   (_ULCAST_(1) << 31)

Definition at line 498 of file mipsregs.h.

#define CONF_CM_CACHABLE_ACCELERATED   7

Definition at line 481 of file mipsregs.h.

#define CONF_CM_CACHABLE_CE   4

Definition at line 478 of file mipsregs.h.

#define CONF_CM_CACHABLE_COW   5

Definition at line 479 of file mipsregs.h.

#define CONF_CM_CACHABLE_CUW   6

Definition at line 480 of file mipsregs.h.

#define CONF_CM_CACHABLE_NO_WA   0

Definition at line 474 of file mipsregs.h.

#define CONF_CM_CACHABLE_NONCOHERENT   3

Definition at line 477 of file mipsregs.h.

#define CONF_CM_CACHABLE_WA   1

Definition at line 475 of file mipsregs.h.

#define CONF_CM_CMASK   7

Definition at line 482 of file mipsregs.h.

#define CONF_CM_UNCACHED   2

Definition at line 476 of file mipsregs.h.

#define CONF_CU   (_ULCAST_(1) << 3)

Definition at line 486 of file mipsregs.h.

#define CONF_DB   (_ULCAST_(1) << 4)

Definition at line 487 of file mipsregs.h.

#define CONF_DC   (_ULCAST_(7) << 6)

Definition at line 489 of file mipsregs.h.

#define CONF_EB   (_ULCAST_(1) << 13)

Definition at line 491 of file mipsregs.h.

#define CONF_EC   (_ULCAST_(7) << 28)

Definition at line 497 of file mipsregs.h.

#define CONF_EM   (_ULCAST_(1) << 14)

Definition at line 492 of file mipsregs.h.

#define CONF_EP   (_ULCAST_(15)<< 24)

Definition at line 496 of file mipsregs.h.

#define CONF_EW   (_ULCAST_(3) << 18)

Definition at line 495 of file mipsregs.h.

#define CONF_IB   (_ULCAST_(1) << 5)

Definition at line 488 of file mipsregs.h.

#define CONF_IC   (_ULCAST_(7) << 9)

Definition at line 490 of file mipsregs.h.

#define CONF_SC   (_ULCAST_(1) << 17)

Definition at line 494 of file mipsregs.h.

#define CONF_SM   (_ULCAST_(1) << 16)

Definition at line 493 of file mipsregs.h.

#define CP0_BADVADDR   $8

Definition at line 52 of file mipsregs.h.

#define CP0_CACHEERR   $27

Definition at line 71 of file mipsregs.h.

#define CP0_CALG   $17

Definition at line 87 of file mipsregs.h.

#define CP0_CAUSE   $13

Definition at line 57 of file mipsregs.h.

#define CP0_COMPARE   $11

Definition at line 55 of file mipsregs.h.

#define CP0_CONF   $3

Definition at line 47 of file mipsregs.h.

#define CP0_CONFIG   $16

Definition at line 60 of file mipsregs.h.

#define CP0_CONTEXT   $4

Definition at line 48 of file mipsregs.h.

#define CP0_COUNT   $9

Definition at line 53 of file mipsregs.h.

#define CP0_DBASE   $2

Definition at line 85 of file mipsregs.h.

#define CP0_DBOUND   $3

Definition at line 86 of file mipsregs.h.

#define CP0_DEBUG   $23

Definition at line 67 of file mipsregs.h.

#define CP0_DEPC   $24

Definition at line 68 of file mipsregs.h.

#define CP0_DESAVE   $31

Definition at line 75 of file mipsregs.h.

#define CP0_DIAGNOSTIC   $22

Definition at line 66 of file mipsregs.h.

#define CP0_DWATCH   $19

Definition at line 89 of file mipsregs.h.

#define CP0_ECC   $26

Definition at line 70 of file mipsregs.h.

#define CP0_ENTRYHI   $10

Definition at line 54 of file mipsregs.h.

#define CP0_ENTRYLO0   $2

Definition at line 45 of file mipsregs.h.

#define CP0_ENTRYLO1   $3

Definition at line 46 of file mipsregs.h.

#define CP0_EPC   $14

Definition at line 58 of file mipsregs.h.

#define CP0_ERROREPC   $30

Definition at line 74 of file mipsregs.h.

#define CP0_FRAMEMASK   $21

Definition at line 65 of file mipsregs.h.

#define CP0_IBASE   $0

Definition at line 83 of file mipsregs.h.

#define CP0_IBOUND   $1

Definition at line 84 of file mipsregs.h.

#define CP0_INDEX   $0

Definition at line 43 of file mipsregs.h.

#define CP0_INFO   $7

Definition at line 51 of file mipsregs.h.

#define CP0_IWATCH   $18

Definition at line 88 of file mipsregs.h.

#define CP0_LLADDR   $17

Definition at line 61 of file mipsregs.h.

#define CP0_PAGEMASK   $5

Definition at line 49 of file mipsregs.h.

#define CP0_PERFORMANCE   $25

Definition at line 69 of file mipsregs.h.

#define CP0_PRID   $15

Definition at line 59 of file mipsregs.h.

#define CP0_RANDOM   $1

Definition at line 44 of file mipsregs.h.

#define CP0_S1_DERRADDR0   $26

Definition at line 94 of file mipsregs.h.

#define CP0_S1_DERRADDR1   $27

Definition at line 95 of file mipsregs.h.

#define CP0_S1_INTCONTROL   $20

Definition at line 96 of file mipsregs.h.

#define CP0_S2_SRSCTL   $12 /* MIPSR2 */

Definition at line 101 of file mipsregs.h.

#define CP0_S3_SRSMAP   $12 /* MIPSR2 */

Definition at line 106 of file mipsregs.h.

#define CP0_STATUS   $12

Definition at line 56 of file mipsregs.h.

#define CP0_TAGHI   $29

Definition at line 73 of file mipsregs.h.

#define CP0_TAGLO   $28

Definition at line 72 of file mipsregs.h.

#define CP0_TX39_CACHE   $7

Definition at line 111 of file mipsregs.h.

#define CP0_WATCHHI   $19

Definition at line 63 of file mipsregs.h.

#define CP0_WATCHLO   $18

Definition at line 62 of file mipsregs.h.

#define CP0_WIRED   $6

Definition at line 50 of file mipsregs.h.

#define CP0_XCONTEXT   $20

Definition at line 64 of file mipsregs.h.

#define CP1_REVISION   $0

Definition at line 116 of file mipsregs.h.

#define CP1_STATUS   $31

Definition at line 117 of file mipsregs.h.

#define FPU_CSR_ALL_E   0x00000f80

Definition at line 156 of file mipsregs.h.

#define FPU_CSR_ALL_S   0x0000007c

Definition at line 163 of file mipsregs.h.

#define FPU_CSR_ALL_X   0x0003f000

Definition at line 148 of file mipsregs.h.

#define FPU_CSR_COND   0x00800000 /* $fcc0 */

Definition at line 127 of file mipsregs.h.

#define FPU_CSR_COND0   0x00800000 /* $fcc0 */

Definition at line 128 of file mipsregs.h.

#define FPU_CSR_COND1   0x02000000 /* $fcc1 */

Definition at line 129 of file mipsregs.h.

#define FPU_CSR_COND2   0x04000000 /* $fcc2 */

Definition at line 130 of file mipsregs.h.

#define FPU_CSR_COND3   0x08000000 /* $fcc3 */

Definition at line 131 of file mipsregs.h.

#define FPU_CSR_COND4   0x10000000 /* $fcc4 */

Definition at line 132 of file mipsregs.h.

#define FPU_CSR_COND5   0x20000000 /* $fcc5 */

Definition at line 133 of file mipsregs.h.

#define FPU_CSR_COND6   0x40000000 /* $fcc6 */

Definition at line 134 of file mipsregs.h.

#define FPU_CSR_COND7   0x80000000 /* $fcc7 */

Definition at line 135 of file mipsregs.h.

#define FPU_CSR_DIV_E   0x00000400

Definition at line 158 of file mipsregs.h.

#define FPU_CSR_DIV_S   0x00000020

Definition at line 165 of file mipsregs.h.

#define FPU_CSR_DIV_X   0x00008000

Definition at line 151 of file mipsregs.h.

#define FPU_CSR_FLUSH   0x01000000 /* flush denormalised results to 0 */

Definition at line 126 of file mipsregs.h.

#define FPU_CSR_INE_E   0x00000080

Definition at line 161 of file mipsregs.h.

#define FPU_CSR_INE_S   0x00000004

Definition at line 168 of file mipsregs.h.

#define FPU_CSR_INE_X   0x00001000

Definition at line 154 of file mipsregs.h.

#define FPU_CSR_INV_E   0x00000800

Definition at line 157 of file mipsregs.h.

#define FPU_CSR_INV_S   0x00000040

Definition at line 164 of file mipsregs.h.

#define FPU_CSR_INV_X   0x00010000

Definition at line 150 of file mipsregs.h.

#define FPU_CSR_OVF_E   0x00000200

Definition at line 159 of file mipsregs.h.

#define FPU_CSR_OVF_S   0x00000010

Definition at line 166 of file mipsregs.h.

#define FPU_CSR_OVF_X   0x00004000

Definition at line 152 of file mipsregs.h.

#define FPU_CSR_RD   0x3 /* towards -Infinity */

Definition at line 175 of file mipsregs.h.

#define FPU_CSR_RM   0x00000003

Definition at line 171 of file mipsregs.h.

#define FPU_CSR_RN   0x0 /* nearest */

Definition at line 172 of file mipsregs.h.

#define FPU_CSR_RSVD   0x001c0000

Definition at line 141 of file mipsregs.h.

#define FPU_CSR_RU   0x2 /* towards +Infinity */

Definition at line 174 of file mipsregs.h.

#define FPU_CSR_RZ   0x1 /* towards zero */

Definition at line 173 of file mipsregs.h.

#define FPU_CSR_UDF_E   0x00000100

Definition at line 160 of file mipsregs.h.

#define FPU_CSR_UDF_S   0x00000008

Definition at line 167 of file mipsregs.h.

#define FPU_CSR_UDF_X   0x00002000

Definition at line 153 of file mipsregs.h.

#define FPU_CSR_UNI_X   0x00020000

Definition at line 149 of file mipsregs.h.

#define IE_IRQ0   (_ULCAST_(1) << 10)

Definition at line 273 of file mipsregs.h.

#define IE_IRQ1   (_ULCAST_(1) << 11)

Definition at line 274 of file mipsregs.h.

#define IE_IRQ2   (_ULCAST_(1) << 12)

Definition at line 275 of file mipsregs.h.

#define IE_IRQ3   (_ULCAST_(1) << 13)

Definition at line 276 of file mipsregs.h.

#define IE_IRQ4   (_ULCAST_(1) << 14)

Definition at line 277 of file mipsregs.h.

#define IE_IRQ5   (_ULCAST_(1) << 15)

Definition at line 278 of file mipsregs.h.

#define IE_SW0   (_ULCAST_(1) << 8)

Definition at line 271 of file mipsregs.h.

#define IE_SW1   (_ULCAST_(1) << 9)

Definition at line 272 of file mipsregs.h.

#define INTCTLB_IPPCI   26

Definition at line 429 of file mipsregs.h.

#define INTCTLB_IPTI   29

Definition at line 431 of file mipsregs.h.

#define INTCTLF_IPPCI   (_ULCAST_(7) << INTCTLB_IPPCI)

Definition at line 430 of file mipsregs.h.

#define INTCTLF_IPTI   (_ULCAST_(7) << INTCTLB_IPTI)

Definition at line 432 of file mipsregs.h.

#define KSU_KERNEL   0x00000000

Definition at line 301 of file mipsregs.h.

#define KSU_SUPERVISOR   0x00000008

Definition at line 300 of file mipsregs.h.

#define KSU_USER   0x00000010

Definition at line 299 of file mipsregs.h.

#define mfhi0 ( )
Value:
({ \
unsigned long __treg; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" # mfhi %0, $ac0 \n" \
" .word 0x00000810 \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__treg)); \
__treg; \
})

Definition at line 1217 of file mipsregs.h.

#define mfhi1 ( )
Value:
({ \
unsigned long __treg; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" # mfhi %0, $ac1 \n" \
" .word 0x00200810 \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__treg)); \
__treg; \
})

Definition at line 1232 of file mipsregs.h.

#define mfhi2 ( )
Value:
({ \
unsigned long __treg; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" # mfhi %0, $ac2 \n" \
" .word 0x00400810 \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__treg)); \
__treg; \
})

Definition at line 1247 of file mipsregs.h.

#define mfhi3 ( )
Value:
({ \
unsigned long __treg; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" # mfhi %0, $ac3 \n" \
" .word 0x00600810 \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__treg)); \
__treg; \
})

Definition at line 1262 of file mipsregs.h.

#define mflo0 ( )
Value:
({ \
unsigned long __treg; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" # mflo %0, $ac0 \n" \
" .word 0x00000812 \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__treg)); \
__treg; \
})

Definition at line 1277 of file mipsregs.h.

#define mflo1 ( )
Value:
({ \
unsigned long __treg; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" # mflo %0, $ac1 \n" \
" .word 0x00200812 \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__treg)); \
__treg; \
})

Definition at line 1292 of file mipsregs.h.

#define mflo2 ( )
Value:
({ \
unsigned long __treg; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" # mflo %0, $ac2 \n" \
" .word 0x00400812 \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__treg)); \
__treg; \
})

Definition at line 1307 of file mipsregs.h.

#define mflo3 ( )
Value:
({ \
unsigned long __treg; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" # mflo %0, $ac3 \n" \
" .word 0x00600812 \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__treg)); \
__treg; \
})

Definition at line 1322 of file mipsregs.h.

#define MIPS_CONF1_C2   (_ULCAST_(1) << 6)

Definition at line 569 of file mipsregs.h.

#define MIPS_CONF1_CA   (_ULCAST_(1) << 2)

Definition at line 565 of file mipsregs.h.

#define MIPS_CONF1_DA   (_ULCAST_(7) << 7)

Definition at line 570 of file mipsregs.h.

#define MIPS_CONF1_DL   (_ULCAST_(7) << 10)

Definition at line 571 of file mipsregs.h.

#define MIPS_CONF1_DS   (_ULCAST_(7) << 13)

Definition at line 572 of file mipsregs.h.

#define MIPS_CONF1_EP   (_ULCAST_(1) << 1)

Definition at line 564 of file mipsregs.h.

#define MIPS_CONF1_FP   (_ULCAST_(1) << 0)

Definition at line 563 of file mipsregs.h.

#define MIPS_CONF1_IA   (_ULCAST_(7) << 16)

Definition at line 573 of file mipsregs.h.

#define MIPS_CONF1_IL   (_ULCAST_(7) << 19)

Definition at line 574 of file mipsregs.h.

#define MIPS_CONF1_IS   (_ULCAST_(7) << 22)

Definition at line 575 of file mipsregs.h.

#define MIPS_CONF1_MD   (_ULCAST_(1) << 5)

Definition at line 568 of file mipsregs.h.

#define MIPS_CONF1_PC   (_ULCAST_(1) << 4)

Definition at line 567 of file mipsregs.h.

#define MIPS_CONF1_TLBS   (_ULCAST_(63)<< 25)

Definition at line 576 of file mipsregs.h.

#define MIPS_CONF1_WR   (_ULCAST_(1) << 3)

Definition at line 566 of file mipsregs.h.

#define MIPS_CONF2_SA   (_ULCAST_(15)<< 0)

Definition at line 578 of file mipsregs.h.

#define MIPS_CONF2_SL   (_ULCAST_(15)<< 4)

Definition at line 579 of file mipsregs.h.

#define MIPS_CONF2_SS   (_ULCAST_(15)<< 8)

Definition at line 580 of file mipsregs.h.

#define MIPS_CONF2_SU   (_ULCAST_(15)<< 12)

Definition at line 581 of file mipsregs.h.

#define MIPS_CONF2_TA   (_ULCAST_(15)<< 16)

Definition at line 582 of file mipsregs.h.

#define MIPS_CONF2_TL   (_ULCAST_(15)<< 20)

Definition at line 583 of file mipsregs.h.

#define MIPS_CONF2_TS   (_ULCAST_(15)<< 24)

Definition at line 584 of file mipsregs.h.

#define MIPS_CONF2_TU   (_ULCAST_(7) << 28)

Definition at line 585 of file mipsregs.h.

#define MIPS_CONF3_DSP   (_ULCAST_(1) << 10)

Definition at line 594 of file mipsregs.h.

#define MIPS_CONF3_DSP2P   (_ULCAST_(1) << 11)

Definition at line 595 of file mipsregs.h.

#define MIPS_CONF3_LPA   (_ULCAST_(1) << 7)

Definition at line 593 of file mipsregs.h.

#define MIPS_CONF3_MT   (_ULCAST_(1) << 2)

Definition at line 589 of file mipsregs.h.

#define MIPS_CONF3_RXI   (_ULCAST_(1) << 12)

Definition at line 596 of file mipsregs.h.

#define MIPS_CONF3_SM   (_ULCAST_(1) << 1)

Definition at line 588 of file mipsregs.h.

#define MIPS_CONF3_SP   (_ULCAST_(1) << 4)

Definition at line 590 of file mipsregs.h.

#define MIPS_CONF3_TL   (_ULCAST_(1) << 0)

Definition at line 587 of file mipsregs.h.

#define MIPS_CONF3_ULRI   (_ULCAST_(1) << 13)

Definition at line 597 of file mipsregs.h.

#define MIPS_CONF3_VEIC   (_ULCAST_(1) << 6)

Definition at line 592 of file mipsregs.h.

#define MIPS_CONF3_VINT   (_ULCAST_(1) << 5)

Definition at line 591 of file mipsregs.h.

#define MIPS_CONF4_MMUEXTDEF   (_ULCAST_(3) << 14)

Definition at line 600 of file mipsregs.h.

#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT   (_ULCAST_(1) << 14)

Definition at line 601 of file mipsregs.h.

#define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)

Definition at line 599 of file mipsregs.h.

#define MIPS_CONF6_SYND   (_ULCAST_(1) << 13)

Definition at line 603 of file mipsregs.h.

#define MIPS_CONF7_RPS   (_ULCAST_(1) << 2)

Definition at line 607 of file mipsregs.h.

#define MIPS_CONF7_WII   (_ULCAST_(1) << 31)

Definition at line 605 of file mipsregs.h.

#define MIPS_CONF_AR   (_ULCAST_(7) << 10)

Definition at line 556 of file mipsregs.h.

#define MIPS_CONF_AT   (_ULCAST_(3) << 13)

Definition at line 557 of file mipsregs.h.

#define MIPS_CONF_M   (_ULCAST_(1) << 31)

Definition at line 558 of file mipsregs.h.

#define MIPS_CONF_MT   (_ULCAST_(7) << 7)

Definition at line 555 of file mipsregs.h.

#define MIPS_FPIR_3D   (_ULCAST_(1) << 19)

Definition at line 616 of file mipsregs.h.

#define MIPS_FPIR_D   (_ULCAST_(1) << 17)

Definition at line 614 of file mipsregs.h.

#define MIPS_FPIR_F64   (_ULCAST_(1) << 22)

Definition at line 619 of file mipsregs.h.

#define MIPS_FPIR_L   (_ULCAST_(1) << 21)

Definition at line 618 of file mipsregs.h.

#define MIPS_FPIR_PS   (_ULCAST_(1) << 18)

Definition at line 615 of file mipsregs.h.

#define MIPS_FPIR_S   (_ULCAST_(1) << 16)

Definition at line 613 of file mipsregs.h.

#define MIPS_FPIR_W   (_ULCAST_(1) << 20)

Definition at line 617 of file mipsregs.h.

#define mthi0 (   x)
Value:
do { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
" # mthi $1, $ac0 \n" \
" .word 0x00200011 \n" \
" .set pop \n" \
: \
: "r" (x)); \
} while (0)

Definition at line 1337 of file mipsregs.h.

#define mthi1 (   x)
Value:
do { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
" # mthi $1, $ac1 \n" \
" .word 0x00200811 \n" \
" .set pop \n" \
: \
: "r" (x)); \
} while (0)

Definition at line 1350 of file mipsregs.h.

#define mthi2 (   x)
Value:
do { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
" # mthi $1, $ac2 \n" \
" .word 0x00201011 \n" \
" .set pop \n" \
: \
: "r" (x)); \
} while (0)

Definition at line 1363 of file mipsregs.h.

#define mthi3 (   x)
Value:
do { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
" # mthi $1, $ac3 \n" \
" .word 0x00201811 \n" \
" .set pop \n" \
: \
: "r" (x)); \
} while (0)

Definition at line 1376 of file mipsregs.h.

#define mtlo0 (   x)
Value:
do { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
" # mtlo $1, $ac0 \n" \
" .word 0x00200013 \n" \
" .set pop \n" \
: \
: "r" (x)); \
} while (0)

Definition at line 1389 of file mipsregs.h.

#define mtlo1 (   x)
Value:
do { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
" # mtlo $1, $ac1 \n" \
" .word 0x00200813 \n" \
" .set pop \n" \
: \
: "r" (x)); \
} while (0)

Definition at line 1402 of file mipsregs.h.

#define mtlo2 (   x)
Value:
do { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
" # mtlo $1, $ac2 \n" \
" .word 0x00201013 \n" \
" .set pop \n" \
: \
: "r" (x)); \
} while (0)

Definition at line 1415 of file mipsregs.h.

#define mtlo3 (   x)
Value:
do { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
" # mtlo $1, $ac3 \n" \
" .word 0x00201813 \n" \
" .set pop \n" \
: \
: "r" (x)); \
} while (0)

Definition at line 1428 of file mipsregs.h.

#define PG_ELPA   (_ULCAST_(1) << 29)

Definition at line 265 of file mipsregs.h.

#define PG_ESP   (_ULCAST_(1) << 28)

Definition at line 266 of file mipsregs.h.

#define PG_RIE   (_ULCAST_(1) << 31)

Definition at line 263 of file mipsregs.h.

#define PG_XIE   (_ULCAST_(1) << 30)

Definition at line 264 of file mipsregs.h.

#define PL_16K   14

Definition at line 251 of file mipsregs.h.

#define PL_16M   24

Definition at line 256 of file mipsregs.h.

#define PL_1M   20

Definition at line 254 of file mipsregs.h.

#define PL_256K   18

Definition at line 253 of file mipsregs.h.

#define PL_256M   28

Definition at line 258 of file mipsregs.h.

#define PL_4K   12

Definition at line 250 of file mipsregs.h.

#define PL_4M   22

Definition at line 255 of file mipsregs.h.

#define PL_64K   16

Definition at line 252 of file mipsregs.h.

#define PL_64M   26

Definition at line 257 of file mipsregs.h.

#define PM_128K   0x0003e000

Definition at line 198 of file mipsregs.h.

#define PM_16K   0x00006000

Definition at line 195 of file mipsregs.h.

#define PM_16M   0x01ffe000

Definition at line 205 of file mipsregs.h.

#define PM_1G   0x7fffe000

Definition at line 209 of file mipsregs.h.

#define PM_1M   0x001fe000

Definition at line 201 of file mipsregs.h.

#define PM_256K   0x0007e000

Definition at line 199 of file mipsregs.h.

#define PM_256M   0x1fffe000

Definition at line 208 of file mipsregs.h.

#define PM_2M   0x003fe000

Definition at line 202 of file mipsregs.h.

#define PM_32K   0x0000e000

Definition at line 196 of file mipsregs.h.

#define PM_32M   0x03ffe000

Definition at line 206 of file mipsregs.h.

#define PM_4K   0x00000000

Definition at line 193 of file mipsregs.h.

#define PM_4M   0x007fe000

Definition at line 203 of file mipsregs.h.

#define PM_512K   0x000fe000

Definition at line 200 of file mipsregs.h.

#define PM_64K   0x0001e000

Definition at line 197 of file mipsregs.h.

#define PM_64M   0x07ffe000

Definition at line 207 of file mipsregs.h.

#define PM_8K   0x00002000

Definition at line 194 of file mipsregs.h.

#define PM_8M   0x00ffe000

Definition at line 204 of file mipsregs.h.

#define R10K_CONF_CT   (_ULCAST_(1) << 5)

Definition at line 519 of file mipsregs.h.

#define R10K_CONF_DC   (_ULCAST_(7) << 26)

Definition at line 527 of file mipsregs.h.

#define R10K_CONF_DN   (_ULCAST_(3) << 3)

Definition at line 518 of file mipsregs.h.

#define R10K_CONF_EC   (_ULCAST_(15)<< 9)

Definition at line 522 of file mipsregs.h.

#define R10K_CONF_IC   (_ULCAST_(7) << 29)

Definition at line 528 of file mipsregs.h.

#define R10K_CONF_PE   (_ULCAST_(1) << 6)

Definition at line 520 of file mipsregs.h.

#define R10K_CONF_PM   (_ULCAST_(3) << 7)

Definition at line 521 of file mipsregs.h.

#define R10K_CONF_SB   (_ULCAST_(1) << 13)

Definition at line 523 of file mipsregs.h.

#define R10K_CONF_SC   (_ULCAST_(7) << 19)

Definition at line 526 of file mipsregs.h.

#define R10K_CONF_SK   (_ULCAST_(1) << 14)

Definition at line 524 of file mipsregs.h.

#define R10K_CONF_SS   (_ULCAST_(7) << 16)

Definition at line 525 of file mipsregs.h.

#define R30XX_CONF_AC   (_ULCAST_(1) << 23)

Definition at line 540 of file mipsregs.h.

#define R30XX_CONF_DBR   (_ULCAST_(1) << 29)

Definition at line 544 of file mipsregs.h.

#define R30XX_CONF_FDM   (_ULCAST_(1) << 19)

Definition at line 538 of file mipsregs.h.

#define R30XX_CONF_FPINT   (_ULCAST_(7) << 26)

Definition at line 543 of file mipsregs.h.

#define R30XX_CONF_HALT   (_ULCAST_(1) << 25)

Definition at line 542 of file mipsregs.h.

#define R30XX_CONF_LOCK   (_ULCAST_(1) << 31)

Definition at line 546 of file mipsregs.h.

#define R30XX_CONF_REV   (_ULCAST_(1) << 22)

Definition at line 539 of file mipsregs.h.

#define R30XX_CONF_RF   (_ULCAST_(1) << 24)

Definition at line 541 of file mipsregs.h.

#define R30XX_CONF_SB   (_ULCAST_(1) << 30)

Definition at line 545 of file mipsregs.h.

#define R4K_CONF_SB   (_ULCAST_(3) << 22)

Definition at line 503 of file mipsregs.h.

#define R4K_CONF_SS   (_ULCAST_(1) << 21)

Definition at line 502 of file mipsregs.h.

#define R4K_CONF_SW   (_ULCAST_(1) << 20)

Definition at line 501 of file mipsregs.h.

#define R5K_CONF_SE   (_ULCAST_(1) << 12)

Definition at line 506 of file mipsregs.h.

#define R5K_CONF_SS   (_ULCAST_(3) << 20)

Definition at line 507 of file mipsregs.h.

#define rddsp (   mask)
Value:
({ \
unsigned int __res; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" # rddsp $1, %x1 \n" \
" .word 0x7c000cb8 | (%x1 << 16) \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__res) \
: "i" (mask)); \
__res; \
})

Definition at line 1165 of file mipsregs.h.

#define read_32bit_cp1_register (   source)
Value:
({ int __res; \
__asm__ __volatile__( \
".set\tpush\n\t" \
".set\treorder\n\t" \
/* gas fails to assemble cfc1 for some archs (octeon).*/ \
".set\tmips1\n\t" \
"cfc1\t%0,"STR(source)"\n\t" \
".set\tpop" \
: "=r" (__res)); \
__res;})

Definition at line 1153 of file mipsregs.h.

#define read_c0_badvaddr ( )    __read_ulong_c0_register($8, 0)

Definition at line 866 of file mipsregs.h.

#define read_c0_brcm_action ( )    __read_32bit_c0_register($22, 2)

Definition at line 1138 of file mipsregs.h.

#define read_c0_brcm_bootvec ( )    __read_32bit_c0_register($22, 4)

Definition at line 1144 of file mipsregs.h.

#define read_c0_brcm_bus_pll ( )    __read_32bit_c0_register($22, 4)

Definition at line 1109 of file mipsregs.h.

#define read_c0_brcm_cbr ( )    __read_32bit_c0_register($22, 6)

Definition at line 1128 of file mipsregs.h.

#define read_c0_brcm_cmt_ctrl ( )    __read_32bit_c0_register($22, 2)

Definition at line 1119 of file mipsregs.h.

#define read_c0_brcm_cmt_intr ( )    __read_32bit_c0_register($22, 1)

Definition at line 1116 of file mipsregs.h.

#define read_c0_brcm_cmt_local ( )    __read_32bit_c0_register($22, 3)

Definition at line 1122 of file mipsregs.h.

#define read_c0_brcm_config ( )    __read_32bit_c0_register($22, 0)

Definition at line 1132 of file mipsregs.h.

#define read_c0_brcm_config_0 ( )    __read_32bit_c0_register($22, 0)

Definition at line 1106 of file mipsregs.h.

#define read_c0_brcm_config_1 ( )    __read_32bit_c0_register($22, 5)

Definition at line 1125 of file mipsregs.h.

#define read_c0_brcm_edsp ( )    __read_32bit_c0_register($22, 3)

Definition at line 1141 of file mipsregs.h.

#define read_c0_brcm_mode ( )    __read_32bit_c0_register($22, 1)

Definition at line 1135 of file mipsregs.h.

#define read_c0_brcm_reset ( )    __read_32bit_c0_register($22, 5)

Definition at line 1112 of file mipsregs.h.

#define read_c0_brcm_sleepcount ( )    __read_32bit_c0_register($22, 7)

Definition at line 1147 of file mipsregs.h.

#define read_c0_cache ( )    __read_32bit_c0_register($7, 0) /* TX39xx */

Definition at line 863 of file mipsregs.h.

#define read_c0_cacheerr ( )    __read_32bit_c0_register($27, 0)

Definition at line 1046 of file mipsregs.h.

#define read_c0_cause ( )    __read_32bit_c0_register($13, 0)

Definition at line 905 of file mipsregs.h.

#define read_c0_compare ( )    __read_32bit_c0_register($11, 0)

Definition at line 881 of file mipsregs.h.

#define read_c0_compare2 ( )    __read_32bit_c0_register($11, 6) /* pnx8550 */

Definition at line 884 of file mipsregs.h.

#define read_c0_compare3 ( )    __read_32bit_c0_register($11, 7) /* pnx8550 */

Definition at line 887 of file mipsregs.h.

#define read_c0_conf ( )    __read_32bit_c0_register($3, 0)

Definition at line 843 of file mipsregs.h.

#define read_c0_config ( )    __read_32bit_c0_register($16, 0)

Definition at line 913 of file mipsregs.h.

#define read_c0_config1 ( )    __read_32bit_c0_register($16, 1)

Definition at line 914 of file mipsregs.h.

#define read_c0_config2 ( )    __read_32bit_c0_register($16, 2)

Definition at line 915 of file mipsregs.h.

#define read_c0_config3 ( )    __read_32bit_c0_register($16, 3)

Definition at line 916 of file mipsregs.h.

#define read_c0_config4 ( )    __read_32bit_c0_register($16, 4)

Definition at line 917 of file mipsregs.h.

#define read_c0_config5 ( )    __read_32bit_c0_register($16, 5)

Definition at line 918 of file mipsregs.h.

#define read_c0_config6 ( )    __read_32bit_c0_register($16, 6)

Definition at line 919 of file mipsregs.h.

#define read_c0_config7 ( )    __read_32bit_c0_register($16, 7)

Definition at line 920 of file mipsregs.h.

#define read_c0_context ( )    __read_ulong_c0_register($4, 0)

Definition at line 846 of file mipsregs.h.

#define read_c0_count ( )    __read_32bit_c0_register($9, 0)

Definition at line 869 of file mipsregs.h.

#define read_c0_count2 ( )    __read_32bit_c0_register($9, 6) /* pnx8550 */

Definition at line 872 of file mipsregs.h.

#define read_c0_count3 ( )    __read_32bit_c0_register($9, 7) /* pnx8550 */

Definition at line 875 of file mipsregs.h.

#define read_c0_cvmcount ( )    __read_ulong_c0_register($9, 6)

Definition at line 1087 of file mipsregs.h.

#define read_c0_cvmctl ( )    __read_64bit_c0_register($9, 7)

Definition at line 1090 of file mipsregs.h.

#define read_c0_cvmmemctl ( )    __read_64bit_c0_register($11, 7)

Definition at line 1093 of file mipsregs.h.

#define read_c0_ddatalo ( )    __read_32bit_c0_register($28, 3)

Definition at line 1057 of file mipsregs.h.

#define read_c0_debug ( )    __read_32bit_c0_register($23, 0)

Definition at line 1002 of file mipsregs.h.

#define read_c0_depc ( )    __read_ulong_c0_register($24, 0)

Definition at line 1005 of file mipsregs.h.

#define read_c0_derraddr0 ( )    __read_ulong_c0_register($26, 1)

Definition at line 1043 of file mipsregs.h.

#define read_c0_derraddr1 ( )    __read_ulong_c0_register($27, 1)

Definition at line 1048 of file mipsregs.h.

#define read_c0_diag ( )    __read_32bit_c0_register($22, 0)

Definition at line 984 of file mipsregs.h.

#define read_c0_diag1 ( )    __read_32bit_c0_register($22, 1)

Definition at line 987 of file mipsregs.h.

#define read_c0_diag2 ( )    __read_32bit_c0_register($22, 2)

Definition at line 990 of file mipsregs.h.

#define read_c0_diag3 ( )    __read_32bit_c0_register($22, 3)

Definition at line 993 of file mipsregs.h.

#define read_c0_diag4 ( )    __read_32bit_c0_register($22, 4)

Definition at line 996 of file mipsregs.h.

#define read_c0_diag5 ( )    __read_32bit_c0_register($22, 5)

Definition at line 999 of file mipsregs.h.

#define read_c0_dtaglo ( )    __read_32bit_c0_register($28, 2)

Definition at line 1054 of file mipsregs.h.

#define read_c0_ebase ( )    __read_32bit_c0_register($15, 1)

Definition at line 1082 of file mipsregs.h.

#define read_c0_ecc ( )    __read_32bit_c0_register($26, 0)

Definition at line 1040 of file mipsregs.h.

#define read_c0_entryhi ( )    __read_ulong_c0_register($10, 0)

Definition at line 878 of file mipsregs.h.

#define read_c0_entrylo0 ( )    __read_ulong_c0_register($2, 0)

Definition at line 837 of file mipsregs.h.

#define read_c0_entrylo1 ( )    __read_ulong_c0_register($3, 0)

Definition at line 840 of file mipsregs.h.

#define read_c0_epc ( )    __read_ulong_c0_register($14, 0)

Definition at line 908 of file mipsregs.h.

#define read_c0_errorepc ( )    __read_ulong_c0_register($30, 0)

Definition at line 1066 of file mipsregs.h.

#define read_c0_framemask ( )    __read_32bit_c0_register($21, 0)

Definition at line 977 of file mipsregs.h.

#define read_c0_hwrena ( )    __read_32bit_c0_register($7, 0)

Definition at line 1070 of file mipsregs.h.

#define read_c0_index ( )    __read_32bit_c0_register($0, 0)

Definition at line 831 of file mipsregs.h.

#define read_c0_info ( )    __read_32bit_c0_register($7, 0)

Definition at line 861 of file mipsregs.h.

#define read_c0_intcontrol ( )    __read_32bit_c0_ctrl_register($20)

Definition at line 974 of file mipsregs.h.

#define read_c0_intctl ( )    __read_32bit_c0_register($12, 1)

Definition at line 1073 of file mipsregs.h.

#define read_c0_pagegrain ( )    __read_32bit_c0_register($5, 1)

Definition at line 855 of file mipsregs.h.

#define read_c0_pagemask ( )    __read_32bit_c0_register($5, 0)

Definition at line 852 of file mipsregs.h.

#define read_c0_perfcntr0 ( )    __read_32bit_c0_register($25, 1)

Definition at line 1013 of file mipsregs.h.

#define read_c0_perfcntr0_64 ( )    __read_64bit_c0_register($25, 1)

Definition at line 1015 of file mipsregs.h.

#define read_c0_perfcntr1 ( )    __read_32bit_c0_register($25, 3)

Definition at line 1019 of file mipsregs.h.

#define read_c0_perfcntr1_64 ( )    __read_64bit_c0_register($25, 3)

Definition at line 1021 of file mipsregs.h.

#define read_c0_perfcntr2 ( )    __read_32bit_c0_register($25, 5)

Definition at line 1025 of file mipsregs.h.

#define read_c0_perfcntr2_64 ( )    __read_64bit_c0_register($25, 5)

Definition at line 1027 of file mipsregs.h.

#define read_c0_perfcntr3 ( )    __read_32bit_c0_register($25, 7)

Definition at line 1031 of file mipsregs.h.

#define read_c0_perfcntr3_64 ( )    __read_64bit_c0_register($25, 7)

Definition at line 1033 of file mipsregs.h.

#define read_c0_perfcontrol ( )    __read_32bit_c0_register($22, 0)

Definition at line 981 of file mipsregs.h.

#define read_c0_perfcount ( )    __read_64bit_c0_register($25, 0)

Definition at line 1037 of file mipsregs.h.

#define read_c0_perfctrl0 ( )    __read_32bit_c0_register($25, 0)

Definition at line 1011 of file mipsregs.h.

#define read_c0_perfctrl1 ( )    __read_32bit_c0_register($25, 2)

Definition at line 1017 of file mipsregs.h.

#define read_c0_perfctrl2 ( )    __read_32bit_c0_register($25, 4)

Definition at line 1023 of file mipsregs.h.

#define read_c0_perfctrl3 ( )    __read_32bit_c0_register($25, 6)

Definition at line 1029 of file mipsregs.h.

#define read_c0_prid ( )    __read_32bit_c0_register($15, 0)

Definition at line 911 of file mipsregs.h.

#define read_c0_random ( )    __read_32bit_c0_register($1, 0)

Definition at line 834 of file mipsregs.h.

#define read_c0_srsctl ( )    __read_32bit_c0_register($12, 2)

Definition at line 1076 of file mipsregs.h.

#define read_c0_srsmap ( )    __read_32bit_c0_register($12, 3)

Definition at line 1079 of file mipsregs.h.

#define read_c0_staglo ( )    __read_32bit_c0_register($28, 4)

Definition at line 1060 of file mipsregs.h.

#define read_c0_status ( )    __read_32bit_c0_register($12, 0)

Definition at line 890 of file mipsregs.h.

#define read_c0_taghi ( )    __read_32bit_c0_register($29, 0)

Definition at line 1063 of file mipsregs.h.

#define read_c0_taglo ( )    __read_32bit_c0_register($28, 0)

Definition at line 1051 of file mipsregs.h.

#define read_c0_userlocal ( )    __read_ulong_c0_register($4, 2)

Definition at line 849 of file mipsregs.h.

#define read_c0_watchhi0 ( )    __read_32bit_c0_register($19, 0)

Definition at line 953 of file mipsregs.h.

#define read_c0_watchhi1 ( )    __read_32bit_c0_register($19, 1)

Definition at line 954 of file mipsregs.h.

#define read_c0_watchhi2 ( )    __read_32bit_c0_register($19, 2)

Definition at line 955 of file mipsregs.h.

#define read_c0_watchhi3 ( )    __read_32bit_c0_register($19, 3)

Definition at line 956 of file mipsregs.h.

#define read_c0_watchhi4 ( )    __read_32bit_c0_register($19, 4)

Definition at line 957 of file mipsregs.h.

#define read_c0_watchhi5 ( )    __read_32bit_c0_register($19, 5)

Definition at line 958 of file mipsregs.h.

#define read_c0_watchhi6 ( )    __read_32bit_c0_register($19, 6)

Definition at line 959 of file mipsregs.h.

#define read_c0_watchhi7 ( )    __read_32bit_c0_register($19, 7)

Definition at line 960 of file mipsregs.h.

#define read_c0_watchlo0 ( )    __read_ulong_c0_register($18, 0)

Definition at line 933 of file mipsregs.h.

#define read_c0_watchlo1 ( )    __read_ulong_c0_register($18, 1)

Definition at line 934 of file mipsregs.h.

#define read_c0_watchlo2 ( )    __read_ulong_c0_register($18, 2)

Definition at line 935 of file mipsregs.h.

#define read_c0_watchlo3 ( )    __read_ulong_c0_register($18, 3)

Definition at line 936 of file mipsregs.h.

#define read_c0_watchlo4 ( )    __read_ulong_c0_register($18, 4)

Definition at line 937 of file mipsregs.h.

#define read_c0_watchlo5 ( )    __read_ulong_c0_register($18, 5)

Definition at line 938 of file mipsregs.h.

#define read_c0_watchlo6 ( )    __read_ulong_c0_register($18, 6)

Definition at line 939 of file mipsregs.h.

#define read_c0_watchlo7 ( )    __read_ulong_c0_register($18, 7)

Definition at line 940 of file mipsregs.h.

#define read_c0_wired ( )    __read_32bit_c0_register($6, 0)

Definition at line 858 of file mipsregs.h.

#define read_c0_xcontext ( )    __read_ulong_c0_register($20, 0)

Definition at line 971 of file mipsregs.h.

#define read_octeon_c0_dcacheerr ( )    __read_64bit_c0_register($27, 1)

Definition at line 1102 of file mipsregs.h.

#define read_octeon_c0_icacheerr ( )    __read_64bit_c0_register($27, 0)

Definition at line 1099 of file mipsregs.h.

#define read_r10k_perf_cntr (   counter)
Value:
({ \
unsigned int __res; \
__asm__ __volatile__( \
"mfpc\t%0, %1" \
: "=r" (__res) \
: "i" (counter)); \
\
__res; \
})

Definition at line 630 of file mipsregs.h.

#define read_r10k_perf_event (   counter)
Value:
({ \
unsigned int __res; \
__asm__ __volatile__( \
"mfps\t%0, %1" \
: "=r" (__res) \
: "i" (counter)); \
\
__res; \
})

Definition at line 649 of file mipsregs.h.

#define RM7K_CONF_CLK   (_ULCAST_(1) << 16)

Definition at line 512 of file mipsregs.h.

#define RM7K_CONF_SC   (_ULCAST_(1) << 31)

Definition at line 515 of file mipsregs.h.

#define RM7K_CONF_SE   (_ULCAST_(1) << 3)

Definition at line 510 of file mipsregs.h.

#define RM7K_CONF_SI   (_ULCAST_(3) << 20)

Definition at line 514 of file mipsregs.h.

#define RM7K_CONF_TC   (_ULCAST_(1) << 17)

Definition at line 513 of file mipsregs.h.

#define RM7K_CONF_TE   (_ULCAST_(1) << 12)

Definition at line 511 of file mipsregs.h.

#define ST0_BEV   0x00400000

Definition at line 414 of file mipsregs.h.

#define ST0_CE   0x00020000

Definition at line 306 of file mipsregs.h.

#define ST0_CH   0x00040000

Definition at line 410 of file mipsregs.h.

#define ST0_CM   0x00080000

Definition at line 327 of file mipsregs.h.

#define ST0_CO   0x08000000

Definition at line 313 of file mipsregs.h.

#define ST0_CU   0xf0000000

Definition at line 417 of file mipsregs.h.

#define ST0_CU0   0x10000000

Definition at line 418 of file mipsregs.h.

#define ST0_CU1   0x20000000

Definition at line 419 of file mipsregs.h.

#define ST0_CU2   0x40000000

Definition at line 420 of file mipsregs.h.

#define ST0_CU3   0x80000000

Definition at line 421 of file mipsregs.h.

#define ST0_DE   0x00010000

Definition at line 305 of file mipsregs.h.

#define ST0_DL   (_ULCAST_(1) << 24)

Definition at line 334 of file mipsregs.h.

#define ST0_ERL   0x00000004

Definition at line 297 of file mipsregs.h.

#define ST0_EXL   0x00000002

Definition at line 296 of file mipsregs.h.

#define ST0_FR   0x04000000

Definition at line 416 of file mipsregs.h.

#define ST0_IE   0x00000001

Definition at line 295 of file mipsregs.h.

#define ST0_IEC   0x00000001

Definition at line 318 of file mipsregs.h.

#define ST0_IEO   0x00000010

Definition at line 322 of file mipsregs.h.

#define ST0_IEP   0x00000004

Definition at line 320 of file mipsregs.h.

#define ST0_IL   (_ULCAST_(1) << 23)

Definition at line 333 of file mipsregs.h.

#define ST0_IM   0x0000ff00

Definition at line 377 of file mipsregs.h.

#define ST0_ISC   0x00010000

Definition at line 325 of file mipsregs.h.

#define ST0_KSU   0x00000018

Definition at line 298 of file mipsregs.h.

#define ST0_KUC   0x00000002

Definition at line 319 of file mipsregs.h.

#define ST0_KUO   0x00000020

Definition at line 323 of file mipsregs.h.

#define ST0_KUP   0x00000008

Definition at line 321 of file mipsregs.h.

#define ST0_KX   0x00000080

Definition at line 304 of file mipsregs.h.

#define ST0_MX   0x01000000

Definition at line 339 of file mipsregs.h.

#define ST0_NMI   0x00080000

Definition at line 411 of file mipsregs.h.

#define ST0_RE   0x02000000

Definition at line 415 of file mipsregs.h.

#define ST0_SR   0x00100000

Definition at line 412 of file mipsregs.h.

#define ST0_SWC   0x00020000

Definition at line 326 of file mipsregs.h.

#define ST0_SX   0x00000040

Definition at line 303 of file mipsregs.h.

#define ST0_TS   0x00200000

Definition at line 413 of file mipsregs.h.

#define ST0_UM   (_ULCAST_(1) << 4)

Definition at line 332 of file mipsregs.h.

#define ST0_UX   0x00000020

Definition at line 302 of file mipsregs.h.

#define ST0_XX   0x80000000 /* MIPS IV naming */

Definition at line 422 of file mipsregs.h.

#define STATUSB_IP0   8

Definition at line 378 of file mipsregs.h.

#define STATUSB_IP1   9

Definition at line 380 of file mipsregs.h.

#define STATUSB_IP10   2

Definition at line 398 of file mipsregs.h.

#define STATUSB_IP11   3

Definition at line 400 of file mipsregs.h.

#define STATUSB_IP12   4

Definition at line 402 of file mipsregs.h.

#define STATUSB_IP13   5

Definition at line 404 of file mipsregs.h.

#define STATUSB_IP14   6

Definition at line 406 of file mipsregs.h.

#define STATUSB_IP15   7

Definition at line 408 of file mipsregs.h.

#define STATUSB_IP2   10

Definition at line 382 of file mipsregs.h.

#define STATUSB_IP3   11

Definition at line 384 of file mipsregs.h.

#define STATUSB_IP4   12

Definition at line 386 of file mipsregs.h.

#define STATUSB_IP5   13

Definition at line 388 of file mipsregs.h.

#define STATUSB_IP6   14

Definition at line 390 of file mipsregs.h.

#define STATUSB_IP7   15

Definition at line 392 of file mipsregs.h.

#define STATUSB_IP8   0

Definition at line 394 of file mipsregs.h.

#define STATUSB_IP9   1

Definition at line 396 of file mipsregs.h.

#define STATUSF_IP0   (_ULCAST_(1) << 8)

Definition at line 379 of file mipsregs.h.

#define STATUSF_IP1   (_ULCAST_(1) << 9)

Definition at line 381 of file mipsregs.h.

#define STATUSF_IP10   (_ULCAST_(1) << 2)

Definition at line 399 of file mipsregs.h.

#define STATUSF_IP11   (_ULCAST_(1) << 3)

Definition at line 401 of file mipsregs.h.

#define STATUSF_IP12   (_ULCAST_(1) << 4)

Definition at line 403 of file mipsregs.h.

#define STATUSF_IP13   (_ULCAST_(1) << 5)

Definition at line 405 of file mipsregs.h.

#define STATUSF_IP14   (_ULCAST_(1) << 6)

Definition at line 407 of file mipsregs.h.

#define STATUSF_IP15   (_ULCAST_(1) << 7)

Definition at line 409 of file mipsregs.h.

#define STATUSF_IP2   (_ULCAST_(1) << 10)

Definition at line 383 of file mipsregs.h.

#define STATUSF_IP3   (_ULCAST_(1) << 11)

Definition at line 385 of file mipsregs.h.

#define STATUSF_IP4   (_ULCAST_(1) << 12)

Definition at line 387 of file mipsregs.h.

#define STATUSF_IP5   (_ULCAST_(1) << 13)

Definition at line 389 of file mipsregs.h.

#define STATUSF_IP6   (_ULCAST_(1) << 14)

Definition at line 391 of file mipsregs.h.

#define STATUSF_IP7   (_ULCAST_(1) << 15)

Definition at line 393 of file mipsregs.h.

#define STATUSF_IP8   (_ULCAST_(1) << 0)

Definition at line 395 of file mipsregs.h.

#define STATUSF_IP9   (_ULCAST_(1) << 1)

Definition at line 397 of file mipsregs.h.

#define STR (   x)    __STR(x)

Definition at line 28 of file mipsregs.h.

#define TX39_CONF_CWFON   0x00004000

Definition at line 360 of file mipsregs.h.

#define TX39_CONF_DCE   0x00000010

Definition at line 368 of file mipsregs.h.

#define TX39_CONF_DCS_16KB   0x00040000

Definition at line 358 of file mipsregs.h.

#define TX39_CONF_DCS_1KB   0x00000000

Definition at line 354 of file mipsregs.h.

#define TX39_CONF_DCS_2KB   0x00010000

Definition at line 355 of file mipsregs.h.

#define TX39_CONF_DCS_4KB   0x00020000

Definition at line 356 of file mipsregs.h.

#define TX39_CONF_DCS_8KB   0x00030000

Definition at line 357 of file mipsregs.h.

#define TX39_CONF_DCS_MASK   0x00070000

Definition at line 353 of file mipsregs.h.

#define TX39_CONF_DCS_SHIFT   16

Definition at line 352 of file mipsregs.h.

#define TX39_CONF_DOZE   0x00000200

Definition at line 364 of file mipsregs.h.

#define TX39_CONF_DRSIZE_MASK   0x00000003

Definition at line 372 of file mipsregs.h.

#define TX39_CONF_DRSIZE_SHIFT   0

Definition at line 371 of file mipsregs.h.

#define TX39_CONF_HALT   0x00000100

Definition at line 365 of file mipsregs.h.

#define TX39_CONF_ICE   0x00000020

Definition at line 367 of file mipsregs.h.

#define TX39_CONF_ICS_16KB   0x00200000

Definition at line 350 of file mipsregs.h.

#define TX39_CONF_ICS_1KB   0x00000000

Definition at line 346 of file mipsregs.h.

#define TX39_CONF_ICS_2KB   0x00080000

Definition at line 347 of file mipsregs.h.

#define TX39_CONF_ICS_4KB   0x00100000

Definition at line 348 of file mipsregs.h.

#define TX39_CONF_ICS_8KB   0x00180000

Definition at line 349 of file mipsregs.h.

#define TX39_CONF_ICS_MASK   0x00380000

Definition at line 345 of file mipsregs.h.

#define TX39_CONF_ICS_SHIFT   19

Definition at line 344 of file mipsregs.h.

#define TX39_CONF_IRSIZE_MASK   0x0000000c

Definition at line 370 of file mipsregs.h.

#define TX39_CONF_IRSIZE_SHIFT   2

Definition at line 369 of file mipsregs.h.

#define TX39_CONF_LOCK   0x00000080

Definition at line 366 of file mipsregs.h.

#define TX39_CONF_RF_MASK   0x00000c00

Definition at line 363 of file mipsregs.h.

#define TX39_CONF_RF_SHIFT   10

Definition at line 362 of file mipsregs.h.

#define TX39_CONF_WBON   0x00002000

Definition at line 361 of file mipsregs.h.

#define TX49_CONF_CWFON   (_ULCAST_(1) << 27)

Definition at line 552 of file mipsregs.h.

#define TX49_CONF_DC   (_ULCAST_(1) << 16)

Definition at line 549 of file mipsregs.h.

#define TX49_CONF_HALT   (_ULCAST_(1) << 18)

Definition at line 551 of file mipsregs.h.

#define TX49_CONF_IC   (_ULCAST_(1) << 17) /* conflict with CONF_SC */

Definition at line 550 of file mipsregs.h.

#define VR41_CONF_AD   (_ULCAST_(1) << 23)

Definition at line 535 of file mipsregs.h.

#define VR41_CONF_BP   (_ULCAST_(1) << 16)

Definition at line 533 of file mipsregs.h.

#define VR41_CONF_CS   (_ULCAST_(1) << 12)

Definition at line 531 of file mipsregs.h.

#define VR41_CONF_M16   (_ULCAST_(1) << 20)

Definition at line 534 of file mipsregs.h.

#define VR41_CONF_P4K   (_ULCAST_(1) << 13)

Definition at line 532 of file mipsregs.h.

#define wrdsp (   val,
  mask 
)
Value:
do { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
" # wrdsp $1, %x1 \n" \
" .word 0x7c2004f8 | (%x1 << 11) \n" \
" .set pop \n" \
: \
: "r" (val), "i" (mask)); \
} while (0)

Definition at line 1181 of file mipsregs.h.

#define write_c0_badvaddr (   val)    __write_ulong_c0_register($8, 0, val)

Definition at line 867 of file mipsregs.h.

#define write_c0_brcm_action (   val)    __write_32bit_c0_register($22, 2, val)

Definition at line 1139 of file mipsregs.h.

#define write_c0_brcm_bootvec (   val)    __write_32bit_c0_register($22, 4, val)

Definition at line 1145 of file mipsregs.h.

#define write_c0_brcm_bus_pll (   val)    __write_32bit_c0_register($22, 4, val)

Definition at line 1110 of file mipsregs.h.

#define write_c0_brcm_cbr (   val)    __write_32bit_c0_register($22, 6, val)

Definition at line 1129 of file mipsregs.h.

#define write_c0_brcm_cmt_ctrl (   val)    __write_32bit_c0_register($22, 2, val)

Definition at line 1120 of file mipsregs.h.

#define write_c0_brcm_cmt_intr (   val)    __write_32bit_c0_register($22, 1, val)

Definition at line 1117 of file mipsregs.h.

#define write_c0_brcm_cmt_local (   val)    __write_32bit_c0_register($22, 3, val)

Definition at line 1123 of file mipsregs.h.

#define write_c0_brcm_config (   val)    __write_32bit_c0_register($22, 0, val)

Definition at line 1133 of file mipsregs.h.

#define write_c0_brcm_config_0 (   val)    __write_32bit_c0_register($22, 0, val)

Definition at line 1107 of file mipsregs.h.

#define write_c0_brcm_config_1 (   val)    __write_32bit_c0_register($22, 5, val)

Definition at line 1126 of file mipsregs.h.

#define write_c0_brcm_edsp (   val)    __write_32bit_c0_register($22, 3, val)

Definition at line 1142 of file mipsregs.h.

#define write_c0_brcm_mode (   val)    __write_32bit_c0_register($22, 1, val)

Definition at line 1136 of file mipsregs.h.

#define write_c0_brcm_reset (   val)    __write_32bit_c0_register($22, 5, val)

Definition at line 1113 of file mipsregs.h.

#define write_c0_brcm_sleepcount (   val)    __write_32bit_c0_register($22, 7, val)

Definition at line 1148 of file mipsregs.h.

#define write_c0_cache (   val)    __write_32bit_c0_register($7, 0, val)

Definition at line 864 of file mipsregs.h.

#define write_c0_cause (   val)    __write_32bit_c0_register($13, 0, val)

Definition at line 906 of file mipsregs.h.

#define write_c0_compare (   val)    __write_32bit_c0_register($11, 0, val)

Definition at line 882 of file mipsregs.h.

#define write_c0_compare2 (   val)    __write_32bit_c0_register($11, 6, val)

Definition at line 885 of file mipsregs.h.

#define write_c0_compare3 (   val)    __write_32bit_c0_register($11, 7, val)

Definition at line 888 of file mipsregs.h.

#define write_c0_conf (   val)    __write_32bit_c0_register($3, 0, val)

Definition at line 844 of file mipsregs.h.

#define write_c0_config (   val)    __write_32bit_c0_register($16, 0, val)

Definition at line 921 of file mipsregs.h.

#define write_c0_config1 (   val)    __write_32bit_c0_register($16, 1, val)

Definition at line 922 of file mipsregs.h.

#define write_c0_config2 (   val)    __write_32bit_c0_register($16, 2, val)

Definition at line 923 of file mipsregs.h.

#define write_c0_config3 (   val)    __write_32bit_c0_register($16, 3, val)

Definition at line 924 of file mipsregs.h.

#define write_c0_config4 (   val)    __write_32bit_c0_register($16, 4, val)

Definition at line 925 of file mipsregs.h.

#define write_c0_config5 (   val)    __write_32bit_c0_register($16, 5, val)

Definition at line 926 of file mipsregs.h.

#define write_c0_config6 (   val)    __write_32bit_c0_register($16, 6, val)

Definition at line 927 of file mipsregs.h.

#define write_c0_config7 (   val)    __write_32bit_c0_register($16, 7, val)

Definition at line 928 of file mipsregs.h.

#define write_c0_context (   val)    __write_ulong_c0_register($4, 0, val)

Definition at line 847 of file mipsregs.h.

#define write_c0_count (   val)    __write_32bit_c0_register($9, 0, val)

Definition at line 870 of file mipsregs.h.

#define write_c0_count2 (   val)    __write_32bit_c0_register($9, 6, val)

Definition at line 873 of file mipsregs.h.

#define write_c0_count3 (   val)    __write_32bit_c0_register($9, 7, val)

Definition at line 876 of file mipsregs.h.

#define write_c0_cvmcount (   val)    __write_ulong_c0_register($9, 6, val)

Definition at line 1088 of file mipsregs.h.

#define write_c0_cvmctl (   val)    __write_64bit_c0_register($9, 7, val)

Definition at line 1091 of file mipsregs.h.

#define write_c0_cvmmemctl (   val)    __write_64bit_c0_register($11, 7, val)

Definition at line 1094 of file mipsregs.h.

#define write_c0_ddatalo (   val)    __write_32bit_c0_register($28, 3, val)

Definition at line 1058 of file mipsregs.h.

#define write_c0_debug (   val)    __write_32bit_c0_register($23, 0, val)

Definition at line 1003 of file mipsregs.h.

#define write_c0_depc (   val)    __write_ulong_c0_register($24, 0, val)

Definition at line 1006 of file mipsregs.h.

#define write_c0_derraddr0 (   val)    __write_ulong_c0_register($26, 1, val)

Definition at line 1044 of file mipsregs.h.

#define write_c0_derraddr1 (   val)    __write_ulong_c0_register($27, 1, val)

Definition at line 1049 of file mipsregs.h.

#define write_c0_diag (   val)    __write_32bit_c0_register($22, 0, val)

Definition at line 985 of file mipsregs.h.

#define write_c0_diag1 (   val)    __write_32bit_c0_register($22, 1, val)

Definition at line 988 of file mipsregs.h.

#define write_c0_diag2 (   val)    __write_32bit_c0_register($22, 2, val)

Definition at line 991 of file mipsregs.h.

#define write_c0_diag3 (   val)    __write_32bit_c0_register($22, 3, val)

Definition at line 994 of file mipsregs.h.

#define write_c0_diag4 (   val)    __write_32bit_c0_register($22, 4, val)

Definition at line 997 of file mipsregs.h.

#define write_c0_diag5 (   val)    __write_32bit_c0_register($22, 5, val)

Definition at line 1000 of file mipsregs.h.

#define write_c0_dtaglo (   val)    __write_32bit_c0_register($28, 2, val)

Definition at line 1055 of file mipsregs.h.

#define write_c0_ebase (   val)    __write_32bit_c0_register($15, 1, val)

Definition at line 1083 of file mipsregs.h.

#define write_c0_ecc (   val)    __write_32bit_c0_register($26, 0, val)

Definition at line 1041 of file mipsregs.h.

#define write_c0_entryhi (   val)    __write_ulong_c0_register($10, 0, val)

Definition at line 879 of file mipsregs.h.

#define write_c0_entrylo0 (   val)    __write_ulong_c0_register($2, 0, val)

Definition at line 838 of file mipsregs.h.

#define write_c0_entrylo1 (   val)    __write_ulong_c0_register($3, 0, val)

Definition at line 841 of file mipsregs.h.

#define write_c0_epc (   val)    __write_ulong_c0_register($14, 0, val)

Definition at line 909 of file mipsregs.h.

#define write_c0_errorepc (   val)    __write_ulong_c0_register($30, 0, val)

Definition at line 1067 of file mipsregs.h.

#define write_c0_framemask (   val)    __write_32bit_c0_register($21, 0, val)

Definition at line 978 of file mipsregs.h.

#define write_c0_hwrena (   val)    __write_32bit_c0_register($7, 0, val)

Definition at line 1071 of file mipsregs.h.

#define write_c0_index (   val)    __write_32bit_c0_register($0, 0, val)

Definition at line 832 of file mipsregs.h.

#define write_c0_intcontrol (   val)    __write_32bit_c0_ctrl_register($20, val)

Definition at line 975 of file mipsregs.h.

#define write_c0_intctl (   val)    __write_32bit_c0_register($12, 1, val)

Definition at line 1074 of file mipsregs.h.

#define write_c0_pagegrain (   val)    __write_32bit_c0_register($5, 1, val)

Definition at line 856 of file mipsregs.h.

#define write_c0_pagemask (   val)    __write_32bit_c0_register($5, 0, val)

Definition at line 853 of file mipsregs.h.

#define write_c0_perfcntr0 (   val)    __write_32bit_c0_register($25, 1, val)

Definition at line 1014 of file mipsregs.h.

#define write_c0_perfcntr0_64 (   val)    __write_64bit_c0_register($25, 1, val)

Definition at line 1016 of file mipsregs.h.

#define write_c0_perfcntr1 (   val)    __write_32bit_c0_register($25, 3, val)

Definition at line 1020 of file mipsregs.h.

#define write_c0_perfcntr1_64 (   val)    __write_64bit_c0_register($25, 3, val)

Definition at line 1022 of file mipsregs.h.

#define write_c0_perfcntr2 (   val)    __write_32bit_c0_register($25, 5, val)

Definition at line 1026 of file mipsregs.h.

#define write_c0_perfcntr2_64 (   val)    __write_64bit_c0_register($25, 5, val)

Definition at line 1028 of file mipsregs.h.

#define write_c0_perfcntr3 (   val)    __write_32bit_c0_register($25, 7, val)

Definition at line 1032 of file mipsregs.h.

#define write_c0_perfcntr3_64 (   val)    __write_64bit_c0_register($25, 7, val)

Definition at line 1034 of file mipsregs.h.

#define write_c0_perfcontrol (   val)    __write_32bit_c0_register($22, 0, val)

Definition at line 982 of file mipsregs.h.

#define write_c0_perfcount (   val)    __write_64bit_c0_register($25, 0, val)

Definition at line 1038 of file mipsregs.h.

#define write_c0_perfctrl0 (   val)    __write_32bit_c0_register($25, 0, val)

Definition at line 1012 of file mipsregs.h.

#define write_c0_perfctrl1 (   val)    __write_32bit_c0_register($25, 2, val)

Definition at line 1018 of file mipsregs.h.

#define write_c0_perfctrl2 (   val)    __write_32bit_c0_register($25, 4, val)

Definition at line 1024 of file mipsregs.h.

#define write_c0_perfctrl3 (   val)    __write_32bit_c0_register($25, 6, val)

Definition at line 1030 of file mipsregs.h.

#define write_c0_random (   val)    __write_32bit_c0_register($1, 0, val)

Definition at line 835 of file mipsregs.h.

#define write_c0_srsctl (   val)    __write_32bit_c0_register($12, 2, val)

Definition at line 1077 of file mipsregs.h.

#define write_c0_srsmap (   val)    __write_32bit_c0_register($12, 3, val)

Definition at line 1080 of file mipsregs.h.

#define write_c0_staglo (   val)    __write_32bit_c0_register($28, 4, val)

Definition at line 1061 of file mipsregs.h.

#define write_c0_status (   val)    __write_32bit_c0_register($12, 0, val)

Definition at line 902 of file mipsregs.h.

#define write_c0_taghi (   val)    __write_32bit_c0_register($29, 0, val)

Definition at line 1064 of file mipsregs.h.

#define write_c0_taglo (   val)    __write_32bit_c0_register($28, 0, val)

Definition at line 1052 of file mipsregs.h.

#define write_c0_userlocal (   val)    __write_ulong_c0_register($4, 2, val)

Definition at line 850 of file mipsregs.h.

#define write_c0_watchhi0 (   val)    __write_32bit_c0_register($19, 0, val)

Definition at line 962 of file mipsregs.h.

#define write_c0_watchhi1 (   val)    __write_32bit_c0_register($19, 1, val)

Definition at line 963 of file mipsregs.h.

#define write_c0_watchhi2 (   val)    __write_32bit_c0_register($19, 2, val)

Definition at line 964 of file mipsregs.h.

#define write_c0_watchhi3 (   val)    __write_32bit_c0_register($19, 3, val)

Definition at line 965 of file mipsregs.h.

#define write_c0_watchhi4 (   val)    __write_32bit_c0_register($19, 4, val)

Definition at line 966 of file mipsregs.h.

#define write_c0_watchhi5 (   val)    __write_32bit_c0_register($19, 5, val)

Definition at line 967 of file mipsregs.h.

#define write_c0_watchhi6 (   val)    __write_32bit_c0_register($19, 6, val)

Definition at line 968 of file mipsregs.h.

#define write_c0_watchhi7 (   val)    __write_32bit_c0_register($19, 7, val)

Definition at line 969 of file mipsregs.h.

#define write_c0_watchlo0 (   val)    __write_ulong_c0_register($18, 0, val)

Definition at line 941 of file mipsregs.h.

#define write_c0_watchlo1 (   val)    __write_ulong_c0_register($18, 1, val)

Definition at line 942 of file mipsregs.h.

#define write_c0_watchlo2 (   val)    __write_ulong_c0_register($18, 2, val)

Definition at line 943 of file mipsregs.h.

#define write_c0_watchlo3 (   val)    __write_ulong_c0_register($18, 3, val)

Definition at line 944 of file mipsregs.h.

#define write_c0_watchlo4 (   val)    __write_ulong_c0_register($18, 4, val)

Definition at line 945 of file mipsregs.h.

#define write_c0_watchlo5 (   val)    __write_ulong_c0_register($18, 5, val)

Definition at line 946 of file mipsregs.h.

#define write_c0_watchlo6 (   val)    __write_ulong_c0_register($18, 6, val)

Definition at line 947 of file mipsregs.h.

#define write_c0_watchlo7 (   val)    __write_ulong_c0_register($18, 7, val)

Definition at line 948 of file mipsregs.h.

#define write_c0_wired (   val)    __write_32bit_c0_register($6, 0, val)

Definition at line 859 of file mipsregs.h.

#define write_c0_xcontext (   val)    __write_ulong_c0_register($20, 0, val)

Definition at line 972 of file mipsregs.h.

#define write_octeon_c0_dcacheerr (   val)    __write_64bit_c0_register($27, 1, val)

Definition at line 1103 of file mipsregs.h.

#define write_octeon_c0_icacheerr (   val)    __write_64bit_c0_register($27, 0, val)

Definition at line 1100 of file mipsregs.h.

#define write_r10k_perf_cntl (   counter,
  val 
)
Value:
do { \
__asm__ __volatile__( \
"mtps\t%0, %1" \
: \
: "r" (val), "i" (counter)); \
} while (0)

Definition at line 660 of file mipsregs.h.

#define write_r10k_perf_cntr (   counter,
  val 
)
Value:
do { \
__asm__ __volatile__( \
"mtpc\t%0, %1" \
: \
: "r" (val), "i" (counter)); \
} while (0)

Definition at line 641 of file mipsregs.h.

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