|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
Go to the source code of this file.
Macros | |
| #define | MSR_EFER 0xc0000080 /* extended feature register */ |
| #define | MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ |
| #define | MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ |
| #define | MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ |
| #define | MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ |
| #define | MSR_FS_BASE 0xc0000100 /* 64bit FS base */ |
| #define | MSR_GS_BASE 0xc0000101 /* 64bit GS base */ |
| #define | MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ |
| #define | MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ |
| #define | _EFER_SCE 0 /* SYSCALL/SYSRET */ |
| #define | _EFER_LME 8 /* Long mode enable */ |
| #define | _EFER_LMA 10 /* Long mode active (read-only) */ |
| #define | _EFER_NX 11 /* No execute enable */ |
| #define | _EFER_SVME 12 /* Enable virtualization */ |
| #define | _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ |
| #define | _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ |
| #define | EFER_SCE (1<<_EFER_SCE) |
| #define | EFER_LME (1<<_EFER_LME) |
| #define | EFER_LMA (1<<_EFER_LMA) |
| #define | EFER_NX (1<<_EFER_NX) |
| #define | EFER_SVME (1<<_EFER_SVME) |
| #define | EFER_LMSLE (1<<_EFER_LMSLE) |
| #define | EFER_FFXSR (1<<_EFER_FFXSR) |
| #define | MSR_IA32_PERFCTR0 0x000000c1 |
| #define | MSR_IA32_PERFCTR1 0x000000c2 |
| #define | MSR_FSB_FREQ 0x000000cd |
| #define | MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 |
| #define | NHM_C3_AUTO_DEMOTE (1UL << 25) |
| #define | NHM_C1_AUTO_DEMOTE (1UL << 26) |
| #define | ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) |
| #define | MSR_MTRRcap 0x000000fe |
| #define | MSR_IA32_BBL_CR_CTL 0x00000119 |
| #define | MSR_IA32_BBL_CR_CTL3 0x0000011e |
| #define | MSR_IA32_SYSENTER_CS 0x00000174 |
| #define | MSR_IA32_SYSENTER_ESP 0x00000175 |
| #define | MSR_IA32_SYSENTER_EIP 0x00000176 |
| #define | MSR_IA32_MCG_CAP 0x00000179 |
| #define | MSR_IA32_MCG_STATUS 0x0000017a |
| #define | MSR_IA32_MCG_CTL 0x0000017b |
| #define | MSR_OFFCORE_RSP_0 0x000001a6 |
| #define | MSR_OFFCORE_RSP_1 0x000001a7 |
| #define | MSR_LBR_SELECT 0x000001c8 |
| #define | MSR_LBR_TOS 0x000001c9 |
| #define | MSR_LBR_NHM_FROM 0x00000680 |
| #define | MSR_LBR_NHM_TO 0x000006c0 |
| #define | MSR_LBR_CORE_FROM 0x00000040 |
| #define | MSR_LBR_CORE_TO 0x00000060 |
| #define | MSR_IA32_PEBS_ENABLE 0x000003f1 |
| #define | MSR_IA32_DS_AREA 0x00000600 |
| #define | MSR_IA32_PERF_CAPABILITIES 0x00000345 |
| #define | MSR_MTRRfix64K_00000 0x00000250 |
| #define | MSR_MTRRfix16K_80000 0x00000258 |
| #define | MSR_MTRRfix16K_A0000 0x00000259 |
| #define | MSR_MTRRfix4K_C0000 0x00000268 |
| #define | MSR_MTRRfix4K_C8000 0x00000269 |
| #define | MSR_MTRRfix4K_D0000 0x0000026a |
| #define | MSR_MTRRfix4K_D8000 0x0000026b |
| #define | MSR_MTRRfix4K_E0000 0x0000026c |
| #define | MSR_MTRRfix4K_E8000 0x0000026d |
| #define | MSR_MTRRfix4K_F0000 0x0000026e |
| #define | MSR_MTRRfix4K_F8000 0x0000026f |
| #define | MSR_MTRRdefType 0x000002ff |
| #define | MSR_IA32_CR_PAT 0x00000277 |
| #define | MSR_IA32_DEBUGCTLMSR 0x000001d9 |
| #define | MSR_IA32_LASTBRANCHFROMIP 0x000001db |
| #define | MSR_IA32_LASTBRANCHTOIP 0x000001dc |
| #define | MSR_IA32_LASTINTFROMIP 0x000001dd |
| #define | MSR_IA32_LASTINTTOIP 0x000001de |
| #define | DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ |
| #define | DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ |
| #define | DEBUGCTLMSR_TR (1UL << 6) |
| #define | DEBUGCTLMSR_BTS (1UL << 7) |
| #define | DEBUGCTLMSR_BTINT (1UL << 8) |
| #define | DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) |
| #define | DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) |
| #define | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) |
| #define | MSR_IA32_MC0_CTL 0x00000400 |
| #define | MSR_IA32_MC0_STATUS 0x00000401 |
| #define | MSR_IA32_MC0_ADDR 0x00000402 |
| #define | MSR_IA32_MC0_MISC 0x00000403 |
| #define | MSR_AMD64_MC0_MASK 0xc0010044 |
| #define | MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |
| #define | MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) |
| #define | MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) |
| #define | MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) |
| #define | MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) |
| #define | MSR_IA32_MC0_CTL2 0x00000280 |
| #define | MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) |
| #define | MSR_P6_PERFCTR0 0x000000c1 |
| #define | MSR_P6_PERFCTR1 0x000000c2 |
| #define | MSR_P6_EVNTSEL0 0x00000186 |
| #define | MSR_P6_EVNTSEL1 0x00000187 |
| #define | MSR_KNC_PERFCTR0 0x00000020 |
| #define | MSR_KNC_PERFCTR1 0x00000021 |
| #define | MSR_KNC_EVNTSEL0 0x00000028 |
| #define | MSR_KNC_EVNTSEL1 0x00000029 |
| #define | MSR_AMD64_PATCH_LEVEL 0x0000008b |
| #define | MSR_AMD64_TSC_RATIO 0xc0000104 |
| #define | MSR_AMD64_NB_CFG 0xc001001f |
| #define | MSR_AMD64_PATCH_LOADER 0xc0010020 |
| #define | MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 |
| #define | MSR_AMD64_OSVW_STATUS 0xc0010141 |
| #define | MSR_AMD64_DC_CFG 0xc0011022 |
| #define | MSR_AMD64_IBSFETCHCTL 0xc0011030 |
| #define | MSR_AMD64_IBSFETCHLINAD 0xc0011031 |
| #define | MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 |
| #define | MSR_AMD64_IBSFETCH_REG_COUNT 3 |
| #define | MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) |
| #define | MSR_AMD64_IBSOPCTL 0xc0011033 |
| #define | MSR_AMD64_IBSOPRIP 0xc0011034 |
| #define | MSR_AMD64_IBSOPDATA 0xc0011035 |
| #define | MSR_AMD64_IBSOPDATA2 0xc0011036 |
| #define | MSR_AMD64_IBSOPDATA3 0xc0011037 |
| #define | MSR_AMD64_IBSDCLINAD 0xc0011038 |
| #define | MSR_AMD64_IBSDCPHYSAD 0xc0011039 |
| #define | MSR_AMD64_IBSOP_REG_COUNT 7 |
| #define | MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) |
| #define | MSR_AMD64_IBSCTL 0xc001103a |
| #define | MSR_AMD64_IBSBRTARGET 0xc001103b |
| #define | MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ |
| #define | MSR_F15H_PERF_CTL 0xc0010200 |
| #define | MSR_F15H_PERF_CTR 0xc0010201 |
| #define | MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 |
| #define | FAM10H_MMIO_CONF_ENABLE (1<<0) |
| #define | FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf |
| #define | FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 |
| #define | FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL |
| #define | FAM10H_MMIO_CONF_BASE_SHIFT 20 |
| #define | MSR_FAM10H_NODE_ID 0xc001100c |
| #define | MSR_K8_TOP_MEM1 0xc001001a |
| #define | MSR_K8_TOP_MEM2 0xc001001d |
| #define | MSR_K8_SYSCFG 0xc0010010 |
| #define | MSR_K8_INT_PENDING_MSG 0xc0010055 |
| #define | K8_INTP_C1E_ACTIVE_MASK 0x18000000 |
| #define | MSR_K8_TSEG_ADDR 0xc0010112 |
| #define | K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ |
| #define | K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ |
| #define | K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ |
| #define | MSR_K7_EVNTSEL0 0xc0010000 |
| #define | MSR_K7_PERFCTR0 0xc0010004 |
| #define | MSR_K7_EVNTSEL1 0xc0010001 |
| #define | MSR_K7_PERFCTR1 0xc0010005 |
| #define | MSR_K7_EVNTSEL2 0xc0010002 |
| #define | MSR_K7_PERFCTR2 0xc0010006 |
| #define | MSR_K7_EVNTSEL3 0xc0010003 |
| #define | MSR_K7_PERFCTR3 0xc0010007 |
| #define | MSR_K7_CLK_CTL 0xc001001b |
| #define | MSR_K7_HWCR 0xc0010015 |
| #define | MSR_K7_FID_VID_CTL 0xc0010041 |
| #define | MSR_K7_FID_VID_STATUS 0xc0010042 |
| #define | MSR_K6_WHCR 0xc0000082 |
| #define | MSR_K6_UWCCR 0xc0000085 |
| #define | MSR_K6_EPMR 0xc0000086 |
| #define | MSR_K6_PSOR 0xc0000087 |
| #define | MSR_K6_PFIR 0xc0000088 |
| #define | MSR_IDT_FCR1 0x00000107 |
| #define | MSR_IDT_FCR2 0x00000108 |
| #define | MSR_IDT_FCR3 0x00000109 |
| #define | MSR_IDT_FCR4 0x0000010a |
| #define | MSR_IDT_MCR0 0x00000110 |
| #define | MSR_IDT_MCR1 0x00000111 |
| #define | MSR_IDT_MCR2 0x00000112 |
| #define | MSR_IDT_MCR3 0x00000113 |
| #define | MSR_IDT_MCR4 0x00000114 |
| #define | MSR_IDT_MCR5 0x00000115 |
| #define | MSR_IDT_MCR6 0x00000116 |
| #define | MSR_IDT_MCR7 0x00000117 |
| #define | MSR_IDT_MCR_CTRL 0x00000120 |
| #define | MSR_VIA_FCR 0x00001107 |
| #define | MSR_VIA_LONGHAUL 0x0000110a |
| #define | MSR_VIA_RNG 0x0000110b |
| #define | MSR_VIA_BCR2 0x00001147 |
| #define | MSR_TMTA_LONGRUN_CTRL 0x80868010 |
| #define | MSR_TMTA_LONGRUN_FLAGS 0x80868011 |
| #define | MSR_TMTA_LRTI_READOUT 0x80868018 |
| #define | MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a |
| #define | MSR_IA32_P5_MC_ADDR 0x00000000 |
| #define | MSR_IA32_P5_MC_TYPE 0x00000001 |
| #define | MSR_IA32_TSC 0x00000010 |
| #define | MSR_IA32_PLATFORM_ID 0x00000017 |
| #define | MSR_IA32_EBL_CR_POWERON 0x0000002a |
| #define | MSR_EBC_FREQUENCY_ID 0x0000002c |
| #define | MSR_IA32_FEATURE_CONTROL 0x0000003a |
| #define | FEATURE_CONTROL_LOCKED (1<<0) |
| #define | FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) |
| #define | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) |
| #define | MSR_IA32_APICBASE 0x0000001b |
| #define | MSR_IA32_APICBASE_BSP (1<<8) |
| #define | MSR_IA32_APICBASE_ENABLE (1<<11) |
| #define | MSR_IA32_APICBASE_BASE (0xfffff<<12) |
| #define | MSR_IA32_TSCDEADLINE 0x000006e0 |
| #define | MSR_IA32_UCODE_WRITE 0x00000079 |
| #define | MSR_IA32_UCODE_REV 0x0000008b |
| #define | MSR_IA32_PERF_STATUS 0x00000198 |
| #define | MSR_IA32_PERF_CTL 0x00000199 |
| #define | MSR_AMD_PSTATE_DEF_BASE 0xc0010064 |
| #define | MSR_AMD_PERF_STATUS 0xc0010063 |
| #define | MSR_AMD_PERF_CTL 0xc0010062 |
| #define | MSR_IA32_MPERF 0x000000e7 |
| #define | MSR_IA32_APERF 0x000000e8 |
| #define | MSR_IA32_THERM_CONTROL 0x0000019a |
| #define | MSR_IA32_THERM_INTERRUPT 0x0000019b |
| #define | THERM_INT_HIGH_ENABLE (1 << 0) |
| #define | THERM_INT_LOW_ENABLE (1 << 1) |
| #define | THERM_INT_PLN_ENABLE (1 << 24) |
| #define | MSR_IA32_THERM_STATUS 0x0000019c |
| #define | THERM_STATUS_PROCHOT (1 << 0) |
| #define | THERM_STATUS_POWER_LIMIT (1 << 10) |
| #define | MSR_THERM2_CTL 0x0000019d |
| #define | MSR_THERM2_CTL_TM_SELECT (1ULL << 16) |
| #define | MSR_IA32_MISC_ENABLE 0x000001a0 |
| #define | MSR_IA32_TEMPERATURE_TARGET 0x000001a2 |
| #define | MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 |
| #define | ENERGY_PERF_BIAS_PERFORMANCE 0 |
| #define | ENERGY_PERF_BIAS_NORMAL 6 |
| #define | ENERGY_PERF_BIAS_POWERSAVE 15 |
| #define | MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 |
| #define | PACKAGE_THERM_STATUS_PROCHOT (1 << 0) |
| #define | PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) |
| #define | MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 |
| #define | PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) |
| #define | PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) |
| #define | PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) |
| #define | THERM_INT_THRESHOLD0_ENABLE (1 << 15) |
| #define | THERM_SHIFT_THRESHOLD0 8 |
| #define | THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) |
| #define | THERM_INT_THRESHOLD1_ENABLE (1 << 23) |
| #define | THERM_SHIFT_THRESHOLD1 16 |
| #define | THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) |
| #define | THERM_STATUS_THRESHOLD0 (1 << 6) |
| #define | THERM_LOG_THRESHOLD0 (1 << 7) |
| #define | THERM_STATUS_THRESHOLD1 (1 << 8) |
| #define | THERM_LOG_THRESHOLD1 (1 << 9) |
| #define | MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) |
| #define | MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) |
| #define | MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) |
| #define | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) |
| #define | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) |
| #define | MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) |
| #define | MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) |
| #define | MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) |
| #define | MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) |
| #define | MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) |
| #define | MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) |
| #define | MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) |
| #define | MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) |
| #define | MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) |
| #define | MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) |
| #define | MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) |
| #define | MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) |
| #define | MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) |
| #define | MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) |
| #define | MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) |
| #define | MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) |
| #define | MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) |
| #define | MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) |
| #define | MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) |
| #define | MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) |
| #define | MSR_IA32_MCG_EAX 0x00000180 |
| #define | MSR_IA32_MCG_EBX 0x00000181 |
| #define | MSR_IA32_MCG_ECX 0x00000182 |
| #define | MSR_IA32_MCG_EDX 0x00000183 |
| #define | MSR_IA32_MCG_ESI 0x00000184 |
| #define | MSR_IA32_MCG_EDI 0x00000185 |
| #define | MSR_IA32_MCG_EBP 0x00000186 |
| #define | MSR_IA32_MCG_ESP 0x00000187 |
| #define | MSR_IA32_MCG_EFLAGS 0x00000188 |
| #define | MSR_IA32_MCG_EIP 0x00000189 |
| #define | MSR_IA32_MCG_RESERVED 0x0000018a |
| #define | MSR_P4_BPU_PERFCTR0 0x00000300 |
| #define | MSR_P4_BPU_PERFCTR1 0x00000301 |
| #define | MSR_P4_BPU_PERFCTR2 0x00000302 |
| #define | MSR_P4_BPU_PERFCTR3 0x00000303 |
| #define | MSR_P4_MS_PERFCTR0 0x00000304 |
| #define | MSR_P4_MS_PERFCTR1 0x00000305 |
| #define | MSR_P4_MS_PERFCTR2 0x00000306 |
| #define | MSR_P4_MS_PERFCTR3 0x00000307 |
| #define | MSR_P4_FLAME_PERFCTR0 0x00000308 |
| #define | MSR_P4_FLAME_PERFCTR1 0x00000309 |
| #define | MSR_P4_FLAME_PERFCTR2 0x0000030a |
| #define | MSR_P4_FLAME_PERFCTR3 0x0000030b |
| #define | MSR_P4_IQ_PERFCTR0 0x0000030c |
| #define | MSR_P4_IQ_PERFCTR1 0x0000030d |
| #define | MSR_P4_IQ_PERFCTR2 0x0000030e |
| #define | MSR_P4_IQ_PERFCTR3 0x0000030f |
| #define | MSR_P4_IQ_PERFCTR4 0x00000310 |
| #define | MSR_P4_IQ_PERFCTR5 0x00000311 |
| #define | MSR_P4_BPU_CCCR0 0x00000360 |
| #define | MSR_P4_BPU_CCCR1 0x00000361 |
| #define | MSR_P4_BPU_CCCR2 0x00000362 |
| #define | MSR_P4_BPU_CCCR3 0x00000363 |
| #define | MSR_P4_MS_CCCR0 0x00000364 |
| #define | MSR_P4_MS_CCCR1 0x00000365 |
| #define | MSR_P4_MS_CCCR2 0x00000366 |
| #define | MSR_P4_MS_CCCR3 0x00000367 |
| #define | MSR_P4_FLAME_CCCR0 0x00000368 |
| #define | MSR_P4_FLAME_CCCR1 0x00000369 |
| #define | MSR_P4_FLAME_CCCR2 0x0000036a |
| #define | MSR_P4_FLAME_CCCR3 0x0000036b |
| #define | MSR_P4_IQ_CCCR0 0x0000036c |
| #define | MSR_P4_IQ_CCCR1 0x0000036d |
| #define | MSR_P4_IQ_CCCR2 0x0000036e |
| #define | MSR_P4_IQ_CCCR3 0x0000036f |
| #define | MSR_P4_IQ_CCCR4 0x00000370 |
| #define | MSR_P4_IQ_CCCR5 0x00000371 |
| #define | MSR_P4_ALF_ESCR0 0x000003ca |
| #define | MSR_P4_ALF_ESCR1 0x000003cb |
| #define | MSR_P4_BPU_ESCR0 0x000003b2 |
| #define | MSR_P4_BPU_ESCR1 0x000003b3 |
| #define | MSR_P4_BSU_ESCR0 0x000003a0 |
| #define | MSR_P4_BSU_ESCR1 0x000003a1 |
| #define | MSR_P4_CRU_ESCR0 0x000003b8 |
| #define | MSR_P4_CRU_ESCR1 0x000003b9 |
| #define | MSR_P4_CRU_ESCR2 0x000003cc |
| #define | MSR_P4_CRU_ESCR3 0x000003cd |
| #define | MSR_P4_CRU_ESCR4 0x000003e0 |
| #define | MSR_P4_CRU_ESCR5 0x000003e1 |
| #define | MSR_P4_DAC_ESCR0 0x000003a8 |
| #define | MSR_P4_DAC_ESCR1 0x000003a9 |
| #define | MSR_P4_FIRM_ESCR0 0x000003a4 |
| #define | MSR_P4_FIRM_ESCR1 0x000003a5 |
| #define | MSR_P4_FLAME_ESCR0 0x000003a6 |
| #define | MSR_P4_FLAME_ESCR1 0x000003a7 |
| #define | MSR_P4_FSB_ESCR0 0x000003a2 |
| #define | MSR_P4_FSB_ESCR1 0x000003a3 |
| #define | MSR_P4_IQ_ESCR0 0x000003ba |
| #define | MSR_P4_IQ_ESCR1 0x000003bb |
| #define | MSR_P4_IS_ESCR0 0x000003b4 |
| #define | MSR_P4_IS_ESCR1 0x000003b5 |
| #define | MSR_P4_ITLB_ESCR0 0x000003b6 |
| #define | MSR_P4_ITLB_ESCR1 0x000003b7 |
| #define | MSR_P4_IX_ESCR0 0x000003c8 |
| #define | MSR_P4_IX_ESCR1 0x000003c9 |
| #define | MSR_P4_MOB_ESCR0 0x000003aa |
| #define | MSR_P4_MOB_ESCR1 0x000003ab |
| #define | MSR_P4_MS_ESCR0 0x000003c0 |
| #define | MSR_P4_MS_ESCR1 0x000003c1 |
| #define | MSR_P4_PMH_ESCR0 0x000003ac |
| #define | MSR_P4_PMH_ESCR1 0x000003ad |
| #define | MSR_P4_RAT_ESCR0 0x000003bc |
| #define | MSR_P4_RAT_ESCR1 0x000003bd |
| #define | MSR_P4_SAAT_ESCR0 0x000003ae |
| #define | MSR_P4_SAAT_ESCR1 0x000003af |
| #define | MSR_P4_SSU_ESCR0 0x000003be |
| #define | MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ |
| #define | MSR_P4_TBPU_ESCR0 0x000003c2 |
| #define | MSR_P4_TBPU_ESCR1 0x000003c3 |
| #define | MSR_P4_TC_ESCR0 0x000003c4 |
| #define | MSR_P4_TC_ESCR1 0x000003c5 |
| #define | MSR_P4_U2L_ESCR0 0x000003b0 |
| #define | MSR_P4_U2L_ESCR1 0x000003b1 |
| #define | MSR_P4_PEBS_MATRIX_VERT 0x000003f2 |
| #define | MSR_CORE_PERF_FIXED_CTR0 0x00000309 |
| #define | MSR_CORE_PERF_FIXED_CTR1 0x0000030a |
| #define | MSR_CORE_PERF_FIXED_CTR2 0x0000030b |
| #define | MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d |
| #define | MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e |
| #define | MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f |
| #define | MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 |
| #define | MSR_GEODE_BUSCONT_CONF0 0x00001900 |
| #define | MSR_IA32_VMX_BASIC 0x00000480 |
| #define | MSR_IA32_VMX_PINBASED_CTLS 0x00000481 |
| #define | MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 |
| #define | MSR_IA32_VMX_EXIT_CTLS 0x00000483 |
| #define | MSR_IA32_VMX_ENTRY_CTLS 0x00000484 |
| #define | MSR_IA32_VMX_MISC 0x00000485 |
| #define | MSR_IA32_VMX_CR0_FIXED0 0x00000486 |
| #define | MSR_IA32_VMX_CR0_FIXED1 0x00000487 |
| #define | MSR_IA32_VMX_CR4_FIXED0 0x00000488 |
| #define | MSR_IA32_VMX_CR4_FIXED1 0x00000489 |
| #define | MSR_IA32_VMX_VMCS_ENUM 0x0000048a |
| #define | MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b |
| #define | MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c |
| #define | MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d |
| #define | MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e |
| #define | MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f |
| #define | MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 |
| #define | VMX_BASIC_VMCS_SIZE_SHIFT 32 |
| #define | VMX_BASIC_64 0x0001000000000000LLU |
| #define | VMX_BASIC_MEM_TYPE_SHIFT 50 |
| #define | VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU |
| #define | VMX_BASIC_MEM_TYPE_WB 6LLU |
| #define | VMX_BASIC_INOUT 0x0040000000000000LLU |
| #define | MSR_VM_CR 0xc0010114 |
| #define | MSR_VM_IGNNE 0xc0010115 |
| #define | MSR_VM_HSAVE_PA 0xc0010117 |
| #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ |
Definition at line 24 of file msr-index.h.
Definition at line 20 of file msr-index.h.
Definition at line 19 of file msr-index.h.
| #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ |
Definition at line 23 of file msr-index.h.
Definition at line 21 of file msr-index.h.
| #define _EFER_SCE 0 /* SYSCALL/SYSRET */ |
Definition at line 18 of file msr-index.h.
| #define _EFER_SVME 12 /* Enable virtualization */ |
Definition at line 22 of file msr-index.h.
| #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) |
Definition at line 42 of file msr-index.h.
| #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ |
Definition at line 93 of file msr-index.h.
| #define DEBUGCTLMSR_BTINT (1UL << 8) |
Definition at line 96 of file msr-index.h.
| #define DEBUGCTLMSR_BTS (1UL << 7) |
Definition at line 95 of file msr-index.h.
| #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) |
Definition at line 97 of file msr-index.h.
| #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) |
Definition at line 98 of file msr-index.h.
| #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) |
Definition at line 99 of file msr-index.h.
| #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ |
Definition at line 92 of file msr-index.h.
| #define DEBUGCTLMSR_TR (1UL << 6) |
Definition at line 94 of file msr-index.h.
| #define EFER_FFXSR (1<<_EFER_FFXSR) |
Definition at line 32 of file msr-index.h.
| #define EFER_LMA (1<<_EFER_LMA) |
Definition at line 28 of file msr-index.h.
| #define EFER_LME (1<<_EFER_LME) |
Definition at line 27 of file msr-index.h.
| #define EFER_LMSLE (1<<_EFER_LMSLE) |
Definition at line 31 of file msr-index.h.
| #define EFER_NX (1<<_EFER_NX) |
Definition at line 29 of file msr-index.h.
| #define EFER_SCE (1<<_EFER_SCE) |
Definition at line 26 of file msr-index.h.
| #define EFER_SVME (1<<_EFER_SVME) |
Definition at line 30 of file msr-index.h.
| #define ENERGY_PERF_BIAS_NORMAL 6 |
Definition at line 285 of file msr-index.h.
| #define ENERGY_PERF_BIAS_PERFORMANCE 0 |
Definition at line 284 of file msr-index.h.
| #define ENERGY_PERF_BIAS_POWERSAVE 15 |
Definition at line 286 of file msr-index.h.
| #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL |
Definition at line 166 of file msr-index.h.
| #define FAM10H_MMIO_CONF_BASE_SHIFT 20 |
Definition at line 167 of file msr-index.h.
| #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf |
Definition at line 164 of file msr-index.h.
| #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 |
Definition at line 165 of file msr-index.h.
| #define FAM10H_MMIO_CONF_ENABLE (1<<0) |
Definition at line 163 of file msr-index.h.
| #define FEATURE_CONTROL_LOCKED (1<<0) |
Definition at line 240 of file msr-index.h.
| #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) |
Definition at line 241 of file msr-index.h.
| #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) |
Definition at line 242 of file msr-index.h.
| #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 |
Definition at line 176 of file msr-index.h.
| #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ |
Definition at line 180 of file msr-index.h.
| #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ |
Definition at line 178 of file msr-index.h.
| #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ |
Definition at line 179 of file msr-index.h.
| #define MSR_AMD64_DC_CFG 0xc0011022 |
Definition at line 138 of file msr-index.h.
| #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ |
Definition at line 155 of file msr-index.h.
| #define MSR_AMD64_IBSBRTARGET 0xc001103b |
Definition at line 154 of file msr-index.h.
| #define MSR_AMD64_IBSCTL 0xc001103a |
Definition at line 153 of file msr-index.h.
| #define MSR_AMD64_IBSDCLINAD 0xc0011038 |
Definition at line 149 of file msr-index.h.
| #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 |
Definition at line 150 of file msr-index.h.
| #define MSR_AMD64_IBSFETCH_REG_COUNT 3 |
Definition at line 142 of file msr-index.h.
| #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) |
Definition at line 143 of file msr-index.h.
| #define MSR_AMD64_IBSFETCHCTL 0xc0011030 |
Definition at line 139 of file msr-index.h.
| #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 |
Definition at line 140 of file msr-index.h.
| #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 |
Definition at line 141 of file msr-index.h.
| #define MSR_AMD64_IBSOP_REG_COUNT 7 |
Definition at line 151 of file msr-index.h.
| #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) |
Definition at line 152 of file msr-index.h.
| #define MSR_AMD64_IBSOPCTL 0xc0011033 |
Definition at line 144 of file msr-index.h.
| #define MSR_AMD64_IBSOPDATA 0xc0011035 |
Definition at line 146 of file msr-index.h.
| #define MSR_AMD64_IBSOPDATA2 0xc0011036 |
Definition at line 147 of file msr-index.h.
| #define MSR_AMD64_IBSOPDATA3 0xc0011037 |
Definition at line 148 of file msr-index.h.
| #define MSR_AMD64_IBSOPRIP 0xc0011034 |
Definition at line 145 of file msr-index.h.
| #define MSR_AMD64_MC0_MASK 0xc0010044 |
Definition at line 106 of file msr-index.h.
| #define MSR_AMD64_MCx_MASK | ( | x | ) | (MSR_AMD64_MC0_MASK + (x)) |
Definition at line 113 of file msr-index.h.
| #define MSR_AMD64_NB_CFG 0xc001001f |
Definition at line 134 of file msr-index.h.
| #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 |
Definition at line 136 of file msr-index.h.
| #define MSR_AMD64_OSVW_STATUS 0xc0010141 |
Definition at line 137 of file msr-index.h.
| #define MSR_AMD64_PATCH_LEVEL 0x0000008b |
Definition at line 132 of file msr-index.h.
| #define MSR_AMD64_PATCH_LOADER 0xc0010020 |
Definition at line 135 of file msr-index.h.
| #define MSR_AMD64_TSC_RATIO 0xc0000104 |
Definition at line 133 of file msr-index.h.
| #define MSR_AMD_PERF_CTL 0xc0010062 |
Definition at line 258 of file msr-index.h.
| #define MSR_AMD_PERF_STATUS 0xc0010063 |
Definition at line 257 of file msr-index.h.
| #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 |
Definition at line 256 of file msr-index.h.
| #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 |
Definition at line 441 of file msr-index.h.
| #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a |
Definition at line 442 of file msr-index.h.
| #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b |
Definition at line 443 of file msr-index.h.
| #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d |
Definition at line 444 of file msr-index.h.
| #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f |
Definition at line 446 of file msr-index.h.
| #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 |
Definition at line 447 of file msr-index.h.
| #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e |
Definition at line 445 of file msr-index.h.
| #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ |
Definition at line 10 of file msr-index.h.
| #define MSR_EBC_FREQUENCY_ID 0x0000002c |
Definition at line 237 of file msr-index.h.
| #define MSR_EFER 0xc0000080 /* extended feature register */ |
Definition at line 7 of file msr-index.h.
| #define MSR_F15H_PERF_CTL 0xc0010200 |
Definition at line 158 of file msr-index.h.
| #define MSR_F15H_PERF_CTR 0xc0010201 |
Definition at line 159 of file msr-index.h.
| #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 |
Definition at line 162 of file msr-index.h.
| #define MSR_FAM10H_NODE_ID 0xc001100c |
Definition at line 168 of file msr-index.h.
| #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ |
Definition at line 12 of file msr-index.h.
| #define MSR_FSB_FREQ 0x000000cd |
Definition at line 37 of file msr-index.h.
| #define MSR_GEODE_BUSCONT_CONF0 0x00001900 |
Definition at line 450 of file msr-index.h.
| #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ |
Definition at line 13 of file msr-index.h.
| #define MSR_IA32_APERF 0x000000e8 |
Definition at line 261 of file msr-index.h.
| #define MSR_IA32_APICBASE 0x0000001b |
Definition at line 244 of file msr-index.h.
| #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
Definition at line 247 of file msr-index.h.
| #define MSR_IA32_APICBASE_BSP (1<<8) |
Definition at line 245 of file msr-index.h.
| #define MSR_IA32_APICBASE_ENABLE (1<<11) |
Definition at line 246 of file msr-index.h.
| #define MSR_IA32_BBL_CR_CTL 0x00000119 |
Definition at line 45 of file msr-index.h.
| #define MSR_IA32_BBL_CR_CTL3 0x0000011e |
Definition at line 46 of file msr-index.h.
| #define MSR_IA32_CR_PAT 0x00000277 |
Definition at line 83 of file msr-index.h.
| #define MSR_IA32_DEBUGCTLMSR 0x000001d9 |
Definition at line 85 of file msr-index.h.
| #define MSR_IA32_DS_AREA 0x00000600 |
Definition at line 67 of file msr-index.h.
| #define MSR_IA32_EBL_CR_POWERON 0x0000002a |
Definition at line 236 of file msr-index.h.
| #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 |
Definition at line 283 of file msr-index.h.
| #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
Definition at line 238 of file msr-index.h.
| #define MSR_IA32_LASTBRANCHFROMIP 0x000001db |
Definition at line 86 of file msr-index.h.
| #define MSR_IA32_LASTBRANCHTOIP 0x000001dc |
Definition at line 87 of file msr-index.h.
| #define MSR_IA32_LASTINTFROMIP 0x000001dd |
Definition at line 88 of file msr-index.h.
| #define MSR_IA32_LASTINTTOIP 0x000001de |
Definition at line 89 of file msr-index.h.
| #define MSR_IA32_MC0_ADDR 0x00000402 |
Definition at line 103 of file msr-index.h.
| #define MSR_IA32_MC0_CTL 0x00000400 |
Definition at line 101 of file msr-index.h.
| #define MSR_IA32_MC0_CTL2 0x00000280 |
Definition at line 116 of file msr-index.h.
| #define MSR_IA32_MC0_MISC 0x00000403 |
Definition at line 104 of file msr-index.h.
| #define MSR_IA32_MC0_STATUS 0x00000401 |
Definition at line 102 of file msr-index.h.
| #define MSR_IA32_MCG_CAP 0x00000179 |
Definition at line 52 of file msr-index.h.
| #define MSR_IA32_MCG_CTL 0x0000017b |
Definition at line 54 of file msr-index.h.
| #define MSR_IA32_MCG_EAX 0x00000180 |
Definition at line 341 of file msr-index.h.
| #define MSR_IA32_MCG_EBP 0x00000186 |
Definition at line 347 of file msr-index.h.
| #define MSR_IA32_MCG_EBX 0x00000181 |
Definition at line 342 of file msr-index.h.
| #define MSR_IA32_MCG_ECX 0x00000182 |
Definition at line 343 of file msr-index.h.
| #define MSR_IA32_MCG_EDI 0x00000185 |
Definition at line 346 of file msr-index.h.
| #define MSR_IA32_MCG_EDX 0x00000183 |
Definition at line 344 of file msr-index.h.
| #define MSR_IA32_MCG_EFLAGS 0x00000188 |
Definition at line 349 of file msr-index.h.
| #define MSR_IA32_MCG_EIP 0x00000189 |
Definition at line 350 of file msr-index.h.
| #define MSR_IA32_MCG_ESI 0x00000184 |
Definition at line 345 of file msr-index.h.
| #define MSR_IA32_MCG_ESP 0x00000187 |
Definition at line 348 of file msr-index.h.
| #define MSR_IA32_MCG_RESERVED 0x0000018a |
Definition at line 351 of file msr-index.h.
| #define MSR_IA32_MCG_STATUS 0x0000017a |
Definition at line 53 of file msr-index.h.
| #define MSR_IA32_MCx_ADDR | ( | x | ) | (MSR_IA32_MC0_ADDR + 4*(x)) |
Definition at line 110 of file msr-index.h.
| #define MSR_IA32_MCx_CTL | ( | x | ) | (MSR_IA32_MC0_CTL + 4*(x)) |
Definition at line 108 of file msr-index.h.
| #define MSR_IA32_MCx_CTL2 | ( | x | ) | (MSR_IA32_MC0_CTL2 + (x)) |
Definition at line 117 of file msr-index.h.
| #define MSR_IA32_MCx_MISC | ( | x | ) | (MSR_IA32_MC0_MISC + 4*(x)) |
Definition at line 111 of file msr-index.h.
| #define MSR_IA32_MCx_STATUS | ( | x | ) | (MSR_IA32_MC0_STATUS + 4*(x)) |
Definition at line 109 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE 0x000001a0 |
Definition at line 279 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) |
Definition at line 333 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) |
Definition at line 315 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) |
Definition at line 336 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) |
Definition at line 314 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) |
Definition at line 317 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) |
Definition at line 312 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) |
Definition at line 330 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) |
Definition at line 331 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) |
Definition at line 338 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) |
Definition at line 335 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) |
Definition at line 327 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) |
Definition at line 319 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) |
Definition at line 318 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) |
Definition at line 316 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) |
Definition at line 329 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) |
Definition at line 334 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) |
Definition at line 326 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) |
Definition at line 328 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) |
Definition at line 313 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) |
Definition at line 325 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) |
Definition at line 332 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) |
Definition at line 337 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) |
Definition at line 324 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) |
Definition at line 321 of file msr-index.h.
| #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) |
Definition at line 320 of file msr-index.h.
| #define MSR_IA32_MPERF 0x000000e7 |
Definition at line 260 of file msr-index.h.
| #define MSR_IA32_P5_MC_ADDR 0x00000000 |
Definition at line 232 of file msr-index.h.
| #define MSR_IA32_P5_MC_TYPE 0x00000001 |
Definition at line 233 of file msr-index.h.
| #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 |
Definition at line 293 of file msr-index.h.
| #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 |
Definition at line 288 of file msr-index.h.
| #define MSR_IA32_PEBS_ENABLE 0x000003f1 |
Definition at line 66 of file msr-index.h.
| #define MSR_IA32_PERF_CAPABILITIES 0x00000345 |
Definition at line 68 of file msr-index.h.
| #define MSR_IA32_PERF_CTL 0x00000199 |
Definition at line 255 of file msr-index.h.
| #define MSR_IA32_PERF_STATUS 0x00000198 |
Definition at line 254 of file msr-index.h.
| #define MSR_IA32_PERFCTR0 0x000000c1 |
Definition at line 35 of file msr-index.h.
| #define MSR_IA32_PERFCTR1 0x000000c2 |
Definition at line 36 of file msr-index.h.
| #define MSR_IA32_PLATFORM_ID 0x00000017 |
Definition at line 235 of file msr-index.h.
| #define MSR_IA32_SYSENTER_CS 0x00000174 |
Definition at line 48 of file msr-index.h.
| #define MSR_IA32_SYSENTER_EIP 0x00000176 |
Definition at line 50 of file msr-index.h.
| #define MSR_IA32_SYSENTER_ESP 0x00000175 |
Definition at line 49 of file msr-index.h.
| #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 |
Definition at line 281 of file msr-index.h.
| #define MSR_IA32_THERM_CONTROL 0x0000019a |
Definition at line 263 of file msr-index.h.
| #define MSR_IA32_THERM_INTERRUPT 0x0000019b |
Definition at line 264 of file msr-index.h.
| #define MSR_IA32_THERM_STATUS 0x0000019c |
Definition at line 270 of file msr-index.h.
| #define MSR_IA32_TSC 0x00000010 |
Definition at line 234 of file msr-index.h.
| #define MSR_IA32_TSCDEADLINE 0x000006e0 |
Definition at line 249 of file msr-index.h.
| #define MSR_IA32_UCODE_REV 0x0000008b |
Definition at line 252 of file msr-index.h.
| #define MSR_IA32_UCODE_WRITE 0x00000079 |
Definition at line 251 of file msr-index.h.
| #define MSR_IA32_VMX_BASIC 0x00000480 |
Definition at line 453 of file msr-index.h.
| #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 |
Definition at line 459 of file msr-index.h.
| #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 |
Definition at line 460 of file msr-index.h.
| #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 |
Definition at line 461 of file msr-index.h.
| #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 |
Definition at line 462 of file msr-index.h.
| #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 |
Definition at line 457 of file msr-index.h.
| #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c |
Definition at line 465 of file msr-index.h.
| #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 |
Definition at line 456 of file msr-index.h.
| #define MSR_IA32_VMX_MISC 0x00000485 |
Definition at line 458 of file msr-index.h.
| #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 |
Definition at line 454 of file msr-index.h.
| #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 |
Definition at line 455 of file msr-index.h.
| #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b |
Definition at line 464 of file msr-index.h.
| #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 |
Definition at line 469 of file msr-index.h.
| #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f |
Definition at line 468 of file msr-index.h.
| #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d |
Definition at line 466 of file msr-index.h.
| #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e |
Definition at line 467 of file msr-index.h.
| #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a |
Definition at line 463 of file msr-index.h.
| #define MSR_IDT_FCR1 0x00000107 |
Definition at line 204 of file msr-index.h.
| #define MSR_IDT_FCR2 0x00000108 |
Definition at line 205 of file msr-index.h.
| #define MSR_IDT_FCR3 0x00000109 |
Definition at line 206 of file msr-index.h.
| #define MSR_IDT_FCR4 0x0000010a |
Definition at line 207 of file msr-index.h.
| #define MSR_IDT_MCR0 0x00000110 |
Definition at line 209 of file msr-index.h.
| #define MSR_IDT_MCR1 0x00000111 |
Definition at line 210 of file msr-index.h.
| #define MSR_IDT_MCR2 0x00000112 |
Definition at line 211 of file msr-index.h.
| #define MSR_IDT_MCR3 0x00000113 |
Definition at line 212 of file msr-index.h.
| #define MSR_IDT_MCR4 0x00000114 |
Definition at line 213 of file msr-index.h.
| #define MSR_IDT_MCR5 0x00000115 |
Definition at line 214 of file msr-index.h.
| #define MSR_IDT_MCR6 0x00000116 |
Definition at line 215 of file msr-index.h.
| #define MSR_IDT_MCR7 0x00000117 |
Definition at line 216 of file msr-index.h.
| #define MSR_IDT_MCR_CTRL 0x00000120 |
Definition at line 217 of file msr-index.h.
| #define MSR_K6_EPMR 0xc0000086 |
Definition at line 199 of file msr-index.h.
| #define MSR_K6_PFIR 0xc0000088 |
Definition at line 201 of file msr-index.h.
| #define MSR_K6_PSOR 0xc0000087 |
Definition at line 200 of file msr-index.h.
| #define MSR_K6_UWCCR 0xc0000085 |
Definition at line 198 of file msr-index.h.
| #define MSR_K6_WHCR 0xc0000082 |
Definition at line 197 of file msr-index.h.
| #define MSR_K7_CLK_CTL 0xc001001b |
Definition at line 191 of file msr-index.h.
| #define MSR_K7_EVNTSEL0 0xc0010000 |
Definition at line 183 of file msr-index.h.
| #define MSR_K7_EVNTSEL1 0xc0010001 |
Definition at line 185 of file msr-index.h.
| #define MSR_K7_EVNTSEL2 0xc0010002 |
Definition at line 187 of file msr-index.h.
| #define MSR_K7_EVNTSEL3 0xc0010003 |
Definition at line 189 of file msr-index.h.
| #define MSR_K7_FID_VID_CTL 0xc0010041 |
Definition at line 193 of file msr-index.h.
| #define MSR_K7_FID_VID_STATUS 0xc0010042 |
Definition at line 194 of file msr-index.h.
| #define MSR_K7_HWCR 0xc0010015 |
Definition at line 192 of file msr-index.h.
| #define MSR_K7_PERFCTR0 0xc0010004 |
Definition at line 184 of file msr-index.h.
| #define MSR_K7_PERFCTR1 0xc0010005 |
Definition at line 186 of file msr-index.h.
| #define MSR_K7_PERFCTR2 0xc0010006 |
Definition at line 188 of file msr-index.h.
| #define MSR_K7_PERFCTR3 0xc0010007 |
Definition at line 190 of file msr-index.h.
| #define MSR_K8_INT_PENDING_MSG 0xc0010055 |
Definition at line 174 of file msr-index.h.
| #define MSR_K8_SYSCFG 0xc0010010 |
Definition at line 173 of file msr-index.h.
| #define MSR_K8_TOP_MEM1 0xc001001a |
Definition at line 171 of file msr-index.h.
| #define MSR_K8_TOP_MEM2 0xc001001d |
Definition at line 172 of file msr-index.h.
| #define MSR_K8_TSEG_ADDR 0xc0010112 |
Definition at line 177 of file msr-index.h.
| #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ |
Definition at line 14 of file msr-index.h.
| #define MSR_KNC_EVNTSEL0 0x00000028 |
Definition at line 126 of file msr-index.h.
| #define MSR_KNC_EVNTSEL1 0x00000029 |
Definition at line 127 of file msr-index.h.
| #define MSR_KNC_PERFCTR0 0x00000020 |
Definition at line 124 of file msr-index.h.
| #define MSR_KNC_PERFCTR1 0x00000021 |
Definition at line 125 of file msr-index.h.
| #define MSR_LBR_CORE_FROM 0x00000040 |
Definition at line 63 of file msr-index.h.
| #define MSR_LBR_CORE_TO 0x00000060 |
Definition at line 64 of file msr-index.h.
| #define MSR_LBR_NHM_FROM 0x00000680 |
Definition at line 61 of file msr-index.h.
| #define MSR_LBR_NHM_TO 0x000006c0 |
Definition at line 62 of file msr-index.h.
| #define MSR_LBR_SELECT 0x000001c8 |
Definition at line 59 of file msr-index.h.
| #define MSR_LBR_TOS 0x000001c9 |
Definition at line 60 of file msr-index.h.
| #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ |
Definition at line 9 of file msr-index.h.
| #define MSR_MTRRcap 0x000000fe |
Definition at line 44 of file msr-index.h.
| #define MSR_MTRRdefType 0x000002ff |
Definition at line 81 of file msr-index.h.
| #define MSR_MTRRfix16K_80000 0x00000258 |
Definition at line 71 of file msr-index.h.
| #define MSR_MTRRfix16K_A0000 0x00000259 |
Definition at line 72 of file msr-index.h.
| #define MSR_MTRRfix4K_C0000 0x00000268 |
Definition at line 73 of file msr-index.h.
| #define MSR_MTRRfix4K_C8000 0x00000269 |
Definition at line 74 of file msr-index.h.
| #define MSR_MTRRfix4K_D0000 0x0000026a |
Definition at line 75 of file msr-index.h.
| #define MSR_MTRRfix4K_D8000 0x0000026b |
Definition at line 76 of file msr-index.h.
| #define MSR_MTRRfix4K_E0000 0x0000026c |
Definition at line 77 of file msr-index.h.
| #define MSR_MTRRfix4K_E8000 0x0000026d |
Definition at line 78 of file msr-index.h.
| #define MSR_MTRRfix4K_F0000 0x0000026e |
Definition at line 79 of file msr-index.h.
| #define MSR_MTRRfix4K_F8000 0x0000026f |
Definition at line 80 of file msr-index.h.
| #define MSR_MTRRfix64K_00000 0x00000250 |
Definition at line 70 of file msr-index.h.
| #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 |
Definition at line 39 of file msr-index.h.
| #define MSR_OFFCORE_RSP_0 0x000001a6 |
Definition at line 56 of file msr-index.h.
| #define MSR_OFFCORE_RSP_1 0x000001a7 |
Definition at line 57 of file msr-index.h.
| #define MSR_P4_ALF_ESCR0 0x000003ca |
Definition at line 390 of file msr-index.h.
| #define MSR_P4_ALF_ESCR1 0x000003cb |
Definition at line 391 of file msr-index.h.
| #define MSR_P4_BPU_CCCR0 0x00000360 |
Definition at line 372 of file msr-index.h.
| #define MSR_P4_BPU_CCCR1 0x00000361 |
Definition at line 373 of file msr-index.h.
| #define MSR_P4_BPU_CCCR2 0x00000362 |
Definition at line 374 of file msr-index.h.
| #define MSR_P4_BPU_CCCR3 0x00000363 |
Definition at line 375 of file msr-index.h.
| #define MSR_P4_BPU_ESCR0 0x000003b2 |
Definition at line 392 of file msr-index.h.
| #define MSR_P4_BPU_ESCR1 0x000003b3 |
Definition at line 393 of file msr-index.h.
| #define MSR_P4_BPU_PERFCTR0 0x00000300 |
Definition at line 354 of file msr-index.h.
| #define MSR_P4_BPU_PERFCTR1 0x00000301 |
Definition at line 355 of file msr-index.h.
| #define MSR_P4_BPU_PERFCTR2 0x00000302 |
Definition at line 356 of file msr-index.h.
| #define MSR_P4_BPU_PERFCTR3 0x00000303 |
Definition at line 357 of file msr-index.h.
| #define MSR_P4_BSU_ESCR0 0x000003a0 |
Definition at line 394 of file msr-index.h.
| #define MSR_P4_BSU_ESCR1 0x000003a1 |
Definition at line 395 of file msr-index.h.
| #define MSR_P4_CRU_ESCR0 0x000003b8 |
Definition at line 396 of file msr-index.h.
| #define MSR_P4_CRU_ESCR1 0x000003b9 |
Definition at line 397 of file msr-index.h.
| #define MSR_P4_CRU_ESCR2 0x000003cc |
Definition at line 398 of file msr-index.h.
| #define MSR_P4_CRU_ESCR3 0x000003cd |
Definition at line 399 of file msr-index.h.
| #define MSR_P4_CRU_ESCR4 0x000003e0 |
Definition at line 400 of file msr-index.h.
| #define MSR_P4_CRU_ESCR5 0x000003e1 |
Definition at line 401 of file msr-index.h.
| #define MSR_P4_DAC_ESCR0 0x000003a8 |
Definition at line 402 of file msr-index.h.
| #define MSR_P4_DAC_ESCR1 0x000003a9 |
Definition at line 403 of file msr-index.h.
| #define MSR_P4_FIRM_ESCR0 0x000003a4 |
Definition at line 404 of file msr-index.h.
| #define MSR_P4_FIRM_ESCR1 0x000003a5 |
Definition at line 405 of file msr-index.h.
| #define MSR_P4_FLAME_CCCR0 0x00000368 |
Definition at line 380 of file msr-index.h.
| #define MSR_P4_FLAME_CCCR1 0x00000369 |
Definition at line 381 of file msr-index.h.
| #define MSR_P4_FLAME_CCCR2 0x0000036a |
Definition at line 382 of file msr-index.h.
| #define MSR_P4_FLAME_CCCR3 0x0000036b |
Definition at line 383 of file msr-index.h.
| #define MSR_P4_FLAME_ESCR0 0x000003a6 |
Definition at line 406 of file msr-index.h.
| #define MSR_P4_FLAME_ESCR1 0x000003a7 |
Definition at line 407 of file msr-index.h.
| #define MSR_P4_FLAME_PERFCTR0 0x00000308 |
Definition at line 362 of file msr-index.h.
| #define MSR_P4_FLAME_PERFCTR1 0x00000309 |
Definition at line 363 of file msr-index.h.
| #define MSR_P4_FLAME_PERFCTR2 0x0000030a |
Definition at line 364 of file msr-index.h.
| #define MSR_P4_FLAME_PERFCTR3 0x0000030b |
Definition at line 365 of file msr-index.h.
| #define MSR_P4_FSB_ESCR0 0x000003a2 |
Definition at line 408 of file msr-index.h.
| #define MSR_P4_FSB_ESCR1 0x000003a3 |
Definition at line 409 of file msr-index.h.
| #define MSR_P4_IQ_CCCR0 0x0000036c |
Definition at line 384 of file msr-index.h.
| #define MSR_P4_IQ_CCCR1 0x0000036d |
Definition at line 385 of file msr-index.h.
| #define MSR_P4_IQ_CCCR2 0x0000036e |
Definition at line 386 of file msr-index.h.
| #define MSR_P4_IQ_CCCR3 0x0000036f |
Definition at line 387 of file msr-index.h.
| #define MSR_P4_IQ_CCCR4 0x00000370 |
Definition at line 388 of file msr-index.h.
| #define MSR_P4_IQ_CCCR5 0x00000371 |
Definition at line 389 of file msr-index.h.
| #define MSR_P4_IQ_ESCR0 0x000003ba |
Definition at line 410 of file msr-index.h.
| #define MSR_P4_IQ_ESCR1 0x000003bb |
Definition at line 411 of file msr-index.h.
| #define MSR_P4_IQ_PERFCTR0 0x0000030c |
Definition at line 366 of file msr-index.h.
| #define MSR_P4_IQ_PERFCTR1 0x0000030d |
Definition at line 367 of file msr-index.h.
| #define MSR_P4_IQ_PERFCTR2 0x0000030e |
Definition at line 368 of file msr-index.h.
| #define MSR_P4_IQ_PERFCTR3 0x0000030f |
Definition at line 369 of file msr-index.h.
| #define MSR_P4_IQ_PERFCTR4 0x00000310 |
Definition at line 370 of file msr-index.h.
| #define MSR_P4_IQ_PERFCTR5 0x00000311 |
Definition at line 371 of file msr-index.h.
| #define MSR_P4_IS_ESCR0 0x000003b4 |
Definition at line 412 of file msr-index.h.
| #define MSR_P4_IS_ESCR1 0x000003b5 |
Definition at line 413 of file msr-index.h.
| #define MSR_P4_ITLB_ESCR0 0x000003b6 |
Definition at line 414 of file msr-index.h.
| #define MSR_P4_ITLB_ESCR1 0x000003b7 |
Definition at line 415 of file msr-index.h.
| #define MSR_P4_IX_ESCR0 0x000003c8 |
Definition at line 416 of file msr-index.h.
| #define MSR_P4_IX_ESCR1 0x000003c9 |
Definition at line 417 of file msr-index.h.
| #define MSR_P4_MOB_ESCR0 0x000003aa |
Definition at line 418 of file msr-index.h.
| #define MSR_P4_MOB_ESCR1 0x000003ab |
Definition at line 419 of file msr-index.h.
| #define MSR_P4_MS_CCCR0 0x00000364 |
Definition at line 376 of file msr-index.h.
| #define MSR_P4_MS_CCCR1 0x00000365 |
Definition at line 377 of file msr-index.h.
| #define MSR_P4_MS_CCCR2 0x00000366 |
Definition at line 378 of file msr-index.h.
| #define MSR_P4_MS_CCCR3 0x00000367 |
Definition at line 379 of file msr-index.h.
| #define MSR_P4_MS_ESCR0 0x000003c0 |
Definition at line 420 of file msr-index.h.
| #define MSR_P4_MS_ESCR1 0x000003c1 |
Definition at line 421 of file msr-index.h.
| #define MSR_P4_MS_PERFCTR0 0x00000304 |
Definition at line 358 of file msr-index.h.
| #define MSR_P4_MS_PERFCTR1 0x00000305 |
Definition at line 359 of file msr-index.h.
| #define MSR_P4_MS_PERFCTR2 0x00000306 |
Definition at line 360 of file msr-index.h.
| #define MSR_P4_MS_PERFCTR3 0x00000307 |
Definition at line 361 of file msr-index.h.
| #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 |
Definition at line 438 of file msr-index.h.
| #define MSR_P4_PMH_ESCR0 0x000003ac |
Definition at line 422 of file msr-index.h.
| #define MSR_P4_PMH_ESCR1 0x000003ad |
Definition at line 423 of file msr-index.h.
| #define MSR_P4_RAT_ESCR0 0x000003bc |
Definition at line 424 of file msr-index.h.
| #define MSR_P4_RAT_ESCR1 0x000003bd |
Definition at line 425 of file msr-index.h.
| #define MSR_P4_SAAT_ESCR0 0x000003ae |
Definition at line 426 of file msr-index.h.
| #define MSR_P4_SAAT_ESCR1 0x000003af |
Definition at line 427 of file msr-index.h.
| #define MSR_P4_SSU_ESCR0 0x000003be |
Definition at line 428 of file msr-index.h.
| #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ |
Definition at line 429 of file msr-index.h.
| #define MSR_P4_TBPU_ESCR0 0x000003c2 |
Definition at line 431 of file msr-index.h.
| #define MSR_P4_TBPU_ESCR1 0x000003c3 |
Definition at line 432 of file msr-index.h.
| #define MSR_P4_TC_ESCR0 0x000003c4 |
Definition at line 433 of file msr-index.h.
| #define MSR_P4_TC_ESCR1 0x000003c5 |
Definition at line 434 of file msr-index.h.
| #define MSR_P4_U2L_ESCR0 0x000003b0 |
Definition at line 435 of file msr-index.h.
| #define MSR_P4_U2L_ESCR1 0x000003b1 |
Definition at line 436 of file msr-index.h.
| #define MSR_P6_EVNTSEL0 0x00000186 |
Definition at line 121 of file msr-index.h.
| #define MSR_P6_EVNTSEL1 0x00000187 |
Definition at line 122 of file msr-index.h.
| #define MSR_P6_PERFCTR0 0x000000c1 |
Definition at line 119 of file msr-index.h.
| #define MSR_P6_PERFCTR1 0x000000c2 |
Definition at line 120 of file msr-index.h.
| #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ |
Definition at line 8 of file msr-index.h.
| #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ |
Definition at line 11 of file msr-index.h.
| #define MSR_THERM2_CTL 0x0000019d |
Definition at line 275 of file msr-index.h.
| #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) |
Definition at line 277 of file msr-index.h.
| #define MSR_TMTA_LONGRUN_CTRL 0x80868010 |
Definition at line 226 of file msr-index.h.
| #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 |
Definition at line 227 of file msr-index.h.
| #define MSR_TMTA_LRTI_READOUT 0x80868018 |
Definition at line 228 of file msr-index.h.
| #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a |
Definition at line 229 of file msr-index.h.
| #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ |
Definition at line 15 of file msr-index.h.
| #define MSR_VIA_BCR2 0x00001147 |
Definition at line 223 of file msr-index.h.
| #define MSR_VIA_FCR 0x00001107 |
Definition at line 220 of file msr-index.h.
| #define MSR_VIA_LONGHAUL 0x0000110a |
Definition at line 221 of file msr-index.h.
| #define MSR_VIA_RNG 0x0000110b |
Definition at line 222 of file msr-index.h.
| #define MSR_VM_CR 0xc0010114 |
Definition at line 481 of file msr-index.h.
| #define MSR_VM_HSAVE_PA 0xc0010117 |
Definition at line 483 of file msr-index.h.
| #define MSR_VM_IGNNE 0xc0010115 |
Definition at line 482 of file msr-index.h.
| #define NHM_C1_AUTO_DEMOTE (1UL << 26) |
Definition at line 41 of file msr-index.h.
| #define NHM_C3_AUTO_DEMOTE (1UL << 25) |
Definition at line 40 of file msr-index.h.
| #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) |
Definition at line 295 of file msr-index.h.
| #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) |
Definition at line 296 of file msr-index.h.
| #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) |
Definition at line 297 of file msr-index.h.
| #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) |
Definition at line 291 of file msr-index.h.
| #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) |
Definition at line 290 of file msr-index.h.
| #define THERM_INT_HIGH_ENABLE (1 << 0) |
Definition at line 266 of file msr-index.h.
| #define THERM_INT_LOW_ENABLE (1 << 1) |
Definition at line 267 of file msr-index.h.
| #define THERM_INT_PLN_ENABLE (1 << 24) |
Definition at line 268 of file msr-index.h.
| #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) |
Definition at line 300 of file msr-index.h.
| #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) |
Definition at line 303 of file msr-index.h.
| #define THERM_LOG_THRESHOLD0 (1 << 7) |
Definition at line 307 of file msr-index.h.
| #define THERM_LOG_THRESHOLD1 (1 << 9) |
Definition at line 309 of file msr-index.h.
| #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) |
Definition at line 302 of file msr-index.h.
| #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) |
Definition at line 305 of file msr-index.h.
| #define THERM_SHIFT_THRESHOLD0 8 |
Definition at line 301 of file msr-index.h.
| #define THERM_SHIFT_THRESHOLD1 16 |
Definition at line 304 of file msr-index.h.
| #define THERM_STATUS_POWER_LIMIT (1 << 10) |
Definition at line 273 of file msr-index.h.
| #define THERM_STATUS_PROCHOT (1 << 0) |
Definition at line 272 of file msr-index.h.
| #define THERM_STATUS_THRESHOLD0 (1 << 6) |
Definition at line 306 of file msr-index.h.
| #define THERM_STATUS_THRESHOLD1 (1 << 8) |
Definition at line 308 of file msr-index.h.
| #define VMX_BASIC_64 0x0001000000000000LLU |
Definition at line 473 of file msr-index.h.
| #define VMX_BASIC_INOUT 0x0040000000000000LLU |
Definition at line 477 of file msr-index.h.
| #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU |
Definition at line 475 of file msr-index.h.
| #define VMX_BASIC_MEM_TYPE_SHIFT 50 |
Definition at line 474 of file msr-index.h.
| #define VMX_BASIC_MEM_TYPE_WB 6LLU |
Definition at line 476 of file msr-index.h.
| #define VMX_BASIC_VMCS_SIZE_SHIFT 32 |
Definition at line 472 of file msr-index.h.
1.8.2