20 #include <linux/module.h>
25 #ifdef CONFIG_OMAP_MUX
27 #define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
29 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
31 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
36 #define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
38 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
44 #define _OMAP4_BALLENTRY(M0, bb, bt) \
46 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
47 .balls = { bb, bt }, \
89 "gpio_41",
"venc_656_data1",
NULL,
NULL,
"safe_mode"),
91 "gpio_42",
"venc_656_data2",
NULL,
NULL,
"safe_mode"),
93 "gpio_43",
"venc_656_data3",
NULL,
NULL,
"safe_mode"),
95 "gpio_44",
"venc_656_data4",
NULL,
NULL,
"safe_mode"),
97 "gpio_45",
"venc_656_data5",
NULL,
NULL,
"safe_mode"),
99 "gpio_46",
"venc_656_data6",
NULL,
NULL,
"safe_mode"),
101 "gpio_47",
"venc_656_data7",
NULL,
NULL,
"safe_mode"),
134 "c2c_dataout3",
"gpio_100",
"sys_ndmareq0",
NULL,
137 "c2c_clkin0",
"gpio_101",
"sys_ndmareq1",
NULL,
NULL,
140 "c2c_clkin1",
"gpio_102",
"sys_ndmareq2",
NULL,
NULL,
143 "c2c_dataout0",
"gpio_103",
"sys_ndmareq3",
NULL,
191 "hsi1_cawake",
NULL,
"gpio_84",
"usbb1_ulpiphy_clk",
192 NULL,
"hw_dbg20",
"safe_mode"),
194 "hsi1_cadata",
"mcbsp4_clkr",
"gpio_85",
195 "usbb1_ulpiphy_stp",
"usbb1_mm_rxdp",
"hw_dbg21",
198 "hsi1_caflag",
"mcbsp4_fsr",
"gpio_86",
199 "usbb1_ulpiphy_dir",
NULL,
"hw_dbg22",
"safe_mode"),
201 "hsi1_acready",
"mcbsp4_fsx",
"gpio_87",
202 "usbb1_ulpiphy_nxt",
"usbb1_mm_rxdm",
"hw_dbg23",
205 "hsi1_acwake",
"mcbsp4_clkx",
"gpio_88",
206 "usbb1_ulpiphy_dat0",
"usbb1_mm_rxrcv",
"hw_dbg24",
209 "hsi1_acdata",
"mcbsp4_dx",
"gpio_89",
210 "usbb1_ulpiphy_dat1",
"usbb1_mm_txse0",
"hw_dbg25",
213 "hsi1_acflag",
"mcbsp4_dr",
"gpio_90",
214 "usbb1_ulpiphy_dat2",
"usbb1_mm_txdat",
"hw_dbg26",
217 "hsi1_caready",
NULL,
"gpio_91",
"usbb1_ulpiphy_dat3",
218 "usbb1_mm_txen",
"hw_dbg27",
"safe_mode"),
220 "dmtimer8_pwm_evt",
"abe_mcbsp3_dr",
"gpio_92",
221 "usbb1_ulpiphy_dat4",
NULL,
"hw_dbg28",
"safe_mode"),
223 "dmtimer9_pwm_evt",
"abe_mcbsp3_dx",
"gpio_93",
224 "usbb1_ulpiphy_dat5",
NULL,
"hw_dbg29",
"safe_mode"),
226 "dmtimer10_pwm_evt",
"abe_mcbsp3_clkx",
"gpio_94",
227 "usbb1_ulpiphy_dat6",
"abe_dmic_din3",
"hw_dbg30",
230 "dmtimer11_pwm_evt",
"abe_mcbsp3_fsx",
"gpio_95",
231 "usbb1_ulpiphy_dat7",
"abe_dmic_clk3",
"hw_dbg31",
250 "gpio_104",
"jtag_tms_tmsc",
NULL,
NULL,
"safe_mode"),
252 "gpio_105",
"jtag_tck",
NULL,
NULL,
"safe_mode"),
262 "abe_mcasp_ahclkx",
"gpio_110",
"usbb2_mm_rxdm",
265 "abe_mcasp_axr",
"gpio_111",
"usbb2_mm_rxdp",
NULL,
268 "abe_mcasp_amute",
"gpio_112",
"usbb2_mm_rxrcv",
NULL,
271 "abe_mcasp_afsx",
"gpio_113",
"usbb2_mm_txen",
NULL,
298 "gpio_119",
"usbb2_mm_txse0",
NULL,
NULL,
301 "gpio_120",
"usbb2_mm_txdat",
NULL,
NULL,
389 "usbb2_ulpiphy_clk",
"sdmmc4_cmd",
"gpio_157",
390 "hsi2_cawake",
NULL,
NULL,
"safe_mode"),
392 "usbb2_ulpiphy_stp",
"sdmmc4_clk",
"gpio_158",
393 "hsi2_cadata",
"dispc2_data23",
NULL,
"reserved"),
395 "usbb2_ulpiphy_dir",
"sdmmc4_dat0",
"gpio_159",
396 "hsi2_caflag",
"dispc2_data22",
NULL,
"reserved"),
398 "usbb2_ulpiphy_nxt",
"sdmmc4_dat1",
"gpio_160",
399 "hsi2_acready",
"dispc2_data21",
NULL,
"reserved"),
401 "usbb2_ulpiphy_dat0",
"sdmmc4_dat2",
"gpio_161",
402 "hsi2_acwake",
"dispc2_data20",
NULL,
"reserved"),
404 "usbb2_ulpiphy_dat1",
"sdmmc4_dat3",
"gpio_162",
405 "hsi2_acdata",
"dispc2_data19",
NULL,
"reserved"),
407 "usbb2_ulpiphy_dat2",
"sdmmc3_dat2",
"gpio_163",
408 "hsi2_acflag",
"dispc2_data18",
NULL,
"reserved"),
410 "usbb2_ulpiphy_dat3",
"sdmmc3_dat1",
"gpio_164",
411 "hsi2_caready",
"dispc2_data15",
NULL,
"reserved"),
413 "usbb2_ulpiphy_dat4",
"sdmmc3_dat0",
"gpio_165",
414 "mcspi3_somi",
"dispc2_data14",
NULL,
"reserved"),
416 "usbb2_ulpiphy_dat5",
"sdmmc3_dat3",
"gpio_166",
417 "mcspi3_cs0",
"dispc2_data13",
NULL,
"reserved"),
419 "usbb2_ulpiphy_dat6",
"sdmmc3_cmd",
"gpio_167",
420 "mcspi3_simo",
"dispc2_data12",
NULL,
"reserved"),
422 "usbb2_ulpiphy_dat7",
"sdmmc3_clk",
"gpio_168",
423 "mcspi3_clk",
"dispc2_data11",
NULL,
"reserved"),
481 NULL,
"hw_dbg0",
"safe_mode"),
483 NULL,
"hw_dbg1",
"safe_mode"),
485 "gpio_13",
NULL,
"dispc2_fid",
"hw_dbg2",
"reserved"),
487 "gpio_14",
NULL,
"dispc2_data10",
"hw_dbg3",
490 "gpio_15",
NULL,
"dispc2_data9",
"hw_dbg4",
493 "gpio_16",
"rfbi_te_vsync0",
"dispc2_data16",
494 "hw_dbg5",
"reserved"),
496 "uart3_tx_irtx",
"gpio_17",
"rfbi_hsync0",
497 "dispc2_data17",
"hw_dbg6",
"reserved"),
499 "uart3_rx_irrx",
"gpio_18",
"rfbi_cs0",
500 "dispc2_hsync",
"hw_dbg7",
"reserved"),
502 "uart3_rts_sd",
"gpio_19",
"rfbi_re",
"dispc2_pclk",
503 "hw_dbg8",
"reserved"),
505 "uart3_cts_rctx",
"gpio_20",
"rfbi_we",
506 "dispc2_vsync",
"hw_dbg9",
"reserved"),
508 NULL,
"gpio_21",
"rfbi_a0",
"dispc2_de",
"hw_dbg10",
511 NULL,
"gpio_22",
"rfbi_data8",
"dispc2_data8",
512 "hw_dbg11",
"reserved"),
514 NULL,
"gpio_23",
"rfbi_data7",
"dispc2_data7",
515 "hw_dbg12",
"reserved"),
517 NULL,
"gpio_24",
"rfbi_data6",
"dispc2_data6",
518 "hw_dbg13",
"reserved"),
520 "uart1_rx",
"gpio_25",
"rfbi_data5",
"dispc2_data5",
521 "hw_dbg14",
"reserved"),
523 NULL,
"gpio_26",
"rfbi_data4",
"dispc2_data4",
524 "hw_dbg15",
"reserved"),
526 "dsi1_te0",
"gpio_27",
"rfbi_data3",
"dispc2_data3",
527 "hw_dbg16",
"reserved"),
529 "dsi1_te1",
"gpio_28",
"rfbi_data2",
"dispc2_data2",
530 "hw_dbg17",
"reserved"),
532 "dsi2_te0",
"gpio_190",
"rfbi_data1",
"dispc2_data1",
533 "hw_dbg18",
"reserved"),
535 "dsi2_te1",
"gpio_191",
"rfbi_data0",
"dispc2_data0",
536 "hw_dbg19",
"reserved"),
545 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
546 && defined(CONFIG_OMAP_PACKAGE_CBL)
754 #define omap4_core_cbl_ball NULL
778 "gpio_40",
"venc_656_data0",
NULL,
NULL,
"safe_mode"),
785 "sys_ndmareq2",
"sdmmc1_cmd",
NULL,
NULL),
787 "gpio_56",
"sys_ndmareq3",
"sdmmc1_clk",
NULL,
NULL),
789 "c2c_dataout3",
"gpio_100",
"sys_ndmareq0",
NULL,
792 "gpio_101",
"sys_ndmareq1",
NULL,
NULL,
"safe_mode"),
794 "gpio_102",
"sys_ndmareq2",
NULL,
NULL,
"safe_mode"),
796 "c2c_dataout0",
"gpio_103",
"sys_ndmareq3",
NULL,
802 "hsi1_acwake",
"mcbsp4_clkx",
"gpio_88",
803 "usbb1_ulpiphy_dat0",
"usbb1_mm_txen",
"hw_dbg24",
806 "hsi1_acdata",
"mcbsp4_dx",
"gpio_89",
807 "usbb1_ulpiphy_dat1",
"usbb1_mm_txdat",
"hw_dbg25",
810 "hsi1_acflag",
"mcbsp4_dr",
"gpio_90",
811 "usbb1_ulpiphy_dat2",
"usbb1_mm_txse0",
"hw_dbg26",
814 "hsi1_caready",
NULL,
"gpio_91",
"usbb1_ulpiphy_dat3",
815 "usbb1_mm_rxrcv",
"hw_dbg27",
"safe_mode"),
817 "gpio_119",
"usbb2_mm_txse0",
"uart4_cts",
NULL,
820 "gpio_120",
"usbb2_mm_txdat",
"uart4_rts",
NULL,
823 "abe_mcasp_axr",
"gpio_121",
NULL,
824 "dmtimer11_pwm_evt",
NULL,
"safe_mode"),
826 "abe_dmic_clk2",
"gpio_122",
NULL,
"dmtimer9_pwm_evt",
829 "usbc1_icusb_dp",
"gpio_145",
NULL,
"sdmmc2_clk",
832 "usbc1_icusb_dm",
"gpio_146",
NULL,
"sdmmc2_cmd",
835 "usbc1_icusb_rcv",
"gpio_147",
NULL,
"sdmmc2_dat0",
838 "usbc1_icusb_txen",
"gpio_148",
NULL,
"sdmmc2_dat1",
841 "gpio_149",
NULL,
"sdmmc2_dat2",
NULL,
"safe_mode"),
843 "gpio_150",
NULL,
"sdmmc2_dat3",
NULL,
"safe_mode"),
861 "usbb2_ulpiphy_stp",
"sdmmc4_clk",
"gpio_158",
862 "hsi2_cadata",
"dispc2_data23",
NULL,
"safe_mode"),
864 "usbb2_ulpiphy_dir",
"sdmmc4_dat0",
"gpio_159",
865 "hsi2_caflag",
"dispc2_data22",
NULL,
"safe_mode"),
867 "usbb2_ulpiphy_nxt",
"sdmmc4_dat1",
"gpio_160",
868 "hsi2_acready",
"dispc2_data21",
NULL,
"safe_mode"),
870 "usbb2_ulpiphy_dat0",
"sdmmc4_dat2",
"gpio_161",
871 "hsi2_acwake",
"dispc2_data20",
"usbb2_mm_txen",
874 "usbb2_ulpiphy_dat1",
"sdmmc4_dat3",
"gpio_162",
875 "hsi2_acdata",
"dispc2_data19",
"usbb2_mm_txdat",
878 "usbb2_ulpiphy_dat2",
"sdmmc3_dat2",
"gpio_163",
879 "hsi2_acflag",
"dispc2_data18",
"usbb2_mm_txse0",
882 "usbb2_ulpiphy_dat3",
"sdmmc3_dat1",
"gpio_164",
883 "hsi2_caready",
"dispc2_data15",
"rfbi_data15",
886 "usbb2_ulpiphy_dat4",
"sdmmc3_dat0",
"gpio_165",
887 "mcspi3_somi",
"dispc2_data14",
"rfbi_data14",
890 "usbb2_ulpiphy_dat5",
"sdmmc3_dat3",
"gpio_166",
891 "mcspi3_cs0",
"dispc2_data13",
"rfbi_data13",
894 "usbb2_ulpiphy_dat6",
"sdmmc3_cmd",
"gpio_167",
895 "mcspi3_simo",
"dispc2_data12",
"rfbi_data12",
898 "usbb2_ulpiphy_dat7",
"sdmmc3_clk",
"gpio_168",
899 "mcspi3_clk",
"dispc2_data11",
"rfbi_data11",
930 "gpio_13",
NULL,
"dispc2_fid",
"hw_dbg2",
933 "gpio_14",
"rfbi_data10",
"dispc2_data10",
"hw_dbg3",
936 "gpio_15",
"rfbi_data9",
"dispc2_data9",
"hw_dbg4",
939 "gpio_16",
"rfbi_te_vsync0",
"dispc2_data16",
940 "hw_dbg5",
"safe_mode"),
942 "uart3_tx_irtx",
"gpio_17",
"rfbi_hsync0",
943 "dispc2_data17",
"hw_dbg6",
"safe_mode"),
945 "uart3_rx_irrx",
"gpio_18",
"rfbi_cs0",
946 "dispc2_hsync",
"hw_dbg7",
"safe_mode"),
948 "uart3_rts_sd",
"gpio_19",
"rfbi_re",
"dispc2_pclk",
949 "hw_dbg8",
"safe_mode"),
951 "uart3_cts_rctx",
"gpio_20",
"rfbi_we",
952 "dispc2_vsync",
"hw_dbg9",
"safe_mode"),
954 NULL,
"gpio_21",
"rfbi_a0",
"dispc2_de",
"hw_dbg10",
957 NULL,
"gpio_22",
"rfbi_data8",
"dispc2_data8",
958 "hw_dbg11",
"safe_mode"),
960 NULL,
"gpio_23",
"rfbi_data7",
"dispc2_data7",
961 "hw_dbg12",
"safe_mode"),
963 NULL,
"gpio_24",
"rfbi_data6",
"dispc2_data6",
964 "hw_dbg13",
"safe_mode"),
966 "uart1_rx",
"gpio_25",
"rfbi_data5",
"dispc2_data5",
967 "hw_dbg14",
"safe_mode"),
969 NULL,
"gpio_26",
"rfbi_data4",
"dispc2_data4",
970 "hw_dbg15",
"safe_mode"),
972 "dsi1_te0",
"gpio_27",
"rfbi_data3",
"dispc2_data3",
973 "hw_dbg16",
"safe_mode"),
975 "dsi1_te1",
"gpio_28",
"rfbi_data2",
"dispc2_data2",
976 "hw_dbg17",
"safe_mode"),
978 "dsi2_te0",
"gpio_190",
"rfbi_data1",
"dispc2_data1",
979 "hw_dbg18",
"safe_mode"),
981 "dsi2_te1",
"gpio_191",
"rfbi_data0",
"dispc2_data0",
982 "hw_dbg19",
"safe_mode"),
991 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
992 && defined(CONFIG_OMAP_PACKAGE_CBS)
1200 #define omap4_core_cbs_ball NULL
1224 "gpi_wk5",
"c2c_wakereqin",
NULL,
NULL,
"safe_mode"),
1231 "sys_drm_msecure",
"gpio_wk30",
"c2c_wakereqin",
NULL,
1234 "sys_secure_indicator",
"gpio_wk31",
"c2c_wakereqout",
1251 "gpio_wk9",
"c2c_wakereqout",
NULL,
NULL,
1275 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1276 && defined(CONFIG_OMAP_PACKAGE_CBL)
1309 #define omap4_wkup_cbl_cbs_ball NULL
1323 pr_debug(
"%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__);
1325 core_muxmodes = omap4_core_muxmodes;
1328 pr_debug(
"%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__);
1330 core_muxmodes = omap4_core_muxmodes;
1331 core_subset = omap4_es2_core_subset;
1334 pr_err(
"%s: Unknown omap package, mux disabled\n", __func__);
1342 core_muxmodes, core_subset, board_subset,
1343 package_balls_core);
1351 omap4_wkup_muxmodes,
NULL, board_wkup_subset,
1352 package_balls_wkup);