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nes_hw.h
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32 
33 #ifndef __NES_HW_H
34 #define __NES_HW_H
35 
36 #include <linux/inet_lro.h>
37 
38 #define NES_PHY_TYPE_CX4 1
39 #define NES_PHY_TYPE_1G 2
40 #define NES_PHY_TYPE_ARGUS 4
41 #define NES_PHY_TYPE_PUMA_1G 5
42 #define NES_PHY_TYPE_PUMA_10G 6
43 #define NES_PHY_TYPE_GLADIUS 7
44 #define NES_PHY_TYPE_SFP_D 8
45 #define NES_PHY_TYPE_KR 9
46 
47 #define NES_MULTICAST_PF_MAX 8
48 #define NES_A0 3
49 
50 #define NES_ENABLE_PAU 0x07000001
51 #define NES_DISABLE_PAU 0x07000000
52 #define NES_PAU_COUNTER 10
53 #define NES_CQP_OPCODE_MASK 0x3f
54 
55 enum pci_regs {
56  NES_INT_STAT = 0x0000,
57  NES_INT_MASK = 0x0004,
58  NES_INT_PENDING = 0x0008,
59  NES_INTF_INT_STAT = 0x000C,
60  NES_INTF_INT_MASK = 0x0010,
61  NES_TIMER_STAT = 0x0014,
62  NES_PERIODIC_CONTROL = 0x0018,
63  NES_ONE_SHOT_CONTROL = 0x001C,
64  NES_EEPROM_COMMAND = 0x0020,
65  NES_EEPROM_DATA = 0x0024,
66  NES_FLASH_COMMAND = 0x0028,
67  NES_FLASH_DATA = 0x002C,
68  NES_SOFTWARE_RESET = 0x0030,
69  NES_CQ_ACK = 0x0034,
70  NES_WQE_ALLOC = 0x0040,
71  NES_CQE_ALLOC = 0x0044,
72  NES_AEQ_ALLOC = 0x0048
73 };
74 
75 enum indexed_regs {
76  NES_IDX_CREATE_CQP_LOW = 0x0000,
77  NES_IDX_CREATE_CQP_HIGH = 0x0004,
78  NES_IDX_QP_CONTROL = 0x0040,
79  NES_IDX_FLM_CONTROL = 0x0080,
80  NES_IDX_INT_CPU_STATUS = 0x00a0,
81  NES_IDX_GPR_TRIGGER = 0x00bc,
82  NES_IDX_GPIO_CONTROL = 0x00f0,
83  NES_IDX_GPIO_DATA = 0x00f4,
84  NES_IDX_GPR2 = 0x010c,
85  NES_IDX_TCP_CONFIG0 = 0x01e4,
86  NES_IDX_TCP_TIMER_CONFIG = 0x01ec,
87  NES_IDX_TCP_NOW = 0x01f0,
88  NES_IDX_QP_MAX_CFG_SIZES = 0x0200,
89  NES_IDX_QP_CTX_SIZE = 0x0218,
90  NES_IDX_TCP_TIMER_SIZE0 = 0x0238,
91  NES_IDX_TCP_TIMER_SIZE1 = 0x0240,
92  NES_IDX_ARP_CACHE_SIZE = 0x0258,
93  NES_IDX_CQ_CTX_SIZE = 0x0260,
94  NES_IDX_MRT_SIZE = 0x0278,
95  NES_IDX_PBL_REGION_SIZE = 0x0280,
96  NES_IDX_IRRQ_COUNT = 0x02b0,
97  NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x02f0,
98  NES_IDX_RX_WINDOW_BUFFER_SIZE = 0x0300,
99  NES_IDX_DST_IP_ADDR = 0x0400,
100  NES_IDX_PCIX_DIAG = 0x08e8,
101  NES_IDX_MPP_DEBUG = 0x0a00,
102  NES_IDX_PORT_RX_DISCARDS = 0x0a30,
103  NES_IDX_PORT_TX_DISCARDS = 0x0a34,
104  NES_IDX_MPP_LB_DEBUG = 0x0b00,
105  NES_IDX_DENALI_CTL_22 = 0x1058,
106  NES_IDX_MAC_TX_CONTROL = 0x2000,
107  NES_IDX_MAC_TX_CONFIG = 0x2004,
108  NES_IDX_MAC_TX_PAUSE_QUANTA = 0x2008,
109  NES_IDX_MAC_RX_CONTROL = 0x200c,
110  NES_IDX_MAC_RX_CONFIG = 0x2010,
111  NES_IDX_MAC_EXACT_MATCH_BOTTOM = 0x201c,
112  NES_IDX_MAC_MDIO_CONTROL = 0x2084,
113  NES_IDX_MAC_TX_OCTETS_LOW = 0x2100,
114  NES_IDX_MAC_TX_OCTETS_HIGH = 0x2104,
115  NES_IDX_MAC_TX_FRAMES_LOW = 0x2108,
116  NES_IDX_MAC_TX_FRAMES_HIGH = 0x210c,
117  NES_IDX_MAC_TX_PAUSE_FRAMES = 0x2118,
118  NES_IDX_MAC_TX_ERRORS = 0x2138,
119  NES_IDX_MAC_RX_OCTETS_LOW = 0x213c,
120  NES_IDX_MAC_RX_OCTETS_HIGH = 0x2140,
121  NES_IDX_MAC_RX_FRAMES_LOW = 0x2144,
122  NES_IDX_MAC_RX_FRAMES_HIGH = 0x2148,
123  NES_IDX_MAC_RX_BC_FRAMES_LOW = 0x214c,
124  NES_IDX_MAC_RX_MC_FRAMES_HIGH = 0x2150,
125  NES_IDX_MAC_RX_PAUSE_FRAMES = 0x2154,
126  NES_IDX_MAC_RX_SHORT_FRAMES = 0x2174,
127  NES_IDX_MAC_RX_OVERSIZED_FRAMES = 0x2178,
128  NES_IDX_MAC_RX_JABBER_FRAMES = 0x217c,
129  NES_IDX_MAC_RX_CRC_ERR_FRAMES = 0x2180,
130  NES_IDX_MAC_RX_LENGTH_ERR_FRAMES = 0x2184,
131  NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES = 0x2188,
132  NES_IDX_MAC_INT_STATUS = 0x21f0,
133  NES_IDX_MAC_INT_MASK = 0x21f4,
134  NES_IDX_PHY_PCS_CONTROL_STATUS0 = 0x2800,
135  NES_IDX_PHY_PCS_CONTROL_STATUS1 = 0x2a00,
136  NES_IDX_ETH_SERDES_COMMON_CONTROL0 = 0x2808,
137  NES_IDX_ETH_SERDES_COMMON_CONTROL1 = 0x2a08,
138  NES_IDX_ETH_SERDES_COMMON_STATUS0 = 0x280c,
139  NES_IDX_ETH_SERDES_COMMON_STATUS1 = 0x2a0c,
140  NES_IDX_ETH_SERDES_TX_EMP0 = 0x2810,
141  NES_IDX_ETH_SERDES_TX_EMP1 = 0x2a10,
142  NES_IDX_ETH_SERDES_TX_DRIVE0 = 0x2814,
143  NES_IDX_ETH_SERDES_TX_DRIVE1 = 0x2a14,
144  NES_IDX_ETH_SERDES_RX_MODE0 = 0x2818,
145  NES_IDX_ETH_SERDES_RX_MODE1 = 0x2a18,
146  NES_IDX_ETH_SERDES_RX_SIGDET0 = 0x281c,
147  NES_IDX_ETH_SERDES_RX_SIGDET1 = 0x2a1c,
148  NES_IDX_ETH_SERDES_BYPASS0 = 0x2820,
149  NES_IDX_ETH_SERDES_BYPASS1 = 0x2a20,
150  NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0 = 0x2824,
151  NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1 = 0x2a24,
152  NES_IDX_ETH_SERDES_RX_EQ_CONTROL0 = 0x2828,
153  NES_IDX_ETH_SERDES_RX_EQ_CONTROL1 = 0x2a28,
154  NES_IDX_ETH_SERDES_RX_EQ_STATUS0 = 0x282c,
155  NES_IDX_ETH_SERDES_RX_EQ_STATUS1 = 0x2a2c,
156  NES_IDX_ETH_SERDES_CDR_RESET0 = 0x2830,
157  NES_IDX_ETH_SERDES_CDR_RESET1 = 0x2a30,
158  NES_IDX_ETH_SERDES_CDR_CONTROL0 = 0x2834,
159  NES_IDX_ETH_SERDES_CDR_CONTROL1 = 0x2a34,
160  NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0 = 0x2838,
161  NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1 = 0x2a38,
162  NES_IDX_ENDNODE0_NSTAT_RX_DISCARD = 0x3080,
163  NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO = 0x3000,
164  NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI = 0x3004,
165  NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO = 0x3008,
166  NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI = 0x300c,
167  NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO = 0x7000,
168  NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004,
169  NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008,
170  NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c,
171  NES_IDX_WQM_CONFIG0 = 0x5000,
172  NES_IDX_WQM_CONFIG1 = 0x5004,
173  NES_IDX_CM_CONFIG = 0x5100,
174  NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000,
175  NES_IDX_NIC_PHYPORT_TO_USW = 0x6008,
176  NES_IDX_NIC_ACTIVE = 0x6010,
177  NES_IDX_NIC_UNICAST_ALL = 0x6018,
178  NES_IDX_NIC_MULTICAST_ALL = 0x6020,
179  NES_IDX_NIC_MULTICAST_ENABLE = 0x6028,
180  NES_IDX_NIC_BROADCAST_ON = 0x6030,
181  NES_IDX_USED_CHUNKS_TX = 0x60b0,
182  NES_IDX_TX_POOL_SIZE = 0x60b8,
183  NES_IDX_QUAD_HASH_TABLE_SIZE = 0x6148,
184  NES_IDX_PERFECT_FILTER_LOW = 0x6200,
185  NES_IDX_PERFECT_FILTER_HIGH = 0x6204,
186  NES_IDX_IPV4_TCP_REXMITS = 0x7080,
187  NES_IDX_DEBUG_ERROR_CONTROL_STATUS = 0x913c,
188  NES_IDX_DEBUG_ERROR_MASKS0 = 0x9140,
189  NES_IDX_DEBUG_ERROR_MASKS1 = 0x9144,
190  NES_IDX_DEBUG_ERROR_MASKS2 = 0x9148,
191  NES_IDX_DEBUG_ERROR_MASKS3 = 0x914c,
192  NES_IDX_DEBUG_ERROR_MASKS4 = 0x9150,
193  NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154,
194 };
195 
196 #define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE 1
197 #define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17)
198 
199 enum nes_cqp_opcodes {
200  NES_CQP_CREATE_QP = 0x00,
201  NES_CQP_MODIFY_QP = 0x01,
202  NES_CQP_DESTROY_QP = 0x02,
203  NES_CQP_CREATE_CQ = 0x03,
204  NES_CQP_MODIFY_CQ = 0x04,
205  NES_CQP_DESTROY_CQ = 0x05,
206  NES_CQP_ALLOCATE_STAG = 0x09,
207  NES_CQP_REGISTER_STAG = 0x0a,
208  NES_CQP_QUERY_STAG = 0x0b,
209  NES_CQP_REGISTER_SHARED_STAG = 0x0c,
210  NES_CQP_DEALLOCATE_STAG = 0x0d,
211  NES_CQP_MANAGE_ARP_CACHE = 0x0f,
212  NES_CQP_DOWNLOAD_SEGMENT = 0x10,
213  NES_CQP_SUSPEND_QPS = 0x11,
214  NES_CQP_UPLOAD_CONTEXT = 0x13,
215  NES_CQP_CREATE_CEQ = 0x16,
216  NES_CQP_DESTROY_CEQ = 0x18,
217  NES_CQP_CREATE_AEQ = 0x19,
218  NES_CQP_DESTROY_AEQ = 0x1b,
219  NES_CQP_LMI_ACCESS = 0x20,
220  NES_CQP_FLUSH_WQES = 0x22,
221  NES_CQP_MANAGE_APBVT = 0x23,
222  NES_CQP_MANAGE_QUAD_HASH = 0x25
223 };
224 
225 enum nes_cqp_wqe_word_idx {
226  NES_CQP_WQE_OPCODE_IDX = 0,
227  NES_CQP_WQE_ID_IDX = 1,
228  NES_CQP_WQE_COMP_CTX_LOW_IDX = 2,
229  NES_CQP_WQE_COMP_CTX_HIGH_IDX = 3,
230  NES_CQP_WQE_COMP_SCRATCH_LOW_IDX = 4,
231  NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX = 5,
232 };
233 
234 enum nes_cqp_wqe_word_download_idx { /* format differs from other cqp ops */
235  NES_CQP_WQE_DL_OPCODE_IDX = 0,
236  NES_CQP_WQE_DL_COMP_CTX_LOW_IDX = 1,
237  NES_CQP_WQE_DL_COMP_CTX_HIGH_IDX = 2,
238  NES_CQP_WQE_DL_LENGTH_0_TOTAL_IDX = 3
239  /* For index values 4-15 use NES_NIC_SQ_WQE_ values */
240 };
241 
242 enum nes_cqp_cq_wqeword_idx {
243  NES_CQP_CQ_WQE_PBL_LOW_IDX = 6,
244  NES_CQP_CQ_WQE_PBL_HIGH_IDX = 7,
245  NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX = 8,
246  NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX = 9,
247  NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX = 10,
248 };
249 
250 enum nes_cqp_stag_wqeword_idx {
251  NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX = 1,
252  NES_CQP_STAG_WQE_LEN_HIGH_PD_IDX = 6,
253  NES_CQP_STAG_WQE_LEN_LOW_IDX = 7,
254  NES_CQP_STAG_WQE_STAG_IDX = 8,
255  NES_CQP_STAG_WQE_VA_LOW_IDX = 10,
256  NES_CQP_STAG_WQE_VA_HIGH_IDX = 11,
257  NES_CQP_STAG_WQE_PA_LOW_IDX = 12,
258  NES_CQP_STAG_WQE_PA_HIGH_IDX = 13,
259  NES_CQP_STAG_WQE_PBL_LEN_IDX = 14
260 };
261 
262 #define NES_CQP_OP_LOGICAL_PORT_SHIFT 26
263 #define NES_CQP_OP_IWARP_STATE_SHIFT 28
264 #define NES_CQP_OP_TERMLEN_SHIFT 28
265 
266 enum nes_cqp_qp_bits {
267  NES_CQP_QP_ARP_VALID = (1<<8),
268  NES_CQP_QP_WINBUF_VALID = (1<<9),
269  NES_CQP_QP_CONTEXT_VALID = (1<<10),
270  NES_CQP_QP_ORD_VALID = (1<<11),
271  NES_CQP_QP_WINBUF_DATAIND_EN = (1<<12),
272  NES_CQP_QP_VIRT_WQS = (1<<13),
273  NES_CQP_QP_DEL_HTE = (1<<14),
274  NES_CQP_QP_CQS_VALID = (1<<15),
275  NES_CQP_QP_TYPE_TSA = 0,
276  NES_CQP_QP_TYPE_IWARP = (1<<16),
277  NES_CQP_QP_TYPE_CQP = (4<<16),
278  NES_CQP_QP_TYPE_NIC = (5<<16),
279  NES_CQP_QP_MSS_CHG = (1<<20),
280  NES_CQP_QP_STATIC_RESOURCES = (1<<21),
281  NES_CQP_QP_IGNORE_MW_BOUND = (1<<22),
282  NES_CQP_QP_VWQ_USE_LMI = (1<<23),
283  NES_CQP_QP_IWARP_STATE_IDLE = (1<<NES_CQP_OP_IWARP_STATE_SHIFT),
284  NES_CQP_QP_IWARP_STATE_RTS = (2<<NES_CQP_OP_IWARP_STATE_SHIFT),
285  NES_CQP_QP_IWARP_STATE_CLOSING = (3<<NES_CQP_OP_IWARP_STATE_SHIFT),
286  NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT),
287  NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT),
288  NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT),
289  NES_CQP_QP_TERM_DONT_SEND_FIN = (1<<24),
290  NES_CQP_QP_TERM_DONT_SEND_TERM_MSG = (1<<25),
291  NES_CQP_QP_RESET = (1<<31),
292 };
293 
294 enum nes_cqp_qp_wqe_word_idx {
295  NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6,
296  NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7,
297  NES_CQP_QP_WQE_FLUSH_SQ_CODE = 8,
298  NES_CQP_QP_WQE_FLUSH_RQ_CODE = 9,
299  NES_CQP_QP_WQE_NEW_MSS_IDX = 15,
300 };
301 
302 enum nes_nic_ctx_bits {
303  NES_NIC_CTX_RQ_SIZE_32 = (3<<8),
304  NES_NIC_CTX_RQ_SIZE_512 = (3<<8),
305  NES_NIC_CTX_SQ_SIZE_32 = (1<<10),
306  NES_NIC_CTX_SQ_SIZE_512 = (3<<10),
307 };
308 
309 enum nes_nic_qp_ctx_word_idx {
310  NES_NIC_CTX_MISC_IDX = 0,
311  NES_NIC_CTX_SQ_LOW_IDX = 2,
312  NES_NIC_CTX_SQ_HIGH_IDX = 3,
313  NES_NIC_CTX_RQ_LOW_IDX = 4,
314  NES_NIC_CTX_RQ_HIGH_IDX = 5,
315 };
316 
317 enum nes_cqp_cq_bits {
318  NES_CQP_CQ_CEQE_MASK = (1<<9),
319  NES_CQP_CQ_CEQ_VALID = (1<<10),
320  NES_CQP_CQ_RESIZE = (1<<11),
321  NES_CQP_CQ_CHK_OVERFLOW = (1<<12),
322  NES_CQP_CQ_4KB_CHUNK = (1<<14),
323  NES_CQP_CQ_VIRT = (1<<15),
324 };
325 
326 enum nes_cqp_stag_bits {
327  NES_CQP_STAG_VA_TO = (1<<9),
328  NES_CQP_STAG_DEALLOC_PBLS = (1<<10),
329  NES_CQP_STAG_PBL_BLK_SIZE = (1<<11),
330  NES_CQP_STAG_MR = (1<<13),
331  NES_CQP_STAG_RIGHTS_LOCAL_READ = (1<<16),
332  NES_CQP_STAG_RIGHTS_LOCAL_WRITE = (1<<17),
333  NES_CQP_STAG_RIGHTS_REMOTE_READ = (1<<18),
334  NES_CQP_STAG_RIGHTS_REMOTE_WRITE = (1<<19),
335  NES_CQP_STAG_RIGHTS_WINDOW_BIND = (1<<20),
336  NES_CQP_STAG_REM_ACC_EN = (1<<21),
337  NES_CQP_STAG_LEAVE_PENDING = (1<<31),
338 };
339 
340 enum nes_cqp_ceq_wqeword_idx {
341  NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX = 1,
342  NES_CQP_CEQ_WQE_PBL_LOW_IDX = 6,
343  NES_CQP_CEQ_WQE_PBL_HIGH_IDX = 7,
344 };
345 
346 enum nes_cqp_ceq_bits {
347  NES_CQP_CEQ_4KB_CHUNK = (1<<14),
348  NES_CQP_CEQ_VIRT = (1<<15),
349 };
350 
351 enum nes_cqp_aeq_wqeword_idx {
352  NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX = 1,
353  NES_CQP_AEQ_WQE_PBL_LOW_IDX = 6,
354  NES_CQP_AEQ_WQE_PBL_HIGH_IDX = 7,
355 };
356 
357 enum nes_cqp_aeq_bits {
358  NES_CQP_AEQ_4KB_CHUNK = (1<<14),
359  NES_CQP_AEQ_VIRT = (1<<15),
360 };
361 
362 enum nes_cqp_lmi_wqeword_idx {
363  NES_CQP_LMI_WQE_LMI_OFFSET_IDX = 1,
364  NES_CQP_LMI_WQE_FRAG_LOW_IDX = 8,
365  NES_CQP_LMI_WQE_FRAG_HIGH_IDX = 9,
366  NES_CQP_LMI_WQE_FRAG_LEN_IDX = 10,
367 };
368 
369 enum nes_cqp_arp_wqeword_idx {
370  NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX = 6,
371  NES_CQP_ARP_WQE_MAC_HIGH_IDX = 7,
372  NES_CQP_ARP_WQE_REACHABILITY_MAX_IDX = 1,
373 };
374 
375 enum nes_cqp_upload_wqeword_idx {
376  NES_CQP_UPLOAD_WQE_CTXT_LOW_IDX = 6,
377  NES_CQP_UPLOAD_WQE_CTXT_HIGH_IDX = 7,
378  NES_CQP_UPLOAD_WQE_HTE_IDX = 8,
379 };
380 
381 enum nes_cqp_arp_bits {
382  NES_CQP_ARP_VALID = (1<<8),
383  NES_CQP_ARP_PERM = (1<<9),
384 };
385 
386 enum nes_cqp_flush_bits {
387  NES_CQP_FLUSH_SQ = (1<<30),
388  NES_CQP_FLUSH_RQ = (1<<31),
389  NES_CQP_FLUSH_MAJ_MIN = (1<<28),
390 };
391 
392 enum nes_cqe_opcode_bits {
393  NES_CQE_STAG_VALID = (1<<6),
394  NES_CQE_ERROR = (1<<7),
395  NES_CQE_SQ = (1<<8),
396  NES_CQE_SE = (1<<9),
397  NES_CQE_PSH = (1<<29),
398  NES_CQE_FIN = (1<<30),
399  NES_CQE_VALID = (1<<31),
400 };
401 
402 
403 enum nes_cqe_word_idx {
404  NES_CQE_PAYLOAD_LENGTH_IDX = 0,
405  NES_CQE_COMP_COMP_CTX_LOW_IDX = 2,
406  NES_CQE_COMP_COMP_CTX_HIGH_IDX = 3,
407  NES_CQE_INV_STAG_IDX = 4,
408  NES_CQE_QP_ID_IDX = 5,
409  NES_CQE_ERROR_CODE_IDX = 6,
410  NES_CQE_OPCODE_IDX = 7,
411 };
412 
413 enum nes_ceqe_word_idx {
414  NES_CEQE_CQ_CTX_LOW_IDX = 0,
415  NES_CEQE_CQ_CTX_HIGH_IDX = 1,
416 };
417 
418 enum nes_ceqe_status_bit {
419  NES_CEQE_VALID = (1<<31),
420 };
421 
422 enum nes_int_bits {
423  NES_INT_CEQ0 = (1<<0),
424  NES_INT_CEQ1 = (1<<1),
425  NES_INT_CEQ2 = (1<<2),
426  NES_INT_CEQ3 = (1<<3),
427  NES_INT_CEQ4 = (1<<4),
428  NES_INT_CEQ5 = (1<<5),
429  NES_INT_CEQ6 = (1<<6),
430  NES_INT_CEQ7 = (1<<7),
431  NES_INT_CEQ8 = (1<<8),
432  NES_INT_CEQ9 = (1<<9),
433  NES_INT_CEQ10 = (1<<10),
434  NES_INT_CEQ11 = (1<<11),
435  NES_INT_CEQ12 = (1<<12),
436  NES_INT_CEQ13 = (1<<13),
437  NES_INT_CEQ14 = (1<<14),
438  NES_INT_CEQ15 = (1<<15),
439  NES_INT_AEQ0 = (1<<16),
440  NES_INT_AEQ1 = (1<<17),
441  NES_INT_AEQ2 = (1<<18),
442  NES_INT_AEQ3 = (1<<19),
443  NES_INT_AEQ4 = (1<<20),
444  NES_INT_AEQ5 = (1<<21),
445  NES_INT_AEQ6 = (1<<22),
446  NES_INT_AEQ7 = (1<<23),
447  NES_INT_MAC0 = (1<<24),
448  NES_INT_MAC1 = (1<<25),
449  NES_INT_MAC2 = (1<<26),
450  NES_INT_MAC3 = (1<<27),
451  NES_INT_TSW = (1<<28),
452  NES_INT_TIMER = (1<<29),
453  NES_INT_INTF = (1<<30),
454 };
455 
456 enum nes_intf_int_bits {
457  NES_INTF_INT_PCIERR = (1<<0),
458  NES_INTF_PERIODIC_TIMER = (1<<2),
459  NES_INTF_ONE_SHOT_TIMER = (1<<3),
460  NES_INTF_INT_CRITERR = (1<<14),
461  NES_INTF_INT_AEQ0_OFLOW = (1<<16),
462  NES_INTF_INT_AEQ1_OFLOW = (1<<17),
463  NES_INTF_INT_AEQ2_OFLOW = (1<<18),
464  NES_INTF_INT_AEQ3_OFLOW = (1<<19),
465  NES_INTF_INT_AEQ4_OFLOW = (1<<20),
466  NES_INTF_INT_AEQ5_OFLOW = (1<<21),
467  NES_INTF_INT_AEQ6_OFLOW = (1<<22),
468  NES_INTF_INT_AEQ7_OFLOW = (1<<23),
469  NES_INTF_INT_AEQ_OFLOW = (0xff<<16),
470 };
471 
472 enum nes_mac_int_bits {
473  NES_MAC_INT_LINK_STAT_CHG = (1<<1),
474  NES_MAC_INT_XGMII_EXT = (1<<2),
475  NES_MAC_INT_TX_UNDERFLOW = (1<<6),
476  NES_MAC_INT_TX_ERROR = (1<<7),
477 };
478 
479 enum nes_cqe_allocate_bits {
480  NES_CQE_ALLOC_INC_SELECT = (1<<28),
481  NES_CQE_ALLOC_NOTIFY_NEXT = (1<<29),
482  NES_CQE_ALLOC_NOTIFY_SE = (1<<30),
483  NES_CQE_ALLOC_RESET = (1<<31),
484 };
485 
486 enum nes_nic_rq_wqe_word_idx {
487  NES_NIC_RQ_WQE_LENGTH_1_0_IDX = 0,
488  NES_NIC_RQ_WQE_LENGTH_3_2_IDX = 1,
489  NES_NIC_RQ_WQE_FRAG0_LOW_IDX = 2,
490  NES_NIC_RQ_WQE_FRAG0_HIGH_IDX = 3,
491  NES_NIC_RQ_WQE_FRAG1_LOW_IDX = 4,
492  NES_NIC_RQ_WQE_FRAG1_HIGH_IDX = 5,
493  NES_NIC_RQ_WQE_FRAG2_LOW_IDX = 6,
494  NES_NIC_RQ_WQE_FRAG2_HIGH_IDX = 7,
495  NES_NIC_RQ_WQE_FRAG3_LOW_IDX = 8,
496  NES_NIC_RQ_WQE_FRAG3_HIGH_IDX = 9,
497 };
498 
499 enum nes_nic_sq_wqe_word_idx {
500  NES_NIC_SQ_WQE_MISC_IDX = 0,
501  NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX = 1,
502  NES_NIC_SQ_WQE_LSO_INFO_IDX = 2,
503  NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX = 3,
504  NES_NIC_SQ_WQE_LENGTH_2_1_IDX = 4,
505  NES_NIC_SQ_WQE_LENGTH_4_3_IDX = 5,
506  NES_NIC_SQ_WQE_FRAG0_LOW_IDX = 6,
507  NES_NIC_SQ_WQE_FRAG0_HIGH_IDX = 7,
508  NES_NIC_SQ_WQE_FRAG1_LOW_IDX = 8,
509  NES_NIC_SQ_WQE_FRAG1_HIGH_IDX = 9,
510  NES_NIC_SQ_WQE_FRAG2_LOW_IDX = 10,
511  NES_NIC_SQ_WQE_FRAG2_HIGH_IDX = 11,
512  NES_NIC_SQ_WQE_FRAG3_LOW_IDX = 12,
513  NES_NIC_SQ_WQE_FRAG3_HIGH_IDX = 13,
514  NES_NIC_SQ_WQE_FRAG4_LOW_IDX = 14,
515  NES_NIC_SQ_WQE_FRAG4_HIGH_IDX = 15,
516 };
517 
518 enum nes_iwarp_sq_wqe_word_idx {
519  NES_IWARP_SQ_WQE_MISC_IDX = 0,
520  NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX = 1,
521  NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX = 2,
522  NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX = 3,
523  NES_IWARP_SQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
524  NES_IWARP_SQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
525  NES_IWARP_SQ_WQE_INV_STAG_LOW_IDX = 7,
526  NES_IWARP_SQ_WQE_RDMA_TO_LOW_IDX = 8,
527  NES_IWARP_SQ_WQE_RDMA_TO_HIGH_IDX = 9,
528  NES_IWARP_SQ_WQE_RDMA_LENGTH_IDX = 10,
529  NES_IWARP_SQ_WQE_RDMA_STAG_IDX = 11,
530  NES_IWARP_SQ_WQE_IMM_DATA_START_IDX = 12,
531  NES_IWARP_SQ_WQE_FRAG0_LOW_IDX = 16,
532  NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX = 17,
533  NES_IWARP_SQ_WQE_LENGTH0_IDX = 18,
534  NES_IWARP_SQ_WQE_STAG0_IDX = 19,
535  NES_IWARP_SQ_WQE_FRAG1_LOW_IDX = 20,
536  NES_IWARP_SQ_WQE_FRAG1_HIGH_IDX = 21,
537  NES_IWARP_SQ_WQE_LENGTH1_IDX = 22,
538  NES_IWARP_SQ_WQE_STAG1_IDX = 23,
539  NES_IWARP_SQ_WQE_FRAG2_LOW_IDX = 24,
540  NES_IWARP_SQ_WQE_FRAG2_HIGH_IDX = 25,
541  NES_IWARP_SQ_WQE_LENGTH2_IDX = 26,
542  NES_IWARP_SQ_WQE_STAG2_IDX = 27,
543  NES_IWARP_SQ_WQE_FRAG3_LOW_IDX = 28,
544  NES_IWARP_SQ_WQE_FRAG3_HIGH_IDX = 29,
545  NES_IWARP_SQ_WQE_LENGTH3_IDX = 30,
546  NES_IWARP_SQ_WQE_STAG3_IDX = 31,
547 };
548 
549 enum nes_iwarp_sq_bind_wqe_word_idx {
550  NES_IWARP_SQ_BIND_WQE_MR_IDX = 6,
551  NES_IWARP_SQ_BIND_WQE_MW_IDX = 7,
552  NES_IWARP_SQ_BIND_WQE_LENGTH_LOW_IDX = 8,
553  NES_IWARP_SQ_BIND_WQE_LENGTH_HIGH_IDX = 9,
554  NES_IWARP_SQ_BIND_WQE_VA_FBO_LOW_IDX = 10,
555  NES_IWARP_SQ_BIND_WQE_VA_FBO_HIGH_IDX = 11,
556 };
557 
558 enum nes_iwarp_sq_fmr_wqe_word_idx {
559  NES_IWARP_SQ_FMR_WQE_MR_STAG_IDX = 7,
560  NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX = 8,
561  NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX = 9,
562  NES_IWARP_SQ_FMR_WQE_VA_FBO_LOW_IDX = 10,
563  NES_IWARP_SQ_FMR_WQE_VA_FBO_HIGH_IDX = 11,
564  NES_IWARP_SQ_FMR_WQE_PBL_ADDR_LOW_IDX = 12,
565  NES_IWARP_SQ_FMR_WQE_PBL_ADDR_HIGH_IDX = 13,
566  NES_IWARP_SQ_FMR_WQE_PBL_LENGTH_IDX = 14,
567 };
568 
569 enum nes_iwarp_sq_fmr_opcodes {
570  NES_IWARP_SQ_FMR_WQE_ZERO_BASED = (1<<6),
571  NES_IWARP_SQ_FMR_WQE_PAGE_SIZE_4K = (0<<7),
572  NES_IWARP_SQ_FMR_WQE_PAGE_SIZE_2M = (1<<7),
573  NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_LOCAL_READ = (1<<16),
574  NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_LOCAL_WRITE = (1<<17),
575  NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_REMOTE_READ = (1<<18),
576  NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_REMOTE_WRITE = (1<<19),
577  NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_WINDOW_BIND = (1<<20),
578 };
579 
580 #define NES_IWARP_SQ_FMR_WQE_MR_LENGTH_HIGH_MASK 0xFF;
581 
582 enum nes_iwarp_sq_locinv_wqe_word_idx {
583  NES_IWARP_SQ_LOCINV_WQE_INV_STAG_IDX = 6,
584 };
585 
586 enum nes_iwarp_rq_wqe_word_idx {
587  NES_IWARP_RQ_WQE_TOTAL_PAYLOAD_IDX = 1,
588  NES_IWARP_RQ_WQE_COMP_CTX_LOW_IDX = 2,
589  NES_IWARP_RQ_WQE_COMP_CTX_HIGH_IDX = 3,
590  NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
591  NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
592  NES_IWARP_RQ_WQE_FRAG0_LOW_IDX = 8,
593  NES_IWARP_RQ_WQE_FRAG0_HIGH_IDX = 9,
594  NES_IWARP_RQ_WQE_LENGTH0_IDX = 10,
595  NES_IWARP_RQ_WQE_STAG0_IDX = 11,
596  NES_IWARP_RQ_WQE_FRAG1_LOW_IDX = 12,
597  NES_IWARP_RQ_WQE_FRAG1_HIGH_IDX = 13,
598  NES_IWARP_RQ_WQE_LENGTH1_IDX = 14,
599  NES_IWARP_RQ_WQE_STAG1_IDX = 15,
600  NES_IWARP_RQ_WQE_FRAG2_LOW_IDX = 16,
601  NES_IWARP_RQ_WQE_FRAG2_HIGH_IDX = 17,
602  NES_IWARP_RQ_WQE_LENGTH2_IDX = 18,
603  NES_IWARP_RQ_WQE_STAG2_IDX = 19,
604  NES_IWARP_RQ_WQE_FRAG3_LOW_IDX = 20,
605  NES_IWARP_RQ_WQE_FRAG3_HIGH_IDX = 21,
606  NES_IWARP_RQ_WQE_LENGTH3_IDX = 22,
607  NES_IWARP_RQ_WQE_STAG3_IDX = 23,
608 };
609 
610 enum nes_nic_sq_wqe_bits {
611  NES_NIC_SQ_WQE_PHDR_CS_READY = (1<<21),
612  NES_NIC_SQ_WQE_LSO_ENABLE = (1<<22),
613  NES_NIC_SQ_WQE_TAGVALUE_ENABLE = (1<<23),
614  NES_NIC_SQ_WQE_DISABLE_CHKSUM = (1<<30),
615  NES_NIC_SQ_WQE_COMPLETION = (1<<31),
616 };
617 
618 enum nes_nic_cqe_word_idx {
619  NES_NIC_CQE_ACCQP_ID_IDX = 0,
620  NES_NIC_CQE_HASH_RCVNXT = 1,
621  NES_NIC_CQE_TAG_PKT_TYPE_IDX = 2,
622  NES_NIC_CQE_MISC_IDX = 3,
623 };
624 
625 #define NES_PKT_TYPE_APBVT_BITS 0xC112
626 #define NES_PKT_TYPE_APBVT_MASK 0xff3e
627 
628 #define NES_PKT_TYPE_PVALID_BITS 0x10000000
629 #define NES_PKT_TYPE_PVALID_MASK 0x30000000
630 
631 #define NES_PKT_TYPE_TCPV4_BITS 0x0110
632 #define NES_PKT_TYPE_TCPV4_MASK 0x3f30
633 
634 #define NES_PKT_TYPE_UDPV4_BITS 0x0210
635 #define NES_PKT_TYPE_UDPV4_MASK 0x3f30
636 
637 #define NES_PKT_TYPE_IPV4_BITS 0x0010
638 #define NES_PKT_TYPE_IPV4_MASK 0x3f30
639 
640 #define NES_PKT_TYPE_OTHER_BITS 0x0000
641 #define NES_PKT_TYPE_OTHER_MASK 0x0030
642 
643 #define NES_NIC_CQE_ERRV_SHIFT 16
644 enum nes_nic_ev_bits {
645  NES_NIC_ERRV_BITS_MODE = (1<<0),
646  NES_NIC_ERRV_BITS_IPV4_CSUM_ERR = (1<<1),
647  NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR = (1<<2),
648  NES_NIC_ERRV_BITS_WQE_OVERRUN = (1<<3),
649  NES_NIC_ERRV_BITS_IPH_ERR = (1<<4),
650 };
651 
652 enum nes_nic_cqe_bits {
653  NES_NIC_CQE_ERRV_MASK = (0xff<<NES_NIC_CQE_ERRV_SHIFT),
654  NES_NIC_CQE_SQ = (1<<24),
655  NES_NIC_CQE_ACCQP_PORT = (1<<28),
656  NES_NIC_CQE_ACCQP_VALID = (1<<29),
657  NES_NIC_CQE_TAG_VALID = (1<<30),
658  NES_NIC_CQE_VALID = (1<<31),
659 };
660 
661 enum nes_aeqe_word_idx {
662  NES_AEQE_COMP_CTXT_LOW_IDX = 0,
663  NES_AEQE_COMP_CTXT_HIGH_IDX = 1,
664  NES_AEQE_COMP_QP_CQ_ID_IDX = 2,
665  NES_AEQE_MISC_IDX = 3,
666 };
667 
668 enum nes_aeqe_bits {
669  NES_AEQE_QP = (1<<16),
670  NES_AEQE_CQ = (1<<17),
671  NES_AEQE_SQ = (1<<18),
672  NES_AEQE_INBOUND_RDMA = (1<<19),
673  NES_AEQE_IWARP_STATE_MASK = (7<<20),
674  NES_AEQE_TCP_STATE_MASK = (0xf<<24),
675  NES_AEQE_Q2_DATA_WRITTEN = (0x3<<28),
676  NES_AEQE_VALID = (1<<31),
677 };
678 
679 #define NES_AEQE_IWARP_STATE_SHIFT 20
680 #define NES_AEQE_TCP_STATE_SHIFT 24
681 #define NES_AEQE_Q2_DATA_ETHERNET (1<<28)
682 #define NES_AEQE_Q2_DATA_MPA (1<<29)
683 
684 enum nes_aeqe_iwarp_state {
685  NES_AEQE_IWARP_STATE_NON_EXISTANT = 0,
686  NES_AEQE_IWARP_STATE_IDLE = 1,
687  NES_AEQE_IWARP_STATE_RTS = 2,
688  NES_AEQE_IWARP_STATE_CLOSING = 3,
689  NES_AEQE_IWARP_STATE_TERMINATE = 5,
690  NES_AEQE_IWARP_STATE_ERROR = 6
691 };
692 
693 enum nes_aeqe_tcp_state {
694  NES_AEQE_TCP_STATE_NON_EXISTANT = 0,
695  NES_AEQE_TCP_STATE_CLOSED = 1,
696  NES_AEQE_TCP_STATE_LISTEN = 2,
697  NES_AEQE_TCP_STATE_SYN_SENT = 3,
698  NES_AEQE_TCP_STATE_SYN_RCVD = 4,
699  NES_AEQE_TCP_STATE_ESTABLISHED = 5,
700  NES_AEQE_TCP_STATE_CLOSE_WAIT = 6,
701  NES_AEQE_TCP_STATE_FIN_WAIT_1 = 7,
702  NES_AEQE_TCP_STATE_CLOSING = 8,
703  NES_AEQE_TCP_STATE_LAST_ACK = 9,
704  NES_AEQE_TCP_STATE_FIN_WAIT_2 = 10,
705  NES_AEQE_TCP_STATE_TIME_WAIT = 11
706 };
707 
708 enum nes_aeqe_aeid {
709  NES_AEQE_AEID_AMP_UNALLOCATED_STAG = 0x0102,
710  NES_AEQE_AEID_AMP_INVALID_STAG = 0x0103,
711  NES_AEQE_AEID_AMP_BAD_QP = 0x0104,
712  NES_AEQE_AEID_AMP_BAD_PD = 0x0105,
713  NES_AEQE_AEID_AMP_BAD_STAG_KEY = 0x0106,
714  NES_AEQE_AEID_AMP_BAD_STAG_INDEX = 0x0107,
715  NES_AEQE_AEID_AMP_BOUNDS_VIOLATION = 0x0108,
716  NES_AEQE_AEID_AMP_RIGHTS_VIOLATION = 0x0109,
717  NES_AEQE_AEID_AMP_TO_WRAP = 0x010a,
718  NES_AEQE_AEID_AMP_FASTREG_SHARED = 0x010b,
719  NES_AEQE_AEID_AMP_FASTREG_VALID_STAG = 0x010c,
720  NES_AEQE_AEID_AMP_FASTREG_MW_STAG = 0x010d,
721  NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS = 0x010e,
722  NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW = 0x010f,
723  NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH = 0x0110,
724  NES_AEQE_AEID_AMP_INVALIDATE_SHARED = 0x0111,
725  NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS = 0x0112,
726  NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS = 0x0113,
727  NES_AEQE_AEID_AMP_MWBIND_VALID_STAG = 0x0114,
728  NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG = 0x0115,
729  NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG = 0x0116,
730  NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG = 0x0117,
731  NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS = 0x0118,
732  NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS = 0x0119,
733  NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT = 0x011a,
734  NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED = 0x011b,
735  NES_AEQE_AEID_BAD_CLOSE = 0x0201,
736  NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE = 0x0202,
737  NES_AEQE_AEID_CQ_OPERATION_ERROR = 0x0203,
738  NES_AEQE_AEID_PRIV_OPERATION_DENIED = 0x0204,
739  NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO = 0x0205,
740  NES_AEQE_AEID_STAG_ZERO_INVALID = 0x0206,
741  NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN = 0x0301,
742  NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID = 0x0302,
743  NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER = 0x0303,
744  NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION = 0x0304,
745  NES_AEQE_AEID_DDP_UBE_INVALID_MO = 0x0305,
746  NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE = 0x0306,
747  NES_AEQE_AEID_DDP_UBE_INVALID_QN = 0x0307,
748  NES_AEQE_AEID_DDP_NO_L_BIT = 0x0308,
749  NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION = 0x0311,
750  NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE = 0x0312,
751  NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST = 0x0313,
752  NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP = 0x0314,
753  NES_AEQE_AEID_INVALID_ARP_ENTRY = 0x0401,
754  NES_AEQE_AEID_INVALID_TCP_OPTION_RCVD = 0x0402,
755  NES_AEQE_AEID_STALE_ARP_ENTRY = 0x0403,
756  NES_AEQE_AEID_LLP_CLOSE_COMPLETE = 0x0501,
757  NES_AEQE_AEID_LLP_CONNECTION_RESET = 0x0502,
758  NES_AEQE_AEID_LLP_FIN_RECEIVED = 0x0503,
759  NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH = 0x0504,
760  NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR = 0x0505,
761  NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE = 0x0506,
762  NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL = 0x0507,
763  NES_AEQE_AEID_LLP_SYN_RECEIVED = 0x0508,
764  NES_AEQE_AEID_LLP_TERMINATE_RECEIVED = 0x0509,
765  NES_AEQE_AEID_LLP_TOO_MANY_RETRIES = 0x050a,
766  NES_AEQE_AEID_LLP_TOO_MANY_KEEPALIVE_RETRIES = 0x050b,
767  NES_AEQE_AEID_RESET_SENT = 0x0601,
768  NES_AEQE_AEID_TERMINATE_SENT = 0x0602,
769  NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC = 0x0700
770 };
771 
772 enum nes_iwarp_sq_opcodes {
773  NES_IWARP_SQ_WQE_WRPDU = (1<<15),
774  NES_IWARP_SQ_WQE_PSH = (1<<21),
775  NES_IWARP_SQ_WQE_STREAMING = (1<<23),
776  NES_IWARP_SQ_WQE_IMM_DATA = (1<<28),
777  NES_IWARP_SQ_WQE_READ_FENCE = (1<<29),
778  NES_IWARP_SQ_WQE_LOCAL_FENCE = (1<<30),
779  NES_IWARP_SQ_WQE_SIGNALED_COMPL = (1<<31),
780 };
781 
782 enum nes_iwarp_sq_wqe_bits {
783  NES_IWARP_SQ_OP_RDMAW = 0,
784  NES_IWARP_SQ_OP_RDMAR = 1,
785  NES_IWARP_SQ_OP_SEND = 3,
786  NES_IWARP_SQ_OP_SENDINV = 4,
787  NES_IWARP_SQ_OP_SENDSE = 5,
788  NES_IWARP_SQ_OP_SENDSEINV = 6,
789  NES_IWARP_SQ_OP_BIND = 8,
790  NES_IWARP_SQ_OP_FAST_REG = 9,
791  NES_IWARP_SQ_OP_LOCINV = 10,
792  NES_IWARP_SQ_OP_RDMAR_LOCINV = 11,
793  NES_IWARP_SQ_OP_NOP = 12,
794 };
795 
796 enum nes_iwarp_cqe_major_code {
797  NES_IWARP_CQE_MAJOR_FLUSH = 1,
798  NES_IWARP_CQE_MAJOR_DRV = 0x8000
799 };
800 
801 enum nes_iwarp_cqe_minor_code {
802  NES_IWARP_CQE_MINOR_FLUSH = 1
803 };
804 
805 #define NES_EEPROM_READ_REQUEST (1<<16)
806 #define NES_MAC_ADDR_VALID (1<<20)
807 
808 /*
809  * NES index registers init values.
810  */
811 struct nes_init_values {
812  u32 index;
813  u32 data;
814  u8 wrt;
815 };
816 
817 /*
818  * NES registers in BAR0.
819  */
820 struct nes_pci_regs {
821  u32 int_status;
822  u32 int_mask;
823  u32 int_pending;
824  u32 intf_int_status;
825  u32 intf_int_mask;
826  u32 other_regs[59]; /* pad out to 256 bytes for now */
827 };
828 
829 #define NES_CQP_SQ_SIZE 128
830 #define NES_CCQ_SIZE 128
831 #define NES_NIC_WQ_SIZE 512
832 #define NES_NIC_CTX_SIZE ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512))
833 #define NES_NIC_BACK_STORE 0x00038000
834 
835 struct nes_device;
836 
837 struct nes_hw_nic_qp_context {
838  __le32 context_words[6];
839 };
840 
841 struct nes_hw_nic_sq_wqe {
842  __le32 wqe_words[16];
843 };
844 
845 struct nes_hw_nic_rq_wqe {
846  __le32 wqe_words[16];
847 };
848 
849 struct nes_hw_nic_cqe {
850  __le32 cqe_words[4];
851 };
852 
853 struct nes_hw_cqp_qp_context {
854  __le32 context_words[4];
855 };
856 
857 struct nes_hw_cqp_wqe {
858  __le32 wqe_words[16];
859 };
860 
861 struct nes_hw_qp_wqe {
862  __le32 wqe_words[32];
863 };
864 
865 struct nes_hw_cqe {
866  __le32 cqe_words[8];
867 };
868 
869 struct nes_hw_ceqe {
870  __le32 ceqe_words[2];
871 };
872 
873 struct nes_hw_aeqe {
874  __le32 aeqe_words[4];
875 };
876 
877 struct nes_cqp_request {
878  union {
879  u64 cqp_callback_context;
880  void *cqp_callback_pointer;
881  };
882  wait_queue_head_t waitq;
883  struct nes_hw_cqp_wqe cqp_wqe;
884  struct list_head list;
885  atomic_t refcount;
886  void (*cqp_callback)(struct nes_device *nesdev, struct nes_cqp_request *cqp_request);
887  u16 major_code;
888  u16 minor_code;
889  u8 waiting;
890  u8 request_done;
891  u8 dynamic;
892  u8 callback;
893 };
894 
895 struct nes_hw_cqp {
896  struct nes_hw_cqp_wqe *sq_vbase;
897  dma_addr_t sq_pbase;
898  spinlock_t lock;
899  wait_queue_head_t waitq;
900  u16 qp_id;
901  u16 sq_head;
902  u16 sq_tail;
903  u16 sq_size;
904 };
905 
906 #define NES_FIRST_FRAG_SIZE 128
907 struct nes_first_frag {
908  u8 buffer[NES_FIRST_FRAG_SIZE];
909 };
910 
911 struct nes_hw_nic {
912  struct nes_first_frag *first_frag_vbase; /* virtual address of first frags */
913  struct nes_hw_nic_sq_wqe *sq_vbase; /* virtual address of sq */
914  struct nes_hw_nic_rq_wqe *rq_vbase; /* virtual address of rq */
915  struct sk_buff *tx_skb[NES_NIC_WQ_SIZE];
916  struct sk_buff *rx_skb[NES_NIC_WQ_SIZE];
917  dma_addr_t frag_paddr[NES_NIC_WQ_SIZE];
918  unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)];
919  dma_addr_t sq_pbase; /* PCI memory for host rings */
920  dma_addr_t rq_pbase; /* PCI memory for host rings */
921 
922  u16 qp_id;
923  u16 sq_head;
924  u16 sq_tail;
925  u16 sq_size;
926  u16 rq_head;
927  u16 rq_tail;
928  u16 rq_size;
929  u8 replenishing_rq;
930  u8 reserved;
931 
932  spinlock_t rq_lock;
933 };
934 
935 struct nes_hw_nic_cq {
936  struct nes_hw_nic_cqe volatile *cq_vbase; /* PCI memory for host rings */
937  void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
938  dma_addr_t cq_pbase; /* PCI memory for host rings */
939  int rx_cqes_completed;
940  int cqe_allocs_pending;
941  int rx_pkts_indicated;
942  u16 cq_head;
943  u16 cq_size;
944  u16 cq_number;
945  u8 cqes_pending;
946 };
947 
948 struct nes_hw_qp {
949  struct nes_hw_qp_wqe *sq_vbase; /* PCI memory for host rings */
950  struct nes_hw_qp_wqe *rq_vbase; /* PCI memory for host rings */
951  void *q2_vbase; /* PCI memory for host rings */
952  dma_addr_t sq_pbase; /* PCI memory for host rings */
953  dma_addr_t rq_pbase; /* PCI memory for host rings */
954  dma_addr_t q2_pbase; /* PCI memory for host rings */
955  u32 qp_id;
956  u16 sq_head;
957  u16 sq_tail;
958  u16 sq_size;
959  u16 rq_head;
960  u16 rq_tail;
961  u16 rq_size;
962  u8 rq_encoded_size;
963  u8 sq_encoded_size;
964 };
965 
966 struct nes_hw_cq {
967  struct nes_hw_cqe *cq_vbase; /* PCI memory for host rings */
968  void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_cq *cq);
969  dma_addr_t cq_pbase; /* PCI memory for host rings */
970  u16 cq_head;
971  u16 cq_size;
972  u16 cq_number;
973 };
974 
975 struct nes_hw_ceq {
976  struct nes_hw_ceqe volatile *ceq_vbase; /* PCI memory for host rings */
977  dma_addr_t ceq_pbase; /* PCI memory for host rings */
978  u16 ceq_head;
979  u16 ceq_size;
980 };
981 
982 struct nes_hw_aeq {
983  struct nes_hw_aeqe volatile *aeq_vbase; /* PCI memory for host rings */
984  dma_addr_t aeq_pbase; /* PCI memory for host rings */
985  u16 aeq_head;
986  u16 aeq_size;
987 };
988 
989 struct nic_qp_map {
990  u8 qpid;
991  u8 nic_index;
992  u8 logical_port;
993  u8 is_hnic;
994 };
995 
996 #define NES_CQP_ARP_AEQ_INDEX_MASK 0x000f0000
997 #define NES_CQP_ARP_AEQ_INDEX_SHIFT 16
998 
999 #define NES_CQP_APBVT_ADD 0x00008000
1000 #define NES_CQP_APBVT_NIC_SHIFT 16
1001 
1002 #define NES_ARP_ADD 1
1003 #define NES_ARP_DELETE 2
1004 #define NES_ARP_RESOLVE 3
1005 
1006 #define NES_MAC_SW_IDLE 0
1007 #define NES_MAC_SW_INTERRUPT 1
1008 #define NES_MAC_SW_MH 2
1009 
1010 struct nes_arp_entry {
1011  u32 ip_addr;
1012  u8 mac_addr[ETH_ALEN];
1013 };
1014 
1015 #define NES_NIC_FAST_TIMER 96
1016 #define NES_NIC_FAST_TIMER_LOW 40
1017 #define NES_NIC_FAST_TIMER_HIGH 1000
1018 #define DEFAULT_NES_QL_HIGH 256
1019 #define DEFAULT_NES_QL_LOW 16
1020 #define DEFAULT_NES_QL_TARGET 64
1021 #define DEFAULT_JUMBO_NES_QL_LOW 12
1022 #define DEFAULT_JUMBO_NES_QL_TARGET 40
1023 #define DEFAULT_JUMBO_NES_QL_HIGH 128
1024 #define NES_NIC_CQ_DOWNWARD_TREND 16
1025 #define NES_PFT_SIZE 48
1026 
1027 #define NES_MGT_WQ_COUNT 32
1028 #define NES_MGT_CTX_SIZE ((NES_NIC_CTX_RQ_SIZE_32) | (NES_NIC_CTX_SQ_SIZE_32))
1029 #define NES_MGT_QP_OFFSET 36
1030 #define NES_MGT_QP_COUNT 4
1031 
1032 struct nes_hw_tune_timer {
1033  /* u16 cq_count; */
1034  u16 threshold_low;
1035  u16 threshold_target;
1036  u16 threshold_high;
1037  u16 timer_in_use;
1038  u16 timer_in_use_old;
1039  u16 timer_in_use_min;
1040  u16 timer_in_use_max;
1041  u8 timer_direction_upward;
1042  u8 timer_direction_downward;
1043  u16 cq_count_old;
1044  u8 cq_direction_downward;
1045 };
1046 
1047 #define NES_TIMER_INT_LIMIT 2
1048 #define NES_TIMER_INT_LIMIT_DYNAMIC 10
1049 #define NES_TIMER_ENABLE_LIMIT 4
1050 #define NES_MAX_LINK_INTERRUPTS 128
1051 #define NES_MAX_LINK_CHECK 200
1052 #define NES_MAX_LRO_DESCRIPTORS 32
1053 #define NES_LRO_MAX_AGGR 64
1054 
1055 struct nes_adapter {
1056  u64 fw_ver;
1057  unsigned long *allocated_qps;
1058  unsigned long *allocated_cqs;
1059  unsigned long *allocated_mrs;
1060  unsigned long *allocated_pds;
1061  unsigned long *allocated_arps;
1062  struct nes_qp **qp_table;
1063  struct workqueue_struct *work_q;
1064 
1065  struct list_head list;
1066  struct list_head active_listeners;
1067  /* list of the netdev's associated with each logical port */
1068  struct list_head nesvnic_list[4];
1069 
1070  struct timer_list mh_timer;
1071  struct timer_list lc_timer;
1072  struct work_struct work;
1073  spinlock_t resource_lock;
1074  spinlock_t phy_lock;
1075  spinlock_t pbl_lock;
1076  spinlock_t periodic_timer_lock;
1077 
1078  struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE];
1079 
1080  /* Adapter CEQ and AEQs */
1081  struct nes_hw_ceq ceq[16];
1082  struct nes_hw_aeq aeq[8];
1083 
1084  struct nes_hw_tune_timer tune_timer;
1085 
1086  unsigned long doorbell_start;
1087 
1088  u32 hw_rev;
1089  u32 vendor_id;
1090  u32 vendor_part_id;
1091  u32 device_cap_flags;
1092  u32 tick_delta;
1093  u32 timer_int_req;
1094  u32 arp_table_size;
1095  u32 next_arp_index;
1096 
1097  u32 max_mr;
1098  u32 max_256pbl;
1099  u32 max_4kpbl;
1100  u32 free_256pbl;
1101  u32 free_4kpbl;
1102  u32 max_mr_size;
1103  u32 max_qp;
1104  u32 next_qp;
1105  u32 max_irrq;
1106  u32 max_qp_wr;
1107  u32 max_sge;
1108  u32 max_cq;
1109  u32 next_cq;
1110  u32 max_cqe;
1111  u32 max_pd;
1112  u32 base_pd;
1113  u32 next_pd;
1114  u32 hte_index_mask;
1115 
1116  /* EEPROM information */
1117  u32 rx_pool_size;
1118  u32 tx_pool_size;
1119  u32 rx_threshold;
1120  u32 tcp_timer_core_clk_divisor;
1121  u32 iwarp_config;
1122  u32 cm_config;
1123  u32 sws_timer_config;
1124  u32 tcp_config1;
1125  u32 wqm_wat;
1126  u32 core_clock;
1127  u32 firmware_version;
1128  u32 eeprom_version;
1129 
1130  u32 nic_rx_eth_route_err;
1131 
1132  u32 et_rx_coalesce_usecs;
1133  u32 et_rx_max_coalesced_frames;
1134  u32 et_rx_coalesce_usecs_irq;
1135  u32 et_rx_max_coalesced_frames_irq;
1136  u32 et_pkt_rate_low;
1137  u32 et_rx_coalesce_usecs_low;
1138  u32 et_rx_max_coalesced_frames_low;
1139  u32 et_pkt_rate_high;
1140  u32 et_rx_coalesce_usecs_high;
1141  u32 et_rx_max_coalesced_frames_high;
1142  u32 et_rate_sample_interval;
1143  u32 timer_int_limit;
1144  u32 wqm_quanta;
1145  u8 allow_unaligned_fpdus;
1146 
1147  /* Adapter base MAC address */
1148  u32 mac_addr_low;
1149  u16 mac_addr_high;
1150 
1151  u16 firmware_eeprom_offset;
1152  u16 software_eeprom_offset;
1153 
1154  u16 max_irrq_wr;
1155 
1156  /* pd config for each port */
1157  u16 pd_config_size[4];
1158  u16 pd_config_base[4];
1159 
1160  u16 link_interrupt_count[4];
1161  u8 crit_error_count[32];
1162 
1163  /* the phy index for each port */
1164  u8 phy_index[4];
1165  u8 mac_sw_state[4];
1166  u8 mac_link_down[4];
1167  u8 phy_type[4];
1168  u8 log_port;
1169 
1170  /* PCI information */
1171  unsigned int devfn;
1172  unsigned char bus_number;
1173  unsigned char OneG_Mode;
1174 
1175  unsigned char ref_count;
1176  u8 netdev_count;
1177  u8 netdev_max; /* from host nic address count in EEPROM */
1178  u8 port_count;
1179  u8 virtwq;
1180  u8 send_term_ok;
1181  u8 et_use_adaptive_rx_coalesce;
1182  u8 adapter_fcn_count;
1183  u8 pft_mcast_map[NES_PFT_SIZE];
1184 };
1185 
1186 struct nes_pbl {
1187  u64 *pbl_vbase;
1188  dma_addr_t pbl_pbase;
1189  struct page *page;
1190  unsigned long user_base;
1191  u32 pbl_size;
1192  struct list_head list;
1193  /* TODO: need to add list for two level tables */
1194 };
1195 
1196 #define NES_4K_PBL_CHUNK_SIZE 4096
1197 
1198 struct nes_fast_mr_wqe_pbl {
1199  u64 *kva;
1200  dma_addr_t paddr;
1201 };
1202 
1203 struct nes_ib_fast_reg_page_list {
1204  struct ib_fast_reg_page_list ibfrpl;
1205  struct nes_fast_mr_wqe_pbl nes_wqe_pbl;
1206  u64 pbl;
1207 };
1208 
1209 struct nes_listener {
1210  struct work_struct work;
1211  struct workqueue_struct *wq;
1212  struct nes_vnic *nesvnic;
1213  struct iw_cm_id *cm_id;
1214  struct list_head list;
1215  unsigned long socket;
1216  u8 accept_failed;
1217 };
1218 
1219 struct nes_ib_device;
1220 
1221 #define NES_EVENT_DELAY msecs_to_jiffies(100)
1222 
1223 struct nes_vnic {
1224  struct nes_ib_device *nesibdev;
1225  u64 sq_full;
1226  u64 tso_requests;
1227  u64 segmented_tso_requests;
1228  u64 linearized_skbs;
1229  u64 tx_sw_dropped;
1230  u64 endnode_nstat_rx_discard;
1231  u64 endnode_nstat_rx_octets;
1232  u64 endnode_nstat_rx_frames;
1233  u64 endnode_nstat_tx_octets;
1234  u64 endnode_nstat_tx_frames;
1235  u64 endnode_ipv4_tcp_retransmits;
1236  /* void *mem; */
1237  struct nes_device *nesdev;
1238  struct net_device *netdev;
1239  atomic_t rx_skbs_needed;
1240  atomic_t rx_skb_timer_running;
1241  int budget;
1242  u32 msg_enable;
1243  /* u32 tx_avail; */
1244  __be32 local_ipaddr;
1245  struct napi_struct napi;
1246  spinlock_t tx_lock; /* could use netdev tx lock? */
1247  struct timer_list rq_wqes_timer;
1248  u32 nic_mem_size;
1249  void *nic_vbase;
1250  dma_addr_t nic_pbase;
1251  struct nes_hw_nic nic;
1252  struct nes_hw_nic_cq nic_cq;
1253  u32 mcrq_qp_id;
1254  struct nes_ucontext *mcrq_ucontext;
1255  struct nes_cqp_request* (*get_cqp_request)(struct nes_device *nesdev);
1256  void (*post_cqp_request)(struct nes_device*, struct nes_cqp_request *);
1257  int (*mcrq_mcast_filter)( struct nes_vnic* nesvnic, __u8* dmi_addr );
1258  struct net_device_stats netstats;
1259  /* used to put the netdev on the adapters logical port list */
1260  struct list_head list;
1261  u16 max_frame_size;
1262  u8 netdev_open;
1263  u8 linkup;
1264  u8 logical_port;
1265  u8 netdev_index; /* might not be needed, indexes nesdev->netdev */
1266  u8 perfect_filter_index;
1267  u8 nic_index;
1268  u8 qp_nic_index[4];
1269  u8 next_qp_nic_index;
1270  u8 of_device_registered;
1271  u8 rdma_enabled;
1272  u32 lro_max_aggr;
1273  struct net_lro_mgr lro_mgr;
1274  struct net_lro_desc lro_desc[NES_MAX_LRO_DESCRIPTORS];
1275  struct timer_list event_timer;
1276  enum ib_event_type delayed_event;
1277  enum ib_event_type last_dispatched_event;
1278  spinlock_t port_ibevent_lock;
1279  u32 mgt_mem_size;
1280  void *mgt_vbase;
1281  dma_addr_t mgt_pbase;
1282  struct nes_vnic_mgt *mgtvnic[NES_MGT_QP_COUNT];
1283  struct task_struct *mgt_thread;
1284  wait_queue_head_t mgt_wait_queue;
1285  struct sk_buff_head mgt_skb_list;
1286 
1287 };
1288 
1289 struct nes_ib_device {
1290  struct ib_device ibdev;
1291  struct nes_vnic *nesvnic;
1292 
1293  /* Virtual RNIC Limits */
1294  u32 max_mr;
1295  u32 max_qp;
1296  u32 max_cq;
1297  u32 max_pd;
1298  u32 num_mr;
1299  u32 num_qp;
1300  u32 num_cq;
1301  u32 num_pd;
1302 };
1303 
1304 enum nes_hdrct_flags {
1305  DDP_LEN_FLAG = 0x80,
1306  DDP_HDR_FLAG = 0x40,
1307  RDMA_HDR_FLAG = 0x20
1308 };
1309 
1310 enum nes_term_layers {
1311  LAYER_RDMA = 0,
1312  LAYER_DDP = 1,
1313  LAYER_MPA = 2
1314 };
1315 
1316 enum nes_term_error_types {
1317  RDMAP_CATASTROPHIC = 0,
1318  RDMAP_REMOTE_PROT = 1,
1319  RDMAP_REMOTE_OP = 2,
1320  DDP_CATASTROPHIC = 0,
1321  DDP_TAGGED_BUFFER = 1,
1322  DDP_UNTAGGED_BUFFER = 2,
1323  DDP_LLP = 3
1324 };
1325 
1326 enum nes_term_rdma_errors {
1327  RDMAP_INV_STAG = 0x00,
1328  RDMAP_INV_BOUNDS = 0x01,
1329  RDMAP_ACCESS = 0x02,
1330  RDMAP_UNASSOC_STAG = 0x03,
1331  RDMAP_TO_WRAP = 0x04,
1332  RDMAP_INV_RDMAP_VER = 0x05,
1333  RDMAP_UNEXPECTED_OP = 0x06,
1334  RDMAP_CATASTROPHIC_LOCAL = 0x07,
1335  RDMAP_CATASTROPHIC_GLOBAL = 0x08,
1336  RDMAP_CANT_INV_STAG = 0x09,
1337  RDMAP_UNSPECIFIED = 0xff
1338 };
1339 
1340 enum nes_term_ddp_errors {
1341  DDP_CATASTROPHIC_LOCAL = 0x00,
1342  DDP_TAGGED_INV_STAG = 0x00,
1343  DDP_TAGGED_BOUNDS = 0x01,
1344  DDP_TAGGED_UNASSOC_STAG = 0x02,
1345  DDP_TAGGED_TO_WRAP = 0x03,
1346  DDP_TAGGED_INV_DDP_VER = 0x04,
1347  DDP_UNTAGGED_INV_QN = 0x01,
1348  DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02,
1349  DDP_UNTAGGED_INV_MSN_RANGE = 0x03,
1350  DDP_UNTAGGED_INV_MO = 0x04,
1351  DDP_UNTAGGED_INV_TOO_LONG = 0x05,
1352  DDP_UNTAGGED_INV_DDP_VER = 0x06
1353 };
1354 
1355 enum nes_term_mpa_errors {
1356  MPA_CLOSED = 0x01,
1357  MPA_CRC = 0x02,
1358  MPA_MARKER = 0x03,
1359  MPA_REQ_RSP = 0x04,
1360 };
1361 
1362 struct nes_terminate_hdr {
1363  u8 layer_etype;
1364  u8 error_code;
1365  u8 hdrct;
1366  u8 rsvd;
1367 };
1368 
1369 /* Used to determine how to fill in terminate error codes */
1370 #define IWARP_OPCODE_WRITE 0
1371 #define IWARP_OPCODE_READREQ 1
1372 #define IWARP_OPCODE_READRSP 2
1373 #define IWARP_OPCODE_SEND 3
1374 #define IWARP_OPCODE_SEND_INV 4
1375 #define IWARP_OPCODE_SEND_SE 5
1376 #define IWARP_OPCODE_SEND_SE_INV 6
1377 #define IWARP_OPCODE_TERM 7
1378 
1379 /* These values are used only during terminate processing */
1380 #define TERM_DDP_LEN_TAGGED 14
1381 #define TERM_DDP_LEN_UNTAGGED 18
1382 #define TERM_RDMA_LEN 28
1383 #define RDMA_OPCODE_MASK 0x0f
1384 #define RDMA_READ_REQ_OPCODE 1
1385 #define BAD_FRAME_OFFSET 64
1386 #define CQE_MAJOR_DRV 0x8000
1387 
1388 /* Used for link status recheck after interrupt processing */
1389 #define NES_LINK_RECHECK_DELAY msecs_to_jiffies(50)
1390 #define NES_LINK_RECHECK_MAX 60
1391 
1392 #endif /* __NES_HW_H */
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