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hw.h File Reference

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Data Structures

struct  ar9170_stream
 

Macros

#define AR9170_UART_REG_BASE   0x1c0000
 
#define AR9170_UART_REG_RX_BUFFER   (AR9170_UART_REG_BASE + 0x000)
 
#define AR9170_UART_REG_TX_HOLDING   (AR9170_UART_REG_BASE + 0x004)
 
#define AR9170_UART_REG_FIFO_CONTROL   (AR9170_UART_REG_BASE + 0x010)
 
#define AR9170_UART_FIFO_CTRL_RESET_RX_FIFO   0x02
 
#define AR9170_UART_FIFO_CTRL_RESET_TX_FIFO   0x04
 
#define AR9170_UART_REG_LINE_CONTROL   (AR9170_UART_REG_BASE + 0x014)
 
#define AR9170_UART_REG_MODEM_CONTROL   (AR9170_UART_REG_BASE + 0x018)
 
#define AR9170_UART_MODEM_CTRL_DTR_BIT   0x01
 
#define AR9170_UART_MODEM_CTRL_RTS_BIT   0x02
 
#define AR9170_UART_MODEM_CTRL_INTERNAL_LOOP_BACK   0x10
 
#define AR9170_UART_MODEM_CTRL_AUTO_RTS   0x20
 
#define AR9170_UART_MODEM_CTRL_AUTO_CTR   0x40
 
#define AR9170_UART_REG_LINE_STATUS   (AR9170_UART_REG_BASE + 0x01c)
 
#define AR9170_UART_LINE_STS_RX_DATA_READY   0x01
 
#define AR9170_UART_LINE_STS_RX_BUFFER_OVERRUN   0x02
 
#define AR9170_UART_LINE_STS_RX_BREAK_IND   0x10
 
#define AR9170_UART_LINE_STS_TX_FIFO_NEAR_EMPTY   0x20
 
#define AR9170_UART_LINE_STS_TRANSMITTER_EMPTY   0x40
 
#define AR9170_UART_REG_MODEM_STATUS   (AR9170_UART_REG_BASE + 0x020)
 
#define AR9170_UART_MODEM_STS_CTS_CHANGE   0x01
 
#define AR9170_UART_MODEM_STS_DSR_CHANGE   0x02
 
#define AR9170_UART_MODEM_STS_DCD_CHANGE   0x08
 
#define AR9170_UART_MODEM_STS_CTS_COMPL   0x10
 
#define AR9170_UART_MODEM_STS_DSR_COMPL   0x20
 
#define AR9170_UART_MODEM_STS_DCD_COMPL   0x80
 
#define AR9170_UART_REG_SCRATCH   (AR9170_UART_REG_BASE + 0x024)
 
#define AR9170_UART_REG_DIVISOR_LSB   (AR9170_UART_REG_BASE + 0x028)
 
#define AR9170_UART_REG_DIVISOR_MSB   (AR9170_UART_REG_BASE + 0x02c)
 
#define AR9170_UART_REG_WORD_RX_BUFFER   (AR9170_UART_REG_BASE + 0x034)
 
#define AR9170_UART_REG_WORD_TX_HOLDING   (AR9170_UART_REG_BASE + 0x038)
 
#define AR9170_UART_REG_FIFO_COUNT   (AR9170_UART_REG_BASE + 0x03c)
 
#define AR9170_UART_REG_REMAINDER   (AR9170_UART_REG_BASE + 0x04c)
 
#define AR9170_TIMER_REG_BASE   0x1c1000
 
#define AR9170_TIMER_REG_WATCH_DOG   (AR9170_TIMER_REG_BASE + 0x000)
 
#define AR9170_TIMER_REG_TIMER0   (AR9170_TIMER_REG_BASE + 0x010)
 
#define AR9170_TIMER_REG_TIMER1   (AR9170_TIMER_REG_BASE + 0x014)
 
#define AR9170_TIMER_REG_TIMER2   (AR9170_TIMER_REG_BASE + 0x018)
 
#define AR9170_TIMER_REG_TIMER3   (AR9170_TIMER_REG_BASE + 0x01c)
 
#define AR9170_TIMER_REG_TIMER4   (AR9170_TIMER_REG_BASE + 0x020)
 
#define AR9170_TIMER_REG_CONTROL   (AR9170_TIMER_REG_BASE + 0x024)
 
#define AR9170_TIMER_CTRL_DISABLE_CLOCK   0x100
 
#define AR9170_TIMER_REG_INTERRUPT   (AR9170_TIMER_REG_BASE + 0x028)
 
#define AR9170_TIMER_INT_TIMER0   0x001
 
#define AR9170_TIMER_INT_TIMER1   0x002
 
#define AR9170_TIMER_INT_TIMER2   0x004
 
#define AR9170_TIMER_INT_TIMER3   0x008
 
#define AR9170_TIMER_INT_TIMER4   0x010
 
#define AR9170_TIMER_INT_TICK_TIMER   0x100
 
#define AR9170_TIMER_REG_TICK_TIMER   (AR9170_TIMER_REG_BASE + 0x030)
 
#define AR9170_TIMER_REG_CLOCK_LOW   (AR9170_TIMER_REG_BASE + 0x040)
 
#define AR9170_TIMER_REG_CLOCK_HIGH   (AR9170_TIMER_REG_BASE + 0x044)
 
#define AR9170_MAC_REG_BASE   0x1c3000
 
#define AR9170_MAC_REG_POWER_STATE_CTRL   (AR9170_MAC_REG_BASE + 0x500)
 
#define AR9170_MAC_POWER_STATE_CTRL_RESET   0x20
 
#define AR9170_MAC_REG_MAC_POWER_STATE_CTRL   (AR9170_MAC_REG_BASE + 0x50c)
 
#define AR9170_MAC_REG_INT_CTRL   (AR9170_MAC_REG_BASE + 0x510)
 
#define AR9170_MAC_INT_TXC   BIT(0)
 
#define AR9170_MAC_INT_RXC   BIT(1)
 
#define AR9170_MAC_INT_RETRY_FAIL   BIT(2)
 
#define AR9170_MAC_INT_WAKEUP   BIT(3)
 
#define AR9170_MAC_INT_ATIM   BIT(4)
 
#define AR9170_MAC_INT_DTIM   BIT(5)
 
#define AR9170_MAC_INT_CFG_BCN   BIT(6)
 
#define AR9170_MAC_INT_ABORT   BIT(7)
 
#define AR9170_MAC_INT_QOS   BIT(8)
 
#define AR9170_MAC_INT_MIMO_PS   BIT(9)
 
#define AR9170_MAC_INT_KEY_GEN   BIT(10)
 
#define AR9170_MAC_INT_DECRY_NOUSER   BIT(11)
 
#define AR9170_MAC_INT_RADAR   BIT(12)
 
#define AR9170_MAC_INT_QUIET_FRAME   BIT(13)
 
#define AR9170_MAC_INT_PRETBTT   BIT(14)
 
#define AR9170_MAC_REG_TSF_L   (AR9170_MAC_REG_BASE + 0x514)
 
#define AR9170_MAC_REG_TSF_H   (AR9170_MAC_REG_BASE + 0x518)
 
#define AR9170_MAC_REG_ATIM_WINDOW   (AR9170_MAC_REG_BASE + 0x51c)
 
#define AR9170_MAC_ATIM_PERIOD_S   0
 
#define AR9170_MAC_ATIM_PERIOD   0x0000ffff
 
#define AR9170_MAC_REG_BCN_PERIOD   (AR9170_MAC_REG_BASE + 0x520)
 
#define AR9170_MAC_BCN_PERIOD_S   0
 
#define AR9170_MAC_BCN_PERIOD   0x0000ffff
 
#define AR9170_MAC_BCN_DTIM_S   16
 
#define AR9170_MAC_BCN_DTIM   0x00ff0000
 
#define AR9170_MAC_BCN_AP_MODE   BIT(24)
 
#define AR9170_MAC_BCN_IBSS_MODE   BIT(25)
 
#define AR9170_MAC_BCN_PWR_MGT   BIT(26)
 
#define AR9170_MAC_BCN_STA_PS   BIT(27)
 
#define AR9170_MAC_REG_PRETBTT   (AR9170_MAC_REG_BASE + 0x524)
 
#define AR9170_MAC_PRETBTT_S   0
 
#define AR9170_MAC_PRETBTT   0x0000ffff
 
#define AR9170_MAC_PRETBTT2_S   16
 
#define AR9170_MAC_PRETBTT2   0xffff0000
 
#define AR9170_MAC_REG_MAC_ADDR_L   (AR9170_MAC_REG_BASE + 0x610)
 
#define AR9170_MAC_REG_MAC_ADDR_H   (AR9170_MAC_REG_BASE + 0x614)
 
#define AR9170_MAC_REG_BSSID_L   (AR9170_MAC_REG_BASE + 0x618)
 
#define AR9170_MAC_REG_BSSID_H   (AR9170_MAC_REG_BASE + 0x61c)
 
#define AR9170_MAC_REG_GROUP_HASH_TBL_L   (AR9170_MAC_REG_BASE + 0x624)
 
#define AR9170_MAC_REG_GROUP_HASH_TBL_H   (AR9170_MAC_REG_BASE + 0x628)
 
#define AR9170_MAC_REG_RX_TIMEOUT   (AR9170_MAC_REG_BASE + 0x62c)
 
#define AR9170_MAC_REG_BASIC_RATE   (AR9170_MAC_REG_BASE + 0x630)
 
#define AR9170_MAC_REG_MANDATORY_RATE   (AR9170_MAC_REG_BASE + 0x634)
 
#define AR9170_MAC_REG_RTS_CTS_RATE   (AR9170_MAC_REG_BASE + 0x638)
 
#define AR9170_MAC_REG_BACKOFF_PROTECT   (AR9170_MAC_REG_BASE + 0x63c)
 
#define AR9170_MAC_REG_RX_THRESHOLD   (AR9170_MAC_REG_BASE + 0x640)
 
#define AR9170_MAC_REG_AFTER_PNP   (AR9170_MAC_REG_BASE + 0x648)
 
#define AR9170_MAC_REG_RX_PE_DELAY   (AR9170_MAC_REG_BASE + 0x64c)
 
#define AR9170_MAC_REG_DYNAMIC_SIFS_ACK   (AR9170_MAC_REG_BASE + 0x658)
 
#define AR9170_MAC_REG_SNIFFER   (AR9170_MAC_REG_BASE + 0x674)
 
#define AR9170_MAC_SNIFFER_ENABLE_PROMISC   BIT(0)
 
#define AR9170_MAC_SNIFFER_DEFAULTS   0x02000000
 
#define AR9170_MAC_REG_ENCRYPTION   (AR9170_MAC_REG_BASE + 0x678)
 
#define AR9170_MAC_ENCRYPTION_MGMT_RX_SOFTWARE   BIT(2)
 
#define AR9170_MAC_ENCRYPTION_RX_SOFTWARE   BIT(3)
 
#define AR9170_MAC_ENCRYPTION_DEFAULTS   0x70
 
#define AR9170_MAC_REG_MISC_680   (AR9170_MAC_REG_BASE + 0x680)
 
#define AR9170_MAC_REG_MISC_684   (AR9170_MAC_REG_BASE + 0x684)
 
#define AR9170_MAC_REG_TX_UNDERRUN   (AR9170_MAC_REG_BASE + 0x688)
 
#define AR9170_MAC_REG_FRAMETYPE_FILTER   (AR9170_MAC_REG_BASE + 0x68c)
 
#define AR9170_MAC_FTF_ASSOC_REQ   BIT(0)
 
#define AR9170_MAC_FTF_ASSOC_RESP   BIT(1)
 
#define AR9170_MAC_FTF_REASSOC_REQ   BIT(2)
 
#define AR9170_MAC_FTF_REASSOC_RESP   BIT(3)
 
#define AR9170_MAC_FTF_PRB_REQ   BIT(4)
 
#define AR9170_MAC_FTF_PRB_RESP   BIT(5)
 
#define AR9170_MAC_FTF_BIT6   BIT(6)
 
#define AR9170_MAC_FTF_BIT7   BIT(7)
 
#define AR9170_MAC_FTF_BEACON   BIT(8)
 
#define AR9170_MAC_FTF_ATIM   BIT(9)
 
#define AR9170_MAC_FTF_DEASSOC   BIT(10)
 
#define AR9170_MAC_FTF_AUTH   BIT(11)
 
#define AR9170_MAC_FTF_DEAUTH   BIT(12)
 
#define AR9170_MAC_FTF_BIT13   BIT(13)
 
#define AR9170_MAC_FTF_BIT14   BIT(14)
 
#define AR9170_MAC_FTF_BIT15   BIT(15)
 
#define AR9170_MAC_FTF_BAR   BIT(24)
 
#define AR9170_MAC_FTF_BA   BIT(25)
 
#define AR9170_MAC_FTF_PSPOLL   BIT(26)
 
#define AR9170_MAC_FTF_RTS   BIT(27)
 
#define AR9170_MAC_FTF_CTS   BIT(28)
 
#define AR9170_MAC_FTF_ACK   BIT(29)
 
#define AR9170_MAC_FTF_CFE   BIT(30)
 
#define AR9170_MAC_FTF_CFE_ACK   BIT(31)
 
#define AR9170_MAC_FTF_DEFAULTS   0x0500ffff
 
#define AR9170_MAC_FTF_MONITOR   0xff00ffff
 
#define AR9170_MAC_REG_ACK_EXTENSION   (AR9170_MAC_REG_BASE + 0x690)
 
#define AR9170_MAC_REG_ACK_TPC   (AR9170_MAC_REG_BASE + 0x694)
 
#define AR9170_MAC_REG_EIFS_AND_SIFS   (AR9170_MAC_REG_BASE + 0x698)
 
#define AR9170_MAC_REG_RX_TIMEOUT_COUNT   (AR9170_MAC_REG_BASE + 0x69c)
 
#define AR9170_MAC_REG_RX_TOTAL   (AR9170_MAC_REG_BASE + 0x6a0)
 
#define AR9170_MAC_REG_RX_CRC32   (AR9170_MAC_REG_BASE + 0x6a4)
 
#define AR9170_MAC_REG_RX_CRC16   (AR9170_MAC_REG_BASE + 0x6a8)
 
#define AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI   (AR9170_MAC_REG_BASE + 0x6ac)
 
#define AR9170_MAC_REG_RX_OVERRUN   (AR9170_MAC_REG_BASE + 0x6b0)
 
#define AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL   (AR9170_MAC_REG_BASE + 0x6bc)
 
#define AR9170_MAC_REG_TX_BLOCKACKS   (AR9170_MAC_REG_BASE + 0x6c0)
 
#define AR9170_MAC_REG_NAV_COUNT   (AR9170_MAC_REG_BASE + 0x6c4)
 
#define AR9170_MAC_REG_BACKOFF_STATUS   (AR9170_MAC_REG_BASE + 0x6c8)
 
#define AR9170_MAC_BACKOFF_CCA   BIT(24)
 
#define AR9170_MAC_BACKOFF_TX_PEX   BIT(25)
 
#define AR9170_MAC_BACKOFF_RX_PE   BIT(26)
 
#define AR9170_MAC_BACKOFF_MD_READY   BIT(27)
 
#define AR9170_MAC_BACKOFF_TX_PE   BIT(28)
 
#define AR9170_MAC_REG_TX_RETRY   (AR9170_MAC_REG_BASE + 0x6cc)
 
#define AR9170_MAC_REG_TX_COMPLETE   (AR9170_MAC_REG_BASE + 0x6d4)
 
#define AR9170_MAC_REG_CHANNEL_BUSY   (AR9170_MAC_REG_BASE + 0x6e8)
 
#define AR9170_MAC_REG_EXT_BUSY   (AR9170_MAC_REG_BASE + 0x6ec)
 
#define AR9170_MAC_REG_SLOT_TIME   (AR9170_MAC_REG_BASE + 0x6f0)
 
#define AR9170_MAC_REG_TX_TOTAL   (AR9170_MAC_REG_BASE + 0x6f4)
 
#define AR9170_MAC_REG_ACK_FC   (AR9170_MAC_REG_BASE + 0x6f8)
 
#define AR9170_MAC_REG_CAM_MODE   (AR9170_MAC_REG_BASE + 0x700)
 
#define AR9170_MAC_CAM_IBSS   0xe0
 
#define AR9170_MAC_CAM_AP   0xa1
 
#define AR9170_MAC_CAM_STA   0x2
 
#define AR9170_MAC_CAM_AP_WDS   0x3
 
#define AR9170_MAC_CAM_DEFAULTS   (0xf << 24)
 
#define AR9170_MAC_CAM_HOST_PENDING   0x80000000
 
#define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_L   (AR9170_MAC_REG_BASE + 0x704)
 
#define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_H   (AR9170_MAC_REG_BASE + 0x708)
 
#define AR9170_MAC_REG_CAM_ADDR   (AR9170_MAC_REG_BASE + 0x70c)
 
#define AR9170_MAC_CAM_ADDR_WRITE   0x80000000
 
#define AR9170_MAC_REG_CAM_DATA0   (AR9170_MAC_REG_BASE + 0x720)
 
#define AR9170_MAC_REG_CAM_DATA1   (AR9170_MAC_REG_BASE + 0x724)
 
#define AR9170_MAC_REG_CAM_DATA2   (AR9170_MAC_REG_BASE + 0x728)
 
#define AR9170_MAC_REG_CAM_DATA3   (AR9170_MAC_REG_BASE + 0x72c)
 
#define AR9170_MAC_REG_CAM_DBG0   (AR9170_MAC_REG_BASE + 0x730)
 
#define AR9170_MAC_REG_CAM_DBG1   (AR9170_MAC_REG_BASE + 0x734)
 
#define AR9170_MAC_REG_CAM_DBG2   (AR9170_MAC_REG_BASE + 0x738)
 
#define AR9170_MAC_REG_CAM_STATE   (AR9170_MAC_REG_BASE + 0x73c)
 
#define AR9170_MAC_CAM_STATE_READ_PENDING   0x40000000
 
#define AR9170_MAC_CAM_STATE_WRITE_PENDING   0x80000000
 
#define AR9170_MAC_REG_CAM_TXKEY   (AR9170_MAC_REG_BASE + 0x740)
 
#define AR9170_MAC_REG_CAM_RXKEY   (AR9170_MAC_REG_BASE + 0x750)
 
#define AR9170_MAC_REG_CAM_TX_ENC_TYPE   (AR9170_MAC_REG_BASE + 0x760)
 
#define AR9170_MAC_REG_CAM_RX_ENC_TYPE   (AR9170_MAC_REG_BASE + 0x770)
 
#define AR9170_MAC_REG_CAM_TX_SERACH_HIT   (AR9170_MAC_REG_BASE + 0x780)
 
#define AR9170_MAC_REG_CAM_RX_SERACH_HIT   (AR9170_MAC_REG_BASE + 0x790)
 
#define AR9170_MAC_REG_AC0_CW   (AR9170_MAC_REG_BASE + 0xb00)
 
#define AR9170_MAC_REG_AC1_CW   (AR9170_MAC_REG_BASE + 0xb04)
 
#define AR9170_MAC_REG_AC2_CW   (AR9170_MAC_REG_BASE + 0xb08)
 
#define AR9170_MAC_REG_AC3_CW   (AR9170_MAC_REG_BASE + 0xb0c)
 
#define AR9170_MAC_REG_AC4_CW   (AR9170_MAC_REG_BASE + 0xb10)
 
#define AR9170_MAC_REG_AC2_AC1_AC0_AIFS   (AR9170_MAC_REG_BASE + 0xb14)
 
#define AR9170_MAC_REG_AC4_AC3_AC2_AIFS   (AR9170_MAC_REG_BASE + 0xb18)
 
#define AR9170_MAC_REG_TXOP_ACK_EXTENSION   (AR9170_MAC_REG_BASE + 0xb1c)
 
#define AR9170_MAC_REG_TXOP_ACK_INTERVAL   (AR9170_MAC_REG_BASE + 0xb20)
 
#define AR9170_MAC_REG_CONTENTION_POINT   (AR9170_MAC_REG_BASE + 0xb24)
 
#define AR9170_MAC_REG_RETRY_MAX   (AR9170_MAC_REG_BASE + 0xb28)
 
#define AR9170_MAC_REG_TID_CFACK_CFEND_RATE   (AR9170_MAC_REG_BASE + 0xb2c)
 
#define AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND   (AR9170_MAC_REG_BASE + 0xb30)
 
#define AR9170_MAC_REG_TKIP_TSC   (AR9170_MAC_REG_BASE + 0xb34)
 
#define AR9170_MAC_REG_TXOP_DURATION   (AR9170_MAC_REG_BASE + 0xb38)
 
#define AR9170_MAC_REG_TX_QOS_THRESHOLD   (AR9170_MAC_REG_BASE + 0xb3c)
 
#define AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA   (AR9170_MAC_REG_BASE + 0xb40)
 
#define AR9170_MAC_VIRTUAL_CCA_Q0   BIT(15)
 
#define AR9170_MAC_VIRTUAL_CCA_Q1   BIT(16)
 
#define AR9170_MAC_VIRTUAL_CCA_Q2   BIT(17)
 
#define AR9170_MAC_VIRTUAL_CCA_Q3   BIT(18)
 
#define AR9170_MAC_VIRTUAL_CCA_Q4   BIT(19)
 
#define AR9170_MAC_VIRTUAL_CCA_ALL   (0xf8000)
 
#define AR9170_MAC_REG_AC1_AC0_TXOP   (AR9170_MAC_REG_BASE + 0xb44)
 
#define AR9170_MAC_REG_AC3_AC2_TXOP   (AR9170_MAC_REG_BASE + 0xb48)
 
#define AR9170_MAC_REG_AMPDU_COUNT   (AR9170_MAC_REG_BASE + 0xb88)
 
#define AR9170_MAC_REG_MPDU_COUNT   (AR9170_MAC_REG_BASE + 0xb8c)
 
#define AR9170_MAC_REG_AMPDU_FACTOR   (AR9170_MAC_REG_BASE + 0xb9c)
 
#define AR9170_MAC_AMPDU_FACTOR   0x7f0000
 
#define AR9170_MAC_AMPDU_FACTOR_S   16
 
#define AR9170_MAC_REG_AMPDU_DENSITY   (AR9170_MAC_REG_BASE + 0xba0)
 
#define AR9170_MAC_AMPDU_DENSITY   0x7
 
#define AR9170_MAC_AMPDU_DENSITY_S   0
 
#define AR9170_MAC_REG_FCS_SELECT   (AR9170_MAC_REG_BASE + 0xbb0)
 
#define AR9170_MAC_FCS_SWFCS   0x1
 
#define AR9170_MAC_FCS_FIFO_PROT   0x4
 
#define AR9170_MAC_REG_RTS_CTS_TPC   (AR9170_MAC_REG_BASE + 0xbb4)
 
#define AR9170_MAC_REG_CFEND_QOSNULL_TPC   (AR9170_MAC_REG_BASE + 0xbb8)
 
#define AR9170_MAC_REG_ACK_TABLE   (AR9170_MAC_REG_BASE + 0xc00)
 
#define AR9170_MAC_REG_RX_CONTROL   (AR9170_MAC_REG_BASE + 0xc40)
 
#define AR9170_MAC_RX_CTRL_DEAGG   0x1
 
#define AR9170_MAC_RX_CTRL_SHORT_FILTER   0x2
 
#define AR9170_MAC_RX_CTRL_SA_DA_SEARCH   0x20
 
#define AR9170_MAC_RX_CTRL_PASS_TO_HOST   BIT(28)
 
#define AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER   BIT(30)
 
#define AR9170_MAC_REG_RX_CONTROL_1   (AR9170_MAC_REG_BASE + 0xc44)
 
#define AR9170_MAC_REG_AMPDU_RX_THRESH   (AR9170_MAC_REG_BASE + 0xc50)
 
#define AR9170_MAC_REG_RX_MPDU   (AR9170_MAC_REG_BASE + 0xca0)
 
#define AR9170_MAC_REG_RX_DROPPED_MPDU   (AR9170_MAC_REG_BASE + 0xca4)
 
#define AR9170_MAC_REG_RX_DEL_MPDU   (AR9170_MAC_REG_BASE + 0xca8)
 
#define AR9170_MAC_REG_RX_PHY_MISC_ERROR   (AR9170_MAC_REG_BASE + 0xcac)
 
#define AR9170_MAC_REG_RX_PHY_XR_ERROR   (AR9170_MAC_REG_BASE + 0xcb0)
 
#define AR9170_MAC_REG_RX_PHY_OFDM_ERROR   (AR9170_MAC_REG_BASE + 0xcb4)
 
#define AR9170_MAC_REG_RX_PHY_CCK_ERROR   (AR9170_MAC_REG_BASE + 0xcb8)
 
#define AR9170_MAC_REG_RX_PHY_HT_ERROR   (AR9170_MAC_REG_BASE + 0xcbc)
 
#define AR9170_MAC_REG_RX_PHY_TOTAL   (AR9170_MAC_REG_BASE + 0xcc0)
 
#define AR9170_MAC_REG_DMA_TXQ_ADDR   (AR9170_MAC_REG_BASE + 0xd00)
 
#define AR9170_MAC_REG_DMA_TXQ_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd04)
 
#define AR9170_MAC_REG_DMA_TXQ0_ADDR   (AR9170_MAC_REG_BASE + 0xd00)
 
#define AR9170_MAC_REG_DMA_TXQ0_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd04)
 
#define AR9170_MAC_REG_DMA_TXQ1_ADDR   (AR9170_MAC_REG_BASE + 0xd08)
 
#define AR9170_MAC_REG_DMA_TXQ1_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd0c)
 
#define AR9170_MAC_REG_DMA_TXQ2_ADDR   (AR9170_MAC_REG_BASE + 0xd10)
 
#define AR9170_MAC_REG_DMA_TXQ2_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd14)
 
#define AR9170_MAC_REG_DMA_TXQ3_ADDR   (AR9170_MAC_REG_BASE + 0xd18)
 
#define AR9170_MAC_REG_DMA_TXQ3_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd1c)
 
#define AR9170_MAC_REG_DMA_TXQ4_ADDR   (AR9170_MAC_REG_BASE + 0xd20)
 
#define AR9170_MAC_REG_DMA_TXQ4_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd24)
 
#define AR9170_MAC_REG_DMA_RXQ_ADDR   (AR9170_MAC_REG_BASE + 0xd28)
 
#define AR9170_MAC_REG_DMA_RXQ_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd2c)
 
#define AR9170_MAC_REG_DMA_TRIGGER   (AR9170_MAC_REG_BASE + 0xd30)
 
#define AR9170_DMA_TRIGGER_TXQ0   BIT(0)
 
#define AR9170_DMA_TRIGGER_TXQ1   BIT(1)
 
#define AR9170_DMA_TRIGGER_TXQ2   BIT(2)
 
#define AR9170_DMA_TRIGGER_TXQ3   BIT(3)
 
#define AR9170_DMA_TRIGGER_TXQ4   BIT(4)
 
#define AR9170_DMA_TRIGGER_RXQ   BIT(8)
 
#define AR9170_MAC_REG_DMA_WLAN_STATUS   (AR9170_MAC_REG_BASE + 0xd38)
 
#define AR9170_MAC_REG_DMA_STATUS   (AR9170_MAC_REG_BASE + 0xd3c)
 
#define AR9170_MAC_REG_DMA_TXQ_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd40)
 
#define AR9170_MAC_REG_DMA_TXQ0_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd40)
 
#define AR9170_MAC_REG_DMA_TXQ1_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd44)
 
#define AR9170_MAC_REG_DMA_TXQ2_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd48)
 
#define AR9170_MAC_REG_DMA_TXQ3_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd4c)
 
#define AR9170_MAC_REG_DMA_TXQ4_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd50)
 
#define AR9170_MAC_REG_DMA_TXQ0Q1_LEN   (AR9170_MAC_REG_BASE + 0xd54)
 
#define AR9170_MAC_REG_DMA_TXQ2Q3_LEN   (AR9170_MAC_REG_BASE + 0xd58)
 
#define AR9170_MAC_REG_DMA_TXQ4_LEN   (AR9170_MAC_REG_BASE + 0xd5c)
 
#define AR9170_MAC_REG_DMA_TXQX_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd74)
 
#define AR9170_MAC_REG_DMA_TXQX_FAIL_ADDR   (AR9170_MAC_REG_BASE + 0xd78)
 
#define AR9170_MAC_REG_TXRX_MPI   (AR9170_MAC_REG_BASE + 0xd7c)
 
#define AR9170_MAC_TXRX_MPI_TX_MPI_MASK   0x0000000f
 
#define AR9170_MAC_TXRX_MPI_TX_TO_MASK   0x0000fff0
 
#define AR9170_MAC_TXRX_MPI_RX_MPI_MASK   0x000f0000
 
#define AR9170_MAC_TXRX_MPI_RX_TO_MASK   0xfff00000
 
#define AR9170_MAC_REG_BCN_ADDR   (AR9170_MAC_REG_BASE + 0xd84)
 
#define AR9170_MAC_REG_BCN_LENGTH   (AR9170_MAC_REG_BASE + 0xd88)
 
#define AR9170_MAC_BCN_LENGTH_MAX   256
 
#define AR9170_MAC_REG_BCN_STATUS   (AR9170_MAC_REG_BASE + 0xd8c)
 
#define AR9170_MAC_REG_BCN_PLCP   (AR9170_MAC_REG_BASE + 0xd90)
 
#define AR9170_MAC_REG_BCN_CTRL   (AR9170_MAC_REG_BASE + 0xd94)
 
#define AR9170_BCN_CTRL_READY   0x01
 
#define AR9170_BCN_CTRL_LOCK   0x02
 
#define AR9170_MAC_REG_BCN_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd98)
 
#define AR9170_MAC_REG_BCN_COUNT   (AR9170_MAC_REG_BASE + 0xd9c)
 
#define AR9170_MAC_REG_BCN_HT1   (AR9170_MAC_REG_BASE + 0xda0)
 
#define AR9170_MAC_BCN_HT1_HT_EN   BIT(0)
 
#define AR9170_MAC_BCN_HT1_GF_PMB   BIT(1)
 
#define AR9170_MAC_BCN_HT1_SP_EXP   BIT(2)
 
#define AR9170_MAC_BCN_HT1_TX_BF   BIT(3)
 
#define AR9170_MAC_BCN_HT1_PWR_CTRL_S   4
 
#define AR9170_MAC_BCN_HT1_PWR_CTRL   0x70
 
#define AR9170_MAC_BCN_HT1_TX_ANT1   BIT(7)
 
#define AR9170_MAC_BCN_HT1_TX_ANT0   BIT(8)
 
#define AR9170_MAC_BCN_HT1_NUM_LFT_S   9
 
#define AR9170_MAC_BCN_HT1_NUM_LFT   0x600
 
#define AR9170_MAC_BCN_HT1_BWC_20M_EXT   BIT(16)
 
#define AR9170_MAC_BCN_HT1_BWC_40M_SHARED   BIT(17)
 
#define AR9170_MAC_BCN_HT1_BWC_40M_DUP   (BIT(16) | BIT(17))
 
#define AR9170_MAC_BCN_HT1_BF_MCS_S   18
 
#define AR9170_MAC_BCN_HT1_BF_MCS   0x1c0000
 
#define AR9170_MAC_BCN_HT1_TPC_S   21
 
#define AR9170_MAC_BCN_HT1_TPC   0x7e00000
 
#define AR9170_MAC_BCN_HT1_CHAIN_MASK_S   27
 
#define AR9170_MAC_BCN_HT1_CHAIN_MASK   0x38000000
 
#define AR9170_MAC_REG_BCN_HT2   (AR9170_MAC_REG_BASE + 0xda4)
 
#define AR9170_MAC_BCN_HT2_MCS_S   0
 
#define AR9170_MAC_BCN_HT2_MCS   0x7f
 
#define AR9170_MAC_BCN_HT2_BW40   BIT(8)
 
#define AR9170_MAC_BCN_HT2_SMOOTHING   BIT(9)
 
#define AR9170_MAC_BCN_HT2_SS   BIT(10)
 
#define AR9170_MAC_BCN_HT2_NSS   BIT(11)
 
#define AR9170_MAC_BCN_HT2_STBC_S   12
 
#define AR9170_MAC_BCN_HT2_STBC   0x3000
 
#define AR9170_MAC_BCN_HT2_ADV_COD   BIT(14)
 
#define AR9170_MAC_BCN_HT2_SGI   BIT(15)
 
#define AR9170_MAC_BCN_HT2_LEN_S   16
 
#define AR9170_MAC_BCN_HT2_LEN   0xffff0000
 
#define AR9170_MAC_REG_DMA_TXQX_ADDR_CURR   (AR9170_MAC_REG_BASE + 0xdc0)
 
#define AR9170_RAND_REG_BASE   0x1d0000
 
#define AR9170_RAND_REG_NUM   (AR9170_RAND_REG_BASE + 0x000)
 
#define AR9170_RAND_REG_MODE   (AR9170_RAND_REG_BASE + 0x004)
 
#define AR9170_RAND_MODE_MANUAL   0x000
 
#define AR9170_RAND_MODE_FREE   0x001
 
#define AR9170_GPIO_REG_BASE   0x1d0100
 
#define AR9170_GPIO_REG_PORT_TYPE   (AR9170_GPIO_REG_BASE + 0x000)
 
#define AR9170_GPIO_REG_PORT_DATA   (AR9170_GPIO_REG_BASE + 0x004)
 
#define AR9170_GPIO_PORT_LED_0   1
 
#define AR9170_GPIO_PORT_LED_1   2
 
#define AR9170_GPIO_PORT_WPS_BUTTON_PRESSED   4
 
#define AR9170_MC_REG_BASE   0x1d1000
 
#define AR9170_MC_REG_FLASH_WAIT_STATE   (AR9170_MC_REG_BASE + 0x000)
 
#define AR9170_MC_REG_SEEPROM_WP0   (AR9170_MC_REG_BASE + 0x400)
 
#define AR9170_MC_REG_SEEPROM_WP1   (AR9170_MC_REG_BASE + 0x404)
 
#define AR9170_MC_REG_SEEPROM_WP2   (AR9170_MC_REG_BASE + 0x408)
 
#define AR9170_MAX_INT_SRC   9
 
#define AR9170_INT_REG_BASE   0x1d2000
 
#define AR9170_INT_REG_FLAG   (AR9170_INT_REG_BASE + 0x000)
 
#define AR9170_INT_REG_FIQ_MASK   (AR9170_INT_REG_BASE + 0x004)
 
#define AR9170_INT_REG_IRQ_MASK   (AR9170_INT_REG_BASE + 0x008)
 
#define AR9170_INT_FLAG_WLAN   0x001
 
#define AR9170_INT_FLAG_PTAB_BIT   0x002
 
#define AR9170_INT_FLAG_SE_BIT   0x004
 
#define AR9170_INT_FLAG_UART_BIT   0x008
 
#define AR9170_INT_FLAG_TIMER_BIT   0x010
 
#define AR9170_INT_FLAG_EXT_BIT   0x020
 
#define AR9170_INT_FLAG_SW_BIT   0x040
 
#define AR9170_INT_FLAG_USB_BIT   0x080
 
#define AR9170_INT_FLAG_ETHERNET_BIT   0x100
 
#define AR9170_INT_REG_PRIORITY1   (AR9170_INT_REG_BASE + 0x00c)
 
#define AR9170_INT_REG_PRIORITY2   (AR9170_INT_REG_BASE + 0x010)
 
#define AR9170_INT_REG_PRIORITY3   (AR9170_INT_REG_BASE + 0x014)
 
#define AR9170_INT_REG_EXT_INT_CONTROL   (AR9170_INT_REG_BASE + 0x018)
 
#define AR9170_INT_REG_SW_INT_CONTROL   (AR9170_INT_REG_BASE + 0x01c)
 
#define AR9170_INT_SW_INT_ENABLE   0x1
 
#define AR9170_INT_REG_FIQ_ENCODE   (AR9170_INT_REG_BASE + 0x020)
 
#define AR9170_INT_INT_IRQ_ENCODE   (AR9170_INT_REG_BASE + 0x024)
 
#define AR9170_PWR_REG_BASE   0x1d4000
 
#define AR9170_PWR_REG_POWER_STATE   (AR9170_PWR_REG_BASE + 0x000)
 
#define AR9170_PWR_REG_RESET   (AR9170_PWR_REG_BASE + 0x004)
 
#define AR9170_PWR_RESET_COMMIT_RESET_MASK   BIT(0)
 
#define AR9170_PWR_RESET_WLAN_MASK   BIT(1)
 
#define AR9170_PWR_RESET_DMA_MASK   BIT(2)
 
#define AR9170_PWR_RESET_BRIDGE_MASK   BIT(3)
 
#define AR9170_PWR_RESET_AHB_MASK   BIT(9)
 
#define AR9170_PWR_RESET_BB_WARM_RESET   BIT(10)
 
#define AR9170_PWR_RESET_BB_COLD_RESET   BIT(11)
 
#define AR9170_PWR_RESET_ADDA_CLK_COLD_RESET   BIT(12)
 
#define AR9170_PWR_RESET_PLL   BIT(13)
 
#define AR9170_PWR_RESET_USB_PLL   BIT(14)
 
#define AR9170_PWR_REG_CLOCK_SEL   (AR9170_PWR_REG_BASE + 0x008)
 
#define AR9170_PWR_CLK_AHB_40MHZ   0
 
#define AR9170_PWR_CLK_AHB_20_22MHZ   1
 
#define AR9170_PWR_CLK_AHB_40_44MHZ   2
 
#define AR9170_PWR_CLK_AHB_80_88MHZ   3
 
#define AR9170_PWR_CLK_DAC_160_INV_DLY   0x70
 
#define AR9170_PWR_REG_CHIP_REVISION   (AR9170_PWR_REG_BASE + 0x010)
 
#define AR9170_PWR_REG_PLL_ADDAC   (AR9170_PWR_REG_BASE + 0x014)
 
#define AR9170_PWR_PLL_ADDAC_DIV_S   2
 
#define AR9170_PWR_PLL_ADDAC_DIV   0xffc
 
#define AR9170_PWR_REG_WATCH_DOG_MAGIC   (AR9170_PWR_REG_BASE + 0x020)
 
#define AR9170_USB_REG_BASE   0x1e1000
 
#define AR9170_USB_REG_MAIN_CTRL   (AR9170_USB_REG_BASE + 0x000)
 
#define AR9170_USB_MAIN_CTRL_REMOTE_WAKEUP   BIT(0)
 
#define AR9170_USB_MAIN_CTRL_ENABLE_GLOBAL_INT   BIT(2)
 
#define AR9170_USB_MAIN_CTRL_GO_TO_SUSPEND   BIT(3)
 
#define AR9170_USB_MAIN_CTRL_RESET   BIT(4)
 
#define AR9170_USB_MAIN_CTRL_CHIP_ENABLE   BIT(5)
 
#define AR9170_USB_MAIN_CTRL_HIGHSPEED   BIT(6)
 
#define AR9170_USB_REG_DEVICE_ADDRESS   (AR9170_USB_REG_BASE + 0x001)
 
#define AR9170_USB_DEVICE_ADDRESS_CONFIGURE   BIT(7)
 
#define AR9170_USB_REG_TEST   (AR9170_USB_REG_BASE + 0x002)
 
#define AR9170_USB_REG_PHY_TEST_SELECT   (AR9170_USB_REG_BASE + 0x008)
 
#define AR9170_USB_REG_CX_CONFIG_STATUS   (AR9170_USB_REG_BASE + 0x00b)
 
#define AR9170_USB_REG_EP0_DATA   (AR9170_USB_REG_BASE + 0x00c)
 
#define AR9170_USB_REG_EP0_DATA1   (AR9170_USB_REG_BASE + 0x00c)
 
#define AR9170_USB_REG_EP0_DATA2   (AR9170_USB_REG_BASE + 0x00d)
 
#define AR9170_USB_REG_INTR_MASK_BYTE_0   (AR9170_USB_REG_BASE + 0x011)
 
#define AR9170_USB_REG_INTR_MASK_BYTE_1   (AR9170_USB_REG_BASE + 0x012)
 
#define AR9170_USB_REG_INTR_MASK_BYTE_2   (AR9170_USB_REG_BASE + 0x013)
 
#define AR9170_USB_REG_INTR_MASK_BYTE_3   (AR9170_USB_REG_BASE + 0x014)
 
#define AR9170_USB_REG_INTR_MASK_BYTE_4   (AR9170_USB_REG_BASE + 0x015)
 
#define AR9170_USB_INTR_DISABLE_OUT_INT   (BIT(7) | BIT(6))
 
#define AR9170_USB_REG_INTR_MASK_BYTE_5   (AR9170_USB_REG_BASE + 0x016)
 
#define AR9170_USB_REG_INTR_MASK_BYTE_6   (AR9170_USB_REG_BASE + 0x017)
 
#define AR9170_USB_INTR_DISABLE_IN_INT   BIT(6)
 
#define AR9170_USB_REG_INTR_MASK_BYTE_7   (AR9170_USB_REG_BASE + 0x018)
 
#define AR9170_USB_REG_INTR_GROUP   (AR9170_USB_REG_BASE + 0x020)
 
#define AR9170_USB_REG_INTR_SOURCE_0   (AR9170_USB_REG_BASE + 0x021)
 
#define AR9170_USB_INTR_SRC0_SETUP   BIT(0)
 
#define AR9170_USB_INTR_SRC0_IN   BIT(1)
 
#define AR9170_USB_INTR_SRC0_OUT   BIT(2)
 
#define AR9170_USB_INTR_SRC0_FAIL   BIT(3) /* ??? */
 
#define AR9170_USB_INTR_SRC0_END   BIT(4) /* ??? */
 
#define AR9170_USB_INTR_SRC0_ABORT   BIT(7)
 
#define AR9170_USB_REG_INTR_SOURCE_1   (AR9170_USB_REG_BASE + 0x022)
 
#define AR9170_USB_REG_INTR_SOURCE_2   (AR9170_USB_REG_BASE + 0x023)
 
#define AR9170_USB_REG_INTR_SOURCE_3   (AR9170_USB_REG_BASE + 0x024)
 
#define AR9170_USB_REG_INTR_SOURCE_4   (AR9170_USB_REG_BASE + 0x025)
 
#define AR9170_USB_REG_INTR_SOURCE_5   (AR9170_USB_REG_BASE + 0x026)
 
#define AR9170_USB_REG_INTR_SOURCE_6   (AR9170_USB_REG_BASE + 0x027)
 
#define AR9170_USB_REG_INTR_SOURCE_7   (AR9170_USB_REG_BASE + 0x028)
 
#define AR9170_USB_INTR_SRC7_USB_RESET   BIT(1)
 
#define AR9170_USB_INTR_SRC7_USB_SUSPEND   BIT(2)
 
#define AR9170_USB_INTR_SRC7_USB_RESUME   BIT(3)
 
#define AR9170_USB_INTR_SRC7_ISO_SEQ_ERR   BIT(4)
 
#define AR9170_USB_INTR_SRC7_ISO_SEQ_ABORT   BIT(5)
 
#define AR9170_USB_INTR_SRC7_TX0BYTE   BIT(6)
 
#define AR9170_USB_INTR_SRC7_RX0BYTE   BIT(7)
 
#define AR9170_USB_REG_IDLE_COUNT   (AR9170_USB_REG_BASE + 0x02f)
 
#define AR9170_USB_REG_EP_MAP   (AR9170_USB_REG_BASE + 0x030)
 
#define AR9170_USB_REG_EP1_MAP   (AR9170_USB_REG_BASE + 0x030)
 
#define AR9170_USB_REG_EP2_MAP   (AR9170_USB_REG_BASE + 0x031)
 
#define AR9170_USB_REG_EP3_MAP   (AR9170_USB_REG_BASE + 0x032)
 
#define AR9170_USB_REG_EP4_MAP   (AR9170_USB_REG_BASE + 0x033)
 
#define AR9170_USB_REG_EP5_MAP   (AR9170_USB_REG_BASE + 0x034)
 
#define AR9170_USB_REG_EP6_MAP   (AR9170_USB_REG_BASE + 0x035)
 
#define AR9170_USB_REG_EP7_MAP   (AR9170_USB_REG_BASE + 0x036)
 
#define AR9170_USB_REG_EP8_MAP   (AR9170_USB_REG_BASE + 0x037)
 
#define AR9170_USB_REG_EP9_MAP   (AR9170_USB_REG_BASE + 0x038)
 
#define AR9170_USB_REG_EP10_MAP   (AR9170_USB_REG_BASE + 0x039)
 
#define AR9170_USB_REG_EP_IN_MAX_SIZE_HIGH   (AR9170_USB_REG_BASE + 0x03f)
 
#define AR9170_USB_EP_IN_TOGGLE   0x10
 
#define AR9170_USB_REG_EP_IN_MAX_SIZE_LOW   (AR9170_USB_REG_BASE + 0x03e)
 
#define AR9170_USB_REG_EP_OUT_MAX_SIZE_HIGH   (AR9170_USB_REG_BASE + 0x05f)
 
#define AR9170_USB_EP_OUT_TOGGLE   0x10
 
#define AR9170_USB_REG_EP_OUT_MAX_SIZE_LOW   (AR9170_USB_REG_BASE + 0x05e)
 
#define AR9170_USB_REG_EP3_BYTE_COUNT_HIGH   (AR9170_USB_REG_BASE + 0x0ae)
 
#define AR9170_USB_REG_EP3_BYTE_COUNT_LOW   (AR9170_USB_REG_BASE + 0x0be)
 
#define AR9170_USB_REG_EP4_BYTE_COUNT_HIGH   (AR9170_USB_REG_BASE + 0x0af)
 
#define AR9170_USB_REG_EP4_BYTE_COUNT_LOW   (AR9170_USB_REG_BASE + 0x0bf)
 
#define AR9170_USB_REG_FIFO_MAP   (AR9170_USB_REG_BASE + 0x080)
 
#define AR9170_USB_REG_FIFO0_MAP   (AR9170_USB_REG_BASE + 0x080)
 
#define AR9170_USB_REG_FIFO1_MAP   (AR9170_USB_REG_BASE + 0x081)
 
#define AR9170_USB_REG_FIFO2_MAP   (AR9170_USB_REG_BASE + 0x082)
 
#define AR9170_USB_REG_FIFO3_MAP   (AR9170_USB_REG_BASE + 0x083)
 
#define AR9170_USB_REG_FIFO4_MAP   (AR9170_USB_REG_BASE + 0x084)
 
#define AR9170_USB_REG_FIFO5_MAP   (AR9170_USB_REG_BASE + 0x085)
 
#define AR9170_USB_REG_FIFO6_MAP   (AR9170_USB_REG_BASE + 0x086)
 
#define AR9170_USB_REG_FIFO7_MAP   (AR9170_USB_REG_BASE + 0x087)
 
#define AR9170_USB_REG_FIFO8_MAP   (AR9170_USB_REG_BASE + 0x088)
 
#define AR9170_USB_REG_FIFO9_MAP   (AR9170_USB_REG_BASE + 0x089)
 
#define AR9170_USB_REG_FIFO_CONFIG   (AR9170_USB_REG_BASE + 0x090)
 
#define AR9170_USB_REG_FIFO0_CONFIG   (AR9170_USB_REG_BASE + 0x090)
 
#define AR9170_USB_REG_FIFO1_CONFIG   (AR9170_USB_REG_BASE + 0x091)
 
#define AR9170_USB_REG_FIFO2_CONFIG   (AR9170_USB_REG_BASE + 0x092)
 
#define AR9170_USB_REG_FIFO3_CONFIG   (AR9170_USB_REG_BASE + 0x093)
 
#define AR9170_USB_REG_FIFO4_CONFIG   (AR9170_USB_REG_BASE + 0x094)
 
#define AR9170_USB_REG_FIFO5_CONFIG   (AR9170_USB_REG_BASE + 0x095)
 
#define AR9170_USB_REG_FIFO6_CONFIG   (AR9170_USB_REG_BASE + 0x096)
 
#define AR9170_USB_REG_FIFO7_CONFIG   (AR9170_USB_REG_BASE + 0x097)
 
#define AR9170_USB_REG_FIFO8_CONFIG   (AR9170_USB_REG_BASE + 0x098)
 
#define AR9170_USB_REG_FIFO9_CONFIG   (AR9170_USB_REG_BASE + 0x099)
 
#define AR9170_USB_REG_EP3_DATA   (AR9170_USB_REG_BASE + 0x0f8)
 
#define AR9170_USB_REG_EP4_DATA   (AR9170_USB_REG_BASE + 0x0fc)
 
#define AR9170_USB_REG_FIFO_SIZE   (AR9170_USB_REG_BASE + 0x100)
 
#define AR9170_USB_REG_DMA_CTL   (AR9170_USB_REG_BASE + 0x108)
 
#define AR9170_USB_DMA_CTL_ENABLE_TO_DEVICE   BIT(0)
 
#define AR9170_USB_DMA_CTL_ENABLE_FROM_DEVICE   BIT(1)
 
#define AR9170_USB_DMA_CTL_HIGH_SPEED   BIT(2)
 
#define AR9170_USB_DMA_CTL_UP_PACKET_MODE   BIT(3)
 
#define AR9170_USB_DMA_CTL_UP_STREAM_S   4
 
#define AR9170_USB_DMA_CTL_UP_STREAM   (BIT(4) | BIT(5))
 
#define AR9170_USB_DMA_CTL_UP_STREAM_4K   (0)
 
#define AR9170_USB_DMA_CTL_UP_STREAM_8K   BIT(4)
 
#define AR9170_USB_DMA_CTL_UP_STREAM_16K   BIT(5)
 
#define AR9170_USB_DMA_CTL_UP_STREAM_32K   (BIT(4) | BIT(5))
 
#define AR9170_USB_DMA_CTL_DOWN_STREAM   BIT(6)
 
#define AR9170_USB_REG_DMA_STATUS   (AR9170_USB_REG_BASE + 0x10c)
 
#define AR9170_USB_DMA_STATUS_UP_IDLE   BIT(8)
 
#define AR9170_USB_DMA_STATUS_DN_IDLE   BIT(16)
 
#define AR9170_USB_REG_MAX_AGG_UPLOAD   (AR9170_USB_REG_BASE + 0x110)
 
#define AR9170_USB_REG_UPLOAD_TIME_CTL   (AR9170_USB_REG_BASE + 0x114)
 
#define AR9170_USB_REG_WAKE_UP   (AR9170_USB_REG_BASE + 0x120)
 
#define AR9170_USB_WAKE_UP_WAKE   BIT(0)
 
#define AR9170_USB_REG_CBUS_CTRL   (AR9170_USB_REG_BASE + 0x1f0)
 
#define AR9170_USB_CBUS_CTRL_BUFFER_END   (BIT(1))
 
#define AR9170_PTA_REG_BASE   0x1e2000
 
#define AR9170_PTA_REG_CMD   (AR9170_PTA_REG_BASE + 0x000)
 
#define AR9170_PTA_REG_PARAM1   (AR9170_PTA_REG_BASE + 0x004)
 
#define AR9170_PTA_REG_PARAM2   (AR9170_PTA_REG_BASE + 0x008)
 
#define AR9170_PTA_REG_PARAM3   (AR9170_PTA_REG_BASE + 0x00c)
 
#define AR9170_PTA_REG_RSP   (AR9170_PTA_REG_BASE + 0x010)
 
#define AR9170_PTA_REG_STATUS1   (AR9170_PTA_REG_BASE + 0x014)
 
#define AR9170_PTA_REG_STATUS2   (AR9170_PTA_REG_BASE + 0x018)
 
#define AR9170_PTA_REG_STATUS3   (AR9170_PTA_REG_BASE + 0x01c)
 
#define AR9170_PTA_REG_AHB_INT_FLAG   (AR9170_PTA_REG_BASE + 0x020)
 
#define AR9170_PTA_REG_AHB_INT_MASK   (AR9170_PTA_REG_BASE + 0x024)
 
#define AR9170_PTA_REG_AHB_INT_ACK   (AR9170_PTA_REG_BASE + 0x028)
 
#define AR9170_PTA_REG_AHB_SCRATCH1   (AR9170_PTA_REG_BASE + 0x030)
 
#define AR9170_PTA_REG_AHB_SCRATCH2   (AR9170_PTA_REG_BASE + 0x034)
 
#define AR9170_PTA_REG_AHB_SCRATCH3   (AR9170_PTA_REG_BASE + 0x038)
 
#define AR9170_PTA_REG_AHB_SCRATCH4   (AR9170_PTA_REG_BASE + 0x03c)
 
#define AR9170_PTA_REG_SHARE_MEM_CTRL   (AR9170_PTA_REG_BASE + 0x124)
 
#define AR9170_PTA_REG_INT_FLAG   (AR9170_PTA_REG_BASE + 0x100)
 
#define AR9170_PTA_INT_FLAG_DN   0x01
 
#define AR9170_PTA_INT_FLAG_UP   0x02
 
#define AR9170_PTA_INT_FLAG_CMD   0x04
 
#define AR9170_PTA_REG_INT_MASK   (AR9170_PTA_REG_BASE + 0x104)
 
#define AR9170_PTA_REG_DN_DMA_ADDRL   (AR9170_PTA_REG_BASE + 0x108)
 
#define AR9170_PTA_REG_DN_DMA_ADDRH   (AR9170_PTA_REG_BASE + 0x10c)
 
#define AR9170_PTA_REG_UP_DMA_ADDRL   (AR9170_PTA_REG_BASE + 0x110)
 
#define AR9170_PTA_REG_UP_DMA_ADDRH   (AR9170_PTA_REG_BASE + 0x114)
 
#define AR9170_PTA_REG_DN_PEND_TIME   (AR9170_PTA_REG_BASE + 0x118)
 
#define AR9170_PTA_REG_UP_PEND_TIME   (AR9170_PTA_REG_BASE + 0x11c)
 
#define AR9170_PTA_REG_CONTROL   (AR9170_PTA_REG_BASE + 0x120)
 
#define AR9170_PTA_CTRL_4_BEAT_BURST   0x00
 
#define AR9170_PTA_CTRL_8_BEAT_BURST   0x01
 
#define AR9170_PTA_CTRL_16_BEAT_BURST   0x02
 
#define AR9170_PTA_CTRL_LOOPBACK_MODE   0x10
 
#define AR9170_PTA_REG_MEM_CTRL   (AR9170_PTA_REG_BASE + 0x124)
 
#define AR9170_PTA_REG_MEM_ADDR   (AR9170_PTA_REG_BASE + 0x128)
 
#define AR9170_PTA_REG_DN_DMA_TRIGGER   (AR9170_PTA_REG_BASE + 0x12c)
 
#define AR9170_PTA_REG_UP_DMA_TRIGGER   (AR9170_PTA_REG_BASE + 0x130)
 
#define AR9170_PTA_REG_DMA_STATUS   (AR9170_PTA_REG_BASE + 0x134)
 
#define AR9170_PTA_REG_DN_CURR_ADDRL   (AR9170_PTA_REG_BASE + 0x138)
 
#define AR9170_PTA_REG_DN_CURR_ADDRH   (AR9170_PTA_REG_BASE + 0x13c)
 
#define AR9170_PTA_REG_UP_CURR_ADDRL   (AR9170_PTA_REG_BASE + 0x140)
 
#define AR9170_PTA_REG_UP_CURR_ADDRH   (AR9170_PTA_REG_BASE + 0x144)
 
#define AR9170_PTA_REG_DMA_MODE_CTRL   (AR9170_PTA_REG_BASE + 0x148)
 
#define AR9170_PTA_DMA_MODE_CTRL_RESET   BIT(0)
 
#define AR9170_PTA_DMA_MODE_CTRL_DISABLE_USB   BIT(1)
 
#define AR9170_MAC_REG_PC_REG_BASE   (AR9170_MAC_REG_BASE + 0xe00)
 
#define AR9170_NUM_LEDS   2
 
#define AR9170_CAM_MAX_USER   64
 
#define AR9170_CAM_MAX_KEY_LENGTH   16
 
#define AR9170_SRAM_OFFSET   0x100000
 
#define AR9170_SRAM_SIZE   0x18000
 
#define AR9170_PRAM_OFFSET   0x200000
 
#define AR9170_PRAM_SIZE   0x8000
 
#define AR9170_TX_STREAM_TAG   0x697e
 
#define AR9170_RX_STREAM_TAG   0x4e00
 
#define AR9170_RX_STREAM_MAX_SIZE   0xffff
 
#define AR9170_STREAM_LEN   4
 
#define AR9170_MAX_ACKTABLE_ENTRIES   8
 
#define AR9170_MAX_VIRTUAL_MAC   7
 
#define AR9170_USB_EP_CTRL_MAX   64
 
#define AR9170_USB_EP_TX_MAX   512
 
#define AR9170_USB_EP_RX_MAX   512
 
#define AR9170_USB_EP_IRQ_MAX   64
 
#define AR9170_USB_EP_CMD_MAX   64
 
#define CARL9170_PRETBTT_KUS   6
 
#define AR5416_MAX_RATE_POWER   63
 
#define SET_VAL(reg, value, newvalue)   (value = ((value) & ~reg) | (((newvalue) << reg##_S) & reg))
 
#define SET_CONSTVAL(reg, newvalue)   (((newvalue) << reg##_S) & reg)
 
#define MOD_VAL(reg, value, newvalue)   (((value) & ~reg) | (((newvalue) << reg##_S) & reg))
 
#define GET_VAL(reg, value)   (((value) & reg) >> reg##_S)
 

Enumerations

enum  cpu_clock {
  AHB_STATIC_40MHZ = 0, AHB_GMODE_22MHZ = 1, AHB_AMODE_20MHZ = 1, AHB_GMODE_44MHZ = 2,
  AHB_AMODE_40MHZ = 2, AHB_GMODE_88MHZ = 3, AHB_AMODE_80MHZ = 3
}
 
enum  ar9170_usb_ep {
  AR9170_USB_EP_CTRL = 0, AR9170_USB_EP_TX, AR9170_USB_EP_RX, AR9170_USB_EP_IRQ,
  AR9170_USB_EP_CMD, AR9170_USB_NUM_EXTRA_EP = 4, __AR9170_USB_NUM_EP, __AR9170_USB_NUM_MAX_EP = 10
}
 
enum  ar9170_usb_fifo { __AR9170_USB_NUM_MAX_FIFO = 10 }
 
enum  ar9170_tx_queues {
  AR9170_TXQ0 = 0, AR9170_TXQ1, AR9170_TXQ2, AR9170_TXQ3,
  AR9170_TXQ_SPECIAL, __AR9170_NUM_TX_QUEUES = 5
}
 

Functions

struct ar9170_stream __aligned (4)
 

Variables

__le16 length
 
__le16 tag
 
u8 payload [0]
 

Macro Definition Documentation

#define AR5416_MAX_RATE_POWER   63

Definition at line 803 of file hw.h.

#define AR9170_BCN_CTRL_LOCK   0x02

Definition at line 394 of file hw.h.

#define AR9170_BCN_CTRL_READY   0x01

Definition at line 393 of file hw.h.

#define AR9170_CAM_MAX_KEY_LENGTH   16

Definition at line 724 of file hw.h.

#define AR9170_CAM_MAX_USER   64

Definition at line 723 of file hw.h.

#define AR9170_DMA_TRIGGER_RXQ   BIT(8)

Definition at line 363 of file hw.h.

#define AR9170_DMA_TRIGGER_TXQ0   BIT(0)

Definition at line 358 of file hw.h.

#define AR9170_DMA_TRIGGER_TXQ1   BIT(1)

Definition at line 359 of file hw.h.

#define AR9170_DMA_TRIGGER_TXQ2   BIT(2)

Definition at line 360 of file hw.h.

#define AR9170_DMA_TRIGGER_TXQ3   BIT(3)

Definition at line 361 of file hw.h.

#define AR9170_DMA_TRIGGER_TXQ4   BIT(4)

Definition at line 362 of file hw.h.

#define AR9170_GPIO_PORT_LED_0   1

Definition at line 447 of file hw.h.

#define AR9170_GPIO_PORT_LED_1   2

Definition at line 448 of file hw.h.

#define AR9170_GPIO_PORT_WPS_BUTTON_PRESSED   4

Definition at line 450 of file hw.h.

#define AR9170_GPIO_REG_BASE   0x1d0100

Definition at line 444 of file hw.h.

#define AR9170_GPIO_REG_PORT_DATA   (AR9170_GPIO_REG_BASE + 0x004)

Definition at line 446 of file hw.h.

#define AR9170_GPIO_REG_PORT_TYPE   (AR9170_GPIO_REG_BASE + 0x000)

Definition at line 445 of file hw.h.

#define AR9170_INT_FLAG_ETHERNET_BIT   0x100

Definition at line 476 of file hw.h.

#define AR9170_INT_FLAG_EXT_BIT   0x020

Definition at line 473 of file hw.h.

#define AR9170_INT_FLAG_PTAB_BIT   0x002

Definition at line 469 of file hw.h.

#define AR9170_INT_FLAG_SE_BIT   0x004

Definition at line 470 of file hw.h.

#define AR9170_INT_FLAG_SW_BIT   0x040

Definition at line 474 of file hw.h.

#define AR9170_INT_FLAG_TIMER_BIT   0x010

Definition at line 472 of file hw.h.

#define AR9170_INT_FLAG_UART_BIT   0x008

Definition at line 471 of file hw.h.

#define AR9170_INT_FLAG_USB_BIT   0x080

Definition at line 475 of file hw.h.

#define AR9170_INT_FLAG_WLAN   0x001

Definition at line 468 of file hw.h.

#define AR9170_INT_INT_IRQ_ENCODE   (AR9170_INT_REG_BASE + 0x024)

Definition at line 486 of file hw.h.

#define AR9170_INT_REG_BASE   0x1d2000

Definition at line 462 of file hw.h.

#define AR9170_INT_REG_EXT_INT_CONTROL   (AR9170_INT_REG_BASE + 0x018)

Definition at line 481 of file hw.h.

#define AR9170_INT_REG_FIQ_ENCODE   (AR9170_INT_REG_BASE + 0x020)

Definition at line 485 of file hw.h.

#define AR9170_INT_REG_FIQ_MASK   (AR9170_INT_REG_BASE + 0x004)

Definition at line 465 of file hw.h.

#define AR9170_INT_REG_FLAG   (AR9170_INT_REG_BASE + 0x000)

Definition at line 464 of file hw.h.

#define AR9170_INT_REG_IRQ_MASK   (AR9170_INT_REG_BASE + 0x008)

Definition at line 466 of file hw.h.

#define AR9170_INT_REG_PRIORITY1   (AR9170_INT_REG_BASE + 0x00c)

Definition at line 478 of file hw.h.

#define AR9170_INT_REG_PRIORITY2   (AR9170_INT_REG_BASE + 0x010)

Definition at line 479 of file hw.h.

#define AR9170_INT_REG_PRIORITY3   (AR9170_INT_REG_BASE + 0x014)

Definition at line 480 of file hw.h.

#define AR9170_INT_REG_SW_INT_CONTROL   (AR9170_INT_REG_BASE + 0x01c)

Definition at line 482 of file hw.h.

#define AR9170_INT_SW_INT_ENABLE   0x1

Definition at line 483 of file hw.h.

#define AR9170_MAC_AMPDU_DENSITY   0x7

Definition at line 310 of file hw.h.

#define AR9170_MAC_AMPDU_DENSITY_S   0

Definition at line 311 of file hw.h.

#define AR9170_MAC_AMPDU_FACTOR   0x7f0000

Definition at line 307 of file hw.h.

#define AR9170_MAC_AMPDU_FACTOR_S   16

Definition at line 308 of file hw.h.

#define AR9170_MAC_ATIM_PERIOD   0x0000ffff

Definition at line 136 of file hw.h.

#define AR9170_MAC_ATIM_PERIOD_S   0

Definition at line 135 of file hw.h.

#define AR9170_MAC_BACKOFF_CCA   BIT(24)

Definition at line 226 of file hw.h.

#define AR9170_MAC_BACKOFF_MD_READY   BIT(27)

Definition at line 229 of file hw.h.

#define AR9170_MAC_BACKOFF_RX_PE   BIT(26)

Definition at line 228 of file hw.h.

#define AR9170_MAC_BACKOFF_TX_PE   BIT(28)

Definition at line 230 of file hw.h.

#define AR9170_MAC_BACKOFF_TX_PEX   BIT(25)

Definition at line 227 of file hw.h.

#define AR9170_MAC_BCN_AP_MODE   BIT(24)

Definition at line 143 of file hw.h.

#define AR9170_MAC_BCN_DTIM   0x00ff0000

Definition at line 142 of file hw.h.

#define AR9170_MAC_BCN_DTIM_S   16

Definition at line 141 of file hw.h.

#define AR9170_MAC_BCN_HT1_BF_MCS   0x1c0000

Definition at line 413 of file hw.h.

#define AR9170_MAC_BCN_HT1_BF_MCS_S   18

Definition at line 412 of file hw.h.

#define AR9170_MAC_BCN_HT1_BWC_20M_EXT   BIT(16)

Definition at line 409 of file hw.h.

#define AR9170_MAC_BCN_HT1_BWC_40M_DUP   (BIT(16) | BIT(17))

Definition at line 411 of file hw.h.

#define AR9170_MAC_BCN_HT1_BWC_40M_SHARED   BIT(17)

Definition at line 410 of file hw.h.

#define AR9170_MAC_BCN_HT1_CHAIN_MASK   0x38000000

Definition at line 417 of file hw.h.

#define AR9170_MAC_BCN_HT1_CHAIN_MASK_S   27

Definition at line 416 of file hw.h.

#define AR9170_MAC_BCN_HT1_GF_PMB   BIT(1)

Definition at line 400 of file hw.h.

#define AR9170_MAC_BCN_HT1_HT_EN   BIT(0)

Definition at line 399 of file hw.h.

#define AR9170_MAC_BCN_HT1_NUM_LFT   0x600

Definition at line 408 of file hw.h.

#define AR9170_MAC_BCN_HT1_NUM_LFT_S   9

Definition at line 407 of file hw.h.

#define AR9170_MAC_BCN_HT1_PWR_CTRL   0x70

Definition at line 404 of file hw.h.

#define AR9170_MAC_BCN_HT1_PWR_CTRL_S   4

Definition at line 403 of file hw.h.

#define AR9170_MAC_BCN_HT1_SP_EXP   BIT(2)

Definition at line 401 of file hw.h.

#define AR9170_MAC_BCN_HT1_TPC   0x7e00000

Definition at line 415 of file hw.h.

#define AR9170_MAC_BCN_HT1_TPC_S   21

Definition at line 414 of file hw.h.

#define AR9170_MAC_BCN_HT1_TX_ANT0   BIT(8)

Definition at line 406 of file hw.h.

#define AR9170_MAC_BCN_HT1_TX_ANT1   BIT(7)

Definition at line 405 of file hw.h.

#define AR9170_MAC_BCN_HT1_TX_BF   BIT(3)

Definition at line 402 of file hw.h.

#define AR9170_MAC_BCN_HT2_ADV_COD   BIT(14)

Definition at line 428 of file hw.h.

#define AR9170_MAC_BCN_HT2_BW40   BIT(8)

Definition at line 422 of file hw.h.

#define AR9170_MAC_BCN_HT2_LEN   0xffff0000

Definition at line 431 of file hw.h.

#define AR9170_MAC_BCN_HT2_LEN_S   16

Definition at line 430 of file hw.h.

#define AR9170_MAC_BCN_HT2_MCS   0x7f

Definition at line 421 of file hw.h.

#define AR9170_MAC_BCN_HT2_MCS_S   0

Definition at line 420 of file hw.h.

#define AR9170_MAC_BCN_HT2_NSS   BIT(11)

Definition at line 425 of file hw.h.

#define AR9170_MAC_BCN_HT2_SGI   BIT(15)

Definition at line 429 of file hw.h.

#define AR9170_MAC_BCN_HT2_SMOOTHING   BIT(9)

Definition at line 423 of file hw.h.

#define AR9170_MAC_BCN_HT2_SS   BIT(10)

Definition at line 424 of file hw.h.

#define AR9170_MAC_BCN_HT2_STBC   0x3000

Definition at line 427 of file hw.h.

#define AR9170_MAC_BCN_HT2_STBC_S   12

Definition at line 426 of file hw.h.

#define AR9170_MAC_BCN_IBSS_MODE   BIT(25)

Definition at line 144 of file hw.h.

#define AR9170_MAC_BCN_LENGTH_MAX   256

Definition at line 387 of file hw.h.

#define AR9170_MAC_BCN_PERIOD   0x0000ffff

Definition at line 140 of file hw.h.

#define AR9170_MAC_BCN_PERIOD_S   0

Definition at line 139 of file hw.h.

#define AR9170_MAC_BCN_PWR_MGT   BIT(26)

Definition at line 145 of file hw.h.

#define AR9170_MAC_BCN_STA_PS   BIT(27)

Definition at line 146 of file hw.h.

#define AR9170_MAC_CAM_ADDR_WRITE   0x80000000

Definition at line 255 of file hw.h.

#define AR9170_MAC_CAM_AP   0xa1

Definition at line 245 of file hw.h.

#define AR9170_MAC_CAM_AP_WDS   0x3

Definition at line 247 of file hw.h.

#define AR9170_MAC_CAM_DEFAULTS   (0xf << 24)

Definition at line 248 of file hw.h.

#define AR9170_MAC_CAM_HOST_PENDING   0x80000000

Definition at line 249 of file hw.h.

#define AR9170_MAC_CAM_IBSS   0xe0

Definition at line 244 of file hw.h.

#define AR9170_MAC_CAM_STA   0x2

Definition at line 246 of file hw.h.

#define AR9170_MAC_CAM_STATE_READ_PENDING   0x40000000

Definition at line 265 of file hw.h.

#define AR9170_MAC_CAM_STATE_WRITE_PENDING   0x80000000

Definition at line 266 of file hw.h.

#define AR9170_MAC_ENCRYPTION_DEFAULTS   0x70

Definition at line 179 of file hw.h.

#define AR9170_MAC_ENCRYPTION_MGMT_RX_SOFTWARE   BIT(2)

Definition at line 177 of file hw.h.

#define AR9170_MAC_ENCRYPTION_RX_SOFTWARE   BIT(3)

Definition at line 178 of file hw.h.

#define AR9170_MAC_FCS_FIFO_PROT   0x4

Definition at line 315 of file hw.h.

#define AR9170_MAC_FCS_SWFCS   0x1

Definition at line 314 of file hw.h.

#define AR9170_MAC_FTF_ACK   BIT(29)

Definition at line 207 of file hw.h.

#define AR9170_MAC_FTF_ASSOC_REQ   BIT(0)

Definition at line 186 of file hw.h.

#define AR9170_MAC_FTF_ASSOC_RESP   BIT(1)

Definition at line 187 of file hw.h.

#define AR9170_MAC_FTF_ATIM   BIT(9)

Definition at line 195 of file hw.h.

#define AR9170_MAC_FTF_AUTH   BIT(11)

Definition at line 197 of file hw.h.

#define AR9170_MAC_FTF_BA   BIT(25)

Definition at line 203 of file hw.h.

#define AR9170_MAC_FTF_BAR   BIT(24)

Definition at line 202 of file hw.h.

#define AR9170_MAC_FTF_BEACON   BIT(8)

Definition at line 194 of file hw.h.

#define AR9170_MAC_FTF_BIT13   BIT(13)

Definition at line 199 of file hw.h.

#define AR9170_MAC_FTF_BIT14   BIT(14)

Definition at line 200 of file hw.h.

#define AR9170_MAC_FTF_BIT15   BIT(15)

Definition at line 201 of file hw.h.

#define AR9170_MAC_FTF_BIT6   BIT(6)

Definition at line 192 of file hw.h.

#define AR9170_MAC_FTF_BIT7   BIT(7)

Definition at line 193 of file hw.h.

#define AR9170_MAC_FTF_CFE   BIT(30)

Definition at line 208 of file hw.h.

#define AR9170_MAC_FTF_CFE_ACK   BIT(31)

Definition at line 209 of file hw.h.

#define AR9170_MAC_FTF_CTS   BIT(28)

Definition at line 206 of file hw.h.

#define AR9170_MAC_FTF_DEASSOC   BIT(10)

Definition at line 196 of file hw.h.

#define AR9170_MAC_FTF_DEAUTH   BIT(12)

Definition at line 198 of file hw.h.

#define AR9170_MAC_FTF_DEFAULTS   0x0500ffff

Definition at line 210 of file hw.h.

#define AR9170_MAC_FTF_MONITOR   0xff00ffff

Definition at line 211 of file hw.h.

#define AR9170_MAC_FTF_PRB_REQ   BIT(4)

Definition at line 190 of file hw.h.

#define AR9170_MAC_FTF_PRB_RESP   BIT(5)

Definition at line 191 of file hw.h.

#define AR9170_MAC_FTF_PSPOLL   BIT(26)

Definition at line 204 of file hw.h.

#define AR9170_MAC_FTF_REASSOC_REQ   BIT(2)

Definition at line 188 of file hw.h.

#define AR9170_MAC_FTF_REASSOC_RESP   BIT(3)

Definition at line 189 of file hw.h.

#define AR9170_MAC_FTF_RTS   BIT(27)

Definition at line 205 of file hw.h.

#define AR9170_MAC_INT_ABORT   BIT(7)

Definition at line 122 of file hw.h.

#define AR9170_MAC_INT_ATIM   BIT(4)

Definition at line 119 of file hw.h.

#define AR9170_MAC_INT_CFG_BCN   BIT(6)

Definition at line 121 of file hw.h.

#define AR9170_MAC_INT_DECRY_NOUSER   BIT(11)

Definition at line 126 of file hw.h.

#define AR9170_MAC_INT_DTIM   BIT(5)

Definition at line 120 of file hw.h.

#define AR9170_MAC_INT_KEY_GEN   BIT(10)

Definition at line 125 of file hw.h.

#define AR9170_MAC_INT_MIMO_PS   BIT(9)

Definition at line 124 of file hw.h.

#define AR9170_MAC_INT_PRETBTT   BIT(14)

Definition at line 129 of file hw.h.

#define AR9170_MAC_INT_QOS   BIT(8)

Definition at line 123 of file hw.h.

#define AR9170_MAC_INT_QUIET_FRAME   BIT(13)

Definition at line 128 of file hw.h.

#define AR9170_MAC_INT_RADAR   BIT(12)

Definition at line 127 of file hw.h.

#define AR9170_MAC_INT_RETRY_FAIL   BIT(2)

Definition at line 117 of file hw.h.

#define AR9170_MAC_INT_RXC   BIT(1)

Definition at line 116 of file hw.h.

#define AR9170_MAC_INT_TXC   BIT(0)

Definition at line 115 of file hw.h.

#define AR9170_MAC_INT_WAKEUP   BIT(3)

Definition at line 118 of file hw.h.

#define AR9170_MAC_POWER_STATE_CTRL_RESET   0x20

Definition at line 110 of file hw.h.

#define AR9170_MAC_PRETBTT   0x0000ffff

Definition at line 150 of file hw.h.

#define AR9170_MAC_PRETBTT2   0xffff0000

Definition at line 152 of file hw.h.

#define AR9170_MAC_PRETBTT2_S   16

Definition at line 151 of file hw.h.

#define AR9170_MAC_PRETBTT_S   0

Definition at line 149 of file hw.h.

#define AR9170_MAC_REG_AC0_CW   (AR9170_MAC_REG_BASE + 0xb00)

Definition at line 276 of file hw.h.

#define AR9170_MAC_REG_AC1_AC0_TXOP   (AR9170_MAC_REG_BASE + 0xb44)

Definition at line 300 of file hw.h.

#define AR9170_MAC_REG_AC1_CW   (AR9170_MAC_REG_BASE + 0xb04)

Definition at line 277 of file hw.h.

#define AR9170_MAC_REG_AC2_AC1_AC0_AIFS   (AR9170_MAC_REG_BASE + 0xb14)

Definition at line 281 of file hw.h.

#define AR9170_MAC_REG_AC2_CW   (AR9170_MAC_REG_BASE + 0xb08)

Definition at line 278 of file hw.h.

#define AR9170_MAC_REG_AC3_AC2_TXOP   (AR9170_MAC_REG_BASE + 0xb48)

Definition at line 301 of file hw.h.

#define AR9170_MAC_REG_AC3_CW   (AR9170_MAC_REG_BASE + 0xb0c)

Definition at line 279 of file hw.h.

#define AR9170_MAC_REG_AC4_AC3_AC2_AIFS   (AR9170_MAC_REG_BASE + 0xb18)

Definition at line 282 of file hw.h.

#define AR9170_MAC_REG_AC4_CW   (AR9170_MAC_REG_BASE + 0xb10)

Definition at line 280 of file hw.h.

#define AR9170_MAC_REG_ACK_EXTENSION   (AR9170_MAC_REG_BASE + 0x690)

Definition at line 213 of file hw.h.

#define AR9170_MAC_REG_ACK_FC   (AR9170_MAC_REG_BASE + 0x6f8)

Definition at line 241 of file hw.h.

#define AR9170_MAC_REG_ACK_TABLE   (AR9170_MAC_REG_BASE + 0xc00)

Definition at line 320 of file hw.h.

#define AR9170_MAC_REG_ACK_TPC   (AR9170_MAC_REG_BASE + 0x694)

Definition at line 214 of file hw.h.

#define AR9170_MAC_REG_AFTER_PNP   (AR9170_MAC_REG_BASE + 0x648)

Definition at line 169 of file hw.h.

#define AR9170_MAC_REG_AMPDU_COUNT   (AR9170_MAC_REG_BASE + 0xb88)

Definition at line 303 of file hw.h.

#define AR9170_MAC_REG_AMPDU_DENSITY   (AR9170_MAC_REG_BASE + 0xba0)

Definition at line 309 of file hw.h.

#define AR9170_MAC_REG_AMPDU_FACTOR   (AR9170_MAC_REG_BASE + 0xb9c)

Definition at line 306 of file hw.h.

#define AR9170_MAC_REG_AMPDU_RX_THRESH   (AR9170_MAC_REG_BASE + 0xc50)

Definition at line 330 of file hw.h.

#define AR9170_MAC_REG_ATIM_WINDOW   (AR9170_MAC_REG_BASE + 0x51c)

Definition at line 134 of file hw.h.

#define AR9170_MAC_REG_BACKOFF_PROTECT   (AR9170_MAC_REG_BASE + 0x63c)

Definition at line 167 of file hw.h.

#define AR9170_MAC_REG_BACKOFF_STATUS   (AR9170_MAC_REG_BASE + 0x6c8)

Definition at line 225 of file hw.h.

#define AR9170_MAC_REG_BASE   0x1c3000

Definition at line 107 of file hw.h.

#define AR9170_MAC_REG_BASIC_RATE   (AR9170_MAC_REG_BASE + 0x630)

Definition at line 164 of file hw.h.

#define AR9170_MAC_REG_BCN_ADDR   (AR9170_MAC_REG_BASE + 0xd84)

Definition at line 385 of file hw.h.

#define AR9170_MAC_REG_BCN_COUNT   (AR9170_MAC_REG_BASE + 0xd9c)

Definition at line 397 of file hw.h.

#define AR9170_MAC_REG_BCN_CTRL   (AR9170_MAC_REG_BASE + 0xd94)

Definition at line 392 of file hw.h.

#define AR9170_MAC_REG_BCN_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd98)

Definition at line 396 of file hw.h.

#define AR9170_MAC_REG_BCN_HT1   (AR9170_MAC_REG_BASE + 0xda0)

Definition at line 398 of file hw.h.

#define AR9170_MAC_REG_BCN_HT2   (AR9170_MAC_REG_BASE + 0xda4)

Definition at line 419 of file hw.h.

#define AR9170_MAC_REG_BCN_LENGTH   (AR9170_MAC_REG_BASE + 0xd88)

Definition at line 386 of file hw.h.

#define AR9170_MAC_REG_BCN_PERIOD   (AR9170_MAC_REG_BASE + 0x520)

Definition at line 138 of file hw.h.

#define AR9170_MAC_REG_BCN_PLCP   (AR9170_MAC_REG_BASE + 0xd90)

Definition at line 391 of file hw.h.

#define AR9170_MAC_REG_BCN_STATUS   (AR9170_MAC_REG_BASE + 0xd8c)

Definition at line 389 of file hw.h.

#define AR9170_MAC_REG_BSSID_H   (AR9170_MAC_REG_BASE + 0x61c)

Definition at line 157 of file hw.h.

#define AR9170_MAC_REG_BSSID_L   (AR9170_MAC_REG_BASE + 0x618)

Definition at line 156 of file hw.h.

#define AR9170_MAC_REG_CAM_ADDR   (AR9170_MAC_REG_BASE + 0x70c)

Definition at line 254 of file hw.h.

#define AR9170_MAC_REG_CAM_DATA0   (AR9170_MAC_REG_BASE + 0x720)

Definition at line 256 of file hw.h.

#define AR9170_MAC_REG_CAM_DATA1   (AR9170_MAC_REG_BASE + 0x724)

Definition at line 257 of file hw.h.

#define AR9170_MAC_REG_CAM_DATA2   (AR9170_MAC_REG_BASE + 0x728)

Definition at line 258 of file hw.h.

#define AR9170_MAC_REG_CAM_DATA3   (AR9170_MAC_REG_BASE + 0x72c)

Definition at line 259 of file hw.h.

#define AR9170_MAC_REG_CAM_DBG0   (AR9170_MAC_REG_BASE + 0x730)

Definition at line 261 of file hw.h.

#define AR9170_MAC_REG_CAM_DBG1   (AR9170_MAC_REG_BASE + 0x734)

Definition at line 262 of file hw.h.

#define AR9170_MAC_REG_CAM_DBG2   (AR9170_MAC_REG_BASE + 0x738)

Definition at line 263 of file hw.h.

#define AR9170_MAC_REG_CAM_MODE   (AR9170_MAC_REG_BASE + 0x700)

Definition at line 243 of file hw.h.

#define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_H   (AR9170_MAC_REG_BASE + 0x708)

Definition at line 252 of file hw.h.

#define AR9170_MAC_REG_CAM_ROLL_CALL_TBL_L   (AR9170_MAC_REG_BASE + 0x704)

Definition at line 251 of file hw.h.

#define AR9170_MAC_REG_CAM_RX_ENC_TYPE   (AR9170_MAC_REG_BASE + 0x770)

Definition at line 272 of file hw.h.

#define AR9170_MAC_REG_CAM_RX_SERACH_HIT   (AR9170_MAC_REG_BASE + 0x790)

Definition at line 274 of file hw.h.

#define AR9170_MAC_REG_CAM_RXKEY   (AR9170_MAC_REG_BASE + 0x750)

Definition at line 269 of file hw.h.

#define AR9170_MAC_REG_CAM_STATE   (AR9170_MAC_REG_BASE + 0x73c)

Definition at line 264 of file hw.h.

#define AR9170_MAC_REG_CAM_TX_ENC_TYPE   (AR9170_MAC_REG_BASE + 0x760)

Definition at line 271 of file hw.h.

#define AR9170_MAC_REG_CAM_TX_SERACH_HIT   (AR9170_MAC_REG_BASE + 0x780)

Definition at line 273 of file hw.h.

#define AR9170_MAC_REG_CAM_TXKEY   (AR9170_MAC_REG_BASE + 0x740)

Definition at line 268 of file hw.h.

#define AR9170_MAC_REG_CFEND_QOSNULL_TPC   (AR9170_MAC_REG_BASE + 0xbb8)

Definition at line 318 of file hw.h.

#define AR9170_MAC_REG_CHANNEL_BUSY   (AR9170_MAC_REG_BASE + 0x6e8)

Definition at line 236 of file hw.h.

#define AR9170_MAC_REG_CONTENTION_POINT   (AR9170_MAC_REG_BASE + 0xb24)

Definition at line 285 of file hw.h.

#define AR9170_MAC_REG_DMA_RXQ_ADDR   (AR9170_MAC_REG_BASE + 0xd28)

Definition at line 354 of file hw.h.

#define AR9170_MAC_REG_DMA_RXQ_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd2c)

Definition at line 355 of file hw.h.

#define AR9170_MAC_REG_DMA_STATUS   (AR9170_MAC_REG_BASE + 0xd3c)

Definition at line 366 of file hw.h.

#define AR9170_MAC_REG_DMA_TRIGGER   (AR9170_MAC_REG_BASE + 0xd30)

Definition at line 357 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ0_ADDR   (AR9170_MAC_REG_BASE + 0xd00)

Definition at line 344 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ0_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd04)

Definition at line 345 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ0_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd40)

Definition at line 368 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ0Q1_LEN   (AR9170_MAC_REG_BASE + 0xd54)

Definition at line 373 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ1_ADDR   (AR9170_MAC_REG_BASE + 0xd08)

Definition at line 346 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ1_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd0c)

Definition at line 347 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ1_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd44)

Definition at line 369 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ2_ADDR   (AR9170_MAC_REG_BASE + 0xd10)

Definition at line 348 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ2_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd14)

Definition at line 349 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ2_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd48)

Definition at line 370 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ2Q3_LEN   (AR9170_MAC_REG_BASE + 0xd58)

Definition at line 374 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ3_ADDR   (AR9170_MAC_REG_BASE + 0xd18)

Definition at line 350 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ3_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd1c)

Definition at line 351 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ3_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd4c)

Definition at line 371 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ4_ADDR   (AR9170_MAC_REG_BASE + 0xd20)

Definition at line 352 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ4_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd24)

Definition at line 353 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ4_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd50)

Definition at line 372 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ4_LEN   (AR9170_MAC_REG_BASE + 0xd5c)

Definition at line 375 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ_ADDR   (AR9170_MAC_REG_BASE + 0xd00)

Definition at line 342 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ_CURR_ADDR   (AR9170_MAC_REG_BASE + 0xd04)

Definition at line 343 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQ_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd40)

Definition at line 367 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQX_ADDR_CURR   (AR9170_MAC_REG_BASE + 0xdc0)

Definition at line 433 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQX_FAIL_ADDR   (AR9170_MAC_REG_BASE + 0xd78)

Definition at line 378 of file hw.h.

#define AR9170_MAC_REG_DMA_TXQX_LAST_ADDR   (AR9170_MAC_REG_BASE + 0xd74)

Definition at line 377 of file hw.h.

#define AR9170_MAC_REG_DMA_WLAN_STATUS   (AR9170_MAC_REG_BASE + 0xd38)

Definition at line 365 of file hw.h.

#define AR9170_MAC_REG_DYNAMIC_SIFS_ACK   (AR9170_MAC_REG_BASE + 0x658)

Definition at line 172 of file hw.h.

#define AR9170_MAC_REG_EIFS_AND_SIFS   (AR9170_MAC_REG_BASE + 0x698)

Definition at line 215 of file hw.h.

#define AR9170_MAC_REG_ENCRYPTION   (AR9170_MAC_REG_BASE + 0x678)

Definition at line 176 of file hw.h.

#define AR9170_MAC_REG_EXT_BUSY   (AR9170_MAC_REG_BASE + 0x6ec)

Definition at line 237 of file hw.h.

#define AR9170_MAC_REG_FCS_SELECT   (AR9170_MAC_REG_BASE + 0xbb0)

Definition at line 313 of file hw.h.

#define AR9170_MAC_REG_FRAMETYPE_FILTER   (AR9170_MAC_REG_BASE + 0x68c)

Definition at line 185 of file hw.h.

#define AR9170_MAC_REG_GROUP_HASH_TBL_H   (AR9170_MAC_REG_BASE + 0x628)

Definition at line 160 of file hw.h.

#define AR9170_MAC_REG_GROUP_HASH_TBL_L   (AR9170_MAC_REG_BASE + 0x624)

Definition at line 159 of file hw.h.

#define AR9170_MAC_REG_INT_CTRL   (AR9170_MAC_REG_BASE + 0x510)

Definition at line 114 of file hw.h.

#define AR9170_MAC_REG_MAC_ADDR_H   (AR9170_MAC_REG_BASE + 0x614)

Definition at line 155 of file hw.h.

#define AR9170_MAC_REG_MAC_ADDR_L   (AR9170_MAC_REG_BASE + 0x610)

Definition at line 154 of file hw.h.

#define AR9170_MAC_REG_MAC_POWER_STATE_CTRL   (AR9170_MAC_REG_BASE + 0x50c)

Definition at line 112 of file hw.h.

#define AR9170_MAC_REG_MANDATORY_RATE   (AR9170_MAC_REG_BASE + 0x634)

Definition at line 165 of file hw.h.

#define AR9170_MAC_REG_MISC_680   (AR9170_MAC_REG_BASE + 0x680)

Definition at line 181 of file hw.h.

#define AR9170_MAC_REG_MISC_684   (AR9170_MAC_REG_BASE + 0x684)

Definition at line 182 of file hw.h.

#define AR9170_MAC_REG_MPDU_COUNT   (AR9170_MAC_REG_BASE + 0xb8c)

Definition at line 304 of file hw.h.

#define AR9170_MAC_REG_NAV_COUNT   (AR9170_MAC_REG_BASE + 0x6c4)

Definition at line 224 of file hw.h.

#define AR9170_MAC_REG_PC_REG_BASE   (AR9170_MAC_REG_BASE + 0xe00)

Definition at line 717 of file hw.h.

#define AR9170_MAC_REG_POWER_STATE_CTRL   (AR9170_MAC_REG_BASE + 0x500)

Definition at line 109 of file hw.h.

#define AR9170_MAC_REG_PRETBTT   (AR9170_MAC_REG_BASE + 0x524)

Definition at line 148 of file hw.h.

#define AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA   (AR9170_MAC_REG_BASE + 0xb40)

Definition at line 292 of file hw.h.

#define AR9170_MAC_REG_RETRY_MAX   (AR9170_MAC_REG_BASE + 0xb28)

Definition at line 286 of file hw.h.

#define AR9170_MAC_REG_RTS_CTS_RATE   (AR9170_MAC_REG_BASE + 0x638)

Definition at line 166 of file hw.h.

#define AR9170_MAC_REG_RTS_CTS_TPC   (AR9170_MAC_REG_BASE + 0xbb4)

Definition at line 317 of file hw.h.

#define AR9170_MAC_REG_RX_CONTROL   (AR9170_MAC_REG_BASE + 0xc40)

Definition at line 321 of file hw.h.

#define AR9170_MAC_REG_RX_CONTROL_1   (AR9170_MAC_REG_BASE + 0xc44)

Definition at line 328 of file hw.h.

#define AR9170_MAC_REG_RX_CRC16   (AR9170_MAC_REG_BASE + 0x6a8)

Definition at line 219 of file hw.h.

#define AR9170_MAC_REG_RX_CRC32   (AR9170_MAC_REG_BASE + 0x6a4)

Definition at line 218 of file hw.h.

#define AR9170_MAC_REG_RX_DEL_MPDU   (AR9170_MAC_REG_BASE + 0xca8)

Definition at line 334 of file hw.h.

#define AR9170_MAC_REG_RX_DROPPED_MPDU   (AR9170_MAC_REG_BASE + 0xca4)

Definition at line 333 of file hw.h.

#define AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL   (AR9170_MAC_REG_BASE + 0x6bc)

Definition at line 222 of file hw.h.

#define AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI   (AR9170_MAC_REG_BASE + 0x6ac)

Definition at line 220 of file hw.h.

#define AR9170_MAC_REG_RX_MPDU   (AR9170_MAC_REG_BASE + 0xca0)

Definition at line 332 of file hw.h.

#define AR9170_MAC_REG_RX_OVERRUN   (AR9170_MAC_REG_BASE + 0x6b0)

Definition at line 221 of file hw.h.

#define AR9170_MAC_REG_RX_PE_DELAY   (AR9170_MAC_REG_BASE + 0x64c)

Definition at line 170 of file hw.h.

#define AR9170_MAC_REG_RX_PHY_CCK_ERROR   (AR9170_MAC_REG_BASE + 0xcb8)

Definition at line 338 of file hw.h.

#define AR9170_MAC_REG_RX_PHY_HT_ERROR   (AR9170_MAC_REG_BASE + 0xcbc)

Definition at line 339 of file hw.h.

#define AR9170_MAC_REG_RX_PHY_MISC_ERROR   (AR9170_MAC_REG_BASE + 0xcac)

Definition at line 335 of file hw.h.

#define AR9170_MAC_REG_RX_PHY_OFDM_ERROR   (AR9170_MAC_REG_BASE + 0xcb4)

Definition at line 337 of file hw.h.

#define AR9170_MAC_REG_RX_PHY_TOTAL   (AR9170_MAC_REG_BASE + 0xcc0)

Definition at line 340 of file hw.h.

#define AR9170_MAC_REG_RX_PHY_XR_ERROR   (AR9170_MAC_REG_BASE + 0xcb0)

Definition at line 336 of file hw.h.

#define AR9170_MAC_REG_RX_THRESHOLD   (AR9170_MAC_REG_BASE + 0x640)

Definition at line 168 of file hw.h.

#define AR9170_MAC_REG_RX_TIMEOUT   (AR9170_MAC_REG_BASE + 0x62c)

Definition at line 162 of file hw.h.

#define AR9170_MAC_REG_RX_TIMEOUT_COUNT   (AR9170_MAC_REG_BASE + 0x69c)

Definition at line 216 of file hw.h.

#define AR9170_MAC_REG_RX_TOTAL   (AR9170_MAC_REG_BASE + 0x6a0)

Definition at line 217 of file hw.h.

#define AR9170_MAC_REG_SLOT_TIME   (AR9170_MAC_REG_BASE + 0x6f0)

Definition at line 239 of file hw.h.

#define AR9170_MAC_REG_SNIFFER   (AR9170_MAC_REG_BASE + 0x674)

Definition at line 173 of file hw.h.

#define AR9170_MAC_REG_TID_CFACK_CFEND_RATE   (AR9170_MAC_REG_BASE + 0xb2c)

Definition at line 287 of file hw.h.

#define AR9170_MAC_REG_TKIP_TSC   (AR9170_MAC_REG_BASE + 0xb34)

Definition at line 289 of file hw.h.

#define AR9170_MAC_REG_TSF_H   (AR9170_MAC_REG_BASE + 0x518)

Definition at line 132 of file hw.h.

#define AR9170_MAC_REG_TSF_L   (AR9170_MAC_REG_BASE + 0x514)

Definition at line 131 of file hw.h.

#define AR9170_MAC_REG_TX_BLOCKACKS   (AR9170_MAC_REG_BASE + 0x6c0)

Definition at line 223 of file hw.h.

#define AR9170_MAC_REG_TX_COMPLETE   (AR9170_MAC_REG_BASE + 0x6d4)

Definition at line 234 of file hw.h.

#define AR9170_MAC_REG_TX_QOS_THRESHOLD   (AR9170_MAC_REG_BASE + 0xb3c)

Definition at line 291 of file hw.h.

#define AR9170_MAC_REG_TX_RETRY   (AR9170_MAC_REG_BASE + 0x6cc)

Definition at line 232 of file hw.h.

#define AR9170_MAC_REG_TX_TOTAL   (AR9170_MAC_REG_BASE + 0x6f4)

Definition at line 240 of file hw.h.

#define AR9170_MAC_REG_TX_UNDERRUN   (AR9170_MAC_REG_BASE + 0x688)

Definition at line 183 of file hw.h.

#define AR9170_MAC_REG_TXOP_ACK_EXTENSION   (AR9170_MAC_REG_BASE + 0xb1c)

Definition at line 283 of file hw.h.

#define AR9170_MAC_REG_TXOP_ACK_INTERVAL   (AR9170_MAC_REG_BASE + 0xb20)

Definition at line 284 of file hw.h.

#define AR9170_MAC_REG_TXOP_DURATION   (AR9170_MAC_REG_BASE + 0xb38)

Definition at line 290 of file hw.h.

#define AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND   (AR9170_MAC_REG_BASE + 0xb30)

Definition at line 288 of file hw.h.

#define AR9170_MAC_REG_TXRX_MPI   (AR9170_MAC_REG_BASE + 0xd7c)

Definition at line 379 of file hw.h.

#define AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER   BIT(30)

Definition at line 326 of file hw.h.

#define AR9170_MAC_RX_CTRL_DEAGG   0x1

Definition at line 322 of file hw.h.

#define AR9170_MAC_RX_CTRL_PASS_TO_HOST   BIT(28)

Definition at line 325 of file hw.h.

#define AR9170_MAC_RX_CTRL_SA_DA_SEARCH   0x20

Definition at line 324 of file hw.h.

#define AR9170_MAC_RX_CTRL_SHORT_FILTER   0x2

Definition at line 323 of file hw.h.

#define AR9170_MAC_SNIFFER_DEFAULTS   0x02000000

Definition at line 175 of file hw.h.

#define AR9170_MAC_SNIFFER_ENABLE_PROMISC   BIT(0)

Definition at line 174 of file hw.h.

#define AR9170_MAC_TXRX_MPI_RX_MPI_MASK   0x000f0000

Definition at line 382 of file hw.h.

#define AR9170_MAC_TXRX_MPI_RX_TO_MASK   0xfff00000

Definition at line 383 of file hw.h.

#define AR9170_MAC_TXRX_MPI_TX_MPI_MASK   0x0000000f

Definition at line 380 of file hw.h.

#define AR9170_MAC_TXRX_MPI_TX_TO_MASK   0x0000fff0

Definition at line 381 of file hw.h.

#define AR9170_MAC_VIRTUAL_CCA_ALL   (0xf8000)

Definition at line 298 of file hw.h.

#define AR9170_MAC_VIRTUAL_CCA_Q0   BIT(15)

Definition at line 293 of file hw.h.

#define AR9170_MAC_VIRTUAL_CCA_Q1   BIT(16)

Definition at line 294 of file hw.h.

#define AR9170_MAC_VIRTUAL_CCA_Q2   BIT(17)

Definition at line 295 of file hw.h.

#define AR9170_MAC_VIRTUAL_CCA_Q3   BIT(18)

Definition at line 296 of file hw.h.

#define AR9170_MAC_VIRTUAL_CCA_Q4   BIT(19)

Definition at line 297 of file hw.h.

#define AR9170_MAX_ACKTABLE_ENTRIES   8

Definition at line 791 of file hw.h.

#define AR9170_MAX_INT_SRC   9

Definition at line 461 of file hw.h.

#define AR9170_MAX_VIRTUAL_MAC   7

Definition at line 792 of file hw.h.

#define AR9170_MC_REG_BASE   0x1d1000

Definition at line 453 of file hw.h.

#define AR9170_MC_REG_FLASH_WAIT_STATE   (AR9170_MC_REG_BASE + 0x000)

Definition at line 455 of file hw.h.

#define AR9170_MC_REG_SEEPROM_WP0   (AR9170_MC_REG_BASE + 0x400)

Definition at line 456 of file hw.h.

#define AR9170_MC_REG_SEEPROM_WP1   (AR9170_MC_REG_BASE + 0x404)

Definition at line 457 of file hw.h.

#define AR9170_MC_REG_SEEPROM_WP2   (AR9170_MC_REG_BASE + 0x408)

Definition at line 458 of file hw.h.

#define AR9170_NUM_LEDS   2

Definition at line 720 of file hw.h.

#define AR9170_PRAM_OFFSET   0x200000

Definition at line 729 of file hw.h.

#define AR9170_PRAM_SIZE   0x8000

Definition at line 730 of file hw.h.

#define AR9170_PTA_CTRL_16_BEAT_BURST   0x02

Definition at line 700 of file hw.h.

#define AR9170_PTA_CTRL_4_BEAT_BURST   0x00

Definition at line 698 of file hw.h.

#define AR9170_PTA_CTRL_8_BEAT_BURST   0x01

Definition at line 699 of file hw.h.

#define AR9170_PTA_CTRL_LOOPBACK_MODE   0x10

Definition at line 701 of file hw.h.

#define AR9170_PTA_DMA_MODE_CTRL_DISABLE_USB   BIT(1)

Definition at line 714 of file hw.h.

#define AR9170_PTA_DMA_MODE_CTRL_RESET   BIT(0)

Definition at line 713 of file hw.h.

#define AR9170_PTA_INT_FLAG_CMD   0x04

Definition at line 688 of file hw.h.

#define AR9170_PTA_INT_FLAG_DN   0x01

Definition at line 686 of file hw.h.

#define AR9170_PTA_INT_FLAG_UP   0x02

Definition at line 687 of file hw.h.

#define AR9170_PTA_REG_AHB_INT_ACK   (AR9170_PTA_REG_BASE + 0x028)

Definition at line 673 of file hw.h.

#define AR9170_PTA_REG_AHB_INT_FLAG   (AR9170_PTA_REG_BASE + 0x020)

Definition at line 671 of file hw.h.

#define AR9170_PTA_REG_AHB_INT_MASK   (AR9170_PTA_REG_BASE + 0x024)

Definition at line 672 of file hw.h.

#define AR9170_PTA_REG_AHB_SCRATCH1   (AR9170_PTA_REG_BASE + 0x030)

Definition at line 674 of file hw.h.

#define AR9170_PTA_REG_AHB_SCRATCH2   (AR9170_PTA_REG_BASE + 0x034)

Definition at line 675 of file hw.h.

#define AR9170_PTA_REG_AHB_SCRATCH3   (AR9170_PTA_REG_BASE + 0x038)

Definition at line 676 of file hw.h.

#define AR9170_PTA_REG_AHB_SCRATCH4   (AR9170_PTA_REG_BASE + 0x03c)

Definition at line 677 of file hw.h.

#define AR9170_PTA_REG_BASE   0x1e2000

Definition at line 661 of file hw.h.

#define AR9170_PTA_REG_CMD   (AR9170_PTA_REG_BASE + 0x000)

Definition at line 663 of file hw.h.

#define AR9170_PTA_REG_CONTROL   (AR9170_PTA_REG_BASE + 0x120)

Definition at line 697 of file hw.h.

#define AR9170_PTA_REG_DMA_MODE_CTRL   (AR9170_PTA_REG_BASE + 0x148)

Definition at line 712 of file hw.h.

#define AR9170_PTA_REG_DMA_STATUS   (AR9170_PTA_REG_BASE + 0x134)

Definition at line 707 of file hw.h.

#define AR9170_PTA_REG_DN_CURR_ADDRH   (AR9170_PTA_REG_BASE + 0x13c)

Definition at line 709 of file hw.h.

#define AR9170_PTA_REG_DN_CURR_ADDRL   (AR9170_PTA_REG_BASE + 0x138)

Definition at line 708 of file hw.h.

#define AR9170_PTA_REG_DN_DMA_ADDRH   (AR9170_PTA_REG_BASE + 0x10c)

Definition at line 692 of file hw.h.

#define AR9170_PTA_REG_DN_DMA_ADDRL   (AR9170_PTA_REG_BASE + 0x108)

Definition at line 691 of file hw.h.

#define AR9170_PTA_REG_DN_DMA_TRIGGER   (AR9170_PTA_REG_BASE + 0x12c)

Definition at line 705 of file hw.h.

#define AR9170_PTA_REG_DN_PEND_TIME   (AR9170_PTA_REG_BASE + 0x118)

Definition at line 695 of file hw.h.

#define AR9170_PTA_REG_INT_FLAG   (AR9170_PTA_REG_BASE + 0x100)

Definition at line 685 of file hw.h.

#define AR9170_PTA_REG_INT_MASK   (AR9170_PTA_REG_BASE + 0x104)

Definition at line 690 of file hw.h.

#define AR9170_PTA_REG_MEM_ADDR   (AR9170_PTA_REG_BASE + 0x128)

Definition at line 704 of file hw.h.

#define AR9170_PTA_REG_MEM_CTRL   (AR9170_PTA_REG_BASE + 0x124)

Definition at line 703 of file hw.h.

#define AR9170_PTA_REG_PARAM1   (AR9170_PTA_REG_BASE + 0x004)

Definition at line 664 of file hw.h.

#define AR9170_PTA_REG_PARAM2   (AR9170_PTA_REG_BASE + 0x008)

Definition at line 665 of file hw.h.

#define AR9170_PTA_REG_PARAM3   (AR9170_PTA_REG_BASE + 0x00c)

Definition at line 666 of file hw.h.

#define AR9170_PTA_REG_RSP   (AR9170_PTA_REG_BASE + 0x010)

Definition at line 667 of file hw.h.

#define AR9170_PTA_REG_SHARE_MEM_CTRL   (AR9170_PTA_REG_BASE + 0x124)

Definition at line 679 of file hw.h.

#define AR9170_PTA_REG_STATUS1   (AR9170_PTA_REG_BASE + 0x014)

Definition at line 668 of file hw.h.

#define AR9170_PTA_REG_STATUS2   (AR9170_PTA_REG_BASE + 0x018)

Definition at line 669 of file hw.h.

#define AR9170_PTA_REG_STATUS3   (AR9170_PTA_REG_BASE + 0x01c)

Definition at line 670 of file hw.h.

#define AR9170_PTA_REG_UP_CURR_ADDRH   (AR9170_PTA_REG_BASE + 0x144)

Definition at line 711 of file hw.h.

#define AR9170_PTA_REG_UP_CURR_ADDRL   (AR9170_PTA_REG_BASE + 0x140)

Definition at line 710 of file hw.h.

#define AR9170_PTA_REG_UP_DMA_ADDRH   (AR9170_PTA_REG_BASE + 0x114)

Definition at line 694 of file hw.h.

#define AR9170_PTA_REG_UP_DMA_ADDRL   (AR9170_PTA_REG_BASE + 0x110)

Definition at line 693 of file hw.h.

#define AR9170_PTA_REG_UP_DMA_TRIGGER   (AR9170_PTA_REG_BASE + 0x130)

Definition at line 706 of file hw.h.

#define AR9170_PTA_REG_UP_PEND_TIME   (AR9170_PTA_REG_BASE + 0x11c)

Definition at line 696 of file hw.h.

#define AR9170_PWR_CLK_AHB_20_22MHZ   1

Definition at line 507 of file hw.h.

#define AR9170_PWR_CLK_AHB_40_44MHZ   2

Definition at line 508 of file hw.h.

#define AR9170_PWR_CLK_AHB_40MHZ   0

Definition at line 506 of file hw.h.

#define AR9170_PWR_CLK_AHB_80_88MHZ   3

Definition at line 509 of file hw.h.

#define AR9170_PWR_CLK_DAC_160_INV_DLY   0x70

Definition at line 510 of file hw.h.

#define AR9170_PWR_PLL_ADDAC_DIV   0xffc

Definition at line 515 of file hw.h.

#define AR9170_PWR_PLL_ADDAC_DIV_S   2

Definition at line 514 of file hw.h.

#define AR9170_PWR_REG_BASE   0x1d4000

Definition at line 489 of file hw.h.

#define AR9170_PWR_REG_CHIP_REVISION   (AR9170_PWR_REG_BASE + 0x010)

Definition at line 512 of file hw.h.

#define AR9170_PWR_REG_CLOCK_SEL   (AR9170_PWR_REG_BASE + 0x008)

Definition at line 505 of file hw.h.

#define AR9170_PWR_REG_PLL_ADDAC   (AR9170_PWR_REG_BASE + 0x014)

Definition at line 513 of file hw.h.

#define AR9170_PWR_REG_POWER_STATE   (AR9170_PWR_REG_BASE + 0x000)

Definition at line 491 of file hw.h.

#define AR9170_PWR_REG_RESET   (AR9170_PWR_REG_BASE + 0x004)

Definition at line 493 of file hw.h.

#define AR9170_PWR_REG_WATCH_DOG_MAGIC   (AR9170_PWR_REG_BASE + 0x020)

Definition at line 516 of file hw.h.

#define AR9170_PWR_RESET_ADDA_CLK_COLD_RESET   BIT(12)

Definition at line 501 of file hw.h.

#define AR9170_PWR_RESET_AHB_MASK   BIT(9)

Definition at line 498 of file hw.h.

#define AR9170_PWR_RESET_BB_COLD_RESET   BIT(11)

Definition at line 500 of file hw.h.

#define AR9170_PWR_RESET_BB_WARM_RESET   BIT(10)

Definition at line 499 of file hw.h.

#define AR9170_PWR_RESET_BRIDGE_MASK   BIT(3)

Definition at line 497 of file hw.h.

#define AR9170_PWR_RESET_COMMIT_RESET_MASK   BIT(0)

Definition at line 494 of file hw.h.

#define AR9170_PWR_RESET_DMA_MASK   BIT(2)

Definition at line 496 of file hw.h.

#define AR9170_PWR_RESET_PLL   BIT(13)

Definition at line 502 of file hw.h.

#define AR9170_PWR_RESET_USB_PLL   BIT(14)

Definition at line 503 of file hw.h.

#define AR9170_PWR_RESET_WLAN_MASK   BIT(1)

Definition at line 495 of file hw.h.

#define AR9170_RAND_MODE_FREE   0x001

Definition at line 441 of file hw.h.

#define AR9170_RAND_MODE_MANUAL   0x000

Definition at line 440 of file hw.h.

#define AR9170_RAND_REG_BASE   0x1d0000

Definition at line 436 of file hw.h.

#define AR9170_RAND_REG_MODE   (AR9170_RAND_REG_BASE + 0x004)

Definition at line 439 of file hw.h.

#define AR9170_RAND_REG_NUM   (AR9170_RAND_REG_BASE + 0x000)

Definition at line 438 of file hw.h.

#define AR9170_RX_STREAM_MAX_SIZE   0xffff

Definition at line 781 of file hw.h.

#define AR9170_RX_STREAM_TAG   0x4e00

Definition at line 780 of file hw.h.

#define AR9170_SRAM_OFFSET   0x100000

Definition at line 726 of file hw.h.

#define AR9170_SRAM_SIZE   0x18000

Definition at line 727 of file hw.h.

#define AR9170_STREAM_LEN   4

Definition at line 789 of file hw.h.

#define AR9170_TIMER_CTRL_DISABLE_CLOCK   0x100

Definition at line 93 of file hw.h.

#define AR9170_TIMER_INT_TICK_TIMER   0x100

Definition at line 101 of file hw.h.

#define AR9170_TIMER_INT_TIMER0   0x001

Definition at line 96 of file hw.h.

#define AR9170_TIMER_INT_TIMER1   0x002

Definition at line 97 of file hw.h.

#define AR9170_TIMER_INT_TIMER2   0x004

Definition at line 98 of file hw.h.

#define AR9170_TIMER_INT_TIMER3   0x008

Definition at line 99 of file hw.h.

#define AR9170_TIMER_INT_TIMER4   0x010

Definition at line 100 of file hw.h.

#define AR9170_TIMER_REG_BASE   0x1c1000

Definition at line 84 of file hw.h.

#define AR9170_TIMER_REG_CLOCK_HIGH   (AR9170_TIMER_REG_BASE + 0x044)

Definition at line 105 of file hw.h.

#define AR9170_TIMER_REG_CLOCK_LOW   (AR9170_TIMER_REG_BASE + 0x040)

Definition at line 104 of file hw.h.

#define AR9170_TIMER_REG_CONTROL   (AR9170_TIMER_REG_BASE + 0x024)

Definition at line 92 of file hw.h.

#define AR9170_TIMER_REG_INTERRUPT   (AR9170_TIMER_REG_BASE + 0x028)

Definition at line 95 of file hw.h.

#define AR9170_TIMER_REG_TICK_TIMER   (AR9170_TIMER_REG_BASE + 0x030)

Definition at line 103 of file hw.h.

#define AR9170_TIMER_REG_TIMER0   (AR9170_TIMER_REG_BASE + 0x010)

Definition at line 87 of file hw.h.

#define AR9170_TIMER_REG_TIMER1   (AR9170_TIMER_REG_BASE + 0x014)

Definition at line 88 of file hw.h.

#define AR9170_TIMER_REG_TIMER2   (AR9170_TIMER_REG_BASE + 0x018)

Definition at line 89 of file hw.h.

#define AR9170_TIMER_REG_TIMER3   (AR9170_TIMER_REG_BASE + 0x01c)

Definition at line 90 of file hw.h.

#define AR9170_TIMER_REG_TIMER4   (AR9170_TIMER_REG_BASE + 0x020)

Definition at line 91 of file hw.h.

#define AR9170_TIMER_REG_WATCH_DOG   (AR9170_TIMER_REG_BASE + 0x000)

Definition at line 86 of file hw.h.

#define AR9170_TX_STREAM_TAG   0x697e

Definition at line 779 of file hw.h.

#define AR9170_UART_FIFO_CTRL_RESET_RX_FIFO   0x02

Definition at line 49 of file hw.h.

#define AR9170_UART_FIFO_CTRL_RESET_TX_FIFO   0x04

Definition at line 50 of file hw.h.

#define AR9170_UART_LINE_STS_RX_BREAK_IND   0x10

Definition at line 63 of file hw.h.

#define AR9170_UART_LINE_STS_RX_BUFFER_OVERRUN   0x02

Definition at line 62 of file hw.h.

#define AR9170_UART_LINE_STS_RX_DATA_READY   0x01

Definition at line 61 of file hw.h.

#define AR9170_UART_LINE_STS_TRANSMITTER_EMPTY   0x40

Definition at line 65 of file hw.h.

#define AR9170_UART_LINE_STS_TX_FIFO_NEAR_EMPTY   0x20

Definition at line 64 of file hw.h.

#define AR9170_UART_MODEM_CTRL_AUTO_CTR   0x40

Definition at line 58 of file hw.h.

#define AR9170_UART_MODEM_CTRL_AUTO_RTS   0x20

Definition at line 57 of file hw.h.

#define AR9170_UART_MODEM_CTRL_DTR_BIT   0x01

Definition at line 54 of file hw.h.

#define AR9170_UART_MODEM_CTRL_INTERNAL_LOOP_BACK   0x10

Definition at line 56 of file hw.h.

#define AR9170_UART_MODEM_CTRL_RTS_BIT   0x02

Definition at line 55 of file hw.h.

#define AR9170_UART_MODEM_STS_CTS_CHANGE   0x01

Definition at line 68 of file hw.h.

#define AR9170_UART_MODEM_STS_CTS_COMPL   0x10

Definition at line 71 of file hw.h.

#define AR9170_UART_MODEM_STS_DCD_CHANGE   0x08

Definition at line 70 of file hw.h.

#define AR9170_UART_MODEM_STS_DCD_COMPL   0x80

Definition at line 73 of file hw.h.

#define AR9170_UART_MODEM_STS_DSR_CHANGE   0x02

Definition at line 69 of file hw.h.

#define AR9170_UART_MODEM_STS_DSR_COMPL   0x20

Definition at line 72 of file hw.h.

#define AR9170_UART_REG_BASE   0x1c0000

Definition at line 43 of file hw.h.

#define AR9170_UART_REG_DIVISOR_LSB   (AR9170_UART_REG_BASE + 0x028)

Definition at line 76 of file hw.h.

#define AR9170_UART_REG_DIVISOR_MSB   (AR9170_UART_REG_BASE + 0x02c)

Definition at line 77 of file hw.h.

#define AR9170_UART_REG_FIFO_CONTROL   (AR9170_UART_REG_BASE + 0x010)

Definition at line 48 of file hw.h.

#define AR9170_UART_REG_FIFO_COUNT   (AR9170_UART_REG_BASE + 0x03c)

Definition at line 80 of file hw.h.

#define AR9170_UART_REG_LINE_CONTROL   (AR9170_UART_REG_BASE + 0x014)

Definition at line 52 of file hw.h.

#define AR9170_UART_REG_LINE_STATUS   (AR9170_UART_REG_BASE + 0x01c)

Definition at line 60 of file hw.h.

#define AR9170_UART_REG_MODEM_CONTROL   (AR9170_UART_REG_BASE + 0x018)

Definition at line 53 of file hw.h.

#define AR9170_UART_REG_MODEM_STATUS   (AR9170_UART_REG_BASE + 0x020)

Definition at line 67 of file hw.h.

#define AR9170_UART_REG_REMAINDER   (AR9170_UART_REG_BASE + 0x04c)

Definition at line 81 of file hw.h.

#define AR9170_UART_REG_RX_BUFFER   (AR9170_UART_REG_BASE + 0x000)

Definition at line 46 of file hw.h.

#define AR9170_UART_REG_SCRATCH   (AR9170_UART_REG_BASE + 0x024)

Definition at line 75 of file hw.h.

#define AR9170_UART_REG_TX_HOLDING   (AR9170_UART_REG_BASE + 0x004)

Definition at line 47 of file hw.h.

#define AR9170_UART_REG_WORD_RX_BUFFER   (AR9170_UART_REG_BASE + 0x034)

Definition at line 78 of file hw.h.

#define AR9170_UART_REG_WORD_TX_HOLDING   (AR9170_UART_REG_BASE + 0x038)

Definition at line 79 of file hw.h.

#define AR9170_USB_CBUS_CTRL_BUFFER_END   (BIT(1))

Definition at line 658 of file hw.h.

#define AR9170_USB_DEVICE_ADDRESS_CONFIGURE   BIT(7)

Definition at line 530 of file hw.h.

#define AR9170_USB_DMA_CTL_DOWN_STREAM   BIT(6)

Definition at line 645 of file hw.h.

#define AR9170_USB_DMA_CTL_ENABLE_FROM_DEVICE   BIT(1)

Definition at line 636 of file hw.h.

#define AR9170_USB_DMA_CTL_ENABLE_TO_DEVICE   BIT(0)

Definition at line 635 of file hw.h.

#define AR9170_USB_DMA_CTL_HIGH_SPEED   BIT(2)

Definition at line 637 of file hw.h.

#define AR9170_USB_DMA_CTL_UP_PACKET_MODE   BIT(3)

Definition at line 638 of file hw.h.

#define AR9170_USB_DMA_CTL_UP_STREAM   (BIT(4) | BIT(5))

Definition at line 640 of file hw.h.

#define AR9170_USB_DMA_CTL_UP_STREAM_16K   BIT(5)

Definition at line 643 of file hw.h.

#define AR9170_USB_DMA_CTL_UP_STREAM_32K   (BIT(4) | BIT(5))

Definition at line 644 of file hw.h.

#define AR9170_USB_DMA_CTL_UP_STREAM_4K   (0)

Definition at line 641 of file hw.h.

#define AR9170_USB_DMA_CTL_UP_STREAM_8K   BIT(4)

Definition at line 642 of file hw.h.

#define AR9170_USB_DMA_CTL_UP_STREAM_S   4

Definition at line 639 of file hw.h.

#define AR9170_USB_DMA_STATUS_DN_IDLE   BIT(16)

Definition at line 649 of file hw.h.

#define AR9170_USB_DMA_STATUS_UP_IDLE   BIT(8)

Definition at line 648 of file hw.h.

#define AR9170_USB_EP_CMD_MAX   64

Definition at line 798 of file hw.h.

#define AR9170_USB_EP_CTRL_MAX   64

Definition at line 794 of file hw.h.

#define AR9170_USB_EP_IN_TOGGLE   0x10

Definition at line 592 of file hw.h.

#define AR9170_USB_EP_IRQ_MAX   64

Definition at line 797 of file hw.h.

#define AR9170_USB_EP_OUT_TOGGLE   0x10

Definition at line 597 of file hw.h.

#define AR9170_USB_EP_RX_MAX   512

Definition at line 796 of file hw.h.

#define AR9170_USB_EP_TX_MAX   512

Definition at line 795 of file hw.h.

#define AR9170_USB_INTR_DISABLE_IN_INT   BIT(6)

Definition at line 548 of file hw.h.

#define AR9170_USB_INTR_DISABLE_OUT_INT   (BIT(7) | BIT(6))

Definition at line 544 of file hw.h.

#define AR9170_USB_INTR_SRC0_ABORT   BIT(7)

Definition at line 560 of file hw.h.

#define AR9170_USB_INTR_SRC0_END   BIT(4) /* ??? */

Definition at line 559 of file hw.h.

#define AR9170_USB_INTR_SRC0_FAIL   BIT(3) /* ??? */

Definition at line 558 of file hw.h.

#define AR9170_USB_INTR_SRC0_IN   BIT(1)

Definition at line 556 of file hw.h.

#define AR9170_USB_INTR_SRC0_OUT   BIT(2)

Definition at line 557 of file hw.h.

#define AR9170_USB_INTR_SRC0_SETUP   BIT(0)

Definition at line 555 of file hw.h.

#define AR9170_USB_INTR_SRC7_ISO_SEQ_ABORT   BIT(5)

Definition at line 573 of file hw.h.

#define AR9170_USB_INTR_SRC7_ISO_SEQ_ERR   BIT(4)

Definition at line 572 of file hw.h.

#define AR9170_USB_INTR_SRC7_RX0BYTE   BIT(7)

Definition at line 575 of file hw.h.

#define AR9170_USB_INTR_SRC7_TX0BYTE   BIT(6)

Definition at line 574 of file hw.h.

#define AR9170_USB_INTR_SRC7_USB_RESET   BIT(1)

Definition at line 569 of file hw.h.

#define AR9170_USB_INTR_SRC7_USB_RESUME   BIT(3)

Definition at line 571 of file hw.h.

#define AR9170_USB_INTR_SRC7_USB_SUSPEND   BIT(2)

Definition at line 570 of file hw.h.

#define AR9170_USB_MAIN_CTRL_CHIP_ENABLE   BIT(5)

Definition at line 526 of file hw.h.

#define AR9170_USB_MAIN_CTRL_ENABLE_GLOBAL_INT   BIT(2)

Definition at line 523 of file hw.h.

#define AR9170_USB_MAIN_CTRL_GO_TO_SUSPEND   BIT(3)

Definition at line 524 of file hw.h.

#define AR9170_USB_MAIN_CTRL_HIGHSPEED   BIT(6)

Definition at line 527 of file hw.h.

#define AR9170_USB_MAIN_CTRL_REMOTE_WAKEUP   BIT(0)

Definition at line 522 of file hw.h.

#define AR9170_USB_MAIN_CTRL_RESET   BIT(4)

Definition at line 525 of file hw.h.

#define AR9170_USB_REG_BASE   0x1e1000

Definition at line 519 of file hw.h.

#define AR9170_USB_REG_CBUS_CTRL   (AR9170_USB_REG_BASE + 0x1f0)

Definition at line 657 of file hw.h.

#define AR9170_USB_REG_CX_CONFIG_STATUS   (AR9170_USB_REG_BASE + 0x00b)

Definition at line 534 of file hw.h.

#define AR9170_USB_REG_DEVICE_ADDRESS   (AR9170_USB_REG_BASE + 0x001)

Definition at line 529 of file hw.h.

#define AR9170_USB_REG_DMA_CTL   (AR9170_USB_REG_BASE + 0x108)

Definition at line 634 of file hw.h.

#define AR9170_USB_REG_DMA_STATUS   (AR9170_USB_REG_BASE + 0x10c)

Definition at line 647 of file hw.h.

#define AR9170_USB_REG_EP0_DATA   (AR9170_USB_REG_BASE + 0x00c)

Definition at line 535 of file hw.h.

#define AR9170_USB_REG_EP0_DATA1   (AR9170_USB_REG_BASE + 0x00c)

Definition at line 536 of file hw.h.

#define AR9170_USB_REG_EP0_DATA2   (AR9170_USB_REG_BASE + 0x00d)

Definition at line 537 of file hw.h.

#define AR9170_USB_REG_EP10_MAP   (AR9170_USB_REG_BASE + 0x039)

Definition at line 589 of file hw.h.

#define AR9170_USB_REG_EP1_MAP   (AR9170_USB_REG_BASE + 0x030)

Definition at line 580 of file hw.h.

#define AR9170_USB_REG_EP2_MAP   (AR9170_USB_REG_BASE + 0x031)

Definition at line 581 of file hw.h.

#define AR9170_USB_REG_EP3_BYTE_COUNT_HIGH   (AR9170_USB_REG_BASE + 0x0ae)

Definition at line 601 of file hw.h.

#define AR9170_USB_REG_EP3_BYTE_COUNT_LOW   (AR9170_USB_REG_BASE + 0x0be)

Definition at line 602 of file hw.h.

#define AR9170_USB_REG_EP3_DATA   (AR9170_USB_REG_BASE + 0x0f8)

Definition at line 630 of file hw.h.

#define AR9170_USB_REG_EP3_MAP   (AR9170_USB_REG_BASE + 0x032)

Definition at line 582 of file hw.h.

#define AR9170_USB_REG_EP4_BYTE_COUNT_HIGH   (AR9170_USB_REG_BASE + 0x0af)

Definition at line 603 of file hw.h.

#define AR9170_USB_REG_EP4_BYTE_COUNT_LOW   (AR9170_USB_REG_BASE + 0x0bf)

Definition at line 604 of file hw.h.

#define AR9170_USB_REG_EP4_DATA   (AR9170_USB_REG_BASE + 0x0fc)

Definition at line 631 of file hw.h.

#define AR9170_USB_REG_EP4_MAP   (AR9170_USB_REG_BASE + 0x033)

Definition at line 583 of file hw.h.

#define AR9170_USB_REG_EP5_MAP   (AR9170_USB_REG_BASE + 0x034)

Definition at line 584 of file hw.h.

#define AR9170_USB_REG_EP6_MAP   (AR9170_USB_REG_BASE + 0x035)

Definition at line 585 of file hw.h.

#define AR9170_USB_REG_EP7_MAP   (AR9170_USB_REG_BASE + 0x036)

Definition at line 586 of file hw.h.

#define AR9170_USB_REG_EP8_MAP   (AR9170_USB_REG_BASE + 0x037)

Definition at line 587 of file hw.h.

#define AR9170_USB_REG_EP9_MAP   (AR9170_USB_REG_BASE + 0x038)

Definition at line 588 of file hw.h.

#define AR9170_USB_REG_EP_IN_MAX_SIZE_HIGH   (AR9170_USB_REG_BASE + 0x03f)

Definition at line 591 of file hw.h.

#define AR9170_USB_REG_EP_IN_MAX_SIZE_LOW   (AR9170_USB_REG_BASE + 0x03e)

Definition at line 594 of file hw.h.

#define AR9170_USB_REG_EP_MAP   (AR9170_USB_REG_BASE + 0x030)

Definition at line 579 of file hw.h.

#define AR9170_USB_REG_EP_OUT_MAX_SIZE_HIGH   (AR9170_USB_REG_BASE + 0x05f)

Definition at line 596 of file hw.h.

#define AR9170_USB_REG_EP_OUT_MAX_SIZE_LOW   (AR9170_USB_REG_BASE + 0x05e)

Definition at line 599 of file hw.h.

#define AR9170_USB_REG_FIFO0_CONFIG   (AR9170_USB_REG_BASE + 0x090)

Definition at line 619 of file hw.h.

#define AR9170_USB_REG_FIFO0_MAP   (AR9170_USB_REG_BASE + 0x080)

Definition at line 607 of file hw.h.

#define AR9170_USB_REG_FIFO1_CONFIG   (AR9170_USB_REG_BASE + 0x091)

Definition at line 620 of file hw.h.

#define AR9170_USB_REG_FIFO1_MAP   (AR9170_USB_REG_BASE + 0x081)

Definition at line 608 of file hw.h.

#define AR9170_USB_REG_FIFO2_CONFIG   (AR9170_USB_REG_BASE + 0x092)

Definition at line 621 of file hw.h.

#define AR9170_USB_REG_FIFO2_MAP   (AR9170_USB_REG_BASE + 0x082)

Definition at line 609 of file hw.h.

#define AR9170_USB_REG_FIFO3_CONFIG   (AR9170_USB_REG_BASE + 0x093)

Definition at line 622 of file hw.h.

#define AR9170_USB_REG_FIFO3_MAP   (AR9170_USB_REG_BASE + 0x083)

Definition at line 610 of file hw.h.

#define AR9170_USB_REG_FIFO4_CONFIG   (AR9170_USB_REG_BASE + 0x094)

Definition at line 623 of file hw.h.

#define AR9170_USB_REG_FIFO4_MAP   (AR9170_USB_REG_BASE + 0x084)

Definition at line 611 of file hw.h.

#define AR9170_USB_REG_FIFO5_CONFIG   (AR9170_USB_REG_BASE + 0x095)

Definition at line 624 of file hw.h.

#define AR9170_USB_REG_FIFO5_MAP   (AR9170_USB_REG_BASE + 0x085)

Definition at line 612 of file hw.h.

#define AR9170_USB_REG_FIFO6_CONFIG   (AR9170_USB_REG_BASE + 0x096)

Definition at line 625 of file hw.h.

#define AR9170_USB_REG_FIFO6_MAP   (AR9170_USB_REG_BASE + 0x086)

Definition at line 613 of file hw.h.

#define AR9170_USB_REG_FIFO7_CONFIG   (AR9170_USB_REG_BASE + 0x097)

Definition at line 626 of file hw.h.

#define AR9170_USB_REG_FIFO7_MAP   (AR9170_USB_REG_BASE + 0x087)

Definition at line 614 of file hw.h.

#define AR9170_USB_REG_FIFO8_CONFIG   (AR9170_USB_REG_BASE + 0x098)

Definition at line 627 of file hw.h.

#define AR9170_USB_REG_FIFO8_MAP   (AR9170_USB_REG_BASE + 0x088)

Definition at line 615 of file hw.h.

#define AR9170_USB_REG_FIFO9_CONFIG   (AR9170_USB_REG_BASE + 0x099)

Definition at line 628 of file hw.h.

#define AR9170_USB_REG_FIFO9_MAP   (AR9170_USB_REG_BASE + 0x089)

Definition at line 616 of file hw.h.

#define AR9170_USB_REG_FIFO_CONFIG   (AR9170_USB_REG_BASE + 0x090)

Definition at line 618 of file hw.h.

#define AR9170_USB_REG_FIFO_MAP   (AR9170_USB_REG_BASE + 0x080)

Definition at line 606 of file hw.h.

#define AR9170_USB_REG_FIFO_SIZE   (AR9170_USB_REG_BASE + 0x100)

Definition at line 633 of file hw.h.

#define AR9170_USB_REG_IDLE_COUNT   (AR9170_USB_REG_BASE + 0x02f)

Definition at line 577 of file hw.h.

#define AR9170_USB_REG_INTR_GROUP   (AR9170_USB_REG_BASE + 0x020)

Definition at line 552 of file hw.h.

#define AR9170_USB_REG_INTR_MASK_BYTE_0   (AR9170_USB_REG_BASE + 0x011)

Definition at line 539 of file hw.h.

#define AR9170_USB_REG_INTR_MASK_BYTE_1   (AR9170_USB_REG_BASE + 0x012)

Definition at line 540 of file hw.h.

#define AR9170_USB_REG_INTR_MASK_BYTE_2   (AR9170_USB_REG_BASE + 0x013)

Definition at line 541 of file hw.h.

#define AR9170_USB_REG_INTR_MASK_BYTE_3   (AR9170_USB_REG_BASE + 0x014)

Definition at line 542 of file hw.h.

#define AR9170_USB_REG_INTR_MASK_BYTE_4   (AR9170_USB_REG_BASE + 0x015)

Definition at line 543 of file hw.h.

#define AR9170_USB_REG_INTR_MASK_BYTE_5   (AR9170_USB_REG_BASE + 0x016)

Definition at line 546 of file hw.h.

#define AR9170_USB_REG_INTR_MASK_BYTE_6   (AR9170_USB_REG_BASE + 0x017)

Definition at line 547 of file hw.h.

#define AR9170_USB_REG_INTR_MASK_BYTE_7   (AR9170_USB_REG_BASE + 0x018)

Definition at line 550 of file hw.h.

#define AR9170_USB_REG_INTR_SOURCE_0   (AR9170_USB_REG_BASE + 0x021)

Definition at line 554 of file hw.h.

#define AR9170_USB_REG_INTR_SOURCE_1   (AR9170_USB_REG_BASE + 0x022)

Definition at line 562 of file hw.h.

#define AR9170_USB_REG_INTR_SOURCE_2   (AR9170_USB_REG_BASE + 0x023)

Definition at line 563 of file hw.h.

#define AR9170_USB_REG_INTR_SOURCE_3   (AR9170_USB_REG_BASE + 0x024)

Definition at line 564 of file hw.h.

#define AR9170_USB_REG_INTR_SOURCE_4   (AR9170_USB_REG_BASE + 0x025)

Definition at line 565 of file hw.h.

#define AR9170_USB_REG_INTR_SOURCE_5   (AR9170_USB_REG_BASE + 0x026)

Definition at line 566 of file hw.h.

#define AR9170_USB_REG_INTR_SOURCE_6   (AR9170_USB_REG_BASE + 0x027)

Definition at line 567 of file hw.h.

#define AR9170_USB_REG_INTR_SOURCE_7   (AR9170_USB_REG_BASE + 0x028)

Definition at line 568 of file hw.h.

#define AR9170_USB_REG_MAIN_CTRL   (AR9170_USB_REG_BASE + 0x000)

Definition at line 521 of file hw.h.

#define AR9170_USB_REG_MAX_AGG_UPLOAD   (AR9170_USB_REG_BASE + 0x110)

Definition at line 651 of file hw.h.

#define AR9170_USB_REG_PHY_TEST_SELECT   (AR9170_USB_REG_BASE + 0x008)

Definition at line 533 of file hw.h.

#define AR9170_USB_REG_TEST   (AR9170_USB_REG_BASE + 0x002)

Definition at line 532 of file hw.h.

#define AR9170_USB_REG_UPLOAD_TIME_CTL   (AR9170_USB_REG_BASE + 0x114)

Definition at line 652 of file hw.h.

#define AR9170_USB_REG_WAKE_UP   (AR9170_USB_REG_BASE + 0x120)

Definition at line 654 of file hw.h.

#define AR9170_USB_WAKE_UP_WAKE   BIT(0)

Definition at line 655 of file hw.h.

#define CARL9170_PRETBTT_KUS   6

Definition at line 801 of file hw.h.

#define GET_VAL (   reg,
  value 
)    (((value) & reg) >> reg##_S)

Definition at line 814 of file hw.h.

#define MOD_VAL (   reg,
  value,
  newvalue 
)    (((value) & ~reg) | (((newvalue) << reg##_S) & reg))

Definition at line 811 of file hw.h.

#define SET_CONSTVAL (   reg,
  newvalue 
)    (((newvalue) << reg##_S) & reg)

Definition at line 808 of file hw.h.

#define SET_VAL (   reg,
  value,
  newvalue 
)    (value = ((value) & ~reg) | (((newvalue) << reg##_S) & reg))

Definition at line 805 of file hw.h.

Enumeration Type Documentation

enum ar9170_tx_queues
Enumerator:
AR9170_TXQ0 
AR9170_TXQ1 
AR9170_TXQ2 
AR9170_TXQ3 
AR9170_TXQ_SPECIAL 
__AR9170_NUM_TX_QUEUES 

Definition at line 768 of file hw.h.

enum ar9170_usb_ep
Enumerator:
AR9170_USB_EP_CTRL 
AR9170_USB_EP_TX 
AR9170_USB_EP_RX 
AR9170_USB_EP_IRQ 
AR9170_USB_EP_CMD 
AR9170_USB_NUM_EXTRA_EP 
__AR9170_USB_NUM_EP 
__AR9170_USB_NUM_MAX_EP 

Definition at line 743 of file hw.h.

enum ar9170_usb_fifo
Enumerator:
__AR9170_USB_NUM_MAX_FIFO 

Definition at line 764 of file hw.h.

enum cpu_clock
Enumerator:
AHB_STATIC_40MHZ 
AHB_GMODE_22MHZ 
AHB_AMODE_20MHZ 
AHB_GMODE_44MHZ 
AHB_AMODE_40MHZ 
AHB_GMODE_88MHZ 
AHB_AMODE_80MHZ 

Definition at line 732 of file hw.h.

Function Documentation

struct ar9170_stream __aligned ( 4  )

Variable Documentation

__le16 length

Definition at line 789 of file hw.h.

u8 payload[0]

Definition at line 792 of file hw.h.

__le16 tag

Definition at line 790 of file hw.h.

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