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| #define ASC_DRV2_SEL 0x02 /* Logical Drive Exchange controlled by TDR */ |
| #define ASC_LPT_IRQ7 0x01 /* Always use IRQ7 for LPT */ |
| #define ASC_RESERVED 0x18 |
| #define CS0CF0_RESERVED 0x00 |
| #define CS0CF1_RESERVED 0x08 |
| #define CS1CF0_RESERVED 0x00 |
| #define CS1CF1_RESERVED 0x08 |
| #define FAR_LPT_MASK 0x03 |
| #define FAR_RESERVED 0x00 |
| #define FCR_LDE 0x10 /* Logical Drive Exchange */ |
| #define FCR_RESERVED 0xc4 |
| #define FCR_ZWS_ENA 0x20 /* Enable short host read/write in ECP/EPP */ |
| #define FER_EDM 0x10 /* Encoded Drive and Motor pin information */ |
| #define FER_RESERVED 0x00 |
| #define KRR_RESERVED 0x00 |
| #define PCR_ECP_CLK_ENA 0x08 /* If 0 ECP Clock is stopped on Power down */ |
| #define PCR_ECP_ENABLE 0x04 |
| #define PCR_EPP_ENABLE 0x01 |
| #define PCR_EPP_IEEE 0x02 /* Enable EPP Version 1.9 (IEEE 1284) */ |
| #define PCR_IRQ_ODRAIN 0x40 /* If 1, IRQ is open drain */ |
| #define PCR_IRQ_POLAR 0x20 /* If 0 IRQ is level high or negative pulse, */ |
| #define PCR_RESERVED 0x10 |
| #define PMC_RESERVED 0x98 |
| #define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */ |
| #define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controls direction */ |
| #define PTR_LPTB_IRQ7 0x08 |
| #define PTR_RESERVED 0x73 |
| #define SIP_RESERVED 0x00 |
| #define TUP_EPP_TIMO 0x02 /* Enable EPP timeout IRQ */ |
| #define TUP_RESERVED 0xfb |
1.8.2