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Data Structures | Macros | Typedefs
nsc-ircc.h File Reference
#include <linux/time.h>
#include <linux/spinlock.h>
#include <linux/pm.h>
#include <linux/types.h>
#include <asm/io.h>

Go to the source code of this file.

Data Structures

struct  nsc_chip
 
struct  st_fifo_entry
 
struct  st_fifo
 
struct  frame_cb
 
struct  tx_fifo
 
struct  nsc_ircc_cb
 

Macros

#define NSC_FORCE_DONGLE_TYPE9   0x00000001
 
#define DMA_TX_MODE   0x08 /* Mem to I/O, ++, demand. */
 
#define DMA_RX_MODE   0x04 /* I/O to mem, ++, demand. */
 
#define CFG_108_BAIC   0x00
 
#define CFG_108_CSRT   0x01
 
#define CFG_108_MCTL   0x02
 
#define CFG_338_FER   0x00
 
#define CFG_338_FAR   0x01
 
#define CFG_338_PTR   0x02
 
#define CFG_338_PNP0   0x1b
 
#define CFG_338_PNP1   0x1c
 
#define CFG_338_PNP3   0x4f
 
#define CFG_39X_LDN   0x07 /* Logical device number (Super I/O bank) */
 
#define CFG_39X_SIOCF1   0x21 /* SuperI/O Config */
 
#define CFG_39X_ACT   0x30 /* Device activation */
 
#define CFG_39X_BASEH   0x60 /* Device base address (high bits) */
 
#define CFG_39X_BASEL   0x61 /* Device base address (low bits) */
 
#define CFG_39X_IRQNUM   0x70 /* Interrupt number & wake up enable */
 
#define CFG_39X_IRQSEL   0x71 /* Interrupt select (edge/level + polarity) */
 
#define CFG_39X_DMA0   0x74 /* DMA 0 configuration */
 
#define CFG_39X_DMA1   0x75 /* DMA 1 configuration */
 
#define CFG_39X_SPC   0xF0 /* Serial port configuration register */
 
#define APEDCRC   0x02
 
#define ENBNKSEL   0x01
 
#define TXD   0x00 /* Transmit data port */
 
#define RXD   0x00 /* Receive data port */
 
#define IER   0x01 /* Interrupt Enable Register*/
 
#define IER_RXHDL_IE   0x01 /* Receiver high data level interrupt */
 
#define IER_TXLDL_IE   0x02 /* Transeiver low data level interrupt */
 
#define IER_LS_IE   0x04
 
#define IER_ETXURI   0x04 /* Tx underrun */
 
#define IER_DMA_IE   0x10 /* DMA finished interrupt */
 
#define IER_TXEMP_IE   0x20
 
#define IER_SFIF_IE   0x40 /* Frame status FIFO intr */
 
#define IER_TMR_IE   0x80 /* Timer event */
 
#define FCR   0x02 /* (write only) */
 
#define FCR_FIFO_EN   0x01 /* Enable FIFO's */
 
#define FCR_RXSR   0x02 /* Rx FIFO soft reset */
 
#define FCR_TXSR   0x04 /* Tx FIFO soft reset */
 
#define FCR_RXTH   0x40 /* Rx FIFO threshold (set to 16) */
 
#define FCR_TXTH   0x20 /* Tx FIFO threshold (set to 17) */
 
#define EIR   0x02 /* (read only) */
 
#define EIR_RXHDL_EV   0x01
 
#define EIR_TXLDL_EV   0x02
 
#define EIR_LS_EV   0x04
 
#define EIR_DMA_EV   0x10
 
#define EIR_TXEMP_EV   0x20
 
#define EIR_SFIF_EV   0x40
 
#define EIR_TMR_EV   0x80
 
#define LCR   0x03 /* Link control register */
 
#define LCR_WLS_8   0x03 /* 8 bits */
 
#define BSR   0x03 /* Bank select register */
 
#define BSR_BKSE   0x80
 
#define BANK0   LCR_WLS_8 /* Must make sure that we set 8N1 */
 
#define BANK1   0x80
 
#define BANK2   0xe0
 
#define BANK3   0xe4
 
#define BANK4   0xe8
 
#define BANK5   0xec
 
#define BANK6   0xf0
 
#define BANK7   0xf4
 
#define MCR   0x04 /* Mode Control Register */
 
#define MCR_MODE_MASK   ~(0xd0)
 
#define MCR_UART   0x00
 
#define MCR_RESERVED   0x20
 
#define MCR_SHARP_IR   0x40
 
#define MCR_SIR   0x60
 
#define MCR_MIR   0x80
 
#define MCR_FIR   0xa0
 
#define MCR_CEIR   0xb0
 
#define MCR_IR_PLS   0x10
 
#define MCR_DMA_EN   0x04
 
#define MCR_EN_IRQ   0x08
 
#define MCR_TX_DFR   0x08
 
#define LSR   0x05 /* Link status register */
 
#define LSR_RXDA   0x01 /* Receiver data available */
 
#define LSR_TXRDY   0x20 /* Transmitter ready */
 
#define LSR_TXEMP   0x40 /* Transmitter empty */
 
#define ASCR   0x07 /* Auxiliary Status and Control Register */
 
#define ASCR_RXF_TOUT   0x01 /* Rx FIFO timeout */
 
#define ASCR_FEND_INF   0x02 /* Frame end bytes in rx FIFO */
 
#define ASCR_S_EOT   0x04 /* Set end of transmission */
 
#define ASCT_RXBSY   0x20 /* Rx busy */
 
#define ASCR_TXUR   0x40 /* Transeiver underrun */
 
#define ASCR_CTE   0x80 /* Clear timer event */
 
#define BGDL   0x00 /* Baud Generator Divisor Port (Low Byte) */
 
#define BGDH   0x01 /* Baud Generator Divisor Port (High Byte) */
 
#define ECR1   0x02 /* Extended Control Register 1 */
 
#define ECR1_EXT_SL   0x01 /* Extended Mode Select */
 
#define ECR1_DMANF   0x02 /* DMA Fairness */
 
#define ECR1_DMATH   0x04 /* DMA Threshold */
 
#define ECR1_DMASWP   0x08 /* DMA Swap */
 
#define EXCR2   0x04
 
#define EXCR2_TFSIZ   0x01 /* Rx FIFO size = 32 */
 
#define EXCR2_RFSIZ   0x04 /* Tx FIFO size = 32 */
 
#define TXFLV   0x06 /* Tx FIFO level */
 
#define RXFLV   0x07 /* Rx FIFO level */
 
#define MID   0x00
 
#define TMRL   0x00 /* Timer low byte */
 
#define TMRH   0x01 /* Timer high byte */
 
#define IRCR1   0x02 /* Infrared control register 1 */
 
#define IRCR1_TMR_EN   0x01 /* Timer enable */
 
#define TFRLL   0x04
 
#define TFRLH   0x05
 
#define RFRLL   0x06
 
#define RFRLH   0x07
 
#define IRCR2   0x04 /* Infrared control register 2 */
 
#define IRCR2_MDRS   0x04 /* MIR data rate select */
 
#define IRCR2_FEND_MD   0x20 /* */
 
#define FRM_ST   0x05 /* Frame status FIFO */
 
#define FRM_ST_VLD   0x80 /* Frame status FIFO data valid */
 
#define FRM_ST_ERR_MSK   0x5f
 
#define FRM_ST_LOST_FR   0x40 /* Frame lost */
 
#define FRM_ST_MAX_LEN   0x10 /* Max frame len exceeded */
 
#define FRM_ST_PHY_ERR   0x08 /* Physical layer error */
 
#define FRM_ST_BAD_CRC   0x04
 
#define FRM_ST_OVR1   0x02 /* Rx FIFO overrun */
 
#define FRM_ST_OVR2   0x01 /* Frame status FIFO overrun */
 
#define RFLFL   0x06
 
#define RFLFH   0x07
 
#define IR_CFG2   0x00
 
#define IR_CFG2_DIS_CRC   0x02
 
#define IRM_CR   0x07 /* Infrared module control register */
 
#define IRM_CR_IRX_MSL   0x40
 
#define IRM_CR_AF_MNT   0x80 /* Automatic format */
 
#define MAX_TX_WINDOW   7
 
#define MAX_RX_WINDOW   7
 

Typedefs

typedef struct nsc_chip nsc_chip_t
 

Macro Definition Documentation

#define APEDCRC   0x02

Definition at line 71 of file nsc-ircc.h.

#define ASCR   0x07 /* Auxiliary Status and Control Register */

Definition at line 138 of file nsc-ircc.h.

#define ASCR_CTE   0x80 /* Clear timer event */

Definition at line 144 of file nsc-ircc.h.

#define ASCR_FEND_INF   0x02 /* Frame end bytes in rx FIFO */

Definition at line 140 of file nsc-ircc.h.

#define ASCR_RXF_TOUT   0x01 /* Rx FIFO timeout */

Definition at line 139 of file nsc-ircc.h.

#define ASCR_S_EOT   0x04 /* Set end of transmission */

Definition at line 141 of file nsc-ircc.h.

#define ASCR_TXUR   0x40 /* Transeiver underrun */

Definition at line 143 of file nsc-ircc.h.

#define ASCT_RXBSY   0x20 /* Rx busy */

Definition at line 142 of file nsc-ircc.h.

#define BANK0   LCR_WLS_8 /* Must make sure that we set 8N1 */

Definition at line 110 of file nsc-ircc.h.

#define BANK1   0x80

Definition at line 111 of file nsc-ircc.h.

#define BANK2   0xe0

Definition at line 112 of file nsc-ircc.h.

#define BANK3   0xe4

Definition at line 113 of file nsc-ircc.h.

#define BANK4   0xe8

Definition at line 114 of file nsc-ircc.h.

#define BANK5   0xec

Definition at line 115 of file nsc-ircc.h.

#define BANK6   0xf0

Definition at line 116 of file nsc-ircc.h.

#define BANK7   0xf4

Definition at line 117 of file nsc-ircc.h.

#define BGDH   0x01 /* Baud Generator Divisor Port (High Byte) */

Definition at line 148 of file nsc-ircc.h.

#define BGDL   0x00 /* Baud Generator Divisor Port (Low Byte) */

Definition at line 147 of file nsc-ircc.h.

#define BSR   0x03 /* Bank select register */

Definition at line 108 of file nsc-ircc.h.

#define BSR_BKSE   0x80

Definition at line 109 of file nsc-ircc.h.

#define CFG_108_BAIC   0x00

Definition at line 46 of file nsc-ircc.h.

#define CFG_108_CSRT   0x01

Definition at line 47 of file nsc-ircc.h.

#define CFG_108_MCTL   0x02

Definition at line 48 of file nsc-ircc.h.

#define CFG_338_FAR   0x01

Definition at line 52 of file nsc-ircc.h.

#define CFG_338_FER   0x00

Definition at line 51 of file nsc-ircc.h.

#define CFG_338_PNP0   0x1b

Definition at line 54 of file nsc-ircc.h.

#define CFG_338_PNP1   0x1c

Definition at line 55 of file nsc-ircc.h.

#define CFG_338_PNP3   0x4f

Definition at line 56 of file nsc-ircc.h.

#define CFG_338_PTR   0x02

Definition at line 53 of file nsc-ircc.h.

#define CFG_39X_ACT   0x30 /* Device activation */

Definition at line 61 of file nsc-ircc.h.

#define CFG_39X_BASEH   0x60 /* Device base address (high bits) */

Definition at line 62 of file nsc-ircc.h.

#define CFG_39X_BASEL   0x61 /* Device base address (low bits) */

Definition at line 63 of file nsc-ircc.h.

#define CFG_39X_DMA0   0x74 /* DMA 0 configuration */

Definition at line 66 of file nsc-ircc.h.

#define CFG_39X_DMA1   0x75 /* DMA 1 configuration */

Definition at line 67 of file nsc-ircc.h.

#define CFG_39X_IRQNUM   0x70 /* Interrupt number & wake up enable */

Definition at line 64 of file nsc-ircc.h.

#define CFG_39X_IRQSEL   0x71 /* Interrupt select (edge/level + polarity) */

Definition at line 65 of file nsc-ircc.h.

#define CFG_39X_LDN   0x07 /* Logical device number (Super I/O bank) */

Definition at line 59 of file nsc-ircc.h.

#define CFG_39X_SIOCF1   0x21 /* SuperI/O Config */

Definition at line 60 of file nsc-ircc.h.

#define CFG_39X_SPC   0xF0 /* Serial port configuration register */

Definition at line 68 of file nsc-ircc.h.

#define DMA_RX_MODE   0x04 /* I/O to mem, ++, demand. */

Definition at line 43 of file nsc-ircc.h.

#define DMA_TX_MODE   0x08 /* Mem to I/O, ++, demand. */

Definition at line 42 of file nsc-ircc.h.

#define ECR1   0x02 /* Extended Control Register 1 */

Definition at line 150 of file nsc-ircc.h.

#define ECR1_DMANF   0x02 /* DMA Fairness */

Definition at line 152 of file nsc-ircc.h.

#define ECR1_DMASWP   0x08 /* DMA Swap */

Definition at line 154 of file nsc-ircc.h.

#define ECR1_DMATH   0x04 /* DMA Threshold */

Definition at line 153 of file nsc-ircc.h.

#define ECR1_EXT_SL   0x01 /* Extended Mode Select */

Definition at line 151 of file nsc-ircc.h.

#define EIR   0x02 /* (read only) */

Definition at line 96 of file nsc-ircc.h.

#define EIR_DMA_EV   0x10

Definition at line 100 of file nsc-ircc.h.

#define EIR_LS_EV   0x04

Definition at line 99 of file nsc-ircc.h.

#define EIR_RXHDL_EV   0x01

Definition at line 97 of file nsc-ircc.h.

#define EIR_SFIF_EV   0x40

Definition at line 102 of file nsc-ircc.h.

#define EIR_TMR_EV   0x80

Definition at line 103 of file nsc-ircc.h.

#define EIR_TXEMP_EV   0x20

Definition at line 101 of file nsc-ircc.h.

#define EIR_TXLDL_EV   0x02

Definition at line 98 of file nsc-ircc.h.

#define ENBNKSEL   0x01

Definition at line 72 of file nsc-ircc.h.

#define EXCR2   0x04

Definition at line 156 of file nsc-ircc.h.

#define EXCR2_RFSIZ   0x04 /* Tx FIFO size = 32 */

Definition at line 158 of file nsc-ircc.h.

#define EXCR2_TFSIZ   0x01 /* Rx FIFO size = 32 */

Definition at line 157 of file nsc-ircc.h.

#define FCR   0x02 /* (write only) */

Definition at line 89 of file nsc-ircc.h.

#define FCR_FIFO_EN   0x01 /* Enable FIFO's */

Definition at line 90 of file nsc-ircc.h.

#define FCR_RXSR   0x02 /* Rx FIFO soft reset */

Definition at line 91 of file nsc-ircc.h.

#define FCR_RXTH   0x40 /* Rx FIFO threshold (set to 16) */

Definition at line 93 of file nsc-ircc.h.

#define FCR_TXSR   0x04 /* Tx FIFO soft reset */

Definition at line 92 of file nsc-ircc.h.

#define FCR_TXTH   0x20 /* Tx FIFO threshold (set to 17) */

Definition at line 94 of file nsc-ircc.h.

#define FRM_ST   0x05 /* Frame status FIFO */

Definition at line 182 of file nsc-ircc.h.

#define FRM_ST_BAD_CRC   0x04

Definition at line 188 of file nsc-ircc.h.

#define FRM_ST_ERR_MSK   0x5f

Definition at line 184 of file nsc-ircc.h.

#define FRM_ST_LOST_FR   0x40 /* Frame lost */

Definition at line 185 of file nsc-ircc.h.

#define FRM_ST_MAX_LEN   0x10 /* Max frame len exceeded */

Definition at line 186 of file nsc-ircc.h.

#define FRM_ST_OVR1   0x02 /* Rx FIFO overrun */

Definition at line 189 of file nsc-ircc.h.

#define FRM_ST_OVR2   0x01 /* Frame status FIFO overrun */

Definition at line 190 of file nsc-ircc.h.

#define FRM_ST_PHY_ERR   0x08 /* Physical layer error */

Definition at line 187 of file nsc-ircc.h.

#define FRM_ST_VLD   0x80 /* Frame status FIFO data valid */

Definition at line 183 of file nsc-ircc.h.

#define IER   0x01 /* Interrupt Enable Register*/

Definition at line 79 of file nsc-ircc.h.

#define IER_DMA_IE   0x10 /* DMA finished interrupt */

Definition at line 84 of file nsc-ircc.h.

#define IER_ETXURI   0x04 /* Tx underrun */

Definition at line 83 of file nsc-ircc.h.

#define IER_LS_IE   0x04

Definition at line 82 of file nsc-ircc.h.

#define IER_RXHDL_IE   0x01 /* Receiver high data level interrupt */

Definition at line 80 of file nsc-ircc.h.

#define IER_SFIF_IE   0x40 /* Frame status FIFO intr */

Definition at line 86 of file nsc-ircc.h.

#define IER_TMR_IE   0x80 /* Timer event */

Definition at line 87 of file nsc-ircc.h.

#define IER_TXEMP_IE   0x20

Definition at line 85 of file nsc-ircc.h.

#define IER_TXLDL_IE   0x02 /* Transeiver low data level interrupt */

Definition at line 81 of file nsc-ircc.h.

#define IR_CFG2   0x00

Definition at line 196 of file nsc-ircc.h.

#define IR_CFG2_DIS_CRC   0x02

Definition at line 197 of file nsc-ircc.h.

#define IRCR1   0x02 /* Infrared control register 1 */

Definition at line 169 of file nsc-ircc.h.

#define IRCR1_TMR_EN   0x01 /* Timer enable */

Definition at line 170 of file nsc-ircc.h.

#define IRCR2   0x04 /* Infrared control register 2 */

Definition at line 178 of file nsc-ircc.h.

#define IRCR2_FEND_MD   0x20 /* */

Definition at line 180 of file nsc-ircc.h.

#define IRCR2_MDRS   0x04 /* MIR data rate select */

Definition at line 179 of file nsc-ircc.h.

#define IRM_CR   0x07 /* Infrared module control register */

Definition at line 200 of file nsc-ircc.h.

#define IRM_CR_AF_MNT   0x80 /* Automatic format */

Definition at line 202 of file nsc-ircc.h.

#define IRM_CR_IRX_MSL   0x40

Definition at line 201 of file nsc-ircc.h.

#define LCR   0x03 /* Link control register */

Definition at line 105 of file nsc-ircc.h.

#define LCR_WLS_8   0x03 /* 8 bits */

Definition at line 106 of file nsc-ircc.h.

#define LSR   0x05 /* Link status register */

Definition at line 133 of file nsc-ircc.h.

#define LSR_RXDA   0x01 /* Receiver data available */

Definition at line 134 of file nsc-ircc.h.

#define LSR_TXEMP   0x40 /* Transmitter empty */

Definition at line 136 of file nsc-ircc.h.

#define LSR_TXRDY   0x20 /* Transmitter ready */

Definition at line 135 of file nsc-ircc.h.

#define MAX_RX_WINDOW   7

Definition at line 225 of file nsc-ircc.h.

#define MAX_TX_WINDOW   7

Definition at line 224 of file nsc-ircc.h.

#define MCR   0x04 /* Mode Control Register */

Definition at line 119 of file nsc-ircc.h.

#define MCR_CEIR   0xb0

Definition at line 127 of file nsc-ircc.h.

#define MCR_DMA_EN   0x04

Definition at line 129 of file nsc-ircc.h.

#define MCR_EN_IRQ   0x08

Definition at line 130 of file nsc-ircc.h.

#define MCR_FIR   0xa0

Definition at line 126 of file nsc-ircc.h.

#define MCR_IR_PLS   0x10

Definition at line 128 of file nsc-ircc.h.

#define MCR_MIR   0x80

Definition at line 125 of file nsc-ircc.h.

#define MCR_MODE_MASK   ~(0xd0)

Definition at line 120 of file nsc-ircc.h.

#define MCR_RESERVED   0x20

Definition at line 122 of file nsc-ircc.h.

#define MCR_SHARP_IR   0x40

Definition at line 123 of file nsc-ircc.h.

#define MCR_SIR   0x60

Definition at line 124 of file nsc-ircc.h.

#define MCR_TX_DFR   0x08

Definition at line 131 of file nsc-ircc.h.

#define MCR_UART   0x00

Definition at line 121 of file nsc-ircc.h.

#define MID   0x00

Definition at line 164 of file nsc-ircc.h.

#define NSC_FORCE_DONGLE_TYPE9   0x00000001

Definition at line 39 of file nsc-ircc.h.

#define RFLFH   0x07

Definition at line 193 of file nsc-ircc.h.

#define RFLFL   0x06

Definition at line 192 of file nsc-ircc.h.

#define RFRLH   0x07

Definition at line 175 of file nsc-ircc.h.

#define RFRLL   0x06

Definition at line 174 of file nsc-ircc.h.

#define RXD   0x00 /* Receive data port */

Definition at line 76 of file nsc-ircc.h.

#define RXFLV   0x07 /* Rx FIFO level */

Definition at line 161 of file nsc-ircc.h.

#define TFRLH   0x05

Definition at line 173 of file nsc-ircc.h.

#define TFRLL   0x04

Definition at line 172 of file nsc-ircc.h.

#define TMRH   0x01 /* Timer high byte */

Definition at line 168 of file nsc-ircc.h.

#define TMRL   0x00 /* Timer low byte */

Definition at line 167 of file nsc-ircc.h.

#define TXD   0x00 /* Transmit data port */

Definition at line 75 of file nsc-ircc.h.

#define TXFLV   0x06 /* Tx FIFO level */

Definition at line 160 of file nsc-ircc.h.

Typedef Documentation

Definition at line 216 of file nsc-ircc.h.