|
| enum | {
OCRDMA_CMD_QUERY_CONFIG = 1,
OCRDMA_CMD_ALLOC_PD,
OCRDMA_CMD_DEALLOC_PD,
OCRDMA_CMD_CREATE_AH_TBL,
OCRDMA_CMD_DELETE_AH_TBL,
OCRDMA_CMD_CREATE_QP,
OCRDMA_CMD_QUERY_QP,
OCRDMA_CMD_MODIFY_QP,
OCRDMA_CMD_DELETE_QP,
OCRDMA_CMD_RSVD1,
OCRDMA_CMD_ALLOC_LKEY,
OCRDMA_CMD_DEALLOC_LKEY,
OCRDMA_CMD_REGISTER_NSMR,
OCRDMA_CMD_REREGISTER_NSMR,
OCRDMA_CMD_REGISTER_NSMR_CONT,
OCRDMA_CMD_QUERY_NSMR,
OCRDMA_CMD_ALLOC_MW,
OCRDMA_CMD_QUERY_MW,
OCRDMA_CMD_CREATE_SRQ,
OCRDMA_CMD_QUERY_SRQ,
OCRDMA_CMD_MODIFY_SRQ,
OCRDMA_CMD_DELETE_SRQ,
OCRDMA_CMD_ATTACH_MCAST,
OCRDMA_CMD_DETACH_MCAST,
OCRDMA_CMD_MAX
} |
| |
| enum | {
OCRDMA_CMD_CREATE_CQ = 12,
OCRDMA_CMD_CREATE_EQ = 13,
OCRDMA_CMD_CREATE_MQ = 21,
OCRDMA_CMD_GET_FW_VER = 35,
OCRDMA_CMD_DELETE_MQ = 53,
OCRDMA_CMD_DELETE_CQ = 54,
OCRDMA_CMD_DELETE_EQ = 55,
OCRDMA_CMD_GET_FW_CONFIG = 58,
OCRDMA_CMD_CREATE_MQ_EXT = 90
} |
| |
| enum | { QTYPE_EQ = 1,
QTYPE_CQ = 2,
QTYPE_MCCQ = 3
} |
| |
| enum | {
OCRDMA_DB_RQ_OFFSET = 0xE0,
OCRDMA_DB_GEN2_RQ1_OFFSET = 0x100,
OCRDMA_DB_GEN2_RQ2_OFFSET = 0xC0,
OCRDMA_DB_SQ_OFFSET = 0x60,
OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0,
OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET,
OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ1_OFFSET,
OCRDMA_DB_CQ_OFFSET = 0x120,
OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET,
OCRDMA_DB_MQ_OFFSET = 0x140
} |
| |
| enum | { OCRDMA_MCH_OPCODE_SHIFT = 0,
OCRDMA_MCH_OPCODE_MASK = 0xFF,
OCRDMA_MCH_SUBSYS_SHIFT = 8,
OCRDMA_MCH_SUBSYS_MASK = 0xFF00
} |
| |
| enum | {
OCRDMA_MBX_RSP_OPCODE_SHIFT = 0,
OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF,
OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8,
OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,
OCRDMA_MBX_RSP_STATUS_SHIFT = 0,
OCRDMA_MBX_RSP_STATUS_MASK = 0xFF,
OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8,
OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
} |
| |
| enum | { OCRDMA_MQE_EMBEDDED = 1,
OCRDMA_MQE_NONEMBEDDED = 0
} |
| |
| enum | {
OCRDMA_MQE_HDR_EMB_SHIFT = 0,
OCRDMA_MQE_HDR_EMB_MASK = Bit(0),
OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3,
OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24,
OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
} |
| |
| enum | { OCRDMA_CREATE_EQ_VALID = Bit(29),
OCRDMA_CREATE_EQ_CNT_SHIFT = 26,
OCRDMA_CREATE_CQ_DELAY_SHIFT = 13
} |
| |
| enum | {
OCRDMA_MCQE_STATUS_SHIFT = 0,
OCRDMA_MCQE_STATUS_MASK = 0xFFFF,
OCRDMA_MCQE_ESTATUS_SHIFT = 16,
OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
OCRDMA_MCQE_CONS_SHIFT = 27,
OCRDMA_MCQE_CONS_MASK = Bit(27),
OCRDMA_MCQE_CMPL_SHIFT = 28,
OCRDMA_MCQE_CMPL_MASK = Bit(28),
OCRDMA_MCQE_AE_SHIFT = 30,
OCRDMA_MCQE_AE_MASK = Bit(30),
OCRDMA_MCQE_VALID_SHIFT = 31,
OCRDMA_MCQE_VALID_MASK = Bit(31)
} |
| |
| enum | {
OCRDMA_AE_MCQE_QPVALID = Bit(31),
OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF,
OCRDMA_AE_MCQE_CQVALID = Bit(31),
OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF,
OCRDMA_AE_MCQE_VALID = Bit(31),
OCRDMA_AE_MCQE_AE = Bit(30),
OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
OCRDMA_AE_MCQE_EVENT_TYPE_MASK,
OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,
OCRDMA_AE_MCQE_EVENT_CODE_MASK
} |
| |
| enum | {
OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16,
OCRDMA_AE_MPA_MCQE_REQ_ID_MASK,
OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8,
OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK,
OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16,
OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK,
OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30,
OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = Bit(30),
OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31,
OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = Bit(31)
} |
| |
| enum | {
OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0,
OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF,
OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16,
OCRDMA_AE_QP_MCQE_QP_ID_MASK,
OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8,
OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK,
OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16,
OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK,
OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30,
OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = Bit(30),
OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31,
OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = Bit(31)
} |
| |
| enum | OCRDMA_ASYNC_EVENT_TYPE {
OCRDMA_CQ_ERROR = 0x00,
OCRDMA_CQ_OVERRUN_ERROR = 0x01,
OCRDMA_CQ_QPCAT_ERROR = 0x02,
OCRDMA_QP_ACCESS_ERROR = 0x03,
OCRDMA_QP_COMM_EST_EVENT = 0x04,
OCRDMA_SQ_DRAINED_EVENT = 0x05,
OCRDMA_DEVICE_FATAL_EVENT = 0x08,
OCRDMA_SRQCAT_ERROR = 0x0E,
OCRDMA_SRQ_LIMIT_EVENT = 0x0F,
OCRDMA_QP_LAST_WQE_EVENT = 0x10
} |
| |
| enum | {
OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2,
OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = Bit(2),
OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3,
OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = Bit(3),
OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8,
OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16,
OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK,
OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8,
OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0,
OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF,
OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT = 16,
OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0,
OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF,
OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16,
OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24,
OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16,
OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0,
OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16,
OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0,
OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16,
OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0,
OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0,
OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16,
OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0,
OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16,
OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0,
OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16,
OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK,
OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0,
OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK
} |
| |
| enum | { OCRDMA_FN_MODE_RDMA = 0x4
} |
| |
| enum | {
OCRDMA_CREATE_CQ_VER2 = 2,
OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF,
OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16,
OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF,
OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12,
OCRDMA_CREATE_CQ_COALESCWM_MASK = Bit(13) | Bit(12),
OCRDMA_CREATE_CQ_FLAGS_NODELAY = Bit(14),
OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = Bit(15),
OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF,
OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF
} |
| |
| enum | {
OCRDMA_CREATE_CQ_VER0 = 0,
OCRDMA_CREATE_CQ_DPP = 1,
OCRDMA_CREATE_CQ_TYPE_SHIFT = 24,
OCRDMA_CREATE_CQ_EQID_SHIFT = 22,
OCRDMA_CREATE_CQ_CNT_SHIFT = 27,
OCRDMA_CREATE_CQ_FLAGS_VALID = Bit(29),
OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = Bit(31),
OCRDMA_CREATE_CQ_DEF_FLAGS
} |
| |
| enum | { OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF
} |
| |
| enum | {
OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22,
OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16,
OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16,
OCRDMA_CREATE_MQ_VALID = Bit(31),
OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = Bit(0)
} |
| |
| enum | { OCRDMA_DESTROY_CQ_QID_SHIFT = 0,
OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF,
OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16,
OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK
} |
| |
| enum | { OCRDMA_QPT_GSI = 1,
OCRDMA_QPT_RC = 2,
OCRDMA_QPT_UD = 4
} |
| |
| enum | {
OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0,
OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF,
OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29,
OCRDMA_CREATE_QP_REQ_QPT_MASK = Bit(31) | Bit(30) | Bit(29),
OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0,
OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF,
OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16,
OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK,
OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0,
OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF,
OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16,
OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK,
OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0,
OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = Bit(0),
OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1,
OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = Bit(1),
OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2,
OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = Bit(2),
OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3,
OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = Bit(3),
OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4,
OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = Bit(4),
OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5,
OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = Bit(5),
OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6,
OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = Bit(6),
OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7,
OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = Bit(7),
OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8,
OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = Bit(8),
OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16,
OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK,
OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0,
OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF,
OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16,
OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK,
OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0,
OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF,
OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16,
OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK,
OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0,
OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF,
OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16,
OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK,
OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0,
OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF,
OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16,
OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK,
OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0,
OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF,
OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16,
OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK
} |
| |
| enum | { OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16,
OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1
} |
| |
| enum | ocrdma_qp_flags {
OCRDMA_QP_MW_BIND = 1,
OCRDMA_QP_LKEY0 = (1 << 1),
OCRDMA_QP_FAST_REG = (1 << 2),
OCRDMA_QP_INB_RD = (1 << 6),
OCRDMA_QP_INB_WR = (1 << 7)
} |
| |
| enum | ocrdma_qp_state {
OCRDMA_QPS_RST = 0,
OCRDMA_QPS_INIT = 1,
OCRDMA_QPS_RTR = 2,
OCRDMA_QPS_RTS = 3,
OCRDMA_QPS_SQE = 4,
OCRDMA_QPS_SQ_DRAINING = 5,
OCRDMA_QPS_ERR = 6,
OCRDMA_QPS_SQD = 7
} |
| |
| enum | {
OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0,
OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF,
OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0,
OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF,
OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16,
OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK,
OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0,
OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF,
OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16,
OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK,
OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16,
OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK,
OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0,
OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF,
OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16,
OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK,
OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0,
OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF,
OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16,
OCRDMA_CREATE_QP_RSP_SQ_ID_MASK,
OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = Bit(0),
OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1,
OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK,
OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16,
OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK
} |
| |
| enum | {
OCRDMA_MODIFY_QP_ID_SHIFT = 0,
OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF,
OCRDMA_QP_PARA_QPS_VALID = Bit(0),
OCRDMA_QP_PARA_SQD_ASYNC_VALID = Bit(1),
OCRDMA_QP_PARA_PKEY_VALID = Bit(2),
OCRDMA_QP_PARA_QKEY_VALID = Bit(3),
OCRDMA_QP_PARA_PMTU_VALID = Bit(4),
OCRDMA_QP_PARA_ACK_TO_VALID = Bit(5),
OCRDMA_QP_PARA_RETRY_CNT_VALID = Bit(6),
OCRDMA_QP_PARA_RRC_VALID = Bit(7),
OCRDMA_QP_PARA_RQPSN_VALID = Bit(8),
OCRDMA_QP_PARA_MAX_IRD_VALID = Bit(9),
OCRDMA_QP_PARA_MAX_ORD_VALID = Bit(10),
OCRDMA_QP_PARA_RNT_VALID = Bit(11),
OCRDMA_QP_PARA_SQPSN_VALID = Bit(12),
OCRDMA_QP_PARA_DST_QPN_VALID = Bit(13),
OCRDMA_QP_PARA_MAX_WQE_VALID = Bit(14),
OCRDMA_QP_PARA_MAX_RQE_VALID = Bit(15),
OCRDMA_QP_PARA_SGE_SEND_VALID = Bit(16),
OCRDMA_QP_PARA_SGE_RECV_VALID = Bit(17),
OCRDMA_QP_PARA_SGE_WR_VALID = Bit(18),
OCRDMA_QP_PARA_INB_RDEN_VALID = Bit(19),
OCRDMA_QP_PARA_INB_WREN_VALID = Bit(20),
OCRDMA_QP_PARA_FLOW_LBL_VALID = Bit(21),
OCRDMA_QP_PARA_BIND_EN_VALID = Bit(22),
OCRDMA_QP_PARA_ZLKEY_EN_VALID = Bit(23),
OCRDMA_QP_PARA_FMR_EN_VALID = Bit(24),
OCRDMA_QP_PARA_INBAT_EN_VALID = Bit(25),
OCRDMA_QP_PARA_VLAN_EN_VALID = Bit(26),
OCRDMA_MODIFY_QP_FLAGS_RD = Bit(0),
OCRDMA_MODIFY_QP_FLAGS_WR = Bit(1),
OCRDMA_MODIFY_QP_FLAGS_SEND = Bit(2),
OCRDMA_MODIFY_QP_FLAGS_ATOMIC = Bit(3)
} |
| |
| enum | {
OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0,
OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF,
OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0,
OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF,
OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16,
OCRDMA_QP_PARAMS_MAX_WQE_MASK,
OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0,
OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF,
OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16,
OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK,
OCRDMA_QP_PARAMS_FLAGS_FMR_EN = Bit(0),
OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = Bit(1),
OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = Bit(2),
OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = Bit(3),
OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = Bit(4),
OCRDMA_QP_PARAMS_STATE_SHIFT = 5,
OCRDMA_QP_PARAMS_STATE_MASK = Bit(5) | Bit(6) | Bit(7),
OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = Bit(8),
OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = Bit(9),
OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16,
OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK,
OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0,
OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF,
OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16,
OCRDMA_QP_PARAMS_MAX_ORD_MASK,
OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0,
OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF,
OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16,
OCRDMA_QP_PARAMS_WQ_CQID_MASK,
OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0,
OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF,
OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24,
OCRDMA_QP_PARAMS_HOP_LMT_MASK,
OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0,
OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF,
OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24,
OCRDMA_QP_PARAMS_TCLASS_MASK,
OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0,
OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF,
OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24,
OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK,
OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27,
OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK,
OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0,
OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF,
OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18,
OCRDMA_QP_PARAMS_PATH_MTU_MASK,
OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0,
OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF,
OCRDMA_QP_PARAMS_SL_SHIFT = 20,
OCRDMA_QP_PARAMS_SL_MASK,
OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24,
OCRDMA_QP_PARAMS_RETRY_CNT_MASK,
OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27,
OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK,
OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0,
OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF,
OCRDMA_QP_PARAMS_VLAN_SHIFT = 16,
OCRDMA_QP_PARAMS_VLAN_MASK
} |
| |
| enum | {
OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0,
OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF,
OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16,
OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK,
OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0,
OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF,
OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16,
OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK
} |
| |
| enum | {
OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0,
OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF,
OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16,
OCRDMA_CREATE_SRQ_PG_SZ_MASK,
OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0,
OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16,
OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK,
OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0,
OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF,
OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16,
OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK
} |
| |
| enum | {
OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0,
OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF,
OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0,
OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF,
OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16,
OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK
} |
| |
| enum | {
OCRDMA_MODIFY_SRQ_ID_SHIFT = 0,
OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF,
OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,
OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF,
OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16,
OCRDMA_MODIFY_SRQ__LIMIT_MASK
} |
| |
| enum | { OCRDMA_QUERY_SRQ_ID_SHIFT = 0,
OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF
} |
| |
| enum | {
OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0,
OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF,
OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16,
OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK,
OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,
OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF,
OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16,
OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK
} |
| |
| enum | { OCRDMA_DESTROY_SRQ_ID_SHIFT = 0,
OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF
} |
| |
| enum | { OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16),
OCRDMA_PD_MAX_DPP_ENABLED_QP = 8,
OCRDMA_DPP_PAGE_SIZE = 4096
} |
| |
| enum | { OCRDMA_ALLOC_PD_RSP_DPP = Bit(16),
OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20,
OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF
} |
| |
| enum | { OCRDMA_ADDR_CHECK_ENABLE = 1,
OCRDMA_ADDR_CHECK_DISABLE = 0
} |
| |
| enum | {
OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0,
OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF,
OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0,
OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = Bit(0),
OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1,
OCRDMA_ALLOC_LKEY_FMR_MASK = Bit(1),
OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2,
OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = Bit(2),
OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3,
OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = Bit(3),
OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4,
OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = Bit(4),
OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5,
OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = Bit(5),
OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = Bit(6),
OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6,
OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16,
OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK
} |
| |
| enum | {
OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0,
OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF,
OCRDMA_REG_NSMR_LRKEY_SHIFT = 24,
OCRDMA_REG_NSMR_LRKEY_MASK,
OCRDMA_REG_NSMR_PD_ID_SHIFT = 0,
OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF,
OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16,
OCRDMA_REG_NSMR_NUM_PBL_MASK,
OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0,
OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF,
OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16,
OCRDMA_REG_NSMR_HPAGE_SIZE_MASK,
OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24,
OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = Bit(24),
OCRDMA_REG_NSMR_ZB_SHIFT = 25,
OCRDMA_REG_NSMR_ZB_SHIFT_MASK = Bit(25),
OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26,
OCRDMA_REG_NSMR_REMOTE_INV_MASK = Bit(26),
OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27,
OCRDMA_REG_NSMR_REMOTE_WR_MASK = Bit(27),
OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28,
OCRDMA_REG_NSMR_REMOTE_RD_MASK = Bit(28),
OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29,
OCRDMA_REG_NSMR_LOCAL_WR_MASK = Bit(29),
OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30,
OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = Bit(30),
OCRDMA_REG_NSMR_LAST_SHIFT = 31,
OCRDMA_REG_NSMR_LAST_MASK = Bit(31)
} |
| |
| enum | {
OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0,
OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF,
OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16,
OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK,
OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31,
OCRDMA_REG_NSMR_CONT_LAST_MASK = Bit(31)
} |
| |
| enum | { OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16,
OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF0000
} |
| |
| enum | {
OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0,
OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF,
OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24,
OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK,
OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16,
OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK
} |
| |
| enum | { OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0,
OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF
} |
| |
| enum | { OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0,
OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF
} |
| |
| enum | {
OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19,
OCRDMA_CREATE_AH_NUM_PAGES_MASK,
OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16,
OCRDMA_CREATE_AH_PAGE_SIZE_MASK,
OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23,
OCRDMA_CREATE_AH_ENTRY_SIZE_MASK
} |
| |
| enum | {
OCRDMA_EQE_VALID_SHIFT = 0,
OCRDMA_EQE_VALID_MASK = Bit(0),
OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE,
OCRDMA_EQE_RESOURCE_ID_SHIFT = 16,
OCRDMA_EQE_RESOURCE_ID_MASK
} |
| |
| enum | OCRDMA_CQE_STATUS {
OCRDMA_CQE_SUCCESS = 0,
OCRDMA_CQE_LOC_LEN_ERR,
OCRDMA_CQE_LOC_QP_OP_ERR,
OCRDMA_CQE_LOC_EEC_OP_ERR,
OCRDMA_CQE_LOC_PROT_ERR,
OCRDMA_CQE_WR_FLUSH_ERR,
OCRDMA_CQE_MW_BIND_ERR,
OCRDMA_CQE_BAD_RESP_ERR,
OCRDMA_CQE_LOC_ACCESS_ERR,
OCRDMA_CQE_REM_INV_REQ_ERR,
OCRDMA_CQE_REM_ACCESS_ERR,
OCRDMA_CQE_REM_OP_ERR,
OCRDMA_CQE_RETRY_EXC_ERR,
OCRDMA_CQE_RNR_RETRY_EXC_ERR,
OCRDMA_CQE_LOC_RDD_VIOL_ERR,
OCRDMA_CQE_REM_INV_RD_REQ_ERR,
OCRDMA_CQE_REM_ABORT_ERR,
OCRDMA_CQE_INV_EECN_ERR,
OCRDMA_CQE_INV_EEC_STATE_ERR,
OCRDMA_CQE_FATAL_ERR,
OCRDMA_CQE_RESP_TIMEOUT_ERR,
OCRDMA_CQE_GENERAL_ERR
} |
| |
| enum | {
OCRDMA_CQE_WQEIDX_SHIFT = 0,
OCRDMA_CQE_WQEIDX_MASK = 0xFFFF,
OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16,
OCRDMA_CQE_PKEY_SHIFT = 0,
OCRDMA_CQE_PKEY_MASK = 0xFFFF,
OCRDMA_CQE_QPN_SHIFT = 0,
OCRDMA_CQE_QPN_MASK = 0x0000FFFF,
OCRDMA_CQE_BUFTAG_SHIFT = 16,
OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,
OCRDMA_CQE_UD_STATUS_SHIFT = 24,
OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
OCRDMA_CQE_STATUS_SHIFT = 16,
OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
OCRDMA_CQE_VALID = Bit(31),
OCRDMA_CQE_INVALIDATE = Bit(30),
OCRDMA_CQE_QTYPE = Bit(29),
OCRDMA_CQE_IMM = Bit(28),
OCRDMA_CQE_WRITE_IMM = Bit(27),
OCRDMA_CQE_QTYPE_SQ = 0,
OCRDMA_CQE_QTYPE_RQ = 1,
OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF
} |
| |
| enum | {
OCRDMA_FLAG_SIG = 0x1,
OCRDMA_FLAG_INV = 0x2,
OCRDMA_FLAG_FENCE_L = 0x4,
OCRDMA_FLAG_FENCE_R = 0x8,
OCRDMA_FLAG_SOLICIT = 0x10,
OCRDMA_FLAG_IMM = 0x20,
OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1,
OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2,
OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4,
OCRDMA_LKEY_FLAG_VATO = 0x8
} |
| |
| enum | OCRDMA_WQE_OPCODE {
OCRDMA_WRITE = 0x06,
OCRDMA_READ = 0x0C,
OCRDMA_RESV0 = 0x02,
OCRDMA_SEND = 0x00,
OCRDMA_CMP_SWP = 0x14,
OCRDMA_BIND_MW = 0x10,
OCRDMA_RESV1 = 0x0A,
OCRDMA_LKEY_INV = 0x15,
OCRDMA_FETCH_ADD = 0x13,
OCRDMA_POST_RQ = 0x12
} |
| |
| enum | { OCRDMA_TYPE_INLINE = 0x0,
OCRDMA_TYPE_LKEY = 0x1
} |
| |
| enum | {
OCRDMA_WQE_OPCODE_SHIFT = 0,
OCRDMA_WQE_OPCODE_MASK = 0x0000001F,
OCRDMA_WQE_FLAGS_SHIFT = 5,
OCRDMA_WQE_TYPE_SHIFT = 16,
OCRDMA_WQE_TYPE_MASK = 0x00030000,
OCRDMA_WQE_SIZE_SHIFT = 18,
OCRDMA_WQE_SIZE_MASK = 0xFF,
OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25,
OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0,
OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF
} |
| |
1.8.2