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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Data Structures | |
| struct | omap_req |
| struct | omap_ep |
| struct | omap_udc |
Macros | |
| #define | UDC_REV (UDC_BASE + 0x0) /* Revision */ |
| #define | UDC_EP_NUM (UDC_BASE + 0x4) /* Which endpoint */ |
| #define | UDC_SETUP_SEL (1 << 6) |
| #define | UDC_EP_SEL (1 << 5) |
| #define | UDC_EP_DIR (1 << 4) |
| #define | UDC_DATA (UDC_BASE + 0x08) /* Endpoint FIFO */ |
| #define | UDC_CTRL (UDC_BASE + 0x0C) /* Endpoint control */ |
| #define | UDC_CLR_HALT (1 << 7) |
| #define | UDC_SET_HALT (1 << 6) |
| #define | UDC_CLRDATA_TOGGLE (1 << 3) |
| #define | UDC_SET_FIFO_EN (1 << 2) |
| #define | UDC_CLR_EP (1 << 1) |
| #define | UDC_RESET_EP (1 << 0) |
| #define | UDC_STAT_FLG (UDC_BASE + 0x10) /* Endpoint status */ |
| #define | UDC_NO_RXPACKET (1 << 15) |
| #define | UDC_MISS_IN (1 << 14) |
| #define | UDC_DATA_FLUSH (1 << 13) |
| #define | UDC_ISO_ERR (1 << 12) |
| #define | UDC_ISO_FIFO_EMPTY (1 << 9) |
| #define | UDC_ISO_FIFO_FULL (1 << 8) |
| #define | UDC_EP_HALTED (1 << 6) |
| #define | UDC_STALL (1 << 5) |
| #define | UDC_NAK (1 << 4) |
| #define | UDC_ACK (1 << 3) |
| #define | UDC_FIFO_EN (1 << 2) |
| #define | UDC_NON_ISO_FIFO_EMPTY (1 << 1) |
| #define | UDC_NON_ISO_FIFO_FULL (1 << 0) |
| #define | UDC_RXFSTAT (UDC_BASE + 0x14) /* OUT bytecount */ |
| #define | UDC_SYSCON1 (UDC_BASE + 0x18) /* System config 1 */ |
| #define | UDC_CFG_LOCK (1 << 8) |
| #define | UDC_DATA_ENDIAN (1 << 7) |
| #define | UDC_DMA_ENDIAN (1 << 6) |
| #define | UDC_NAK_EN (1 << 4) |
| #define | UDC_AUTODECODE_DIS (1 << 3) |
| #define | UDC_SELF_PWR (1 << 2) |
| #define | UDC_SOFF_DIS (1 << 1) |
| #define | UDC_PULLUP_EN (1 << 0) |
| #define | UDC_SYSCON2 (UDC_BASE + 0x1C) /* System config 2 */ |
| #define | UDC_RMT_WKP (1 << 6) |
| #define | UDC_STALL_CMD (1 << 5) |
| #define | UDC_DEV_CFG (1 << 3) |
| #define | UDC_CLR_CFG (1 << 2) |
| #define | UDC_DEVSTAT (UDC_BASE + 0x20) /* Device status */ |
| #define | UDC_B_HNP_ENABLE (1 << 9) |
| #define | UDC_A_HNP_SUPPORT (1 << 8) |
| #define | UDC_A_ALT_HNP_SUPPORT (1 << 7) |
| #define | UDC_R_WK_OK (1 << 6) |
| #define | UDC_USB_RESET (1 << 5) |
| #define | UDC_SUS (1 << 4) |
| #define | UDC_CFG (1 << 3) |
| #define | UDC_ADD (1 << 2) |
| #define | UDC_DEF (1 << 1) |
| #define | UDC_ATT (1 << 0) |
| #define | UDC_SOF (UDC_BASE + 0x24) /* Start of frame */ |
| #define | UDC_FT_LOCK (1 << 12) |
| #define | UDC_TS_OK (1 << 11) |
| #define | UDC_TS 0x03ff |
| #define | UDC_IRQ_EN (UDC_BASE + 0x28) /* Interrupt enable */ |
| #define | UDC_SOF_IE (1 << 7) |
| #define | UDC_EPN_RX_IE (1 << 5) |
| #define | UDC_EPN_TX_IE (1 << 4) |
| #define | UDC_DS_CHG_IE (1 << 3) |
| #define | UDC_EP0_IE (1 << 0) |
| #define | UDC_DMA_IRQ_EN (UDC_BASE + 0x2C) /* DMA irq enable */ |
| #define | UDC_TX_DONE_IE(n) (1 << (4 * (n) - 2)) |
| #define | UDC_RX_CNT_IE(n) (1 << (4 * (n) - 3)) |
| #define | UDC_RX_EOT_IE(n) (1 << (4 * (n) - 4)) |
| #define | UDC_IRQ_SRC (UDC_BASE + 0x30) /* Interrupt source */ |
| #define | UDC_TXN_DONE (1 << 10) |
| #define | UDC_RXN_CNT (1 << 9) |
| #define | UDC_RXN_EOT (1 << 8) |
| #define | UDC_IRQ_SOF (1 << 7) |
| #define | UDC_EPN_RX (1 << 5) |
| #define | UDC_EPN_TX (1 << 4) |
| #define | UDC_DS_CHG (1 << 3) |
| #define | UDC_SETUP (1 << 2) |
| #define | UDC_EP0_RX (1 << 1) |
| #define | UDC_EP0_TX (1 << 0) |
| #define | UDC_IRQ_SRC_MASK 0x7bf |
| #define | UDC_EPN_STAT (UDC_BASE + 0x34) /* EP irq status */ |
| #define | UDC_DMAN_STAT (UDC_BASE + 0x38) /* DMA irq status */ |
| #define | UDC_DMA_RX_SB (1 << 12) |
| #define | UDC_DMA_RX_SRC(x) (((x)>>8) & 0xf) |
| #define | UDC_DMA_TX_SRC(x) (((x)>>0) & 0xf) |
| #define | UDC_RXDMA_CFG (UDC_BASE + 0x40) /* 3 eps for RX DMA */ |
| #define | UDC_DMA_REQ (1 << 12) |
| #define | UDC_TXDMA_CFG (UDC_BASE + 0x44) /* 3 eps for TX DMA */ |
| #define | UDC_DATA_DMA (UDC_BASE + 0x48) /* rx/tx fifo addr */ |
| #define | UDC_TXDMA(chan) (UDC_BASE + 0x50 - 4 + 4 * (chan)) |
| #define | UDC_TXN_EOT (1 << 15) /* bytes vs packets */ |
| #define | UDC_TXN_START (1 << 14) /* start transfer */ |
| #define | UDC_TXN_TSC 0x03ff /* units in xfer */ |
| #define | UDC_RXDMA(chan) (UDC_BASE + 0x60 - 4 + 4 * (chan)) |
| #define | UDC_RXN_STOP (1 << 15) /* enable EOT irq */ |
| #define | UDC_RXN_TC 0x00ff /* packets in xfer */ |
| #define | UDC_EP_RX(endpoint) (UDC_BASE + 0x80 + (endpoint)*4) |
| #define | UDC_EPN_RX_VALID (1 << 15) |
| #define | UDC_EPN_RX_DB (1 << 14) |
| #define | UDC_EPN_RX_ISO (1 << 11) |
| #define | UDC_EP_TX(endpoint) (UDC_BASE + 0xc0 + (endpoint)*4) |
| #define | VDBG(stuff...) do{}while(0) |
| #define | ERR(stuff...) pr_err("udc: " stuff) |
| #define | WARNING(stuff...) pr_warning("udc: " stuff) |
| #define | INFO(stuff...) pr_info("udc: " stuff) |
| #define | DBG(stuff...) pr_debug("udc: " stuff) |
| #define | VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */ |
| #define | VBUS_CTRL_1510 (1 << 19) /* 1 connected (software) */ |
| #define | VBUS_MODE_1510 (1 << 18) /* 0 hardware, 1 software */ |
| #define | HMC_1510 ((omap_readl(MOD_CONF_CTRL_0) >> 1) & 0x3f) |
| #define | HMC_1610 (omap_readl(OTG_SYSCON_2) & 0x3f) |
| #define | HMC (cpu_is_omap15xx() ? HMC_1510 : HMC_1610) |
| #define DBG | ( | stuff... | ) | pr_debug("udc: " stuff) |
Definition at line 192 of file omap_udc.h.
| #define ERR | ( | stuff... | ) | pr_err("udc: " stuff) |
Definition at line 189 of file omap_udc.h.
| #define HMC (cpu_is_omap15xx() ? HMC_1510 : HMC_1610) |
Definition at line 205 of file omap_udc.h.
| #define HMC_1510 ((omap_readl(MOD_CONF_CTRL_0) >> 1) & 0x3f) |
Definition at line 203 of file omap_udc.h.
| #define HMC_1610 (omap_readl(OTG_SYSCON_2) & 0x3f) |
Definition at line 204 of file omap_udc.h.
| #define INFO | ( | stuff... | ) | pr_info("udc: " stuff) |
Definition at line 191 of file omap_udc.h.
| #define UDC_A_ALT_HNP_SUPPORT (1 << 7) |
Definition at line 58 of file omap_udc.h.
| #define UDC_A_HNP_SUPPORT (1 << 8) |
Definition at line 57 of file omap_udc.h.
| #define UDC_ACK (1 << 3) |
Definition at line 36 of file omap_udc.h.
| #define UDC_ADD (1 << 2) |
Definition at line 63 of file omap_udc.h.
| #define UDC_ATT (1 << 0) |
Definition at line 65 of file omap_udc.h.
| #define UDC_AUTODECODE_DIS (1 << 3) |
Definition at line 46 of file omap_udc.h.
| #define UDC_B_HNP_ENABLE (1 << 9) |
Definition at line 56 of file omap_udc.h.
| #define UDC_CFG (1 << 3) |
Definition at line 62 of file omap_udc.h.
| #define UDC_CFG_LOCK (1 << 8) |
Definition at line 42 of file omap_udc.h.
| #define UDC_CLR_CFG (1 << 2) |
Definition at line 54 of file omap_udc.h.
| #define UDC_CLR_EP (1 << 1) |
Definition at line 24 of file omap_udc.h.
| #define UDC_CLR_HALT (1 << 7) |
Definition at line 20 of file omap_udc.h.
| #define UDC_CLRDATA_TOGGLE (1 << 3) |
Definition at line 22 of file omap_udc.h.
| #define UDC_CTRL (UDC_BASE + 0x0C) /* Endpoint control */ |
Definition at line 19 of file omap_udc.h.
| #define UDC_DATA (UDC_BASE + 0x08) /* Endpoint FIFO */ |
Definition at line 18 of file omap_udc.h.
| #define UDC_DATA_DMA (UDC_BASE + 0x48) /* rx/tx fifo addr */ |
Definition at line 104 of file omap_udc.h.
| #define UDC_DATA_ENDIAN (1 << 7) |
Definition at line 43 of file omap_udc.h.
| #define UDC_DATA_FLUSH (1 << 13) |
Definition at line 29 of file omap_udc.h.
| #define UDC_DEF (1 << 1) |
Definition at line 64 of file omap_udc.h.
| #define UDC_DEV_CFG (1 << 3) |
Definition at line 53 of file omap_udc.h.
| #define UDC_DEVSTAT (UDC_BASE + 0x20) /* Device status */ |
Definition at line 55 of file omap_udc.h.
| #define UDC_DMA_ENDIAN (1 << 6) |
Definition at line 44 of file omap_udc.h.
| #define UDC_DMA_IRQ_EN (UDC_BASE + 0x2C) /* DMA irq enable */ |
Definition at line 76 of file omap_udc.h.
| #define UDC_DMA_REQ (1 << 12) |
Definition at line 102 of file omap_udc.h.
| #define UDC_DMA_RX_SB (1 << 12) |
Definition at line 95 of file omap_udc.h.
Definition at line 96 of file omap_udc.h.
Definition at line 97 of file omap_udc.h.
| #define UDC_DMAN_STAT (UDC_BASE + 0x38) /* DMA irq status */ |
Definition at line 94 of file omap_udc.h.
| #define UDC_DS_CHG (1 << 3) |
Definition at line 88 of file omap_udc.h.
| #define UDC_DS_CHG_IE (1 << 3) |
Definition at line 74 of file omap_udc.h.
| #define UDC_EP0_IE (1 << 0) |
Definition at line 75 of file omap_udc.h.
| #define UDC_EP0_RX (1 << 1) |
Definition at line 90 of file omap_udc.h.
| #define UDC_EP0_TX (1 << 0) |
Definition at line 91 of file omap_udc.h.
| #define UDC_EP_DIR (1 << 4) |
Definition at line 16 of file omap_udc.h.
| #define UDC_EP_HALTED (1 << 6) |
Definition at line 33 of file omap_udc.h.
| #define UDC_EP_NUM (UDC_BASE + 0x4) /* Which endpoint */ |
Definition at line 13 of file omap_udc.h.
Definition at line 120 of file omap_udc.h.
| #define UDC_EP_SEL (1 << 5) |
Definition at line 15 of file omap_udc.h.
Definition at line 126 of file omap_udc.h.
| #define UDC_EPN_RX (1 << 5) |
Definition at line 86 of file omap_udc.h.
| #define UDC_EPN_RX_DB (1 << 14) |
Definition at line 122 of file omap_udc.h.
| #define UDC_EPN_RX_IE (1 << 5) |
Definition at line 72 of file omap_udc.h.
| #define UDC_EPN_RX_ISO (1 << 11) |
Definition at line 124 of file omap_udc.h.
| #define UDC_EPN_RX_VALID (1 << 15) |
Definition at line 121 of file omap_udc.h.
| #define UDC_EPN_STAT (UDC_BASE + 0x34) /* EP irq status */ |
Definition at line 93 of file omap_udc.h.
| #define UDC_EPN_TX (1 << 4) |
Definition at line 87 of file omap_udc.h.
| #define UDC_EPN_TX_IE (1 << 4) |
Definition at line 73 of file omap_udc.h.
| #define UDC_FIFO_EN (1 << 2) |
Definition at line 37 of file omap_udc.h.
| #define UDC_FT_LOCK (1 << 12) |
Definition at line 67 of file omap_udc.h.
| #define UDC_IRQ_EN (UDC_BASE + 0x28) /* Interrupt enable */ |
Definition at line 70 of file omap_udc.h.
| #define UDC_IRQ_SOF (1 << 7) |
Definition at line 85 of file omap_udc.h.
| #define UDC_IRQ_SRC (UDC_BASE + 0x30) /* Interrupt source */ |
Definition at line 81 of file omap_udc.h.
| #define UDC_IRQ_SRC_MASK 0x7bf |
Definition at line 92 of file omap_udc.h.
| #define UDC_ISO_ERR (1 << 12) |
Definition at line 30 of file omap_udc.h.
| #define UDC_ISO_FIFO_EMPTY (1 << 9) |
Definition at line 31 of file omap_udc.h.
| #define UDC_ISO_FIFO_FULL (1 << 8) |
Definition at line 32 of file omap_udc.h.
| #define UDC_MISS_IN (1 << 14) |
Definition at line 28 of file omap_udc.h.
| #define UDC_NAK (1 << 4) |
Definition at line 35 of file omap_udc.h.
| #define UDC_NAK_EN (1 << 4) |
Definition at line 45 of file omap_udc.h.
| #define UDC_NO_RXPACKET (1 << 15) |
Definition at line 27 of file omap_udc.h.
| #define UDC_NON_ISO_FIFO_EMPTY (1 << 1) |
Definition at line 38 of file omap_udc.h.
| #define UDC_NON_ISO_FIFO_FULL (1 << 0) |
Definition at line 39 of file omap_udc.h.
| #define UDC_PULLUP_EN (1 << 0) |
Definition at line 49 of file omap_udc.h.
| #define UDC_R_WK_OK (1 << 6) |
Definition at line 59 of file omap_udc.h.
| #define UDC_RESET_EP (1 << 0) |
Definition at line 25 of file omap_udc.h.
| #define UDC_REV (UDC_BASE + 0x0) /* Revision */ |
Definition at line 12 of file omap_udc.h.
| #define UDC_RMT_WKP (1 << 6) |
Definition at line 51 of file omap_udc.h.
Definition at line 79 of file omap_udc.h.
Definition at line 80 of file omap_udc.h.
Definition at line 111 of file omap_udc.h.
| #define UDC_RXDMA_CFG (UDC_BASE + 0x40) /* 3 eps for RX DMA */ |
Definition at line 101 of file omap_udc.h.
| #define UDC_RXFSTAT (UDC_BASE + 0x14) /* OUT bytecount */ |
Definition at line 40 of file omap_udc.h.
| #define UDC_RXN_CNT (1 << 9) |
Definition at line 83 of file omap_udc.h.
| #define UDC_RXN_EOT (1 << 8) |
Definition at line 84 of file omap_udc.h.
Definition at line 112 of file omap_udc.h.
| #define UDC_RXN_TC 0x00ff /* packets in xfer */ |
Definition at line 113 of file omap_udc.h.
| #define UDC_SELF_PWR (1 << 2) |
Definition at line 47 of file omap_udc.h.
| #define UDC_SET_FIFO_EN (1 << 2) |
Definition at line 23 of file omap_udc.h.
| #define UDC_SET_HALT (1 << 6) |
Definition at line 21 of file omap_udc.h.
| #define UDC_SETUP (1 << 2) |
Definition at line 89 of file omap_udc.h.
| #define UDC_SETUP_SEL (1 << 6) |
Definition at line 14 of file omap_udc.h.
| #define UDC_SOF (UDC_BASE + 0x24) /* Start of frame */ |
Definition at line 66 of file omap_udc.h.
| #define UDC_SOF_IE (1 << 7) |
Definition at line 71 of file omap_udc.h.
| #define UDC_SOFF_DIS (1 << 1) |
Definition at line 48 of file omap_udc.h.
| #define UDC_STALL (1 << 5) |
Definition at line 34 of file omap_udc.h.
| #define UDC_STALL_CMD (1 << 5) |
Definition at line 52 of file omap_udc.h.
| #define UDC_STAT_FLG (UDC_BASE + 0x10) /* Endpoint status */ |
Definition at line 26 of file omap_udc.h.
| #define UDC_SUS (1 << 4) |
Definition at line 61 of file omap_udc.h.
| #define UDC_SYSCON1 (UDC_BASE + 0x18) /* System config 1 */ |
Definition at line 41 of file omap_udc.h.
| #define UDC_SYSCON2 (UDC_BASE + 0x1C) /* System config 2 */ |
Definition at line 50 of file omap_udc.h.
| #define UDC_TS 0x03ff |
Definition at line 69 of file omap_udc.h.
| #define UDC_TS_OK (1 << 11) |
Definition at line 68 of file omap_udc.h.
Definition at line 78 of file omap_udc.h.
Definition at line 107 of file omap_udc.h.
| #define UDC_TXDMA_CFG (UDC_BASE + 0x44) /* 3 eps for TX DMA */ |
Definition at line 103 of file omap_udc.h.
| #define UDC_TXN_DONE (1 << 10) |
Definition at line 82 of file omap_udc.h.
Definition at line 108 of file omap_udc.h.
| #define UDC_TXN_START (1 << 14) /* start transfer */ |
Definition at line 109 of file omap_udc.h.
| #define UDC_TXN_TSC 0x03ff /* units in xfer */ |
Definition at line 110 of file omap_udc.h.
| #define UDC_USB_RESET (1 << 5) |
Definition at line 60 of file omap_udc.h.
| #define VBUS_CTRL_1510 (1 << 19) /* 1 connected (software) */ |
Definition at line 200 of file omap_udc.h.
Definition at line 201 of file omap_udc.h.
| #define VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */ |
Definition at line 197 of file omap_udc.h.
| #define VDBG | ( | stuff... | ) | do{}while(0) |
Definition at line 186 of file omap_udc.h.
| #define WARNING | ( | stuff... | ) | pr_warning("udc: " stuff) |
Definition at line 190 of file omap_udc.h.
1.8.2