#include <asm/sizes.h>
#include <asm/types.h>
#include <plat/cpu.h>
#include <plat/tc.h>
#include <plat/serial.h>
#include "omap7xx.h"
#include "omap1510.h"
#include "omap16xx.h"

Macros
#define	OMAP_MPU_TIMER1_BASE (0xfffec500)

#define	OMAP_MPU_TIMER2_BASE (0xfffec600)

#define	OMAP_MPU_TIMER3_BASE (0xfffec700)

#define	MPU_TIMER_FREE (1 << 6)

#define	MPU_TIMER_CLOCK_ENABLE (1 << 5)

#define	MPU_TIMER_AR (1 << 1)

#define	MPU_TIMER_ST (1 << 0)

#define	CLKGEN_REG_BASE (0xfffece00)

#define	ARM_CKCTL (CLKGEN_REG_BASE + 0x0)

#define	ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)

#define	ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)

#define	ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)

#define	ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)

#define	ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)

#define	ARM_SYSST (CLKGEN_REG_BASE + 0x18)

#define	ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)

#define	CK_RATEF 1

#define	CK_IDLEF 2

#define	CK_ENABLEF 4

#define	CK_SELECTF 8

#define	SETARM_IDLE_SHIFT

#define	DPLL_CTL (0xfffecf00)

#define	DSP_CONFIG_REG_BASE IOMEM(0xe1008000)

#define	DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)

#define	DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)

#define	DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)

#define	DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)

#define	ULPD_REG_BASE (0xfffe0800)

#define	ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)

#define	ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)

#define	ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)

#define	DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */

#define	USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */

#define	ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)

#define	SOFT_UDC_REQ (1 << 4)

#define	SOFT_USB_CLK_REQ (1 << 3)

#define	SOFT_DPLL_REQ (1 << 0)

#define	ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)

#define	ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)

#define	ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)

#define	ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)

#define	ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)

#define	DIS_MMC2_DPLL_REQ (1 << 11)

#define	DIS_MMC1_DPLL_REQ (1 << 10)

#define	DIS_UART3_DPLL_REQ (1 << 9)

#define	DIS_UART2_DPLL_REQ (1 << 8)

#define	DIS_UART1_DPLL_REQ (1 << 7)

#define	DIS_USB_HOST_DPLL_REQ (1 << 6)

#define	ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)

#define	ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)

#define	OMAP_MPU_WATCHDOG_BASE (0xfffec800)

#define	OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)

#define	OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)

#define	OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)

#define	OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)

#define	MOD_CONF_CTRL_0 0xfffe1080

#define	MOD_CONF_CTRL_1 0xfffe1110

#define	FUNC_MUX_CTRL_0 0xfffe1000

#define	FUNC_MUX_CTRL_1 0xfffe1004

#define	FUNC_MUX_CTRL_2 0xfffe1008

#define	COMP_MODE_CTRL_0 0xfffe100c

#define	FUNC_MUX_CTRL_3 0xfffe1010

#define	FUNC_MUX_CTRL_4 0xfffe1014

#define	FUNC_MUX_CTRL_5 0xfffe1018

#define	FUNC_MUX_CTRL_6 0xfffe101C

#define	FUNC_MUX_CTRL_7 0xfffe1020

#define	FUNC_MUX_CTRL_8 0xfffe1024

#define	FUNC_MUX_CTRL_9 0xfffe1028

#define	FUNC_MUX_CTRL_A 0xfffe102C

#define	FUNC_MUX_CTRL_B 0xfffe1030

#define	FUNC_MUX_CTRL_C 0xfffe1034

#define	FUNC_MUX_CTRL_D 0xfffe1038

#define	PULL_DWN_CTRL_0 0xfffe1040

#define	PULL_DWN_CTRL_1 0xfffe1044

#define	PULL_DWN_CTRL_2 0xfffe1048

#define	PULL_DWN_CTRL_3 0xfffe104c

#define	PULL_DWN_CTRL_4 0xfffe10ac

#define	FUNC_MUX_CTRL_E 0xfffe1090

#define	FUNC_MUX_CTRL_F 0xfffe1094

#define	FUNC_MUX_CTRL_10 0xfffe1098

#define	FUNC_MUX_CTRL_11 0xfffe109c

#define	FUNC_MUX_CTRL_12 0xfffe10a0

#define	PU_PD_SEL_0 0xfffe10b4

#define	PU_PD_SEL_1 0xfffe10b8

#define	PU_PD_SEL_2 0xfffe10bc

#define	PU_PD_SEL_3 0xfffe10c0

#define	PU_PD_SEL_4 0xfffe10c4

#define	OMAP_TIMER32K_BASE 0xFFFBC400

#define	TIPB_PUBLIC_CNTL_BASE 0xfffed300

#define	MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)

#define	TIPB_PRIVATE_CNTL_BASE 0xfffeca00

#define	MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)

#define	MPUI_BASE (0xfffec900)

#define	MPUI_CTRL (MPUI_BASE + 0x0)

#define	MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)

#define	MPUI_DEBUG_DATA (MPUI_BASE + 0x8)

#define	MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)

#define	MPUI_STATUS_REG (MPUI_BASE + 0x10)

#define	MPUI_DSP_STATUS (MPUI_BASE + 0x14)

#define	MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)

#define	MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)

#define	OMAP_LPG1_BASE 0xfffbd000

#define	OMAP_LPG2_BASE 0xfffbd800

#define	OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)

#define	OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)

#define	OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)

#define	OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)

#define	OMAP_PWL_BASE 0xfffb5800

#define	OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)

#define	OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)

Functions
u8	omap_readb (u32 pa)

u16	omap_readw (u32 pa)

u32	omap_readl (u32 pa)

void	omap_writeb (u8 v, u32 pa)

void	omap_writew (u16 v, u32 pa)

void	omap_writel (u32 v, u32 pa)

Macro Definition Documentation

#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)

Definition at line 104 of file hardware.h.

#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)

Definition at line 107 of file hardware.h.

#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)

Definition at line 105 of file hardware.h.

#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)

Definition at line 106 of file hardware.h.

#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)

Definition at line 111 of file hardware.h.

#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)

Definition at line 108 of file hardware.h.

#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)

Definition at line 109 of file hardware.h.

#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)

Definition at line 110 of file hardware.h.

#define CK_ENABLEF 4

Definition at line 115 of file hardware.h.

#define CK_IDLEF 2

Definition at line 114 of file hardware.h.

#define CK_RATEF 1

Definition at line 113 of file hardware.h.

#define CK_SELECTF 8

Definition at line 116 of file hardware.h.

#define CLKGEN_REG_BASE (0xfffece00)

Definition at line 103 of file hardware.h.

#define COMP_MODE_CTRL_0 0xfffe100c

Definition at line 229 of file hardware.h.

#define DIS_MMC1_DPLL_REQ (1 << 10)

Definition at line 150 of file hardware.h.

#define DIS_MMC2_DPLL_REQ (1 << 11)

Definition at line 149 of file hardware.h.

#define DIS_UART1_DPLL_REQ (1 << 7)

Definition at line 153 of file hardware.h.

#define DIS_UART2_DPLL_REQ (1 << 8)

Definition at line 152 of file hardware.h.

#define DIS_UART3_DPLL_REQ (1 << 9)

Definition at line 151 of file hardware.h.

#define DIS_USB_HOST_DPLL_REQ (1 << 6)

Definition at line 154 of file hardware.h.

#define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */

Definition at line 138 of file hardware.h.

#define DPLL_CTL (0xfffecf00)

Definition at line 120 of file hardware.h.

#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)

Definition at line 124 of file hardware.h.

#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)

Definition at line 123 of file hardware.h.

#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)

Definition at line 125 of file hardware.h.

#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)

Definition at line 126 of file hardware.h.

#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)

Definition at line 127 of file hardware.h.

#define FUNC_MUX_CTRL_0 0xfffe1000

Definition at line 226 of file hardware.h.

#define FUNC_MUX_CTRL_1 0xfffe1004

Definition at line 227 of file hardware.h.

#define FUNC_MUX_CTRL_10 0xfffe1098

Definition at line 250 of file hardware.h.

#define FUNC_MUX_CTRL_11 0xfffe109c

Definition at line 251 of file hardware.h.

#define FUNC_MUX_CTRL_12 0xfffe10a0

Definition at line 252 of file hardware.h.

#define FUNC_MUX_CTRL_2 0xfffe1008

Definition at line 228 of file hardware.h.

#define FUNC_MUX_CTRL_3 0xfffe1010

Definition at line 230 of file hardware.h.

#define FUNC_MUX_CTRL_4 0xfffe1014

Definition at line 231 of file hardware.h.

#define FUNC_MUX_CTRL_5 0xfffe1018

Definition at line 232 of file hardware.h.

#define FUNC_MUX_CTRL_6 0xfffe101C

Definition at line 233 of file hardware.h.

#define FUNC_MUX_CTRL_7 0xfffe1020

Definition at line 234 of file hardware.h.

#define FUNC_MUX_CTRL_8 0xfffe1024

Definition at line 235 of file hardware.h.

#define FUNC_MUX_CTRL_9 0xfffe1028

Definition at line 236 of file hardware.h.

#define FUNC_MUX_CTRL_A 0xfffe102C

Definition at line 237 of file hardware.h.

#define FUNC_MUX_CTRL_B 0xfffe1030

Definition at line 238 of file hardware.h.

#define FUNC_MUX_CTRL_C 0xfffe1034

Definition at line 239 of file hardware.h.

#define FUNC_MUX_CTRL_D 0xfffe1038

Definition at line 240 of file hardware.h.

#define FUNC_MUX_CTRL_E 0xfffe1090

Definition at line 248 of file hardware.h.

#define FUNC_MUX_CTRL_F 0xfffe1094

Definition at line 249 of file hardware.h.

#define MOD_CONF_CTRL_0 0xfffe1080

Definition at line 218 of file hardware.h.

#define MOD_CONF_CTRL_1 0xfffe1110

Definition at line 219 of file hardware.h.

#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)

Definition at line 270 of file hardware.h.

#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)

Definition at line 268 of file hardware.h.

#define MPU_TIMER_AR (1 << 1)

Definition at line 95 of file hardware.h.

#define MPU_TIMER_CLOCK_ENABLE (1 << 5)

Definition at line 94 of file hardware.h.

#define MPU_TIMER_FREE (1 << 6)

Definition at line 93 of file hardware.h.

#define MPU_TIMER_ST (1 << 0)

Definition at line 96 of file hardware.h.

#define MPUI_BASE (0xfffec900)

Definition at line 277 of file hardware.h.

#define MPUI_CTRL (MPUI_BASE + 0x0)

Definition at line 278 of file hardware.h.

#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)

Definition at line 279 of file hardware.h.

#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)

Definition at line 280 of file hardware.h.

#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)

Definition at line 281 of file hardware.h.

#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)

Definition at line 285 of file hardware.h.

#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)

Definition at line 284 of file hardware.h.

#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)

Definition at line 283 of file hardware.h.

#define MPUI_STATUS_REG (MPUI_BASE + 0x10)

Definition at line 282 of file hardware.h.

#define OMAP_LPG1_BASE 0xfffbd000

Definition at line 292 of file hardware.h.

#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)

Definition at line 294 of file hardware.h.

#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)

Definition at line 295 of file hardware.h.

#define OMAP_LPG2_BASE 0xfffbd800

Definition at line 293 of file hardware.h.

#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)

Definition at line 296 of file hardware.h.

#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)

Definition at line 297 of file hardware.h.

#define OMAP_MPU_TIMER1_BASE (0xfffec500)

Definition at line 90 of file hardware.h.

#define OMAP_MPU_TIMER2_BASE (0xfffec600)

Definition at line 91 of file hardware.h.

#define OMAP_MPU_TIMER3_BASE (0xfffec700)

Definition at line 92 of file hardware.h.

#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)

Definition at line 165 of file hardware.h.

#define OMAP_PWL_BASE 0xfffb5800

Definition at line 304 of file hardware.h.

#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)

Definition at line 306 of file hardware.h.

#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)

Definition at line 305 of file hardware.h.

#define OMAP_TIMER32K_BASE 0xFFFBC400

Definition at line 260 of file hardware.h.

#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)

Definition at line 167 of file hardware.h.

#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)

Definition at line 168 of file hardware.h.

#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)

Definition at line 166 of file hardware.h.

#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)

Definition at line 169 of file hardware.h.

#define PU_PD_SEL_0 0xfffe10b4

Definition at line 253 of file hardware.h.

#define PU_PD_SEL_1 0xfffe10b8

Definition at line 254 of file hardware.h.

#define PU_PD_SEL_2 0xfffe10bc

Definition at line 255 of file hardware.h.

#define PU_PD_SEL_3 0xfffe10c0

Definition at line 256 of file hardware.h.

#define PU_PD_SEL_4 0xfffe10c4

Definition at line 257 of file hardware.h.

#define PULL_DWN_CTRL_0 0xfffe1040

Definition at line 241 of file hardware.h.

#define PULL_DWN_CTRL_1 0xfffe1044

Definition at line 242 of file hardware.h.

#define PULL_DWN_CTRL_2 0xfffe1048

Definition at line 243 of file hardware.h.

#define PULL_DWN_CTRL_3 0xfffe104c

Definition at line 244 of file hardware.h.

#define PULL_DWN_CTRL_4 0xfffe10ac

Definition at line 245 of file hardware.h.

#define SETARM_IDLE_SHIFT

Definition at line 117 of file hardware.h.

#define SOFT_DPLL_REQ (1 << 0)

Definition at line 143 of file hardware.h.

#define SOFT_UDC_REQ (1 << 4)

Definition at line 141 of file hardware.h.

#define SOFT_USB_CLK_REQ (1 << 3)

Definition at line 142 of file hardware.h.

#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00

Definition at line 269 of file hardware.h.

#define TIPB_PUBLIC_CNTL_BASE 0xfffed300

Definition at line 267 of file hardware.h.

#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)

Definition at line 146 of file hardware.h.

#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)

Definition at line 156 of file hardware.h.

#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)

Definition at line 137 of file hardware.h.

#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)

Definition at line 144 of file hardware.h.

#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)

Definition at line 135 of file hardware.h.

#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)

Definition at line 147 of file hardware.h.

#define ULPD_REG_BASE (0xfffe0800)

Definition at line 134 of file hardware.h.

#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)

Definition at line 155 of file hardware.h.

#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)

Definition at line 136 of file hardware.h.

#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)

Definition at line 148 of file hardware.h.

#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)

Definition at line 140 of file hardware.h.

#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)

Definition at line 145 of file hardware.h.

#define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */

Definition at line 139 of file hardware.h.

Function Documentation

u8 omap_readb ( u32 pa )

Definition at line 149 of file io.c.

u32 omap_readl ( u32 pa )

Definition at line 161 of file io.c.

u16 omap_readw ( u32 pa )

Definition at line 155 of file io.c.

void omap_writeb	(	u8	v,
		u32	pa
	)

Definition at line 167 of file io.c.

void omap_writel	(	u32	v,
		u32	pa
	)

Definition at line 179 of file io.c.

void omap_writew	(	u16	v,
		u32	pa
	)

Definition at line 173 of file io.c.

Macros

Functions

Macro Definition Documentation

Function Documentation