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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Data Structures | |
| struct | prcm_config |
Macros | |
| #define | RX_CLKSEL_DSS1 (0x10 << 8) |
| #define | RX_CLKSEL_DSS2 (0x0 << 13) |
| #define | RX_CLKSEL_SSI (0x5 << 20) |
| #define | R1_CLKSEL_L3 (4 << 0) |
| #define | R1_CLKSEL_L4 (2 << 5) |
| #define | R1_CLKSEL_USB (4 << 25) |
| #define | R1_CM_CLKSEL1_CORE_VAL |
| #define | R1_CLKSEL_MPU (2 << 0) |
| #define | R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU |
| #define | R1_CLKSEL_DSP (2 << 0) |
| #define | R1_CLKSEL_DSP_IF (2 << 5) |
| #define | R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF) |
| #define | R1_CLKSEL_GFX (2 << 0) |
| #define | R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX |
| #define | R1_CLKSEL_MDM (4 << 0) |
| #define | R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM |
| #define | R2_CLKSEL_L3 (6 << 0) |
| #define | R2_CLKSEL_L4 (2 << 5) |
| #define | R2_CLKSEL_USB (2 << 25) |
| #define | R2_CM_CLKSEL1_CORE_VAL |
| #define | R2_CLKSEL_MPU (2 << 0) |
| #define | R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU |
| #define | R2_CLKSEL_DSP (2 << 0) |
| #define | R2_CLKSEL_DSP_IF (3 << 5) |
| #define | R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF) |
| #define | R2_CLKSEL_GFX (2 << 0) |
| #define | R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX |
| #define | R2_CLKSEL_MDM (6 << 0) |
| #define | R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM |
| #define | RB_CLKSEL_L3 (1 << 0) |
| #define | RB_CLKSEL_L4 (1 << 5) |
| #define | RB_CLKSEL_USB (1 << 25) |
| #define | RB_CM_CLKSEL1_CORE_VAL |
| #define | RB_CLKSEL_MPU (1 << 0) |
| #define | RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU |
| #define | RB_CLKSEL_DSP (1 << 0) |
| #define | RB_CLKSEL_DSP_IF (1 << 5) |
| #define | RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF) |
| #define | RB_CLKSEL_GFX (1 << 0) |
| #define | RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX |
| #define | RB_CLKSEL_MDM (1 << 0) |
| #define | RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM |
| #define | RXX_CLKSEL_VLYNQ (0x12 << 15) |
| #define | RXX_CLKSEL_SSI (0x8 << 20) |
| #define | RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ |
| #define | RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ |
| #define | RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ |
| #define | RIII_CM_CLKSEL1_CORE_VAL |
| #define | RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ |
| #define | RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU |
| #define | RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ |
| #define | RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ |
| #define | RIII_SYNC_DSP (1 << 7) /* Enable sync */ |
| #define | RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ |
| #define | RIII_SYNC_IVA (1 << 13) /* Enable sync */ |
| #define | RIII_CM_CLKSEL_DSP_VAL |
| #define | RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ |
| #define | RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX |
| #define | RII_CLKSEL_L3 (6 << 0) /* 100MHz */ |
| #define | RII_CLKSEL_L4 (2 << 5) /* 50MHz */ |
| #define | RII_CLKSEL_USB (2 << 25) /* 50MHz */ |
| #define | RII_CM_CLKSEL1_CORE_VAL |
| #define | RII_CLKSEL_MPU (2 << 0) /* 300MHz */ |
| #define | RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU |
| #define | RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ |
| #define | RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ |
| #define | RII_SYNC_DSP (0 << 7) /* Bypass sync */ |
| #define | RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ |
| #define | RII_SYNC_IVA (0 << 13) /* Bypass sync */ |
| #define | RII_CM_CLKSEL_DSP_VAL |
| #define | RII_CLKSEL_GFX (2 << 0) /* 50MHz */ |
| #define | RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX |
| #define | RI_CLKSEL_L3 (4 << 0) /* 165MHz */ |
| #define | RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ |
| #define | RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ |
| #define | RI_CM_CLKSEL1_CORE_VAL |
| #define | RI_CLKSEL_MPU (2 << 0) /* 330MHz */ |
| #define | RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU |
| #define | RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ |
| #define | RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ |
| #define | RI_SYNC_DSP (1 << 7) /* Activate sync */ |
| #define | RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ |
| #define | RI_SYNC_IVA (0 << 13) /* Bypass sync */ |
| #define | RI_CM_CLKSEL_DSP_VAL |
| #define | RI_CLKSEL_GFX (1 << 0) /* 165MHz */ |
| #define | RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX |
| #define | RVII_CLKSEL_L3 (1 << 0) |
| #define | RVII_CLKSEL_L4 (1 << 5) |
| #define | RVII_CLKSEL_DSS1 (1 << 8) |
| #define | RVII_CLKSEL_DSS2 (0 << 13) |
| #define | RVII_CLKSEL_VLYNQ (1 << 15) |
| #define | RVII_CLKSEL_SSI (1 << 20) |
| #define | RVII_CLKSEL_USB (1 << 25) |
| #define | RVII_CM_CLKSEL1_CORE_VAL |
| #define | RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ |
| #define | RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU |
| #define | RVII_CLKSEL_DSP (1 << 0) |
| #define | RVII_CLKSEL_DSP_IF (1 << 5) |
| #define | RVII_SYNC_DSP (0 << 7) |
| #define | RVII_CLKSEL_IVA (1 << 8) |
| #define | RVII_SYNC_IVA (0 << 13) |
| #define | RVII_CM_CLKSEL_DSP_VAL |
| #define | RVII_CLKSEL_GFX (1 << 0) |
| #define | RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX |
| #define | MX_48M_SRC (0 << 3) |
| #define | MX_54M_SRC (0 << 5) |
| #define | MX_APLLS_CLIKIN_12 (3 << 23) |
| #define | MX_APLLS_CLIKIN_13 (2 << 23) |
| #define | MX_APLLS_CLIKIN_19_2 (0 << 23) |
| #define | M5A_DPLL_MULT_12 (133 << 12) |
| #define | M5A_DPLL_DIV_12 (5 << 8) |
| #define | M5A_CM_CLKSEL1_PLL_12_VAL |
| #define | M5A_DPLL_MULT_13 (61 << 12) |
| #define | M5A_DPLL_DIV_13 (2 << 8) |
| #define | M5A_CM_CLKSEL1_PLL_13_VAL |
| #define | M5A_DPLL_MULT_19 (55 << 12) |
| #define | M5A_DPLL_DIV_19 (3 << 8) |
| #define | M5A_CM_CLKSEL1_PLL_19_VAL |
| #define | M5B_DPLL_MULT_12 (50 << 12) |
| #define | M5B_DPLL_DIV_12 (2 << 8) |
| #define | M5B_CM_CLKSEL1_PLL_12_VAL |
| #define | M5B_DPLL_MULT_13 (200 << 12) |
| #define | M5B_DPLL_DIV_13 (12 << 8) |
| #define | M5B_CM_CLKSEL1_PLL_13_VAL |
| #define | M5B_DPLL_MULT_19 (125 << 12) |
| #define | M5B_DPLL_DIV_19 (31 << 8) |
| #define | M5B_CM_CLKSEL1_PLL_19_VAL |
| #define | M4_DPLL_MULT_12 (133 << 12) |
| #define | M4_DPLL_DIV_12 (3 << 8) |
| #define | M4_CM_CLKSEL1_PLL_12_VAL |
| #define | M4_DPLL_MULT_13 (399 << 12) |
| #define | M4_DPLL_DIV_13 (12 << 8) |
| #define | M4_CM_CLKSEL1_PLL_13_VAL |
| #define | M4_DPLL_MULT_19 (145 << 12) |
| #define | M4_DPLL_DIV_19 (6 << 8) |
| #define | M4_CM_CLKSEL1_PLL_19_VAL |
| #define | M3_DPLL_MULT_12 (55 << 12) |
| #define | M3_DPLL_DIV_12 (1 << 8) |
| #define | M3_CM_CLKSEL1_PLL_12_VAL |
| #define | M3_DPLL_MULT_13 (76 << 12) |
| #define | M3_DPLL_DIV_13 (2 << 8) |
| #define | M3_CM_CLKSEL1_PLL_13_VAL |
| #define | M3_DPLL_MULT_19 (17 << 12) |
| #define | M3_DPLL_DIV_19 (0 << 8) |
| #define | M3_CM_CLKSEL1_PLL_19_VAL |
| #define | M2_DPLL_MULT_12 (55 << 12) |
| #define | M2_DPLL_DIV_12 (1 << 8) |
| #define | M2_CM_CLKSEL1_PLL_12_VAL |
| #define | M2_DPLL_MULT_13 (76 << 12) |
| #define | M2_DPLL_DIV_13 (2 << 8) |
| #define | M2_CM_CLKSEL1_PLL_13_VAL |
| #define | M2_DPLL_MULT_19 (17 << 12) |
| #define | M2_DPLL_DIV_19 (0 << 8) |
| #define | M2_CM_CLKSEL1_PLL_19_VAL |
| #define | MB_DPLL_MULT (1 << 12) |
| #define | MB_DPLL_DIV (0 << 8) |
| #define | MB_CM_CLKSEL1_PLL_12_VAL |
| #define | MB_CM_CLKSEL1_PLL_13_VAL |
| #define | MB_CM_CLKSEL1_PLL_19_VAL |
| #define | MI_DPLL_MULT_12 (55 << 12) |
| #define | MI_DPLL_DIV_12 (1 << 8) |
| #define | MI_CM_CLKSEL1_PLL_12_VAL |
| #define | MII_DPLL_MULT_12 (50 << 12) |
| #define | MII_DPLL_DIV_12 (1 << 8) |
| #define | MII_CM_CLKSEL1_PLL_12_VAL |
| #define | MII_DPLL_MULT_13 (300 << 12) |
| #define | MII_DPLL_DIV_13 (12 << 8) |
| #define | MII_CM_CLKSEL1_PLL_13_VAL |
| #define | MIII_DPLL_MULT_12 (133 << 12) |
| #define | MIII_DPLL_DIV_12 (5 << 8) |
| #define | MIII_CM_CLKSEL1_PLL_12_VAL |
| #define | MIII_DPLL_MULT_13 (266 << 12) |
| #define | MIII_DPLL_DIV_13 (12 << 8) |
| #define | MIII_CM_CLKSEL1_PLL_13_VAL |
| #define | MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL |
| #define | MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL |
| #define | MX_CLKSEL2_PLL_2x_VAL (2 << 0) |
| #define | MX_CLKSEL2_PLL_1x_VAL (1 << 0) |
| #define | S12M 12000000 |
| #define | S13M 13000000 |
| #define | S19M 19200000 |
| #define | S26M 26000000 |
| #define | S100M 100000000 |
| #define | S133M 133000000 |
| #define | S150M 150000000 |
| #define | S164M 164000000 |
| #define | S165M 165000000 |
| #define | S199M 199000000 |
| #define | S200M 200000000 |
| #define | S266M 266000000 |
| #define | S300M 300000000 |
| #define | S329M 329000000 |
| #define | S330M 330000000 |
| #define | S399M 399000000 |
| #define | S400M 400000000 |
| #define | S532M 532000000 |
| #define | S600M 600000000 |
| #define | S658M 658000000 |
| #define | S660M 660000000 |
| #define | S798M 798000000 |
| #define | omap2430_rate_table NULL |
Variables | |
| struct prcm_config | omap2420_rate_table [] |
| struct prcm_config * | rate_table |
| struct prcm_config * | curr_prcm_set |
| #define M2_CM_CLKSEL1_PLL_12_VAL |
| #define M2_CM_CLKSEL1_PLL_13_VAL |
| #define M2_CM_CLKSEL1_PLL_19_VAL |
| #define M3_CM_CLKSEL1_PLL_12_VAL |
| #define M3_CM_CLKSEL1_PLL_13_VAL |
| #define M3_CM_CLKSEL1_PLL_19_VAL |
| #define M4_CM_CLKSEL1_PLL_12_VAL |
| #define M4_CM_CLKSEL1_PLL_13_VAL |
| #define M4_CM_CLKSEL1_PLL_19_VAL |
| #define M5A_CM_CLKSEL1_PLL_12_VAL |
| #define M5A_CM_CLKSEL1_PLL_13_VAL |
| #define M5A_CM_CLKSEL1_PLL_19_VAL |
| #define M5B_CM_CLKSEL1_PLL_12_VAL |
| #define M5B_CM_CLKSEL1_PLL_13_VAL |
| #define M5B_CM_CLKSEL1_PLL_19_VAL |
| #define MB_CM_CLKSEL1_PLL_12_VAL |
| #define MB_CM_CLKSEL1_PLL_13_VAL |
| #define MB_CM_CLKSEL1_PLL_19_VAL |
| #define MI_CM_CLKSEL1_PLL_12_VAL |
| #define MII_CM_CLKSEL1_PLL_12_VAL |
| #define MII_CM_CLKSEL1_PLL_13_VAL |
| #define MIII_CM_CLKSEL1_PLL_12_VAL |
| #define MIII_CM_CLKSEL1_PLL_13_VAL |
| #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL |
| #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL |
| #define R1_CM_CLKSEL1_CORE_VAL |
| #define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF) |
| #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX |
| #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM |
| #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU |
| #define R2_CM_CLKSEL1_CORE_VAL |
| #define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF) |
| #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX |
| #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM |
| #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU |
| #define RB_CM_CLKSEL1_CORE_VAL |
| #define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF) |
| #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX |
| #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM |
| #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU |
| #define RI_CM_CLKSEL1_CORE_VAL |
| #define RI_CM_CLKSEL_DSP_VAL |
| #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX |
| #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU |
| #define RII_CM_CLKSEL1_CORE_VAL |
| #define RII_CM_CLKSEL_DSP_VAL |
| #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX |
| #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU |
| #define RIII_CM_CLKSEL1_CORE_VAL |
| #define RIII_CM_CLKSEL_DSP_VAL |
| #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX |
| #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU |
| #define RVII_CM_CLKSEL1_CORE_VAL |
| #define RVII_CM_CLKSEL_DSP_VAL |
| #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX |
| #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU |
| struct prcm_config* curr_prcm_set |
Definition at line 47 of file clkt2xxx_virt_prcm_set.c.
| struct prcm_config omap2420_rate_table[] |
Definition at line 55 of file opp2420_data.c.
| struct prcm_config* rate_table |
Definition at line 48 of file clkt2xxx_virt_prcm_set.c.
1.8.2