#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/pch_dma.h>
#include "dmaengine.h"
Go to the source code of this file.
| #define channel_readl |
( |
|
pdc, |
|
|
|
name |
|
) |
| readl((pdc)->membase + PDC_##name) |
| #define DMA_CTL0_BITS_PER_CH 4 |
| #define DMA_CTL0_DIR_SHIFT_BITS 2 |
| #define DMA_CTL0_DISABLE 0x0 |
| #define DMA_CTL0_MODE_MASK_BITS 0x3 |
| #define DMA_CTL0_ONESHOT 0x2 |
| #define DMA_CTL2_IRQ_ENABLE_MASK ((1UL << DMA_CTL2_START_SHIFT_BITS) - 1) |
| #define DMA_CTL2_START_SHIFT_BITS 8 |
| #define DMA_DESC_END_WITH_IRQ 0x1 |
| #define DMA_DESC_END_WITHOUT_IRQ 0x0 |
| #define DMA_DESC_FOLLOW_WITH_IRQ 0x3 |
| #define DMA_DESC_FOLLOW_WITHOUT_IRQ 0x2 |
| #define DMA_DESC_MAX_COUNT_1_BYTE 0x3FF |
| #define DMA_DESC_MAX_COUNT_2_BYTES 0x3FF |
| #define DMA_DESC_MAX_COUNT_4_BYTES 0x7FF |
| #define DMA_DESC_WIDTH_1_BYTE (0x3 << DMA_DESC_WIDTH_SHIFT_BITS) |
| #define DMA_DESC_WIDTH_2_BYTES (0x2 << DMA_DESC_WIDTH_SHIFT_BITS) |
| #define DMA_DESC_WIDTH_4_BYTES (0x0 << DMA_DESC_WIDTH_SHIFT_BITS) |
| #define DMA_DESC_WIDTH_SHIFT_BITS 12 |
| #define DMA_MASK_CTL0_MODE 0x33333333 |
| #define DMA_MASK_CTL2_MODE 0x00003333 |
| #define DMA_STATUS0_ERR |
( |
|
x | ) |
(0x1 << ((x) + 8)) |
| #define DMA_STATUS2_ERR |
( |
|
x | ) |
(0x1 << (x)) |
| #define DMA_STATUS_ACCESS 0x3 |
| #define DMA_STATUS_BITS_PER_CH 2 |
| #define DMA_STATUS_DESC_READ 0x1 |
| #define DMA_STATUS_IDLE 0x0 |
| #define DMA_STATUS_IRQ |
( |
|
x | ) |
(0x1 << (x)) |
| #define DMA_STATUS_MASK_BITS 0x3 |
| #define DMA_STATUS_SHIFT_BITS 16 |
| #define DMA_STATUS_WAIT 0x2 |
| #define DRV_NAME "pch-dma" |
| #define PCH_DMA_CTL0 0x00 |
| #define PCH_DMA_CTL1 0x04 |
| #define PCH_DMA_CTL2 0x08 |
| #define PCH_DMA_CTL3 0x0C |
| #define PCH_DMA_STS0 0x10 |
| #define PCH_DMA_STS1 0x14 |
| #define PCH_DMA_STS2 0x18 |
| #define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH 0x8815 |
| #define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH 0x8810 |
| #define PCI_DEVICE_ID_ML7213_DMA1_8CH 0x8026 |
| #define PCI_DEVICE_ID_ML7213_DMA2_8CH 0x802B |
| #define PCI_DEVICE_ID_ML7213_DMA3_4CH 0x8034 |
| #define PCI_DEVICE_ID_ML7213_DMA4_12CH 0x8032 |
| #define PCI_DEVICE_ID_ML7223_DMA1_4CH 0x800B |
| #define PCI_DEVICE_ID_ML7223_DMA2_4CH 0x800E |
| #define PCI_DEVICE_ID_ML7223_DMA3_4CH 0x8017 |
| #define PCI_DEVICE_ID_ML7223_DMA4_4CH 0x803B |
| #define PCI_DEVICE_ID_ML7831_DMA1_8CH 0x8810 |
| #define PCI_DEVICE_ID_ML7831_DMA2_4CH 0x8815 |
| #define PCI_VENDOR_ID_ROHM 0x10DB |
| #define PDC_DEV_ADDR 0x00 |
| #define PDC_MEM_ADDR 0x04 |
| DEFINE_PCI_DEVICE_TABLE |
( |
pch_dma_id_table |
| ) |
|
| MODULE_DESCRIPTION |
( |
"Intel EG20T PCH / LAPIS Semicon ML7213/ML7223/ML7831 IOH ""DMA controller driver" |
| ) |
|
| module_exit |
( |
pch_dma_exit |
| ) |
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| module_init |
( |
pch_dma_init |
| ) |
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| MODULE_LICENSE |
( |
"GPL v2" |
| ) |
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| module_param |
( |
init_nr_desc_per_channel |
, |
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uint |
, |
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0644 |
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) |
| |
1.8.2