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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ |
| #define | PHY_CONTROL 0x00 /* Control Register */ |
| #define | PHY_STATUS 0x01 /* Status Regiser */ |
| #define | PHY_ID1 0x02 /* Phy Id Register (word 1) */ |
| #define | PHY_ID2 0x03 /* Phy Id Register (word 2) */ |
| #define | PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ |
| #define | PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ |
| #define | PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Register */ |
| #define | PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ |
| #define | PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ |
| #define | PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */ |
| #define | PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */ |
| #define | PHY_EXT_STATUS 0x0F /* Extended Status Register */ |
| #define | PHY_PHYSP_CONTROL 0x10 /* PHY Specific Control Register */ |
| #define | PHY_EXT_PHYSP_CONTROL 0x14 /* Extended PHY Specific Control Register */ |
| #define | PHY_LED_CONTROL 0x18 /* LED Control Register */ |
| #define | PHY_EXT_PHYSP_STATUS 0x1B /* Extended PHY Specific Status Register */ |
| #define | MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ |
| #define | MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ |
| #define | MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ |
| #define | MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |
| #define | MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ |
| #define | MII_CR_POWER_DOWN 0x0800 /* Power down */ |
| #define | MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
| #define | MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ |
| #define | MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ |
| #define | MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ |
| #define | MII_CR_SPEED_1000 0x0040 |
| #define | MII_CR_SPEED_100 0x2000 |
| #define | MII_CR_SPEED_10 0x0000 |
| #define | MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ |
| #define | MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ |
| #define | MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ |
| #define | MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ |
| #define | MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ |
| #define | MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ |
| #define | MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ |
| #define | MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ |
| #define | MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ |
| #define | MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ |
| #define | MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ |
| #define | MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ |
| #define | MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ |
| #define | MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ |
| #define | MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ |
| #define | PHY_REVISION_MASK 0x000F |
| #define | PHYSP_CTRL_ASSERT_CRS_TX 0x0800 |
| #define | PHY_CONTROL_DEFAULT 0x1140 /* Control Register */ |
| #define | PHY_AUTONEG_ADV_DEFAULT 0x01e0 /* Autoneg Advertisement */ |
| #define | PHY_NEXT_PAGE_TX_DEFAULT 0x2001 /* Next Page TX */ |
| #define | PHY_1000T_CTRL_DEFAULT 0x0300 /* 1000Base-T Control Register */ |
| #define | PHY_PHYSP_CONTROL_DEFAULT 0x01EE /* PHY Specific Control Register */ |
| #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
Definition at line 52 of file pch_gbe_phy.c.
| #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ |
Definition at line 47 of file pch_gbe_phy.c.
| #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ |
Definition at line 48 of file pch_gbe_phy.c.
| #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ |
Definition at line 50 of file pch_gbe_phy.c.
| #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ |
Definition at line 54 of file pch_gbe_phy.c.
| #define MII_CR_POWER_DOWN 0x0800 /* Power down */ |
Definition at line 51 of file pch_gbe_phy.c.
| #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ |
Definition at line 55 of file pch_gbe_phy.c.
| #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |
Definition at line 49 of file pch_gbe_phy.c.
| #define MII_CR_SPEED_10 0x0000 |
Definition at line 58 of file pch_gbe_phy.c.
| #define MII_CR_SPEED_100 0x2000 |
Definition at line 57 of file pch_gbe_phy.c.
| #define MII_CR_SPEED_1000 0x0040 |
Definition at line 56 of file pch_gbe_phy.c.
| #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ |
Definition at line 53 of file pch_gbe_phy.c.
| #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ |
Definition at line 46 of file pch_gbe_phy.c.
| #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ |
Definition at line 70 of file pch_gbe_phy.c.
| #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ |
Definition at line 69 of file pch_gbe_phy.c.
| #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ |
Definition at line 75 of file pch_gbe_phy.c.
| #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ |
Definition at line 74 of file pch_gbe_phy.c.
| #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ |
Definition at line 73 of file pch_gbe_phy.c.
| #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ |
Definition at line 72 of file pch_gbe_phy.c.
| #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ |
Definition at line 71 of file pch_gbe_phy.c.
| #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ |
Definition at line 64 of file pch_gbe_phy.c.
| #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ |
Definition at line 66 of file pch_gbe_phy.c.
| #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ |
Definition at line 61 of file pch_gbe_phy.c.
| #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ |
Definition at line 68 of file pch_gbe_phy.c.
| #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ |
Definition at line 62 of file pch_gbe_phy.c.
| #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ |
Definition at line 63 of file pch_gbe_phy.c.
| #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ |
Definition at line 67 of file pch_gbe_phy.c.
| #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ |
Definition at line 65 of file pch_gbe_phy.c.
| #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */ |
Definition at line 37 of file pch_gbe_phy.c.
| #define PHY_1000T_CTRL_DEFAULT 0x0300 /* 1000Base-T Control Register */ |
Definition at line 88 of file pch_gbe_phy.c.
| #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */ |
Definition at line 38 of file pch_gbe_phy.c.
| #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ |
Definition at line 32 of file pch_gbe_phy.c.
| #define PHY_AUTONEG_ADV_DEFAULT 0x01e0 /* Autoneg Advertisement */ |
Definition at line 86 of file pch_gbe_phy.c.
| #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Register */ |
Definition at line 34 of file pch_gbe_phy.c.
| #define PHY_CONTROL 0x00 /* Control Register */ |
Definition at line 28 of file pch_gbe_phy.c.
| #define PHY_CONTROL_DEFAULT 0x1140 /* Control Register */ |
Definition at line 85 of file pch_gbe_phy.c.
| #define PHY_EXT_PHYSP_CONTROL 0x14 /* Extended PHY Specific Control Register */ |
Definition at line 41 of file pch_gbe_phy.c.
| #define PHY_EXT_PHYSP_STATUS 0x1B /* Extended PHY Specific Status Register */ |
Definition at line 43 of file pch_gbe_phy.c.
| #define PHY_EXT_STATUS 0x0F /* Extended Status Register */ |
Definition at line 39 of file pch_gbe_phy.c.
| #define PHY_ID1 0x02 /* Phy Id Register (word 1) */ |
Definition at line 30 of file pch_gbe_phy.c.
| #define PHY_ID2 0x03 /* Phy Id Register (word 2) */ |
Definition at line 31 of file pch_gbe_phy.c.
| #define PHY_LED_CONTROL 0x18 /* LED Control Register */ |
Definition at line 42 of file pch_gbe_phy.c.
| #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ |
Definition at line 33 of file pch_gbe_phy.c.
| #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ |
Definition at line 36 of file pch_gbe_phy.c.
| #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ |
Definition at line 24 of file pch_gbe_phy.c.
| #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ |
Definition at line 35 of file pch_gbe_phy.c.
| #define PHY_NEXT_PAGE_TX_DEFAULT 0x2001 /* Next Page TX */ |
Definition at line 87 of file pch_gbe_phy.c.
| #define PHY_PHYSP_CONTROL 0x10 /* PHY Specific Control Register */ |
Definition at line 40 of file pch_gbe_phy.c.
| #define PHY_PHYSP_CONTROL_DEFAULT 0x01EE /* PHY Specific Control Register */ |
Definition at line 89 of file pch_gbe_phy.c.
| #define PHY_REVISION_MASK 0x000F |
Definition at line 78 of file pch_gbe_phy.c.
| #define PHY_STATUS 0x01 /* Status Regiser */ |
Definition at line 29 of file pch_gbe_phy.c.
| #define PHYSP_CTRL_ASSERT_CRS_TX 0x0800 |
Definition at line 81 of file pch_gbe_phy.c.
| s32 pch_gbe_phy_get_id | ( | struct pch_gbe_hw * | hw | ) |
pch_gbe_phy_get_id - Retrieve the PHY ID and revision : Pointer to the HW structure Returns 0: Successful. Negative value: Failed.
Definition at line 98 of file pch_gbe_phy.c.
| void pch_gbe_phy_hw_reset | ( | struct pch_gbe_hw * | hw | ) |
pch_gbe_phy_hw_reset - PHY hardware reset : Pointer to the HW structure
Definition at line 185 of file pch_gbe_phy.c.
| void pch_gbe_phy_init_setting | ( | struct pch_gbe_hw * | hw | ) |
pch_gbe_phy_init_setting - PHY initial setting : Pointer to the HW structure
Definition at line 247 of file pch_gbe_phy.c.
| void pch_gbe_phy_power_down | ( | struct pch_gbe_hw * | hw | ) |
pch_gbe_phy_power_down - Power down PHY : Pointer to the HW structure
Definition at line 218 of file pch_gbe_phy.c.
| void pch_gbe_phy_power_up | ( | struct pch_gbe_hw * | hw | ) |
pch_gbe_phy_power_up - restore link in case the phy was powered down : Pointer to the HW structure
Definition at line 201 of file pch_gbe_phy.c.
| s32 pch_gbe_phy_read_reg_miic | ( | struct pch_gbe_hw * | hw, |
| u32 | offset, | ||
| u16 * | data | ||
| ) |
pch_gbe_phy_read_reg_miic - Read MII control register : Pointer to the HW structure : Register offset to be read : Pointer to the read data Returns 0: Successful. -EINVAL: Invalid argument.
Definition at line 132 of file pch_gbe_phy.c.
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inline |
pch_gbe_phy_set_rgmii - RGMII interface setting : Pointer to the HW structure
Definition at line 238 of file pch_gbe_phy.c.
| void pch_gbe_phy_sw_reset | ( | struct pch_gbe_hw * | hw | ) |
pch_gbe_phy_sw_reset - PHY software reset : Pointer to the HW structure
Definition at line 171 of file pch_gbe_phy.c.
| s32 pch_gbe_phy_write_reg_miic | ( | struct pch_gbe_hw * | hw, |
| u32 | offset, | ||
| u16 | data | ||
| ) |
pch_gbe_phy_write_reg_miic - Write MII control register : Pointer to the HW structure : Register offset to be read : data to write to register at offset Returns 0: Successful. -EINVAL: Invalid argument.
Definition at line 154 of file pch_gbe_phy.c.
1.8.2