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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/kernel.h>#include <linux/module.h>#include <linux/pci.h>#include <linux/delay.h>#include <linux/errno.h>#include <linux/list.h>#include <linux/interrupt.h>#include <linux/usb/ch9.h>#include <linux/usb/gadget.h>#include <linux/gpio.h>#include <linux/irq.h>Go to the source code of this file.
Data Structures | |
| struct | pch_udc_data_dma_desc |
| struct | pch_udc_stp_dma_desc |
| struct | pch_udc_cfg_data |
| struct | pch_udc_ep |
| struct | pch_vbus_gpio_data |
| struct | pch_udc_dev |
| struct | pch_udc_request |
Macros | |
| #define | pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| #define | PCH_VBUS_PERIOD 3000 /* VBUS polling period (msec) */ |
| #define | PCH_VBUS_INTERVAL 10 /* VBUS polling interval (msec) */ |
| #define | UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */ |
| #define | UDC_EPCTL_ADDR 0x00 /* Endpoint control */ |
| #define | UDC_EPSTS_ADDR 0x04 /* Endpoint status */ |
| #define | UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */ |
| #define | UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */ |
| #define | UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */ |
| #define | UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */ |
| #define | UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */ |
| #define | UDC_DEVCFG_ADDR 0x400 /* Device configuration */ |
| #define | UDC_DEVCTL_ADDR 0x404 /* Device control */ |
| #define | UDC_DEVSTS_ADDR 0x408 /* Device status */ |
| #define | UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */ |
| #define | UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */ |
| #define | UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */ |
| #define | UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */ |
| #define | UDC_DEVLPM_ADDR 0x41C /* LPM control / status */ |
| #define | UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */ |
| #define | UDC_SRST_ADDR 0x4fc /* SOFT RESET register */ |
| #define | UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */ |
| #define | UDC_EPCTL_MRXFLUSH (1 << 12) |
| #define | UDC_EPCTL_RRDY (1 << 9) |
| #define | UDC_EPCTL_CNAK (1 << 8) |
| #define | UDC_EPCTL_SNAK (1 << 7) |
| #define | UDC_EPCTL_NAK (1 << 6) |
| #define | UDC_EPCTL_P (1 << 3) |
| #define | UDC_EPCTL_F (1 << 1) |
| #define | UDC_EPCTL_S (1 << 0) |
| #define | UDC_EPCTL_ET_SHIFT 4 |
| #define | UDC_EPCTL_ET_MASK 0x00000030 |
| #define | UDC_EPCTL_ET_CONTROL 0 |
| #define | UDC_EPCTL_ET_ISO 1 |
| #define | UDC_EPCTL_ET_BULK 2 |
| #define | UDC_EPCTL_ET_INTERRUPT 3 |
| #define | UDC_EPSTS_XFERDONE (1 << 27) |
| #define | UDC_EPSTS_RSS (1 << 26) |
| #define | UDC_EPSTS_RCS (1 << 25) |
| #define | UDC_EPSTS_TXEMPTY (1 << 24) |
| #define | UDC_EPSTS_TDC (1 << 10) |
| #define | UDC_EPSTS_HE (1 << 9) |
| #define | UDC_EPSTS_MRXFIFO_EMP (1 << 8) |
| #define | UDC_EPSTS_BNA (1 << 7) |
| #define | UDC_EPSTS_IN (1 << 6) |
| #define | UDC_EPSTS_OUT_SHIFT 4 |
| #define | UDC_EPSTS_OUT_MASK 0x00000030 |
| #define | UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0 |
| #define | UDC_EPSTS_OUT_SETUP 2 |
| #define | UDC_EPSTS_OUT_DATA 1 |
| #define | UDC_DEVCFG_CSR_PRG (1 << 17) |
| #define | UDC_DEVCFG_SP (1 << 3) |
| #define | UDC_DEVCFG_SPD_HS 0x0 |
| #define | UDC_DEVCFG_SPD_FS 0x1 |
| #define | UDC_DEVCFG_SPD_LS 0x2 |
| #define | UDC_DEVCTL_THLEN_SHIFT 24 |
| #define | UDC_DEVCTL_BRLEN_SHIFT 16 |
| #define | UDC_DEVCTL_CSR_DONE (1 << 13) |
| #define | UDC_DEVCTL_SD (1 << 10) |
| #define | UDC_DEVCTL_MODE (1 << 9) |
| #define | UDC_DEVCTL_BREN (1 << 8) |
| #define | UDC_DEVCTL_THE (1 << 7) |
| #define | UDC_DEVCTL_DU (1 << 4) |
| #define | UDC_DEVCTL_TDE (1 << 3) |
| #define | UDC_DEVCTL_RDE (1 << 2) |
| #define | UDC_DEVCTL_RES (1 << 0) |
| #define | UDC_DEVSTS_TS_SHIFT 18 |
| #define | UDC_DEVSTS_ENUM_SPEED_SHIFT 13 |
| #define | UDC_DEVSTS_ALT_SHIFT 8 |
| #define | UDC_DEVSTS_INTF_SHIFT 4 |
| #define | UDC_DEVSTS_CFG_SHIFT 0 |
| #define | UDC_DEVSTS_TS_MASK 0xfffc0000 |
| #define | UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000 |
| #define | UDC_DEVSTS_ALT_MASK 0x00000f00 |
| #define | UDC_DEVSTS_INTF_MASK 0x000000f0 |
| #define | UDC_DEVSTS_CFG_MASK 0x0000000f |
| #define | UDC_DEVSTS_ENUM_SPEED_FULL 1 |
| #define | UDC_DEVSTS_ENUM_SPEED_HIGH 0 |
| #define | UDC_DEVSTS_ENUM_SPEED_LOW 2 |
| #define | UDC_DEVSTS_ENUM_SPEED_FULLX 3 |
| #define | UDC_DEVINT_RWKP (1 << 7) |
| #define | UDC_DEVINT_ENUM (1 << 6) |
| #define | UDC_DEVINT_SOF (1 << 5) |
| #define | UDC_DEVINT_US (1 << 4) |
| #define | UDC_DEVINT_UR (1 << 3) |
| #define | UDC_DEVINT_ES (1 << 2) |
| #define | UDC_DEVINT_SI (1 << 1) |
| #define | UDC_DEVINT_SC (1 << 0) |
| #define | UDC_DEVINT_MSK 0x7f |
| #define | UDC_EPINT_IN_SHIFT 0 |
| #define | UDC_EPINT_OUT_SHIFT 16 |
| #define | UDC_EPINT_IN_EP0 (1 << 0) |
| #define | UDC_EPINT_OUT_EP0 (1 << 16) |
| #define | UDC_EPINT_MSK_DISABLE_ALL 0xffffffff |
| #define | UDC_CSR_BUSY (1 << 0) |
| #define | UDC_PSRST (1 << 1) |
| #define | UDC_SRST (1 << 0) |
| #define | UDC_CSR_NE_NUM_SHIFT 0 |
| #define | UDC_CSR_NE_DIR_SHIFT 4 |
| #define | UDC_CSR_NE_TYPE_SHIFT 5 |
| #define | UDC_CSR_NE_CFG_SHIFT 7 |
| #define | UDC_CSR_NE_INTF_SHIFT 11 |
| #define | UDC_CSR_NE_ALT_SHIFT 15 |
| #define | UDC_CSR_NE_MAX_PKT_SHIFT 19 |
| #define | UDC_CSR_NE_NUM_MASK 0x0000000f |
| #define | UDC_CSR_NE_DIR_MASK 0x00000010 |
| #define | UDC_CSR_NE_TYPE_MASK 0x00000060 |
| #define | UDC_CSR_NE_CFG_MASK 0x00000780 |
| #define | UDC_CSR_NE_INTF_MASK 0x00007800 |
| #define | UDC_CSR_NE_ALT_MASK 0x00078000 |
| #define | UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000 |
| #define | PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4) |
| #define | PCH_UDC_EPINT(in, num) (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT))) |
| #define | UDC_EP0IN_IDX 0 |
| #define | UDC_EP0OUT_IDX 1 |
| #define | UDC_EPIN_IDX(ep) (ep * 2) |
| #define | UDC_EPOUT_IDX(ep) (ep * 2 + 1) |
| #define | PCH_UDC_EP0 0 |
| #define | PCH_UDC_EP1 1 |
| #define | PCH_UDC_EP2 2 |
| #define | PCH_UDC_EP3 3 |
| #define | PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */ |
| #define | PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */ |
| #define | PCH_UDC_BRLEN 0x0F /* Burst length */ |
| #define | PCH_UDC_THLEN 0x1F /* Threshold length */ |
| #define | UDC_EP0IN_BUFF_SIZE 16 |
| #define | UDC_EPIN_BUFF_SIZE 256 |
| #define | UDC_EP0OUT_BUFF_SIZE 16 |
| #define | UDC_EPOUT_BUFF_SIZE 256 |
| #define | UDC_EP0IN_MAX_PKT_SIZE 64 |
| #define | UDC_EP0OUT_MAX_PKT_SIZE 64 |
| #define | UDC_BULK_MAX_PKT_SIZE 512 |
| #define | DMA_DIR_RX 1 /* DMA for data receive */ |
| #define | DMA_DIR_TX 2 /* DMA for data transmit */ |
| #define | DMA_ADDR_INVALID (~(dma_addr_t)0) |
| #define | UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */ |
| #define | PCH_UDC_BUFF_STS 0xC0000000 |
| #define | PCH_UDC_BS_HST_RDY 0x00000000 |
| #define | PCH_UDC_BS_DMA_BSY 0x40000000 |
| #define | PCH_UDC_BS_DMA_DONE 0x80000000 |
| #define | PCH_UDC_BS_HST_BSY 0xC0000000 |
| #define | PCH_UDC_RXTX_STS 0x30000000 |
| #define | PCH_UDC_RTS_SUCC 0x00000000 |
| #define | PCH_UDC_RTS_DESERR 0x10000000 |
| #define | PCH_UDC_RTS_BUFERR 0x30000000 |
| #define | PCH_UDC_DMA_LAST 0x08000000 |
| #define | PCH_UDC_RXTX_BYTES 0x0000ffff |
| #define | PCH_UDC_PCI_BAR 1 |
| #define | PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808 |
| #define | PCI_VENDOR_ID_ROHM 0x10DB |
| #define | PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D |
| #define | PCI_DEVICE_ID_ML7831_IOH_UDC 0x8808 |
| #define | pch_udc_suspend NULL |
| #define | pch_udc_resume NULL |
Functions | |
| struct pch_udc_stp_dma_desc | __attribute ((packed)) |
| module_param_named (speed_fs, speed_fs, bool, S_IRUGO) | |
| MODULE_PARM_DESC (speed_fs,"true for Full speed operation") | |
| MODULE_DEVICE_TABLE (pci, pch_udc_pcidev_id) | |
| module_pci_driver (pch_udc_driver) | |
| MODULE_DESCRIPTION ("Intel EG20T USB Device Controller") | |
| MODULE_AUTHOR ("LAPIS Semiconductor, <[email protected]>") | |
| MODULE_LICENSE ("GPL") | |
Variables | |
| u32 | status |
| u32 | reserved |
| struct usb_ctrlrequest | request |
| struct pch_udc_cfg_data | __attribute |
| struct pch_udc_dev * | pch_udc |
| #define DMA_ADDR_INVALID (~(dma_addr_t)0) |
| #define PCH_UDC_CSR | ( | ep | ) | (UDC_CSR_ADDR + ep*4) |
| #define PCH_UDC_EPINT | ( | in, | |
| num | |||
| ) | (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT))) |
| #define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */ |
| #define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */ |
| #define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */ |
| #define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */ |
| #define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */ |
| struct pch_udc_stp_dma_desc __attribute | ( | (packed) | ) |
| MODULE_AUTHOR | ( | "LAPIS | Semiconductor, |
| < tomoya-linux @dsn.lapis-semi.com >" | |||
| ) |
| MODULE_DESCRIPTION | ( | "Intel EG20T USB Device Controller" | ) |
| MODULE_DEVICE_TABLE | ( | pci | , |
| pch_udc_pcidev_id | |||
| ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| module_pci_driver | ( | pch_udc_driver | ) |
| struct pch_udc_cfg_data __attribute |
| struct pch_udc_dev* pch_udc |
| struct usb_ctrlrequest request |
1.8.2