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| #define | PCISH5_PID 0x350d |
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| #define | PCISH5_VID 0x1054 |
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| #define | ST_TYPE0 0x00 /* Configuration cycle type 0 */ |
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| #define | ST_TYPE1 0x01 /* Configuration cycle type 1 */ |
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| #define | PCISH5_VCR_STATUS 0x00 |
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| #define | PCISH5_VCR_VERSION 0x08 |
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| #define | PCISH5_ICR_CR 0x100 /* PCI control register values */ |
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| #define | CR_PBAM (1<<12) |
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| #define | CR_PFCS (1<<11) |
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| #define | CR_FTO (1<<10) |
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| #define | CR_PFE (1<<9) |
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| #define | CR_TBS (1<<8) |
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| #define | CR_SPUE (1<<7) |
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| #define | CR_BMAM (1<<6) |
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| #define | CR_HOST (1<<5) |
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| #define | CR_CLKEN (1<<4) |
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| #define | CR_SOCS (1<<3) |
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| #define | CR_IOCS (1<<2) |
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| #define | CR_RSTCTL (1<<1) |
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| #define | CR_CFINT (1<<0) |
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| #define | CR_LOCK_MASK 0xa5000000 |
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| #define | PCISH5_ICR_INT 0x114 /* Interrupt registert values */ |
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| #define | INT_MADIM (1<<2) |
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| #define | PCISH5_ICR_LSR0 0X104 /* Local space register values */ |
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| #define | PCISH5_ICR_LSR1 0X108 /* Local space register values */ |
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| #define | PCISH5_ICR_LAR0 0x10c /* Local address register values */ |
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| #define | PCISH5_ICR_LAR1 0x110 /* Local address register values */ |
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| #define | PCISH5_ICR_INTM 0x118 /* Interrupt mask register values */ |
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| #define | PCISH5_ICR_AIR 0x11c /* Interrupt error address information register values */ |
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| #define | PCISH5_ICR_CIR 0x120 /* Interrupt error command information register values */ |
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| #define | PCISH5_ICR_AINT 0x130 /* Interrupt error arbiter interrupt register values */ |
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| #define | PCISH5_ICR_AINTM 0x134 /* Interrupt error arbiter interrupt mask register values */ |
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| #define | PCISH5_ICR_BMIR 0x138 /* Interrupt error info register of bus master values */ |
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| #define | PCISH5_ICR_PAR 0x1c0 /* Pio address register values */ |
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| #define | PCISH5_ICR_MBR 0x1c4 /* Memory space bank register values */ |
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| #define | PCISH5_ICR_IOBR 0x1c8 /* I/O space bank register values */ |
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| #define | PCISH5_ICR_PINT 0x1cc /* power management interrupt register values */ |
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| #define | PCISH5_ICR_PINTM 0x1d0 /* power management interrupt mask register values */ |
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| #define | PCISH5_ICR_MBMR 0x1d8 /* memory space bank mask register values */ |
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| #define | PCISH5_ICR_IOBMR 0x1dc /* I/O space bank mask register values */ |
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| #define | PCISH5_ICR_CSCR0 0x210 /* PCI cache snoop control register 0 */ |
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| #define | PCISH5_ICR_CSCR1 0x214 /* PCI cache snoop control register 1 */ |
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| #define | PCISH5_ICR_PDR 0x220 /* Pio data register values */ |
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| #define | PCISH5_ICR_CSR_VID 0x000 /* Vendor id */ |
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| #define | PCISH5_ICR_CSR_DID 0x002 /* Device id */ |
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| #define | PCISH5_ICR_CSR_CMD 0x004 /* Command register */ |
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| #define | PCISH5_ICR_CSR_STATUS 0x006 /* Stautus */ |
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| #define | PCISH5_ICR_CSR_IBAR0 0x010 /* I/O base address register */ |
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| #define | PCISH5_ICR_CSR_MBAR0 0x014 /* First Memory base address register */ |
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| #define | PCISH5_ICR_CSR_MBAR1 0x018 /* Second Memory base address register */ |
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| #define | SH5PCI_ICR_BASE (PHYS_PCI_BLOCK + 0x00040000) |
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| #define | SH5PCI_IO_BASE (PHYS_PCI_BLOCK + 0x00800000) |
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| #define | PCISH5_ICR_REG(x) ( pcicr_virt + (PCISH5_ICR_##x)) |
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| #define | SH5PCI_WRITE(reg, val) __raw_writel((u32)(val),PCISH5_ICR_REG(reg)) |
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| #define | SH5PCI_WRITE_SHORT(reg, val) __raw_writew((u16)(val),PCISH5_ICR_REG(reg)) |
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| #define | SH5PCI_WRITE_BYTE(reg, val) __raw_writeb((u8)(val),PCISH5_ICR_REG(reg)) |
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| #define | SH5PCI_READ(reg) __raw_readl(PCISH5_ICR_REG(reg)) |
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| #define | SH5PCI_READ_SHORT(reg) __raw_readw(PCISH5_ICR_REG(reg)) |
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| #define | SH5PCI_READ_BYTE(reg) __raw_readb(PCISH5_ICR_REG(reg)) |
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| #define | SET_CONFIG_BITS(bus, devfn, where) ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000) |
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| #define | CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where) |
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| #define | PCISH5_MEM_SIZCONV(x) (((x / 0x40000) - 1) << 18) |
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| #define | PCISH5_IO_SIZCONV(x) (((x / 0x40000) - 1) << 18) |
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1.8.2