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Macros | Functions
pci_psycho.c File Reference
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/of_device.h>
#include <asm/iommu.h>
#include <asm/irq.h>
#include <asm/starfire.h>
#include <asm/prom.h>
#include <asm/upa.h>
#include "pci_impl.h"
#include "iommu_common.h"
#include "psycho_common.h"

Go to the source code of this file.

Macros

#define DRIVER_NAME   "psycho"
 
#define PFX   DRIVER_NAME ": "
 
#define PSYCHO_CONTROL   0x0010UL
 
#define PSYCHO_CONTROL_IMPL   0xf000000000000000UL /* Implementation of this PSYCHO*/
 
#define PSYCHO_CONTROL_VER   0x0f00000000000000UL /* Version of this PSYCHO */
 
#define PSYCHO_CONTROL_MID   0x00f8000000000000UL /* UPA Module ID of PSYCHO */
 
#define PSYCHO_CONTROL_IGN   0x0007c00000000000UL /* Interrupt Group Number */
 
#define PSYCHO_CONTROL_RESV   0x00003ffffffffff0UL /* Reserved */
 
#define PSYCHO_CONTROL_APCKEN   0x0000000000000008UL /* Address Parity Check Enable */
 
#define PSYCHO_CONTROL_APERR   0x0000000000000004UL /* Incoming System Addr Parerr */
 
#define PSYCHO_CONTROL_IAP   0x0000000000000002UL /* Invert UPA Parity */
 
#define PSYCHO_CONTROL_MODE   0x0000000000000001UL /* PSYCHO clock mode */
 
#define PSYCHO_PCIA_CTRL   0x2000UL
 
#define PSYCHO_PCIB_CTRL   0x4000UL
 
#define PSYCHO_PCICTRL_RESV1   0xfffffff000000000UL /* Reserved */
 
#define PSYCHO_PCICTRL_SBH_ERR   0x0000000800000000UL /* Streaming byte hole error */
 
#define PSYCHO_PCICTRL_SERR   0x0000000400000000UL /* SERR signal asserted */
 
#define PSYCHO_PCICTRL_SPEED   0x0000000200000000UL /* PCI speed (1 is U2P clock) */
 
#define PSYCHO_PCICTRL_RESV2   0x00000001ffc00000UL /* Reserved */
 
#define PSYCHO_PCICTRL_ARB_PARK   0x0000000000200000UL /* PCI arbitration parking */
 
#define PSYCHO_PCICTRL_RESV3   0x00000000001ff800UL /* Reserved */
 
#define PSYCHO_PCICTRL_SBH_INT   0x0000000000000400UL /* Streaming byte hole int enab */
 
#define PSYCHO_PCICTRL_WEN   0x0000000000000200UL /* Power Mgmt Wake Enable */
 
#define PSYCHO_PCICTRL_EEN   0x0000000000000100UL /* PCI Error Interrupt Enable */
 
#define PSYCHO_PCICTRL_RESV4   0x00000000000000c0UL /* Reserved */
 
#define PSYCHO_PCICTRL_AEN   0x000000000000003fUL /* PCI DVMA Arbitration Enable */
 
#define PSYCHO_STRBUF_CONTROL_A   0x2800UL
 
#define PSYCHO_STRBUF_CONTROL_B   0x4800UL
 
#define PSYCHO_STRBUF_CTRL_LPTR   0x00000000000000f0UL /* LRU Lock Pointer */
 
#define PSYCHO_STRBUF_CTRL_LENAB   0x0000000000000008UL /* LRU Lock Enable */
 
#define PSYCHO_STRBUF_CTRL_RRDIS   0x0000000000000004UL /* Rerun Disable */
 
#define PSYCHO_STRBUF_CTRL_DENAB   0x0000000000000002UL /* Diagnostic Mode Enable */
 
#define PSYCHO_STRBUF_CTRL_ENAB   0x0000000000000001UL /* Streaming Buffer Enable */
 
#define PSYCHO_STRBUF_FLUSH_A   0x2808UL
 
#define PSYCHO_STRBUF_FLUSH_B   0x4808UL
 
#define PSYCHO_STRBUF_FSYNC_A   0x2810UL
 
#define PSYCHO_STRBUF_FSYNC_B   0x4810UL
 
#define PSYCHO_STC_DATA_A   0xb000UL
 
#define PSYCHO_STC_DATA_B   0xc000UL
 
#define PSYCHO_STC_ERR_A   0xb400UL
 
#define PSYCHO_STC_ERR_B   0xc400UL
 
#define PSYCHO_STC_TAG_A   0xb800UL
 
#define PSYCHO_STC_TAG_B   0xc800UL
 
#define PSYCHO_STC_LINE_A   0xb900UL
 
#define PSYCHO_STC_LINE_B   0xc900UL
 
#define PSYCHO_IOMMU_CONTROL   0x0200UL
 
#define PSYCHO_IOMMU_CTRL_RESV   0xfffffffff9000000UL /* Reserved */
 
#define PSYCHO_IOMMU_CTRL_XLTESTAT   0x0000000006000000UL /* Translation Error Status */
 
#define PSYCHO_IOMMU_CTRL_XLTEERR   0x0000000001000000UL /* Translation Error encountered */
 
#define PSYCHO_IOMMU_CTRL_LCKEN   0x0000000000800000UL /* Enable translation locking */
 
#define PSYCHO_IOMMU_CTRL_LCKPTR   0x0000000000780000UL /* Translation lock pointer */
 
#define PSYCHO_IOMMU_CTRL_TSBSZ   0x0000000000070000UL /* TSB Size */
 
#define PSYCHO_IOMMU_TSBSZ_1K   0x0000000000000000UL /* TSB Table 1024 8-byte entries */
 
#define PSYCHO_IOMMU_TSBSZ_2K   0x0000000000010000UL /* TSB Table 2048 8-byte entries */
 
#define PSYCHO_IOMMU_TSBSZ_4K   0x0000000000020000UL /* TSB Table 4096 8-byte entries */
 
#define PSYCHO_IOMMU_TSBSZ_8K   0x0000000000030000UL /* TSB Table 8192 8-byte entries */
 
#define PSYCHO_IOMMU_TSBSZ_16K   0x0000000000040000UL /* TSB Table 16k 8-byte entries */
 
#define PSYCHO_IOMMU_TSBSZ_32K   0x0000000000050000UL /* TSB Table 32k 8-byte entries */
 
#define PSYCHO_IOMMU_TSBSZ_64K   0x0000000000060000UL /* TSB Table 64k 8-byte entries */
 
#define PSYCHO_IOMMU_TSBSZ_128K   0x0000000000070000UL /* TSB Table 128k 8-byte entries */
 
#define PSYCHO_IOMMU_CTRL_RESV2   0x000000000000fff8UL /* Reserved */
 
#define PSYCHO_IOMMU_CTRL_TBWSZ   0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
 
#define PSYCHO_IOMMU_CTRL_DENAB   0x0000000000000002UL /* Diagnostic mode enable */
 
#define PSYCHO_IOMMU_CTRL_ENAB   0x0000000000000001UL /* IOMMU Enable */
 
#define PSYCHO_IOMMU_TSBBASE   0x0208UL
 
#define PSYCHO_IOMMU_FLUSH   0x0210UL
 
#define PSYCHO_IOMMU_TAG   0xa580UL
 
#define PSYCHO_IOMMU_DATA   0xa600UL
 
#define PSYCHO_UE_AFSR   0x0030UL
 
#define PSYCHO_UEAFSR_PPIO   0x8000000000000000UL /* Primary PIO is cause */
 
#define PSYCHO_UEAFSR_PDRD   0x4000000000000000UL /* Primary DVMA read is cause */
 
#define PSYCHO_UEAFSR_PDWR   0x2000000000000000UL /* Primary DVMA write is cause */
 
#define PSYCHO_UEAFSR_SPIO   0x1000000000000000UL /* Secondary PIO is cause */
 
#define PSYCHO_UEAFSR_SDRD   0x0800000000000000UL /* Secondary DVMA read is cause */
 
#define PSYCHO_UEAFSR_SDWR   0x0400000000000000UL /* Secondary DVMA write is cause*/
 
#define PSYCHO_UEAFSR_RESV1   0x03ff000000000000UL /* Reserved */
 
#define PSYCHO_UEAFSR_BMSK   0x0000ffff00000000UL /* Bytemask of failed transfer */
 
#define PSYCHO_UEAFSR_DOFF   0x00000000e0000000UL /* Doubleword Offset */
 
#define PSYCHO_UEAFSR_MID   0x000000001f000000UL /* UPA MID causing the fault */
 
#define PSYCHO_UEAFSR_BLK   0x0000000000800000UL /* Trans was block operation */
 
#define PSYCHO_UEAFSR_RESV2   0x00000000007fffffUL /* Reserved */
 
#define PSYCHO_UE_AFAR   0x0038UL
 
#define PSYCHO_CE_AFSR   0x0040UL
 
#define PSYCHO_CEAFSR_PPIO   0x8000000000000000UL /* Primary PIO is cause */
 
#define PSYCHO_CEAFSR_PDRD   0x4000000000000000UL /* Primary DVMA read is cause */
 
#define PSYCHO_CEAFSR_PDWR   0x2000000000000000UL /* Primary DVMA write is cause */
 
#define PSYCHO_CEAFSR_SPIO   0x1000000000000000UL /* Secondary PIO is cause */
 
#define PSYCHO_CEAFSR_SDRD   0x0800000000000000UL /* Secondary DVMA read is cause */
 
#define PSYCHO_CEAFSR_SDWR   0x0400000000000000UL /* Secondary DVMA write is cause*/
 
#define PSYCHO_CEAFSR_RESV1   0x0300000000000000UL /* Reserved */
 
#define PSYCHO_CEAFSR_ESYND   0x00ff000000000000UL /* Syndrome Bits */
 
#define PSYCHO_CEAFSR_BMSK   0x0000ffff00000000UL /* Bytemask of failed transfer */
 
#define PSYCHO_CEAFSR_DOFF   0x00000000e0000000UL /* Double Offset */
 
#define PSYCHO_CEAFSR_MID   0x000000001f000000UL /* UPA MID causing the fault */
 
#define PSYCHO_CEAFSR_BLK   0x0000000000800000UL /* Trans was block operation */
 
#define PSYCHO_CEAFSR_RESV2   0x00000000007fffffUL /* Reserved */
 
#define PSYCHO_CE_AFAR   0x0040UL
 
#define PSYCHO_PCI_AFSR_A   0x2010UL
 
#define PSYCHO_PCI_AFSR_B   0x4010UL
 
#define PSYCHO_PCI_AFAR_A   0x2018UL
 
#define PSYCHO_PCI_AFAR_B   0x4018UL
 
#define PSYCHO_ECC_CTRL   0x0020
 
#define PSYCHO_ECCCTRL_EE   0x8000000000000000UL /* Enable ECC Checking */
 
#define PSYCHO_ECCCTRL_UE   0x4000000000000000UL /* Enable UE Interrupts */
 
#define PSYCHO_ECCCTRL_CE   0x2000000000000000UL /* Enable CE INterrupts */
 
#define PSYCHO_IRQ_RETRY   0x1a00UL
 
#define PSYCHO_PCIA_DIAG   0x2020UL
 
#define PSYCHO_PCIB_DIAG   0x4020UL
 
#define PSYCHO_PCIDIAG_RESV   0xffffffffffffff80UL /* Reserved */
 
#define PSYCHO_PCIDIAG_DRETRY   0x0000000000000040UL /* Disable retry limit */
 
#define PSYCHO_PCIDIAG_DISYNC   0x0000000000000020UL /* Disable DMA wr / irq sync */
 
#define PSYCHO_PCIDIAG_DDWSYNC   0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
 
#define PSYCHO_PCIDIAG_IDDPAR   0x0000000000000008UL /* Invert DMA data parity */
 
#define PSYCHO_PCIDIAG_IPDPAR   0x0000000000000004UL /* Invert PIO data parity */
 
#define PSYCHO_PCIDIAG_IPAPAR   0x0000000000000002UL /* Invert PIO address parity */
 
#define PSYCHO_PCIDIAG_LPBACK   0x0000000000000001UL /* Enable loopback mode */
 
#define PSYCHO_IOSPACE_A   0x002000000UL
 
#define PSYCHO_IOSPACE_B   0x002010000UL
 
#define PSYCHO_IOSPACE_SIZE   0x00000ffffUL
 
#define PSYCHO_MEMSPACE_A   0x100000000UL
 
#define PSYCHO_MEMSPACE_B   0x180000000UL
 
#define PSYCHO_MEMSPACE_SIZE   0x07fffffffUL
 
#define PSYCHO_CONFIGSPACE   0x001000000UL
 

Functions

 subsys_initcall (psycho_init)
 

Macro Definition Documentation

#define DRIVER_NAME   "psycho"

Definition at line 27 of file pci_psycho.c.

#define PFX   DRIVER_NAME ": "

Definition at line 28 of file pci_psycho.c.

#define PSYCHO_CE_AFAR   0x0040UL

Definition at line 209 of file pci_psycho.c.

#define PSYCHO_CE_AFSR   0x0040UL

Definition at line 195 of file pci_psycho.c.

#define PSYCHO_CEAFSR_BLK   0x0000000000800000UL /* Trans was block operation */

Definition at line 207 of file pci_psycho.c.

#define PSYCHO_CEAFSR_BMSK   0x0000ffff00000000UL /* Bytemask of failed transfer */

Definition at line 204 of file pci_psycho.c.

#define PSYCHO_CEAFSR_DOFF   0x00000000e0000000UL /* Double Offset */

Definition at line 205 of file pci_psycho.c.

#define PSYCHO_CEAFSR_ESYND   0x00ff000000000000UL /* Syndrome Bits */

Definition at line 203 of file pci_psycho.c.

#define PSYCHO_CEAFSR_MID   0x000000001f000000UL /* UPA MID causing the fault */

Definition at line 206 of file pci_psycho.c.

#define PSYCHO_CEAFSR_PDRD   0x4000000000000000UL /* Primary DVMA read is cause */

Definition at line 197 of file pci_psycho.c.

#define PSYCHO_CEAFSR_PDWR   0x2000000000000000UL /* Primary DVMA write is cause */

Definition at line 198 of file pci_psycho.c.

#define PSYCHO_CEAFSR_PPIO   0x8000000000000000UL /* Primary PIO is cause */

Definition at line 196 of file pci_psycho.c.

#define PSYCHO_CEAFSR_RESV1   0x0300000000000000UL /* Reserved */

Definition at line 202 of file pci_psycho.c.

#define PSYCHO_CEAFSR_RESV2   0x00000000007fffffUL /* Reserved */

Definition at line 208 of file pci_psycho.c.

#define PSYCHO_CEAFSR_SDRD   0x0800000000000000UL /* Secondary DVMA read is cause */

Definition at line 200 of file pci_psycho.c.

#define PSYCHO_CEAFSR_SDWR   0x0400000000000000UL /* Secondary DVMA write is cause*/

Definition at line 201 of file pci_psycho.c.

#define PSYCHO_CEAFSR_SPIO   0x1000000000000000UL /* Secondary PIO is cause */

Definition at line 199 of file pci_psycho.c.

#define PSYCHO_CONFIGSPACE   0x001000000UL

Definition at line 505 of file pci_psycho.c.

#define PSYCHO_CONTROL   0x0010UL

Definition at line 31 of file pci_psycho.c.

#define PSYCHO_CONTROL_APCKEN   0x0000000000000008UL /* Address Parity Check Enable */

Definition at line 37 of file pci_psycho.c.

#define PSYCHO_CONTROL_APERR   0x0000000000000004UL /* Incoming System Addr Parerr */

Definition at line 38 of file pci_psycho.c.

#define PSYCHO_CONTROL_IAP   0x0000000000000002UL /* Invert UPA Parity */

Definition at line 39 of file pci_psycho.c.

#define PSYCHO_CONTROL_IGN   0x0007c00000000000UL /* Interrupt Group Number */

Definition at line 35 of file pci_psycho.c.

#define PSYCHO_CONTROL_IMPL   0xf000000000000000UL /* Implementation of this PSYCHO*/

Definition at line 32 of file pci_psycho.c.

#define PSYCHO_CONTROL_MID   0x00f8000000000000UL /* UPA Module ID of PSYCHO */

Definition at line 34 of file pci_psycho.c.

#define PSYCHO_CONTROL_MODE   0x0000000000000001UL /* PSYCHO clock mode */

Definition at line 40 of file pci_psycho.c.

#define PSYCHO_CONTROL_RESV   0x00003ffffffffff0UL /* Reserved */

Definition at line 36 of file pci_psycho.c.

#define PSYCHO_CONTROL_VER   0x0f00000000000000UL /* Version of this PSYCHO */

Definition at line 33 of file pci_psycho.c.

#define PSYCHO_ECC_CTRL   0x0020

Definition at line 283 of file pci_psycho.c.

#define PSYCHO_ECCCTRL_CE   0x2000000000000000UL /* Enable CE INterrupts */

Definition at line 286 of file pci_psycho.c.

#define PSYCHO_ECCCTRL_EE   0x8000000000000000UL /* Enable ECC Checking */

Definition at line 284 of file pci_psycho.c.

#define PSYCHO_ECCCTRL_UE   0x4000000000000000UL /* Enable UE Interrupts */

Definition at line 285 of file pci_psycho.c.

#define PSYCHO_IOMMU_CONTROL   0x0200UL

Definition at line 89 of file pci_psycho.c.

#define PSYCHO_IOMMU_CTRL_DENAB   0x0000000000000002UL /* Diagnostic mode enable */

Definition at line 106 of file pci_psycho.c.

#define PSYCHO_IOMMU_CTRL_ENAB   0x0000000000000001UL /* IOMMU Enable */

Definition at line 107 of file pci_psycho.c.

#define PSYCHO_IOMMU_CTRL_LCKEN   0x0000000000800000UL /* Enable translation locking */

Definition at line 93 of file pci_psycho.c.

#define PSYCHO_IOMMU_CTRL_LCKPTR   0x0000000000780000UL /* Translation lock pointer */

Definition at line 94 of file pci_psycho.c.

#define PSYCHO_IOMMU_CTRL_RESV   0xfffffffff9000000UL /* Reserved */

Definition at line 90 of file pci_psycho.c.

#define PSYCHO_IOMMU_CTRL_RESV2   0x000000000000fff8UL /* Reserved */

Definition at line 104 of file pci_psycho.c.

#define PSYCHO_IOMMU_CTRL_TBWSZ   0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */

Definition at line 105 of file pci_psycho.c.

#define PSYCHO_IOMMU_CTRL_TSBSZ   0x0000000000070000UL /* TSB Size */

Definition at line 95 of file pci_psycho.c.

#define PSYCHO_IOMMU_CTRL_XLTEERR   0x0000000001000000UL /* Translation Error encountered */

Definition at line 92 of file pci_psycho.c.

#define PSYCHO_IOMMU_CTRL_XLTESTAT   0x0000000006000000UL /* Translation Error Status */

Definition at line 91 of file pci_psycho.c.

#define PSYCHO_IOMMU_DATA   0xa600UL

Definition at line 111 of file pci_psycho.c.

#define PSYCHO_IOMMU_FLUSH   0x0210UL

Definition at line 109 of file pci_psycho.c.

#define PSYCHO_IOMMU_TAG   0xa580UL

Definition at line 110 of file pci_psycho.c.

#define PSYCHO_IOMMU_TSBBASE   0x0208UL

Definition at line 108 of file pci_psycho.c.

#define PSYCHO_IOMMU_TSBSZ_128K   0x0000000000070000UL /* TSB Table 128k 8-byte entries */

Definition at line 103 of file pci_psycho.c.

#define PSYCHO_IOMMU_TSBSZ_16K   0x0000000000040000UL /* TSB Table 16k 8-byte entries */

Definition at line 100 of file pci_psycho.c.

#define PSYCHO_IOMMU_TSBSZ_1K   0x0000000000000000UL /* TSB Table 1024 8-byte entries */

Definition at line 96 of file pci_psycho.c.

#define PSYCHO_IOMMU_TSBSZ_2K   0x0000000000010000UL /* TSB Table 2048 8-byte entries */

Definition at line 97 of file pci_psycho.c.

#define PSYCHO_IOMMU_TSBSZ_32K   0x0000000000050000UL /* TSB Table 32k 8-byte entries */

Definition at line 101 of file pci_psycho.c.

#define PSYCHO_IOMMU_TSBSZ_4K   0x0000000000020000UL /* TSB Table 4096 8-byte entries */

Definition at line 98 of file pci_psycho.c.

#define PSYCHO_IOMMU_TSBSZ_64K   0x0000000000060000UL /* TSB Table 64k 8-byte entries */

Definition at line 102 of file pci_psycho.c.

#define PSYCHO_IOMMU_TSBSZ_8K   0x0000000000030000UL /* TSB Table 8192 8-byte entries */

Definition at line 99 of file pci_psycho.c.

#define PSYCHO_IOSPACE_A   0x002000000UL

Definition at line 479 of file pci_psycho.c.

#define PSYCHO_IOSPACE_B   0x002010000UL

Definition at line 480 of file pci_psycho.c.

#define PSYCHO_IOSPACE_SIZE   0x00000ffffUL

Definition at line 481 of file pci_psycho.c.

#define PSYCHO_IRQ_RETRY   0x1a00UL

Definition at line 382 of file pci_psycho.c.

#define PSYCHO_MEMSPACE_A   0x100000000UL

Definition at line 482 of file pci_psycho.c.

#define PSYCHO_MEMSPACE_B   0x180000000UL

Definition at line 483 of file pci_psycho.c.

#define PSYCHO_MEMSPACE_SIZE   0x07fffffffUL

Definition at line 484 of file pci_psycho.c.

#define PSYCHO_PCI_AFAR_A   0x2018UL

Definition at line 279 of file pci_psycho.c.

#define PSYCHO_PCI_AFAR_B   0x4018UL

Definition at line 280 of file pci_psycho.c.

#define PSYCHO_PCI_AFSR_A   0x2010UL

Definition at line 277 of file pci_psycho.c.

#define PSYCHO_PCI_AFSR_B   0x4010UL

Definition at line 278 of file pci_psycho.c.

#define PSYCHO_PCIA_CTRL   0x2000UL

Definition at line 41 of file pci_psycho.c.

#define PSYCHO_PCIA_DIAG   0x2020UL

Definition at line 383 of file pci_psycho.c.

#define PSYCHO_PCIB_CTRL   0x4000UL

Definition at line 42 of file pci_psycho.c.

#define PSYCHO_PCIB_DIAG   0x4020UL

Definition at line 384 of file pci_psycho.c.

#define PSYCHO_PCICTRL_AEN   0x000000000000003fUL /* PCI DVMA Arbitration Enable */

Definition at line 54 of file pci_psycho.c.

#define PSYCHO_PCICTRL_ARB_PARK   0x0000000000200000UL /* PCI arbitration parking */

Definition at line 48 of file pci_psycho.c.

#define PSYCHO_PCICTRL_EEN   0x0000000000000100UL /* PCI Error Interrupt Enable */

Definition at line 52 of file pci_psycho.c.

#define PSYCHO_PCICTRL_RESV1   0xfffffff000000000UL /* Reserved */

Definition at line 43 of file pci_psycho.c.

#define PSYCHO_PCICTRL_RESV2   0x00000001ffc00000UL /* Reserved */

Definition at line 47 of file pci_psycho.c.

#define PSYCHO_PCICTRL_RESV3   0x00000000001ff800UL /* Reserved */

Definition at line 49 of file pci_psycho.c.

#define PSYCHO_PCICTRL_RESV4   0x00000000000000c0UL /* Reserved */

Definition at line 53 of file pci_psycho.c.

#define PSYCHO_PCICTRL_SBH_ERR   0x0000000800000000UL /* Streaming byte hole error */

Definition at line 44 of file pci_psycho.c.

#define PSYCHO_PCICTRL_SBH_INT   0x0000000000000400UL /* Streaming byte hole int enab */

Definition at line 50 of file pci_psycho.c.

#define PSYCHO_PCICTRL_SERR   0x0000000400000000UL /* SERR signal asserted */

Definition at line 45 of file pci_psycho.c.

#define PSYCHO_PCICTRL_SPEED   0x0000000200000000UL /* PCI speed (1 is U2P clock) */

Definition at line 46 of file pci_psycho.c.

#define PSYCHO_PCICTRL_WEN   0x0000000000000200UL /* Power Mgmt Wake Enable */

Definition at line 51 of file pci_psycho.c.

#define PSYCHO_PCIDIAG_DDWSYNC   0x0000000000000010UL /* Disable DMA wr / PIO rd sync */

Definition at line 388 of file pci_psycho.c.

#define PSYCHO_PCIDIAG_DISYNC   0x0000000000000020UL /* Disable DMA wr / irq sync */

Definition at line 387 of file pci_psycho.c.

#define PSYCHO_PCIDIAG_DRETRY   0x0000000000000040UL /* Disable retry limit */

Definition at line 386 of file pci_psycho.c.

#define PSYCHO_PCIDIAG_IDDPAR   0x0000000000000008UL /* Invert DMA data parity */

Definition at line 389 of file pci_psycho.c.

#define PSYCHO_PCIDIAG_IPAPAR   0x0000000000000002UL /* Invert PIO address parity */

Definition at line 391 of file pci_psycho.c.

#define PSYCHO_PCIDIAG_IPDPAR   0x0000000000000004UL /* Invert PIO data parity */

Definition at line 390 of file pci_psycho.c.

#define PSYCHO_PCIDIAG_LPBACK   0x0000000000000001UL /* Enable loopback mode */

Definition at line 392 of file pci_psycho.c.

#define PSYCHO_PCIDIAG_RESV   0xffffffffffffff80UL /* Reserved */

Definition at line 385 of file pci_psycho.c.

#define PSYCHO_STC_DATA_A   0xb000UL

Definition at line 77 of file pci_psycho.c.

#define PSYCHO_STC_DATA_B   0xc000UL

Definition at line 78 of file pci_psycho.c.

#define PSYCHO_STC_ERR_A   0xb400UL

Definition at line 79 of file pci_psycho.c.

#define PSYCHO_STC_ERR_B   0xc400UL

Definition at line 80 of file pci_psycho.c.

#define PSYCHO_STC_LINE_A   0xb900UL

Definition at line 83 of file pci_psycho.c.

#define PSYCHO_STC_LINE_B   0xc900UL

Definition at line 84 of file pci_psycho.c.

#define PSYCHO_STC_TAG_A   0xb800UL

Definition at line 81 of file pci_psycho.c.

#define PSYCHO_STC_TAG_B   0xc800UL

Definition at line 82 of file pci_psycho.c.

#define PSYCHO_STRBUF_CONTROL_A   0x2800UL

Definition at line 66 of file pci_psycho.c.

#define PSYCHO_STRBUF_CONTROL_B   0x4800UL

Definition at line 67 of file pci_psycho.c.

#define PSYCHO_STRBUF_CTRL_DENAB   0x0000000000000002UL /* Diagnostic Mode Enable */

Definition at line 71 of file pci_psycho.c.

#define PSYCHO_STRBUF_CTRL_ENAB   0x0000000000000001UL /* Streaming Buffer Enable */

Definition at line 72 of file pci_psycho.c.

#define PSYCHO_STRBUF_CTRL_LENAB   0x0000000000000008UL /* LRU Lock Enable */

Definition at line 69 of file pci_psycho.c.

#define PSYCHO_STRBUF_CTRL_LPTR   0x00000000000000f0UL /* LRU Lock Pointer */

Definition at line 68 of file pci_psycho.c.

#define PSYCHO_STRBUF_CTRL_RRDIS   0x0000000000000004UL /* Rerun Disable */

Definition at line 70 of file pci_psycho.c.

#define PSYCHO_STRBUF_FLUSH_A   0x2808UL

Definition at line 73 of file pci_psycho.c.

#define PSYCHO_STRBUF_FLUSH_B   0x4808UL

Definition at line 74 of file pci_psycho.c.

#define PSYCHO_STRBUF_FSYNC_A   0x2810UL

Definition at line 75 of file pci_psycho.c.

#define PSYCHO_STRBUF_FSYNC_B   0x4810UL

Definition at line 76 of file pci_psycho.c.

#define PSYCHO_UE_AFAR   0x0038UL

Definition at line 130 of file pci_psycho.c.

#define PSYCHO_UE_AFSR   0x0030UL

Definition at line 117 of file pci_psycho.c.

#define PSYCHO_UEAFSR_BLK   0x0000000000800000UL /* Trans was block operation */

Definition at line 128 of file pci_psycho.c.

#define PSYCHO_UEAFSR_BMSK   0x0000ffff00000000UL /* Bytemask of failed transfer */

Definition at line 125 of file pci_psycho.c.

#define PSYCHO_UEAFSR_DOFF   0x00000000e0000000UL /* Doubleword Offset */

Definition at line 126 of file pci_psycho.c.

#define PSYCHO_UEAFSR_MID   0x000000001f000000UL /* UPA MID causing the fault */

Definition at line 127 of file pci_psycho.c.

#define PSYCHO_UEAFSR_PDRD   0x4000000000000000UL /* Primary DVMA read is cause */

Definition at line 119 of file pci_psycho.c.

#define PSYCHO_UEAFSR_PDWR   0x2000000000000000UL /* Primary DVMA write is cause */

Definition at line 120 of file pci_psycho.c.

#define PSYCHO_UEAFSR_PPIO   0x8000000000000000UL /* Primary PIO is cause */

Definition at line 118 of file pci_psycho.c.

#define PSYCHO_UEAFSR_RESV1   0x03ff000000000000UL /* Reserved */

Definition at line 124 of file pci_psycho.c.

#define PSYCHO_UEAFSR_RESV2   0x00000000007fffffUL /* Reserved */

Definition at line 129 of file pci_psycho.c.

#define PSYCHO_UEAFSR_SDRD   0x0800000000000000UL /* Secondary DVMA read is cause */

Definition at line 122 of file pci_psycho.c.

#define PSYCHO_UEAFSR_SDWR   0x0400000000000000UL /* Secondary DVMA write is cause*/

Definition at line 123 of file pci_psycho.c.

#define PSYCHO_UEAFSR_SPIO   0x1000000000000000UL /* Secondary PIO is cause */

Definition at line 121 of file pci_psycho.c.

Function Documentation

subsys_initcall ( psycho_init  )