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pci_impl.h
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1 /* pci_impl.h: Helper definitions for PCI controller support.
2  *
3  * Copyright (C) 1999, 2007 David S. Miller ([email protected])
4  */
5 
6 #ifndef PCI_IMPL_H
7 #define PCI_IMPL_H
8 
9 #include <linux/types.h>
10 #include <linux/spinlock.h>
11 #include <linux/pci.h>
12 #include <linux/msi.h>
13 #include <linux/of_device.h>
14 #include <asm/io.h>
15 #include <asm/prom.h>
16 #include <asm/iommu.h>
17 
18 /* The abstraction used here is that there are PCI controllers,
19  * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
20  * underneath. Each PCI bus module uses an IOMMU (shared by both
21  * PBMs of a controller, or per-PBM), and if a streaming buffer
22  * is present, each PCI bus module has it's own. (ie. the IOMMU
23  * might be shared between PBMs, the STC is never shared)
24  * Furthermore, each PCI bus module controls it's own autonomous
25  * PCI bus.
26  */
27 
28 #define PCI_STC_FLUSHFLAG_INIT(STC) \
29  (*((STC)->strbuf_flushflag) = 0UL)
30 #define PCI_STC_FLUSHFLAG_SET(STC) \
31  (*((STC)->strbuf_flushflag) != 0UL)
32 
33 #ifdef CONFIG_PCI_MSI
34 struct pci_pbm_info;
35 struct sparc64_msiq_ops {
36  int (*get_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
37  unsigned long *head);
38  int (*dequeue_msi)(struct pci_pbm_info *pbm, unsigned long msiqid,
39  unsigned long *head, unsigned long *msi);
40  int (*set_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
41  unsigned long head);
42  int (*msi_setup)(struct pci_pbm_info *pbm, unsigned long msiqid,
43  unsigned long msi, int is_msi64);
44  int (*msi_teardown)(struct pci_pbm_info *pbm, unsigned long msi);
45  int (*msiq_alloc)(struct pci_pbm_info *pbm);
46  void (*msiq_free)(struct pci_pbm_info *pbm);
47  int (*msiq_build_irq)(struct pci_pbm_info *pbm, unsigned long msiqid,
48  unsigned long devino);
49 };
50 
51 extern void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
52  const struct sparc64_msiq_ops *ops);
53 
54 struct sparc64_msiq_cookie {
55  struct pci_pbm_info *pbm;
56  unsigned long msiqid;
57 };
58 #endif
59 
60 struct pci_pbm_info {
61  struct pci_pbm_info *next;
62  struct pci_pbm_info *sibling;
63  int index;
64 
65  /* Physical address base of controller registers. */
66  unsigned long controller_regs;
67 
68  /* Physical address base of PBM registers. */
69  unsigned long pbm_regs;
70 
71  /* Physical address of DMA sync register, if any. */
72  unsigned long sync_reg;
73 
74  /* Opaque 32-bit system bus Port ID. */
75  u32 portid;
76 
77  /* Opaque 32-bit handle used for hypervisor calls. */
78  u32 devhandle;
79 
80  /* Chipset version information. */
81  int chip_type;
82 #define PBM_CHIP_TYPE_SABRE 1
83 #define PBM_CHIP_TYPE_PSYCHO 2
84 #define PBM_CHIP_TYPE_SCHIZO 3
85 #define PBM_CHIP_TYPE_SCHIZO_PLUS 4
86 #define PBM_CHIP_TYPE_TOMATILLO 5
87  int chip_version;
88  int chip_revision;
89 
90  /* Name used for top-level resources. */
91  char *name;
92 
93  /* OBP specific information. */
94  struct platform_device *op;
95  u64 ino_bitmap;
96 
97  /* PBM I/O and Memory space resources. */
98  struct resource io_space;
99  struct resource mem_space;
100  struct resource busn;
101 
102  /* Base of PCI Config space, can be per-PBM or shared. */
103  unsigned long config_space;
104 
105  /* This will be 12 on PCI-E controllers, 8 elsewhere. */
106  unsigned long config_space_reg_bits;
107 
108  unsigned long pci_afsr;
109  unsigned long pci_afar;
110  unsigned long pci_csr;
111 
112  /* State of 66MHz capabilities on this PBM. */
113  int is_66mhz_capable;
114  int all_devs_66mhz;
115 
116 #ifdef CONFIG_PCI_MSI
117  /* MSI info. */
118  u32 msiq_num;
119  u32 msiq_ent_count;
120  u32 msiq_first;
121  u32 msiq_first_devino;
122  u32 msiq_rotor;
123  struct sparc64_msiq_cookie *msiq_irq_cookies;
124  u32 msi_num;
125  u32 msi_first;
126  u32 msi_data_mask;
127  u32 msix_data_width;
128  u64 msi32_start;
129  u64 msi64_start;
130  u32 msi32_len;
131  u32 msi64_len;
132  void *msi_queues;
133  unsigned long *msi_bitmap;
134  unsigned int *msi_irq_table;
135  int (*setup_msi_irq)(unsigned int *irq_p, struct pci_dev *pdev,
136  struct msi_desc *entry);
137  void (*teardown_msi_irq)(unsigned int irq, struct pci_dev *pdev);
138  const struct sparc64_msiq_ops *msi_ops;
139 #endif /* !(CONFIG_PCI_MSI) */
140 
141  /* This PBM's streaming buffer. */
142  struct strbuf stc;
143 
144  /* IOMMU state, potentially shared by both PBM segments. */
145  struct iommu *iommu;
146 
147  /* Now things for the actual PCI bus probes. */
148  unsigned int pci_first_busno;
149  unsigned int pci_last_busno;
150  struct pci_bus *pci_bus;
151  struct pci_ops *pci_ops;
152 
153  int numa_node;
154 };
155 
156 extern struct pci_pbm_info *pci_pbm_root;
157 
158 extern int pci_num_pbms;
159 
160 /* PCI bus scanning and fixup support. */
161 extern void pci_get_pbm_props(struct pci_pbm_info *pbm);
162 extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
163  struct device *parent);
164 extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
165 
166 /* Error reporting support. */
167 extern void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *);
168 extern void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *);
169 extern void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *);
170 
171 /* Configuration space access. */
172 extern void pci_config_read8(u8 *addr, u8 *ret);
173 extern void pci_config_read16(u16 *addr, u16 *ret);
174 extern void pci_config_read32(u32 *addr, u32 *ret);
175 extern void pci_config_write8(u8 *addr, u8 val);
176 extern void pci_config_write16(u16 *addr, u16 val);
177 extern void pci_config_write32(u32 *addr, u32 val);
178 
179 extern struct pci_ops sun4u_pci_ops;
180 extern struct pci_ops sun4v_pci_ops;
181 
182 extern volatile int pci_poke_in_progress;
183 extern volatile int pci_poke_cpu;
184 extern volatile int pci_poke_faulted;
185 
186 #endif /* !(PCI_IMPL_H) */
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