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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/kernel.h>#include <linux/types.h>#include <linux/pci.h>#include <linux/init.h>#include <linux/export.h>#include <linux/slab.h>#include <linux/interrupt.h>#include <linux/of_device.h>#include <asm/apb.h>#include <asm/iommu.h>#include <asm/irq.h>#include <asm/prom.h>#include <asm/upa.h>#include "pci_impl.h"#include "iommu_common.h"#include "psycho_common.h"Go to the source code of this file.
Macros | |
| #define | DRIVER_NAME "sabre" |
| #define | PFX DRIVER_NAME ": " |
| #define | SABRE_UE_AFSR 0x0030UL |
| #define | SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ |
| #define | SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ |
| #define | SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ |
| #define | SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ |
| #define | SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */ |
| #define | SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */ |
| #define | SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ |
| #define | SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */ |
| #define | SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */ |
| #define | SABRE_UECE_AFAR 0x0038UL |
| #define | SABRE_CE_AFSR 0x0040UL |
| #define | SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ |
| #define | SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ |
| #define | SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ |
| #define | SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ |
| #define | SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */ |
| #define | SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ |
| #define | SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */ |
| #define | SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */ |
| #define | SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */ |
| #define | SABRE_IOMMU_CONTROL 0x0200UL |
| #define | SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */ |
| #define | SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */ |
| #define | SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */ |
| #define | SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */ |
| #define | SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ |
| #define | SABRE_IOMMU_TSBSZ_1K 0x0000000000000000 |
| #define | SABRE_IOMMU_TSBSZ_2K 0x0000000000010000 |
| #define | SABRE_IOMMU_TSBSZ_4K 0x0000000000020000 |
| #define | SABRE_IOMMU_TSBSZ_8K 0x0000000000030000 |
| #define | SABRE_IOMMU_TSBSZ_16K 0x0000000000040000 |
| #define | SABRE_IOMMU_TSBSZ_32K 0x0000000000050000 |
| #define | SABRE_IOMMU_TSBSZ_64K 0x0000000000060000 |
| #define | SABRE_IOMMU_TSBSZ_128K 0x0000000000070000 |
| #define | SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */ |
| #define | SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ |
| #define | SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ |
| #define | SABRE_IOMMU_TSBBASE 0x0208UL |
| #define | SABRE_IOMMU_FLUSH 0x0210UL |
| #define | SABRE_IMAP_A_SLOT0 0x0c00UL |
| #define | SABRE_IMAP_B_SLOT0 0x0c20UL |
| #define | SABRE_IMAP_SCSI 0x1000UL |
| #define | SABRE_IMAP_ETH 0x1008UL |
| #define | SABRE_IMAP_BPP 0x1010UL |
| #define | SABRE_IMAP_AU_REC 0x1018UL |
| #define | SABRE_IMAP_AU_PLAY 0x1020UL |
| #define | SABRE_IMAP_PFAIL 0x1028UL |
| #define | SABRE_IMAP_KMS 0x1030UL |
| #define | SABRE_IMAP_FLPY 0x1038UL |
| #define | SABRE_IMAP_SHW 0x1040UL |
| #define | SABRE_IMAP_KBD 0x1048UL |
| #define | SABRE_IMAP_MS 0x1050UL |
| #define | SABRE_IMAP_SER 0x1058UL |
| #define | SABRE_IMAP_UE 0x1070UL |
| #define | SABRE_IMAP_CE 0x1078UL |
| #define | SABRE_IMAP_PCIERR 0x1080UL |
| #define | SABRE_IMAP_GFX 0x1098UL |
| #define | SABRE_IMAP_EUPA 0x10a0UL |
| #define | SABRE_ICLR_A_SLOT0 0x1400UL |
| #define | SABRE_ICLR_B_SLOT0 0x1480UL |
| #define | SABRE_ICLR_SCSI 0x1800UL |
| #define | SABRE_ICLR_ETH 0x1808UL |
| #define | SABRE_ICLR_BPP 0x1810UL |
| #define | SABRE_ICLR_AU_REC 0x1818UL |
| #define | SABRE_ICLR_AU_PLAY 0x1820UL |
| #define | SABRE_ICLR_PFAIL 0x1828UL |
| #define | SABRE_ICLR_KMS 0x1830UL |
| #define | SABRE_ICLR_FLPY 0x1838UL |
| #define | SABRE_ICLR_SHW 0x1840UL |
| #define | SABRE_ICLR_KBD 0x1848UL |
| #define | SABRE_ICLR_MS 0x1850UL |
| #define | SABRE_ICLR_SER 0x1858UL |
| #define | SABRE_ICLR_UE 0x1870UL |
| #define | SABRE_ICLR_CE 0x1878UL |
| #define | SABRE_ICLR_PCIERR 0x1880UL |
| #define | SABRE_WRSYNC 0x1c20UL |
| #define | SABRE_PCICTRL 0x2000UL |
| #define | SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */ |
| #define | SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */ |
| #define | SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */ |
| #define | SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */ |
| #define | SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */ |
| #define | SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */ |
| #define | SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */ |
| #define | SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */ |
| #define | SABRE_PIOAFSR 0x2010UL |
| #define | SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */ |
| #define | SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */ |
| #define | SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */ |
| #define | SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */ |
| #define | SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */ |
| #define | SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */ |
| #define | SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */ |
| #define | SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */ |
| #define | SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */ |
| #define | SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */ |
| #define | SABRE_PIOAFAR 0x2018UL |
| #define | SABRE_PCIDIAG 0x2020UL |
| #define | SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */ |
| #define | SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */ |
| #define | SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */ |
| #define | SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */ |
| #define | SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */ |
| #define | SABRE_PCITASR 0x2028UL |
| #define | SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */ |
| #define | SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */ |
| #define | SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */ |
| #define | SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */ |
| #define | SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */ |
| #define | SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */ |
| #define | SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */ |
| #define | SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */ |
| #define | SABRE_PIOBUF_DIAG 0x5000UL |
| #define | SABRE_DMABUF_DIAGLO 0x5100UL |
| #define | SABRE_DMABUF_DIAGHI 0x51c0UL |
| #define | SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */ |
| #define | SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */ |
| #define | SABRE_IOMMU_VADIAG 0xa400UL |
| #define | SABRE_IOMMU_TCDIAG 0xa408UL |
| #define | SABRE_IOMMU_TAG 0xa580UL |
| #define | SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */ |
| #define | SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */ |
| #define | SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */ |
| #define | SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */ |
| #define | SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */ |
| #define | SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */ |
| #define | SABRE_IOMMU_DATA 0xa600UL |
| #define | SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */ |
| #define | SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */ |
| #define | SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */ |
| #define | SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */ |
| #define | SABRE_PCI_IRQSTATE 0xa800UL |
| #define | SABRE_OBIO_IRQSTATE 0xa808UL |
| #define | SABRE_FFBCFG 0xf000UL |
| #define | SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */ |
| #define | SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */ |
| #define | SABRE_MCCTRL0 0xf010UL |
| #define | SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */ |
| #define | SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */ |
| #define | SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */ |
| #define | SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */ |
| #define | SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */ |
| #define | SABRE_MCCTRL1 0xf018UL |
| #define | SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */ |
| #define | SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */ |
| #define | SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */ |
| #define | SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */ |
| #define | SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */ |
| #define | SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */ |
| #define | SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */ |
| #define | SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */ |
| #define | SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */ |
| #define | SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */ |
| #define | SABRE_RESETCTRL 0xf020UL |
| #define | SABRE_CONFIGSPACE 0x001000000UL |
| #define | SABRE_IOSPACE 0x002000000UL |
| #define | SABRE_IOSPACE_SIZE 0x000ffffffUL |
| #define | SABRE_MEMSPACE 0x100000000UL |
| #define | SABRE_MEMSPACE_SIZE 0x07fffffffUL |
Functions | |
| subsys_initcall (sabre_init) | |
| #define DRIVER_NAME "sabre" |
Definition at line 27 of file pci_sabre.c.
| #define PFX DRIVER_NAME ": " |
Definition at line 28 of file pci_sabre.c.
| #define SABRE_CE_AFSR 0x0040UL |
Definition at line 42 of file pci_sabre.c.
| #define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */ |
Definition at line 50 of file pci_sabre.c.
| #define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ |
Definition at line 48 of file pci_sabre.c.
| #define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */ |
Definition at line 47 of file pci_sabre.c.
| #define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */ |
Definition at line 49 of file pci_sabre.c.
| #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ |
Definition at line 43 of file pci_sabre.c.
| #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ |
Definition at line 44 of file pci_sabre.c.
| #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ |
Definition at line 45 of file pci_sabre.c.
| #define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ |
Definition at line 46 of file pci_sabre.c.
| #define SABRE_CONFIGSPACE 0x001000000UL |
Definition at line 187 of file pci_sabre.c.
| #define SABRE_DMABUF_DIAGHI 0x51c0UL |
Definition at line 146 of file pci_sabre.c.
| #define SABRE_DMABUF_DIAGLO 0x5100UL |
Definition at line 145 of file pci_sabre.c.
| #define SABRE_FFBCFG 0xf000UL |
Definition at line 165 of file pci_sabre.c.
| #define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */ |
Definition at line 167 of file pci_sabre.c.
| #define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */ |
Definition at line 166 of file pci_sabre.c.
| #define SABRE_ICLR_A_SLOT0 0x1400UL |
Definition at line 90 of file pci_sabre.c.
| #define SABRE_ICLR_AU_PLAY 0x1820UL |
Definition at line 96 of file pci_sabre.c.
| #define SABRE_ICLR_AU_REC 0x1818UL |
Definition at line 95 of file pci_sabre.c.
| #define SABRE_ICLR_B_SLOT0 0x1480UL |
Definition at line 91 of file pci_sabre.c.
| #define SABRE_ICLR_BPP 0x1810UL |
Definition at line 94 of file pci_sabre.c.
| #define SABRE_ICLR_CE 0x1878UL |
Definition at line 105 of file pci_sabre.c.
| #define SABRE_ICLR_ETH 0x1808UL |
Definition at line 93 of file pci_sabre.c.
| #define SABRE_ICLR_FLPY 0x1838UL |
Definition at line 99 of file pci_sabre.c.
| #define SABRE_ICLR_KBD 0x1848UL |
Definition at line 101 of file pci_sabre.c.
| #define SABRE_ICLR_KMS 0x1830UL |
Definition at line 98 of file pci_sabre.c.
| #define SABRE_ICLR_MS 0x1850UL |
Definition at line 102 of file pci_sabre.c.
| #define SABRE_ICLR_PCIERR 0x1880UL |
Definition at line 106 of file pci_sabre.c.
| #define SABRE_ICLR_PFAIL 0x1828UL |
Definition at line 97 of file pci_sabre.c.
| #define SABRE_ICLR_SCSI 0x1800UL |
Definition at line 92 of file pci_sabre.c.
| #define SABRE_ICLR_SER 0x1858UL |
Definition at line 103 of file pci_sabre.c.
| #define SABRE_ICLR_SHW 0x1840UL |
Definition at line 100 of file pci_sabre.c.
| #define SABRE_ICLR_UE 0x1870UL |
Definition at line 104 of file pci_sabre.c.
| #define SABRE_IMAP_A_SLOT0 0x0c00UL |
Definition at line 71 of file pci_sabre.c.
| #define SABRE_IMAP_AU_PLAY 0x1020UL |
Definition at line 77 of file pci_sabre.c.
| #define SABRE_IMAP_AU_REC 0x1018UL |
Definition at line 76 of file pci_sabre.c.
| #define SABRE_IMAP_B_SLOT0 0x0c20UL |
Definition at line 72 of file pci_sabre.c.
| #define SABRE_IMAP_BPP 0x1010UL |
Definition at line 75 of file pci_sabre.c.
| #define SABRE_IMAP_CE 0x1078UL |
Definition at line 86 of file pci_sabre.c.
| #define SABRE_IMAP_ETH 0x1008UL |
Definition at line 74 of file pci_sabre.c.
| #define SABRE_IMAP_EUPA 0x10a0UL |
Definition at line 89 of file pci_sabre.c.
| #define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */ |
Definition at line 148 of file pci_sabre.c.
| #define SABRE_IMAP_FLPY 0x1038UL |
Definition at line 80 of file pci_sabre.c.
| #define SABRE_IMAP_GFX 0x1098UL |
Definition at line 88 of file pci_sabre.c.
| #define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */ |
Definition at line 147 of file pci_sabre.c.
| #define SABRE_IMAP_KBD 0x1048UL |
Definition at line 82 of file pci_sabre.c.
| #define SABRE_IMAP_KMS 0x1030UL |
Definition at line 79 of file pci_sabre.c.
| #define SABRE_IMAP_MS 0x1050UL |
Definition at line 83 of file pci_sabre.c.
| #define SABRE_IMAP_PCIERR 0x1080UL |
Definition at line 87 of file pci_sabre.c.
| #define SABRE_IMAP_PFAIL 0x1028UL |
Definition at line 78 of file pci_sabre.c.
| #define SABRE_IMAP_SCSI 0x1000UL |
Definition at line 73 of file pci_sabre.c.
| #define SABRE_IMAP_SER 0x1058UL |
Definition at line 84 of file pci_sabre.c.
| #define SABRE_IMAP_SHW 0x1040UL |
Definition at line 81 of file pci_sabre.c.
| #define SABRE_IMAP_UE 0x1070UL |
Definition at line 85 of file pci_sabre.c.
| #define SABRE_IOMMU_CONTROL 0x0200UL |
Definition at line 52 of file pci_sabre.c.
| #define SABRE_IOMMU_DATA 0xa600UL |
Definition at line 158 of file pci_sabre.c.
| #define SABRE_IOMMU_FLUSH 0x0210UL |
Definition at line 70 of file pci_sabre.c.
| #define SABRE_IOMMU_TAG 0xa580UL |
Definition at line 151 of file pci_sabre.c.
| #define SABRE_IOMMU_TCDIAG 0xa408UL |
Definition at line 150 of file pci_sabre.c.
| #define SABRE_IOMMU_TSBBASE 0x0208UL |
Definition at line 69 of file pci_sabre.c.
| #define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000 |
Definition at line 65 of file pci_sabre.c.
| #define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000 |
Definition at line 62 of file pci_sabre.c.
| #define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000 |
Definition at line 58 of file pci_sabre.c.
| #define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000 |
Definition at line 59 of file pci_sabre.c.
| #define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000 |
Definition at line 63 of file pci_sabre.c.
| #define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000 |
Definition at line 60 of file pci_sabre.c.
| #define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000 |
Definition at line 64 of file pci_sabre.c.
| #define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000 |
Definition at line 61 of file pci_sabre.c.
| #define SABRE_IOMMU_VADIAG 0xa400UL |
Definition at line 149 of file pci_sabre.c.
| #define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ |
Definition at line 67 of file pci_sabre.c.
| #define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ |
Definition at line 68 of file pci_sabre.c.
| #define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */ |
Definition at line 54 of file pci_sabre.c.
| #define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */ |
Definition at line 53 of file pci_sabre.c.
| #define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */ |
Definition at line 55 of file pci_sabre.c.
| #define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */ |
Definition at line 56 of file pci_sabre.c.
| #define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */ |
Definition at line 66 of file pci_sabre.c.
| #define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ |
Definition at line 57 of file pci_sabre.c.
| #define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */ |
Definition at line 161 of file pci_sabre.c.
| #define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */ |
Definition at line 162 of file pci_sabre.c.
| #define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */ |
Definition at line 160 of file pci_sabre.c.
| #define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */ |
Definition at line 159 of file pci_sabre.c.
| #define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */ |
Definition at line 153 of file pci_sabre.c.
| #define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */ |
Definition at line 152 of file pci_sabre.c.
| #define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */ |
Definition at line 156 of file pci_sabre.c.
| #define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */ |
Definition at line 155 of file pci_sabre.c.
| #define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */ |
Definition at line 157 of file pci_sabre.c.
| #define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */ |
Definition at line 154 of file pci_sabre.c.
| #define SABRE_IOSPACE 0x002000000UL |
Definition at line 188 of file pci_sabre.c.
| #define SABRE_IOSPACE_SIZE 0x000ffffffUL |
Definition at line 189 of file pci_sabre.c.
| #define SABRE_MCCTRL0 0xf010UL |
Definition at line 168 of file pci_sabre.c.
| #define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */ |
Definition at line 171 of file pci_sabre.c.
| #define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */ |
Definition at line 172 of file pci_sabre.c.
| #define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */ |
Definition at line 170 of file pci_sabre.c.
| #define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */ |
Definition at line 169 of file pci_sabre.c.
| #define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */ |
Definition at line 173 of file pci_sabre.c.
| #define SABRE_MCCTRL1 0xf018UL |
Definition at line 174 of file pci_sabre.c.
| #define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */ |
Definition at line 175 of file pci_sabre.c.
| #define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */ |
Definition at line 176 of file pci_sabre.c.
| #define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */ |
Definition at line 178 of file pci_sabre.c.
| #define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */ |
Definition at line 183 of file pci_sabre.c.
| #define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */ |
Definition at line 180 of file pci_sabre.c.
| #define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */ |
Definition at line 177 of file pci_sabre.c.
| #define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */ |
Definition at line 182 of file pci_sabre.c.
| #define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */ |
Definition at line 179 of file pci_sabre.c.
| #define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */ |
Definition at line 181 of file pci_sabre.c.
| #define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */ |
Definition at line 184 of file pci_sabre.c.
| #define SABRE_MEMSPACE 0x100000000UL |
Definition at line 190 of file pci_sabre.c.
| #define SABRE_MEMSPACE_SIZE 0x07fffffffUL |
Definition at line 191 of file pci_sabre.c.
| #define SABRE_OBIO_IRQSTATE 0xa808UL |
Definition at line 164 of file pci_sabre.c.
| #define SABRE_PCI_IRQSTATE 0xa800UL |
Definition at line 163 of file pci_sabre.c.
| #define SABRE_PCICTRL 0x2000UL |
Definition at line 108 of file pci_sabre.c.
| #define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */ |
Definition at line 116 of file pci_sabre.c.
| #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */ |
Definition at line 111 of file pci_sabre.c.
| #define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */ |
Definition at line 113 of file pci_sabre.c.
| #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */ |
Definition at line 112 of file pci_sabre.c.
| #define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */ |
Definition at line 114 of file pci_sabre.c.
| #define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */ |
Definition at line 109 of file pci_sabre.c.
| #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */ |
Definition at line 115 of file pci_sabre.c.
| #define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */ |
Definition at line 110 of file pci_sabre.c.
| #define SABRE_PCIDIAG 0x2020UL |
Definition at line 129 of file pci_sabre.c.
| #define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */ |
Definition at line 130 of file pci_sabre.c.
| #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */ |
Definition at line 134 of file pci_sabre.c.
| #define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */ |
Definition at line 133 of file pci_sabre.c.
| #define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */ |
Definition at line 131 of file pci_sabre.c.
| #define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */ |
Definition at line 132 of file pci_sabre.c.
| #define SABRE_PCITASR 0x2028UL |
Definition at line 135 of file pci_sabre.c.
| #define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */ |
Definition at line 143 of file pci_sabre.c.
| #define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */ |
Definition at line 142 of file pci_sabre.c.
| #define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */ |
Definition at line 141 of file pci_sabre.c.
| #define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */ |
Definition at line 140 of file pci_sabre.c.
| #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */ |
Definition at line 139 of file pci_sabre.c.
| #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */ |
Definition at line 138 of file pci_sabre.c.
| #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */ |
Definition at line 137 of file pci_sabre.c.
| #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */ |
Definition at line 136 of file pci_sabre.c.
| #define SABRE_PIOAFAR 0x2018UL |
Definition at line 128 of file pci_sabre.c.
| #define SABRE_PIOAFSR 0x2010UL |
Definition at line 117 of file pci_sabre.c.
| #define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */ |
Definition at line 127 of file pci_sabre.c.
| #define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */ |
Definition at line 126 of file pci_sabre.c.
| #define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */ |
Definition at line 118 of file pci_sabre.c.
| #define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */ |
Definition at line 121 of file pci_sabre.c.
| #define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */ |
Definition at line 120 of file pci_sabre.c.
| #define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */ |
Definition at line 119 of file pci_sabre.c.
| #define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */ |
Definition at line 122 of file pci_sabre.c.
| #define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */ |
Definition at line 125 of file pci_sabre.c.
| #define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */ |
Definition at line 124 of file pci_sabre.c.
| #define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */ |
Definition at line 123 of file pci_sabre.c.
| #define SABRE_PIOBUF_DIAG 0x5000UL |
Definition at line 144 of file pci_sabre.c.
| #define SABRE_RESETCTRL 0xf020UL |
Definition at line 185 of file pci_sabre.c.
| #define SABRE_UE_AFSR 0x0030UL |
Definition at line 31 of file pci_sabre.c.
| #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */ |
Definition at line 40 of file pci_sabre.c.
| #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ |
Definition at line 38 of file pci_sabre.c.
| #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */ |
Definition at line 39 of file pci_sabre.c.
| #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ |
Definition at line 32 of file pci_sabre.c.
| #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */ |
Definition at line 37 of file pci_sabre.c.
| #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ |
Definition at line 33 of file pci_sabre.c.
| #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ |
Definition at line 34 of file pci_sabre.c.
| #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */ |
Definition at line 36 of file pci_sabre.c.
| #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ |
Definition at line 35 of file pci_sabre.c.
| #define SABRE_UECE_AFAR 0x0038UL |
Definition at line 41 of file pci_sabre.c.
| #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */ |
Definition at line 51 of file pci_sabre.c.
| #define SABRE_WRSYNC 0x1c20UL |
Definition at line 107 of file pci_sabre.c.
| subsys_initcall | ( | sabre_init | ) |
1.8.2