| enum | {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
PORT_ALL =(DATA),
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
PORT_ALL =(DATA),
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PORT_ALL =(DATA),
PINMUX_INPUT_PULLUP_END,
PINMUX_INPUT_PULLDOWN_BEGIN,
PORT_ALL =(DATA),
PINMUX_INPUT_PULLDOWN_END,
PINMUX_OUTPUT_BEGIN,
PORT_ALL =(DATA),
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
PORT_ALL =(DATA),
PORT_ALL =(DATA),
PORT_ALL =(DATA),
PORT_ALL =(DATA),
PORT_ALL =(DATA),
PORT_ALL =(DATA),
PORT_ALL =(DATA),
PORT_ALL =(DATA),
PORT_ALL =(DATA),
PORT_ALL =(DATA),
MSEL2CR_MSEL19_0,
MSEL2CR_MSEL19_1,
MSEL2CR_MSEL18_0,
MSEL2CR_MSEL18_1,
MSEL2CR_MSEL17_0,
MSEL2CR_MSEL17_1,
MSEL2CR_MSEL16_0,
MSEL2CR_MSEL16_1,
MSEL2CR_MSEL14_0,
MSEL2CR_MSEL14_1,
MSEL2CR_MSEL13_0,
MSEL2CR_MSEL13_1,
MSEL2CR_MSEL12_0,
MSEL2CR_MSEL12_1,
MSEL2CR_MSEL11_0,
MSEL2CR_MSEL11_1,
MSEL2CR_MSEL10_0,
MSEL2CR_MSEL10_1,
MSEL2CR_MSEL9_0,
MSEL2CR_MSEL9_1,
MSEL2CR_MSEL8_0,
MSEL2CR_MSEL8_1,
MSEL2CR_MSEL7_0,
MSEL2CR_MSEL7_1,
MSEL2CR_MSEL6_0,
MSEL2CR_MSEL6_1,
MSEL2CR_MSEL4_0,
MSEL2CR_MSEL4_1,
MSEL2CR_MSEL5_0,
MSEL2CR_MSEL5_1,
MSEL2CR_MSEL3_0,
MSEL2CR_MSEL3_1,
MSEL2CR_MSEL2_0,
MSEL2CR_MSEL2_1,
MSEL2CR_MSEL1_0,
MSEL2CR_MSEL1_1,
MSEL2CR_MSEL0_0,
MSEL2CR_MSEL0_1,
MSEL3CR_MSEL28_0,
MSEL3CR_MSEL28_1,
MSEL3CR_MSEL15_0,
MSEL3CR_MSEL15_1,
MSEL3CR_MSEL11_0,
MSEL3CR_MSEL11_1,
MSEL3CR_MSEL9_0,
MSEL3CR_MSEL9_1,
MSEL3CR_MSEL6_0,
MSEL3CR_MSEL6_1,
MSEL3CR_MSEL2_0,
MSEL3CR_MSEL2_1,
MSEL4CR_MSEL29_0,
MSEL4CR_MSEL29_1,
MSEL4CR_MSEL27_0,
MSEL4CR_MSEL27_1,
MSEL4CR_MSEL26_0,
MSEL4CR_MSEL26_1,
MSEL4CR_MSEL22_0,
MSEL4CR_MSEL22_1,
MSEL4CR_MSEL21_0,
MSEL4CR_MSEL21_1,
MSEL4CR_MSEL20_0,
MSEL4CR_MSEL20_1,
MSEL4CR_MSEL19_0,
MSEL4CR_MSEL19_1,
MSEL4CR_MSEL15_0,
MSEL4CR_MSEL15_1,
MSEL4CR_MSEL13_0,
MSEL4CR_MSEL13_1,
MSEL4CR_MSEL12_0,
MSEL4CR_MSEL12_1,
MSEL4CR_MSEL11_0,
MSEL4CR_MSEL11_1,
MSEL4CR_MSEL10_0,
MSEL4CR_MSEL10_1,
MSEL4CR_MSEL9_0,
MSEL4CR_MSEL9_1,
MSEL4CR_MSEL8_0,
MSEL4CR_MSEL8_1,
MSEL4CR_MSEL7_0,
MSEL4CR_MSEL7_1,
MSEL4CR_MSEL4_0,
MSEL4CR_MSEL4_1,
MSEL4CR_MSEL1_0,
MSEL4CR_MSEL1_1,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
VBUS_0_MARK,
GPI0_MARK,
GPI1_MARK,
GPI2_MARK,
GPI3_MARK,
GPI4_MARK,
GPI5_MARK,
GPI6_MARK,
GPI7_MARK,
SCIFA7_RXD_MARK,
SCIFA7_CTS__MARK,
GPO7_MARK,
MFG0_OUT2_MARK,
GPO6_MARK,
MFG1_OUT2_MARK,
GPO5_MARK,
SCIFA0_SCK_MARK,
FSICOSLDT3_MARK,
PORT16_VIO_CKOR_MARK,
SCIFA0_TXD_MARK,
SCIFA7_TXD_MARK,
SCIFA7_RTS__MARK,
PORT19_VIO_CKO2_MARK,
GPO0_MARK,
GPO1_MARK,
GPO2_MARK,
STATUS0_MARK,
GPO3_MARK,
STATUS1_MARK,
GPO4_MARK,
STATUS2_MARK,
VINT_MARK,
TCKON_MARK,
XDVFS1_MARK,
PORT27_I2C_SCL2_MARK,
PORT27_I2C_SCL3_MARK,
MFG0_OUT1_MARK,
PORT27_IROUT_MARK,
XDVFS2_MARK,
PORT28_I2C_SDA2_MARK,
PORT28_I2C_SDA3_MARK,
PORT28_TPU1TO1_MARK,
SIM_RST_MARK,
PORT29_TPU1TO1_MARK,
SIM_CLK_MARK,
PORT30_VIO_CKOR_MARK,
SIM_D_MARK,
PORT31_IROUT_MARK,
SCIFA4_TXD_MARK,
SCIFA4_RXD_MARK,
XWUP_MARK,
SCIFA4_RTS__MARK,
SCIFA4_CTS__MARK,
FSIBOBT_MARK,
FSIBIBT_MARK,
FSIBOLR_MARK,
FSIBILR_MARK,
FSIBOSLD_MARK,
FSIBISLD_MARK,
VACK_MARK,
XTAL1L_MARK,
SCIFA0_RTS__MARK,
FSICOSLDT2_MARK,
SCIFA0_RXD_MARK,
SCIFA0_CTS__MARK,
FSICOSLDT1_MARK,
FSICOBT_MARK,
FSICIBT_MARK,
FSIDOBT_MARK,
FSIDIBT_MARK,
FSICOLR_MARK,
FSICILR_MARK,
FSIDOLR_MARK,
FSIDILR_MARK,
FSICOSLD_MARK,
PORT47_FSICSPDIF_MARK,
FSICISLD_MARK,
FSIDISLD_MARK,
FSIACK_MARK,
PORT49_IRDA_OUT_MARK,
PORT49_IROUT_MARK,
FSIAOMC_MARK,
FSIAOLR_MARK,
BBIF2_TSYNC2_MARK,
TPU2TO2_MARK,
FSIAILR_MARK,
FSIAOBT_MARK,
BBIF2_TSCK2_MARK,
TPU2TO3_MARK,
FSIAIBT_MARK,
FSIAOSLD_MARK,
BBIF2_TXD2_MARK,
FSIASPDIF_MARK,
PORT53_IRDA_IN_MARK,
TPU3TO3_MARK,
FSIBSPDIF_MARK,
PORT53_FSICSPDIF_MARK,
FSIBCK_MARK,
PORT54_IRDA_FIRSEL_MARK,
TPU3TO2_MARK,
FSIBOMC_MARK,
FSICCK_MARK,
FSICOMC_MARK,
FSIAISLD_MARK,
TPU0TO0_MARK,
A0_MARK,
BS__MARK,
A12_MARK,
PORT58_KEYOUT7_MARK,
TPU4TO2_MARK,
A13_MARK,
PORT59_KEYOUT6_MARK,
TPU0TO1_MARK,
A14_MARK,
KEYOUT5_MARK,
A15_MARK,
KEYOUT4_MARK,
A16_MARK,
KEYOUT3_MARK,
MSIOF0_SS1_MARK,
A17_MARK,
KEYOUT2_MARK,
MSIOF0_TSYNC_MARK,
A18_MARK,
KEYOUT1_MARK,
MSIOF0_TSCK_MARK,
A19_MARK,
KEYOUT0_MARK,
MSIOF0_TXD_MARK,
A20_MARK,
KEYIN0_MARK,
MSIOF0_RSCK_MARK,
A21_MARK,
KEYIN1_MARK,
MSIOF0_RSYNC_MARK,
A22_MARK,
KEYIN2_MARK,
MSIOF0_MCK0_MARK,
A23_MARK,
KEYIN3_MARK,
MSIOF0_MCK1_MARK,
A24_MARK,
KEYIN4_MARK,
MSIOF0_RXD_MARK,
A25_MARK,
KEYIN5_MARK,
MSIOF0_SS2_MARK,
A26_MARK,
KEYIN6_MARK,
KEYIN7_MARK,
D0_NAF0_MARK,
D1_NAF1_MARK,
D2_NAF2_MARK,
D3_NAF3_MARK,
D4_NAF4_MARK,
D5_NAF5_MARK,
D6_NAF6_MARK,
D7_NAF7_MARK,
D8_NAF8_MARK,
D9_NAF9_MARK,
D10_NAF10_MARK,
D11_NAF11_MARK,
D12_NAF12_MARK,
D13_NAF13_MARK,
D14_NAF14_MARK,
D15_NAF15_MARK,
CS4__MARK,
CS5A__MARK,
PORT91_RDWR_MARK,
CS5B__MARK,
FCE1__MARK,
CS6B__MARK,
DACK0_MARK,
FCE0__MARK,
CS6A__MARK,
WAIT__MARK,
DREQ0_MARK,
RD__FSC_MARK,
WE0__FWE_MARK,
RDWR_FWE_MARK,
WE1__MARK,
FRB_MARK,
CKO_MARK,
NBRSTOUT__MARK,
NBRST__MARK,
BBIF2_TXD_MARK,
BBIF2_RXD_MARK,
BBIF2_SYNC_MARK,
BBIF2_SCK_MARK,
SCIFA3_CTS__MARK,
MFG3_IN2_MARK,
SCIFA3_RXD_MARK,
MFG3_IN1_MARK,
BBIF1_SS2_MARK,
SCIFA3_RTS__MARK,
MFG3_OUT1_MARK,
SCIFA3_TXD_MARK,
HSI_RX_DATA_MARK,
BBIF1_RXD_MARK,
HSI_TX_WAKE_MARK,
BBIF1_TSCK_MARK,
HSI_TX_DATA_MARK,
BBIF1_TSYNC_MARK,
HSI_TX_READY_MARK,
BBIF1_TXD_MARK,
HSI_RX_READY_MARK,
BBIF1_RSCK_MARK,
PORT115_I2C_SCL2_MARK,
PORT115_I2C_SCL3_MARK,
HSI_RX_WAKE_MARK,
BBIF1_RSYNC_MARK,
PORT116_I2C_SDA2_MARK,
PORT116_I2C_SDA3_MARK,
HSI_RX_FLAG_MARK,
BBIF1_SS1_MARK,
BBIF1_FLOW_MARK,
HSI_TX_FLAG_MARK,
VIO_VD_MARK,
PORT128_LCD2VSYN_MARK,
VIO2_VD_MARK,
LCD2D0_MARK,
VIO_HD_MARK,
PORT129_LCD2HSYN_MARK,
PORT129_LCD2CS__MARK,
VIO2_HD_MARK,
LCD2D1_MARK,
VIO_D0_MARK,
PORT130_MSIOF2_RXD_MARK,
LCD2D10_MARK,
VIO_D1_MARK,
PORT131_KEYOUT6_MARK,
PORT131_MSIOF2_SS1_MARK,
PORT131_KEYOUT11_MARK,
LCD2D11_MARK,
VIO_D2_MARK,
PORT132_KEYOUT7_MARK,
PORT132_MSIOF2_SS2_MARK,
PORT132_KEYOUT10_MARK,
LCD2D12_MARK,
VIO_D3_MARK,
MSIOF2_TSYNC_MARK,
LCD2D13_MARK,
VIO_D4_MARK,
MSIOF2_TXD_MARK,
LCD2D14_MARK,
VIO_D5_MARK,
MSIOF2_TSCK_MARK,
LCD2D15_MARK,
VIO_D6_MARK,
PORT136_KEYOUT8_MARK,
LCD2D16_MARK,
VIO_D7_MARK,
PORT137_KEYOUT9_MARK,
LCD2D17_MARK,
VIO_D8_MARK,
PORT138_KEYOUT8_MARK,
VIO2_D0_MARK,
LCD2D6_MARK,
VIO_D9_MARK,
PORT139_KEYOUT9_MARK,
VIO2_D1_MARK,
LCD2D7_MARK,
VIO_D10_MARK,
TPU0TO2_MARK,
VIO2_D2_MARK,
LCD2D8_MARK,
VIO_D11_MARK,
TPU0TO3_MARK,
VIO2_D3_MARK,
LCD2D9_MARK,
VIO_D12_MARK,
PORT142_KEYOUT10_MARK,
VIO2_D4_MARK,
LCD2D2_MARK,
VIO_D13_MARK,
PORT143_KEYOUT11_MARK,
PORT143_KEYOUT6_MARK,
VIO2_D5_MARK,
LCD2D3_MARK,
VIO_D14_MARK,
PORT144_KEYOUT7_MARK,
VIO2_D6_MARK,
LCD2D4_MARK,
VIO_D15_MARK,
TPU1TO3_MARK,
PORT145_LCD2DISP_MARK,
PORT145_LCD2RS_MARK,
VIO2_D7_MARK,
LCD2D5_MARK,
VIO_CLK_MARK,
LCD2DCK_MARK,
PORT146_LCD2WR__MARK,
VIO2_CLK_MARK,
LCD2D18_MARK,
VIO_FIELD_MARK,
LCD2RD__MARK,
VIO2_FIELD_MARK,
LCD2D19_MARK,
VIO_CKO_MARK,
A27_MARK,
PORT149_RDWR_MARK,
MFG0_IN1_MARK,
PORT149_KEYOUT9_MARK,
MFG0_IN2_MARK,
TS_SPSYNC3_MARK,
MSIOF2_RSCK_MARK,
TS_SDAT3_MARK,
MSIOF2_RSYNC_MARK,
TPU1TO2_MARK,
TS_SDEN3_MARK,
PORT153_MSIOF2_SS1_MARK,
SCIFA2_TXD1_MARK,
MSIOF2_MCK0_MARK,
SCIFA2_RXD1_MARK,
MSIOF2_MCK1_MARK,
SCIFA2_RTS1__MARK,
PORT156_MSIOF2_SS2_MARK,
SCIFA2_CTS1__MARK,
PORT157_MSIOF2_RXD_MARK,
DINT__MARK,
SCIFA2_SCK1_MARK,
TS_SCK3_MARK,
PORT159_SCIFB_SCK_MARK,
PORT159_SCIFA5_SCK_MARK,
NMI_MARK,
PORT160_SCIFB_TXD_MARK,
PORT160_SCIFA5_TXD_MARK,
PORT161_SCIFB_CTS__MARK,
PORT161_SCIFA5_CTS__MARK,
PORT162_SCIFB_RXD_MARK,
PORT162_SCIFA5_RXD_MARK,
PORT163_SCIFB_RTS__MARK,
PORT163_SCIFA5_RTS__MARK,
TPU3TO0_MARK,
LCDD0_MARK,
LCDD1_MARK,
PORT193_SCIFA5_CTS__MARK,
BBIF2_TSYNC1_MARK,
LCDD2_MARK,
PORT194_SCIFA5_RTS__MARK,
BBIF2_TSCK1_MARK,
LCDD3_MARK,
PORT195_SCIFA5_RXD_MARK,
BBIF2_TXD1_MARK,
LCDD4_MARK,
PORT196_SCIFA5_TXD_MARK,
LCDD5_MARK,
PORT197_SCIFA5_SCK_MARK,
MFG2_OUT2_MARK,
TPU2TO1_MARK,
LCDD6_MARK,
LCDD7_MARK,
TPU4TO1_MARK,
MFG4_OUT2_MARK,
LCDD8_MARK,
D16_MARK,
LCDD9_MARK,
D17_MARK,
LCDD10_MARK,
D18_MARK,
LCDD11_MARK,
D19_MARK,
LCDD12_MARK,
D20_MARK,
LCDD13_MARK,
D21_MARK,
LCDD14_MARK,
D22_MARK,
LCDD15_MARK,
PORT207_MSIOF0L_SS1_MARK,
D23_MARK,
LCDD16_MARK,
PORT208_MSIOF0L_SS2_MARK,
D24_MARK,
LCDD17_MARK,
D25_MARK,
LCDD18_MARK,
DREQ2_MARK,
PORT210_MSIOF0L_SS1_MARK,
D26_MARK,
LCDD19_MARK,
PORT211_MSIOF0L_SS2_MARK,
D27_MARK,
LCDD20_MARK,
TS_SPSYNC1_MARK,
MSIOF0L_MCK0_MARK,
D28_MARK,
LCDD21_MARK,
TS_SDAT1_MARK,
MSIOF0L_MCK1_MARK,
D29_MARK,
LCDD22_MARK,
TS_SDEN1_MARK,
MSIOF0L_RSCK_MARK,
D30_MARK,
LCDD23_MARK,
TS_SCK1_MARK,
MSIOF0L_RSYNC_MARK,
D31_MARK,
LCDDCK_MARK,
LCDWR__MARK,
LCDRD__MARK,
DACK2_MARK,
PORT217_LCD2RS_MARK,
MSIOF0L_TSYNC_MARK,
VIO2_FIELD3_MARK,
PORT217_LCD2DISP_MARK,
LCDHSYN_MARK,
LCDCS__MARK,
LCDCS2__MARK,
DACK3_MARK,
PORT218_VIO_CKOR_MARK,
LCDDISP_MARK,
LCDRS_MARK,
PORT219_LCD2WR__MARK,
DREQ3_MARK,
MSIOF0L_TSCK_MARK,
VIO2_CLK3_MARK,
LCD2DCK_2_MARK,
LCDVSYN_MARK,
LCDVSYN2_MARK,
LCDLCLK_MARK,
DREQ1_MARK,
PORT221_LCD2CS__MARK,
PWEN_MARK,
MSIOF0L_RXD_MARK,
VIO2_HD3_MARK,
PORT221_LCD2HSYN_MARK,
LCDDON_MARK,
LCDDON2_MARK,
DACK1_MARK,
OVCN_MARK,
MSIOF0L_TXD_MARK,
VIO2_VD3_MARK,
PORT222_LCD2VSYN_MARK,
SCIFA1_TXD_MARK,
OVCN2_MARK,
EXTLP_MARK,
SCIFA1_SCK_MARK,
PORT226_VIO_CKO2_MARK,
SCIFA1_RTS__MARK,
IDIN_MARK,
SCIFA1_RXD_MARK,
SCIFA1_CTS__MARK,
MFG1_IN1_MARK,
MSIOF1_TXD_MARK,
SCIFA2_TXD2_MARK,
MSIOF1_TSYNC_MARK,
SCIFA2_CTS2__MARK,
MSIOF1_TSCK_MARK,
SCIFA2_SCK2_MARK,
MSIOF1_RXD_MARK,
SCIFA2_RXD2_MARK,
MSIOF1_RSCK_MARK,
SCIFA2_RTS2__MARK,
VIO2_CLK2_MARK,
LCD2D20_MARK,
MSIOF1_RSYNC_MARK,
MFG1_IN2_MARK,
VIO2_VD2_MARK,
LCD2D21_MARK,
MSIOF1_MCK0_MARK,
PORT236_I2C_SDA2_MARK,
MSIOF1_MCK1_MARK,
PORT237_I2C_SCL2_MARK,
MSIOF1_SS1_MARK,
VIO2_FIELD2_MARK,
LCD2D22_MARK,
MSIOF1_SS2_MARK,
VIO2_HD2_MARK,
LCD2D23_MARK,
SCIFA6_TXD_MARK,
PORT241_IRDA_OUT_MARK,
PORT241_IROUT_MARK,
MFG4_OUT1_MARK,
TPU4TO0_MARK,
PORT242_IRDA_IN_MARK,
MFG4_IN2_MARK,
PORT243_IRDA_FIRSEL_MARK,
PORT243_VIO_CKO2_MARK,
PORT244_SCIFA5_CTS__MARK,
MFG2_IN1_MARK,
PORT244_SCIFB_CTS__MARK,
MSIOF2R_RXD_MARK,
PORT245_SCIFA5_RTS__MARK,
MFG2_IN2_MARK,
PORT245_SCIFB_RTS__MARK,
MSIOF2R_TXD_MARK,
PORT246_SCIFA5_RXD_MARK,
MFG1_OUT1_MARK,
PORT246_SCIFB_RXD_MARK,
TPU1TO0_MARK,
PORT247_SCIFA5_TXD_MARK,
MFG3_OUT2_MARK,
PORT247_SCIFB_TXD_MARK,
TPU3TO1_MARK,
PORT248_SCIFA5_SCK_MARK,
MFG2_OUT1_MARK,
PORT248_SCIFB_SCK_MARK,
TPU2TO0_MARK,
PORT248_I2C_SCL3_MARK,
MSIOF2R_TSCK_MARK,
PORT249_IROUT_MARK,
MFG4_IN1_MARK,
PORT249_I2C_SDA3_MARK,
MSIOF2R_TSYNC_MARK,
SDHICLK0_MARK,
SDHICD0_MARK,
SDHID0_0_MARK,
SDHID0_1_MARK,
SDHID0_2_MARK,
SDHID0_3_MARK,
SDHICMD0_MARK,
SDHIWP0_MARK,
SDHICLK1_MARK,
SDHID1_0_MARK,
TS_SPSYNC2_MARK,
SDHID1_1_MARK,
TS_SDAT2_MARK,
SDHID1_2_MARK,
TS_SDEN2_MARK,
SDHID1_3_MARK,
TS_SCK2_MARK,
SDHICMD1_MARK,
SDHICLK2_MARK,
SDHID2_0_MARK,
TS_SPSYNC4_MARK,
SDHID2_1_MARK,
TS_SDAT4_MARK,
SDHID2_2_MARK,
TS_SDEN4_MARK,
SDHID2_3_MARK,
TS_SCK4_MARK,
SDHICMD2_MARK,
MMCCLK0_MARK,
MMCD0_0_MARK,
MMCD0_1_MARK,
MMCD0_2_MARK,
MMCD0_3_MARK,
MMCD0_4_MARK,
TS_SPSYNC5_MARK,
MMCD0_5_MARK,
TS_SDAT5_MARK,
MMCD0_6_MARK,
TS_SDEN5_MARK,
MMCD0_7_MARK,
TS_SCK5_MARK,
MMCCMD0_MARK,
RESETOUTS__MARK,
EXTAL2OUT_MARK,
MCP_WAIT__MCP_FRB_MARK,
MCP_CKO_MARK,
MMCCLK1_MARK,
MCP_D15_MCP_NAF15_MARK,
MCP_D14_MCP_NAF14_MARK,
MCP_D13_MCP_NAF13_MARK,
MCP_D12_MCP_NAF12_MARK,
MCP_D11_MCP_NAF11_MARK,
MCP_D10_MCP_NAF10_MARK,
MCP_D9_MCP_NAF9_MARK,
MCP_D8_MCP_NAF8_MARK,
MMCCMD1_MARK,
MCP_D7_MCP_NAF7_MARK,
MMCD1_7_MARK,
MCP_D6_MCP_NAF6_MARK,
MMCD1_6_MARK,
MCP_D5_MCP_NAF5_MARK,
MMCD1_5_MARK,
MCP_D4_MCP_NAF4_MARK,
MMCD1_4_MARK,
MCP_D3_MCP_NAF3_MARK,
MMCD1_3_MARK,
MCP_D2_MCP_NAF2_MARK,
MMCD1_2_MARK,
MCP_D1_MCP_NAF1_MARK,
MMCD1_1_MARK,
MCP_D0_MCP_NAF0_MARK,
MMCD1_0_MARK,
MCP_NBRSTOUT__MARK,
MCP_WE0__MCP_FWE_MARK,
MCP_RDWR_MCP_FWE_MARK,
TSIF2_TS_XX1_MARK,
TSIF2_TS_XX2_MARK,
TSIF2_TS_XX3_MARK,
TSIF2_TS_XX4_MARK,
TSIF2_TS_XX5_MARK,
TSIF1_TS_XX1_MARK,
TSIF1_TS_XX2_MARK,
TSIF1_TS_XX3_MARK,
TSIF1_TS_XX4_MARK,
TSIF1_TS_XX5_MARK,
TSIF0_TS_XX1_MARK,
TSIF0_TS_XX2_MARK,
TSIF0_TS_XX3_MARK,
TSIF0_TS_XX4_MARK,
TSIF0_TS_XX5_MARK,
MST1_TS_XX1_MARK,
MST1_TS_XX2_MARK,
MST1_TS_XX3_MARK,
MST1_TS_XX4_MARK,
MST1_TS_XX5_MARK,
MST0_TS_XX1_MARK,
MST0_TS_XX2_MARK,
MST0_TS_XX3_MARK,
MST0_TS_XX4_MARK,
MST0_TS_XX5_MARK,
SDHI0_VCCQ_MC0_ON_MARK,
SDHI0_VCCQ_MC0_OFF_MARK,
DEBUG_MON_VIO_MARK,
DEBUG_MON_LCDD_MARK,
LCDC_LCDC0_MARK,
LCDC_LCDC1_MARK,
IRQ9_MEM_INT_MARK,
IRQ9_MCP_INT_MARK,
A11_MARK,
KEYOUT8_MARK,
TPU4TO3_MARK,
RESETA_N_PU_ON_MARK,
RESETA_N_PU_OFF_MARK,
EDBGREQ_PD_MARK,
EDBGREQ_PU_MARK,
KEYIN0_PU_MARK,
KEYIN1_PU_MARK,
KEYIN2_PU_MARK,
KEYIN3_PU_MARK,
KEYIN4_PU_MARK,
KEYIN5_PU_MARK,
KEYIN6_PU_MARK,
KEYIN7_PU_MARK,
SDHICD0_PU_MARK,
SDHID0_0_PU_MARK,
SDHID0_1_PU_MARK,
SDHID0_2_PU_MARK,
SDHID0_3_PU_MARK,
SDHICMD0_PU_MARK,
SDHIWP0_PU_MARK,
SDHID1_0_PU_MARK,
SDHID1_1_PU_MARK,
SDHID1_2_PU_MARK,
SDHID1_3_PU_MARK,
SDHICMD1_PU_MARK,
SDHID2_0_PU_MARK,
SDHID2_1_PU_MARK,
SDHID2_2_PU_MARK,
SDHID2_3_PU_MARK,
SDHICMD2_PU_MARK,
MMCCMD0_PU_MARK,
MMCCMD1_PU_MARK,
MMCD0_0_PU_MARK,
MMCD0_1_PU_MARK,
MMCD0_2_PU_MARK,
MMCD0_3_PU_MARK,
MMCD0_4_PU_MARK,
MMCD0_5_PU_MARK,
MMCD0_6_PU_MARK,
MMCD0_7_PU_MARK,
FSIBISLD_PU_MARK,
FSIACK_PU_MARK,
FSIAILR_PU_MARK,
FSIAIBT_PU_MARK,
FSIAISLD_PU_MARK,
PINMUX_MARK_END
} |
1.8.2