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#define B43_PHY_HT_BANDCTL 0x009 /* Band control */ |
#define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ |
#define B43_PHY_HT_BBCFG 0x001 /* BB config */ |
#define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */ |
#define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */ |
#define B43_PHY_HT_BW1 0x1CE |
#define B43_PHY_HT_BW2 0x1CF |
#define B43_PHY_HT_BW3 0x1D0 |
#define B43_PHY_HT_BW4 0x1D1 |
#define B43_PHY_HT_BW5 0x1D2 |
#define B43_PHY_HT_BW6 0x1D3 |
#define B43_PHY_HT_RF_SEQ_TRIG_RST2RX 0x0020 /* Reset to RX */ |
#define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */ |
#define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */ |
#define B43_PHY_HT_RF_SEQ_TRIG_UPGH 0x0004 /* Update gain H */ |
#define B43_PHY_HT_RF_SEQ_TRIG_UPGL 0x0008 /* Update gain L */ |
#define B43_PHY_HT_RF_SEQ_TRIG_UPGU 0x0010 /* Update gain U */ |
#define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */ |
#define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */ |
#define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */ |