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pm-pxa910.h
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1 /*
2  * PXA910 Power Management Routines
3  *
4  * This software program is licensed subject to the GNU General Public License
5  * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
6  *
7  * (C) Copyright 2009 Marvell International Ltd.
8  * All Rights Reserved
9  */
10 
11 #ifndef __PXA910_PM_H__
12 #define __PXA910_PM_H__
13 
14 #define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
15 #define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
16 #define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
17 #define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
18 #define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
19 #define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
20 #define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
21 #define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
22 
23 #define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
24 #define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
25 
26 #define MPMU_FCCR MPMU_REG(0x0008)
27 #define MPMU_APCR MPMU_REG(0x1000)
28 #define MPMU_APCR_AXISD (1 << 31)
29 #define MPMU_APCR_DSPSD (1 << 30)
30 #define MPMU_APCR_SLPEN (1 << 29)
31 #define MPMU_APCR_DTCMSD (1 << 28)
32 #define MPMU_APCR_DDRCORSD (1 << 27)
33 #define MPMU_APCR_APBSD (1 << 26)
34 #define MPMU_APCR_BBSD (1 << 25)
35 #define MPMU_APCR_SLPWP0 (1 << 23)
36 #define MPMU_APCR_SLPWP1 (1 << 22)
37 #define MPMU_APCR_SLPWP2 (1 << 21)
38 #define MPMU_APCR_SLPWP3 (1 << 20)
39 #define MPMU_APCR_VCTCXOSD (1 << 19)
40 #define MPMU_APCR_SLPWP4 (1 << 18)
41 #define MPMU_APCR_SLPWP5 (1 << 17)
42 #define MPMU_APCR_SLPWP6 (1 << 16)
43 #define MPMU_APCR_SLPWP7 (1 << 15)
44 #define MPMU_APCR_MSASLPEN (1 << 14)
45 #define MPMU_APCR_STBYEN (1 << 13)
46 
47 #define MPMU_AWUCRM MPMU_REG(0x104c)
48 #define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
49 #define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
50 #define MPMU_AWUCRM_SDH1 (1 << 23)
51 #define MPMU_AWUCRM_SDH2 (1 << 22)
52 #define MPMU_AWUCRM_KEYPRESS (1 << 21)
53 #define MPMU_AWUCRM_TRACKBALL (1 << 20)
54 #define MPMU_AWUCRM_NEWROTARY (1 << 19)
55 #define MPMU_AWUCRM_RTC_ALARM (1 << 17)
56 #define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
57 #define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
58 #define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
59 #define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
60 #define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
61 #define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
62 #define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
63 
64 enum {
73 };
74 
75 extern int pxa910_set_wake(struct irq_data *data, unsigned int on);
76 
77 #endif