#include <mach/addr-map.h>
Go to the source code of this file.
| #define APMU_PJ_IDLE_CFG APMU_REG(0x018) |
| #define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28) |
| #define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19) |
| #define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1) |
| #define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5) |
| #define APMU_PJ_IDLE_CFG_PWR_SW |
( |
|
x | ) |
((x) << 16) |
| #define APMU_SRAM_PWR_DWN APMU_REG(0x08c) |
| #define MPMU_PCR_PJ_APBSD (1 << 26) |
| #define MPMU_PCR_PJ_AXISD (1 << 31) |
| #define MPMU_PCR_PJ_DDRCORSD (1 << 27) |
| #define MPMU_PCR_PJ_INTCLR (1 << 24) |
| #define MPMU_PCR_PJ_SLPEN (1 << 29) |
| #define MPMU_PCR_PJ_SLPWP0 (1 << 23) |
| #define MPMU_PCR_PJ_SLPWP1 (1 << 22) |
| #define MPMU_PCR_PJ_SLPWP2 (1 << 21) |
| #define MPMU_PCR_PJ_SLPWP3 (1 << 20) |
| #define MPMU_PCR_PJ_SLPWP4 (1 << 18) |
| #define MPMU_PCR_PJ_SLPWP5 (1 << 17) |
| #define MPMU_PCR_PJ_SLPWP6 (1 << 16) |
| #define MPMU_PCR_PJ_SLPWP7 (1 << 15) |
| #define MPMU_PCR_PJ_SPSD (1 << 28) |
| #define MPMU_PCR_PJ_VCTCXOSD (1 << 19) |
| #define MPMU_PLL2_CTRL1 MPMU_REG(0x0414) |
| #define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17) |
| #define MPMU_WUCRM_PJ_WAKEUP |
( |
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x | ) |
(1 << (x)) |
- Enumerator:
| POWER_MODE_ACTIVE |
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| POWER_MODE_CORE_INTIDLE |
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| POWER_MODE_CORE_EXTIDLE |
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| POWER_MODE_APPS_IDLE |
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| POWER_MODE_APPS_SLEEP |
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| POWER_MODE_CHIP_SLEEP |
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| POWER_MODE_SYS_SLEEP |
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Definition at line 49 of file pm-mmp2.h.
| void mmp2_pm_enter_lowpower_mode |
( |
int |
state | ) |
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1.8.2