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| #define | AM33XX_PRM_BASE 0x44E00000 |
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| #define | AM33XX_PRM_REGADDR(inst, reg) AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg)) |
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| #define | AM33XX_PRM_OCP_SOCKET_MOD 0x0B00 |
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| #define | AM33XX_PRM_PER_MOD 0x0C00 |
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| #define | AM33XX_PRM_WKUP_MOD 0x0D00 |
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| #define | AM33XX_PRM_MPU_MOD 0x0E00 |
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| #define | AM33XX_PRM_DEVICE_MOD 0x0F00 |
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| #define | AM33XX_PRM_RTC_MOD 0x1000 |
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| #define | AM33XX_PRM_GFX_MOD 0x1100 |
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| #define | AM33XX_PRM_CEFUSE_MOD 0x1200 |
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| #define | AM33XX_REVISION_PRM_OFFSET 0x0000 |
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| #define | AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000) |
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| #define | AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 |
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| #define | AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004) |
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| #define | AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 |
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| #define | AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008) |
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| #define | AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c |
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| #define | AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c) |
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| #define | AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010 |
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| #define | AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010) |
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| #define | AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000 |
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| #define | AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000) |
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| #define | AM33XX_RM_PER_RSTST_OFFSET 0x0004 |
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| #define | AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004) |
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| #define | AM33XX_PM_PER_PWRSTST_OFFSET 0x0008 |
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| #define | AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008) |
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| #define | AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c |
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| #define | AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c) |
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| #define | AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000 |
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| #define | AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000) |
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| #define | AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004 |
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| #define | AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004) |
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| #define | AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008 |
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| #define | AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008) |
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| #define | AM33XX_RM_WKUP_RSTST_OFFSET 0x000c |
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| #define | AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c) |
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| #define | AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 |
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| #define | AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000) |
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| #define | AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004 |
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| #define | AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004) |
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| #define | AM33XX_RM_MPU_RSTST_OFFSET 0x0008 |
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| #define | AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008) |
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| #define | AM33XX_PRM_RSTCTRL_OFFSET 0x0000 |
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| #define | AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000) |
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| #define | AM33XX_PRM_RSTTIME_OFFSET 0x0004 |
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| #define | AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004) |
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| #define | AM33XX_PRM_RSTST_OFFSET 0x0008 |
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| #define | AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008) |
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| #define | AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c |
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| #define | AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c) |
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| #define | AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010 |
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| #define | AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010) |
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| #define | AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014 |
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| #define | AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014) |
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| #define | AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018 |
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| #define | AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018) |
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| #define | AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c |
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| #define | AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c) |
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| #define | AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000 |
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| #define | AM33XX_PM_RTC_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000) |
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| #define | AM33XX_PM_RTC_PWRSTST_OFFSET 0x0004 |
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| #define | AM33XX_PM_RTC_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004) |
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| #define | AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000 |
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| #define | AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000) |
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| #define | AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004 |
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| #define | AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004) |
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| #define | AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010 |
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| #define | AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010) |
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| #define | AM33XX_RM_GFX_RSTST_OFFSET 0x0014 |
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| #define | AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014) |
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| #define | AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 |
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| #define | AM33XX_PM_CEFUSE_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000) |
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| #define | AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004 |
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| #define | AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) |
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| int am33xx_prm_assert_hardreset |
( |
u8 |
shift, |
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s16 |
inst, |
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u16 |
rstctrl_offs |
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) |
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am33xx_prm_assert_hardreset - assert the HW reset line of a submodule : register bit shift corresponding to the reset line to assert : CM instance register offset (*_INST macro) : RM_RSTCTRL register address for this module
Some IPs like dsp, ipu or iva contain processors that require an HW reset line to be asserted / deasserted in order to fully enable the IP. These modules may have multiple hard-reset lines that reset different 'submodules' inside the IP block. This function will place the submodule into reset. Returns 0 upon success or -EINVAL upon an argument error.
Definition at line 88 of file prm33xx.c.
| int am33xx_prm_deassert_hardreset |
( |
u8 |
shift, |
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s16 |
inst, |
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u16 |
rstctrl_offs, |
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u16 |
rstst_offs |
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) |
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am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and wait : register bit shift corresponding to the reset line to deassert : CM instance register offset (*_INST macro) : RM_RSTCTRL register address for this module : RM_RSTST register address for this module
Some IPs like dsp, ipu or iva contain processors that require an HW reset line to be asserted / deasserted in order to fully enable the IP. These modules may have multiple hard-reset lines that reset different 'submodules' inside the IP block. This function will take the submodule out of reset and wait until the PRCM indicates that the reset has completed before returning. Returns 0 upon success or -EINVAL upon an argument error, -EEXIST if the submodule was already out of reset, or -EBUSY if the submodule did not exit reset promptly.
Definition at line 114 of file prm33xx.c.
| int am33xx_prm_is_hardreset_asserted |
( |
u8 |
shift, |
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s16 |
inst, |
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u16 |
rstctrl_offs |
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) |
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am33xx_prm_is_hardreset_asserted - read the HW reset line state of submodules contained in the hwmod module : register bit shift corresponding to the reset line to check : CM instance register offset (*_INST macro) : RM_RSTCTRL register address offset for this module
Returns 1 if the (sub)module hardreset line is currently asserted, 0 if the (sub)module hardreset line is not currently asserted, or -EINVAL upon parameter error.
Definition at line 64 of file prm33xx.c.
1.8.2