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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/init.h>#include <linux/dma-mapping.h>#include <linux/in.h>#include <linux/ip.h>#include <linux/tcp.h>#include <linux/udp.h>#include <linux/etherdevice.h>#include <linux/bitops.h>#include <linux/delay.h>#include <linux/ethtool.h>#include <linux/platform_device.h>#include <linux/module.h>#include <linux/kernel.h>#include <linux/workqueue.h>#include <linux/clk.h>#include <linux/phy.h>#include <linux/io.h>#include <linux/interrupt.h>#include <linux/types.h>#include <asm/pgtable.h>#include <asm/cacheflush.h>#include <linux/pxa168_eth.h>Go to the source code of this file.
Data Structures | |
| struct | rx_desc |
| struct | tx_desc |
| struct | pxa168_eth_private |
| struct | addr_table_entry |
Macros | |
| #define | DRIVER_NAME "pxa168-eth" |
| #define | DRIVER_VERSION "0.3" |
| #define | PHY_ADDRESS 0x0000 |
| #define | SMI 0x0010 |
| #define | PORT_CONFIG 0x0400 |
| #define | PORT_CONFIG_EXT 0x0408 |
| #define | PORT_COMMAND 0x0410 |
| #define | PORT_STATUS 0x0418 |
| #define | HTPR 0x0428 |
| #define | SDMA_CONFIG 0x0440 |
| #define | SDMA_CMD 0x0448 |
| #define | INT_CAUSE 0x0450 |
| #define | INT_W_CLEAR 0x0454 |
| #define | INT_MASK 0x0458 |
| #define | ETH_F_RX_DESC_0 0x0480 |
| #define | ETH_C_RX_DESC_0 0x04A0 |
| #define | ETH_C_TX_DESC_1 0x04E4 |
| #define | SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */ |
| #define | SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */ |
| #define | SMI_OP_W (0 << 26) /* Write operation */ |
| #define | SMI_OP_R (1 << 26) /* Read operation */ |
| #define | PHY_WAIT_ITERATIONS 10 |
| #define | PXA168_ETH_PHY_ADDR_DEFAULT 0 |
| #define | BUF_OWNED_BY_DMA (1 << 31) |
| #define | RX_EN_INT (1 << 23) |
| #define | RX_FIRST_DESC (1 << 17) |
| #define | RX_LAST_DESC (1 << 16) |
| #define | RX_ERROR (1 << 15) |
| #define | TX_EN_INT (1 << 23) |
| #define | TX_GEN_CRC (1 << 22) |
| #define | TX_ZERO_PADDING (1 << 18) |
| #define | TX_FIRST_DESC (1 << 17) |
| #define | TX_LAST_DESC (1 << 16) |
| #define | TX_ERROR (1 << 15) |
| #define | SDMA_CMD_AT (1 << 31) |
| #define | SDMA_CMD_TXDL (1 << 24) |
| #define | SDMA_CMD_TXDH (1 << 23) |
| #define | SDMA_CMD_AR (1 << 15) |
| #define | SDMA_CMD_ERD (1 << 7) |
| #define | PCR_HS (1 << 12) |
| #define | PCR_EN (1 << 7) |
| #define | PCR_PM (1 << 0) |
| #define | PCXR_2BSM (1 << 28) |
| #define | PCXR_DSCP_EN (1 << 21) |
| #define | PCXR_MFL_1518 (0 << 14) |
| #define | PCXR_MFL_1536 (1 << 14) |
| #define | PCXR_MFL_2048 (2 << 14) |
| #define | PCXR_MFL_64K (3 << 14) |
| #define | PCXR_FLP (1 << 11) |
| #define | PCXR_PRIO_TX_OFF 3 |
| #define | PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF) |
| #define | SDCR_BSZ_OFF 12 |
| #define | SDCR_BSZ8 (3 << SDCR_BSZ_OFF) |
| #define | SDCR_BSZ4 (2 << SDCR_BSZ_OFF) |
| #define | SDCR_BSZ2 (1 << SDCR_BSZ_OFF) |
| #define | SDCR_BSZ1 (0 << SDCR_BSZ_OFF) |
| #define | SDCR_BLMR (1 << 6) |
| #define | SDCR_BLMT (1 << 7) |
| #define | SDCR_RIFB (1 << 9) |
| #define | SDCR_RC_OFF 2 |
| #define | SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) |
| #define | ICR_RXBUF (1 << 0) |
| #define | ICR_TXBUF_H (1 << 2) |
| #define | ICR_TXBUF_L (1 << 3) |
| #define | ICR_TXEND_H (1 << 6) |
| #define | ICR_TXEND_L (1 << 7) |
| #define | ICR_RXERR (1 << 8) |
| #define | ICR_TXERR_H (1 << 10) |
| #define | ICR_TXERR_L (1 << 11) |
| #define | ICR_TX_UDR (1 << 13) |
| #define | ICR_MII_CH (1 << 28) |
| #define | ALL_INTS |
| #define | ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ |
| #define | NUM_RX_DESCS 64 |
| #define | NUM_TX_DESCS 64 |
| #define | HASH_ADD 0 |
| #define | HASH_DELETE 1 |
| #define | HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ |
| #define | HOP_NUMBER 12 |
| #define | PORT_SPEED_100 (1 << 0) |
| #define | FULL_DUPLEX (1 << 1) |
| #define | FLOW_CONTROL_ENABLED (1 << 2) |
| #define | LINK_UP (1 << 3) |
| #define | WORK_LINK (1 << 0) |
| #define | WORK_TX_DONE (1 << 1) |
| #define | SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) |
| #define | pxa168_eth_resume NULL |
| #define | pxa168_eth_suspend NULL |
Enumerations | |
| enum | hash_table_entry { HASH_ENTRY_VALID = 1, SKIP = 2, HASH_ENTRY_RECEIVE_DISCARD = 4, HASH_ENTRY_RECEIVE_DISCARD_BIT = 2 } |
Functions | |
| module_platform_driver (pxa168_eth_driver) | |
| MODULE_LICENSE ("GPL") | |
| MODULE_DESCRIPTION ("Ethernet driver for Marvell PXA168") | |
| MODULE_ALIAS ("platform:pxa168_eth") | |
| #define ALL_INTS |
Definition at line 148 of file pxa168_eth.c.
| #define BUF_OWNED_BY_DMA (1 << 31) |
Definition at line 82 of file pxa168_eth.c.
| #define DRIVER_NAME "pxa168-eth" |
Definition at line 49 of file pxa168_eth.c.
| #define DRIVER_VERSION "0.3" |
Definition at line 50 of file pxa168_eth.c.
| #define ETH_C_RX_DESC_0 0x04A0 |
Definition at line 69 of file pxa168_eth.c.
| #define ETH_C_TX_DESC_1 0x04E4 |
Definition at line 70 of file pxa168_eth.c.
| #define ETH_F_RX_DESC_0 0x0480 |
Definition at line 68 of file pxa168_eth.c.
Definition at line 153 of file pxa168_eth.c.
| #define FLOW_CONTROL_ENABLED (1 << 2) |
Definition at line 166 of file pxa168_eth.c.
| #define FULL_DUPLEX (1 << 1) |
Definition at line 165 of file pxa168_eth.c.
| #define HASH_ADD 0 |
Definition at line 158 of file pxa168_eth.c.
| #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ |
Definition at line 160 of file pxa168_eth.c.
| #define HASH_DELETE 1 |
Definition at line 159 of file pxa168_eth.c.
| #define HOP_NUMBER 12 |
Definition at line 161 of file pxa168_eth.c.
| #define HTPR 0x0428 |
Definition at line 62 of file pxa168_eth.c.
| #define ICR_MII_CH (1 << 28) |
Definition at line 146 of file pxa168_eth.c.
| #define ICR_RXBUF (1 << 0) |
Definition at line 137 of file pxa168_eth.c.
| #define ICR_RXERR (1 << 8) |
Definition at line 142 of file pxa168_eth.c.
| #define ICR_TX_UDR (1 << 13) |
Definition at line 145 of file pxa168_eth.c.
| #define ICR_TXBUF_H (1 << 2) |
Definition at line 138 of file pxa168_eth.c.
| #define ICR_TXBUF_L (1 << 3) |
Definition at line 139 of file pxa168_eth.c.
| #define ICR_TXEND_H (1 << 6) |
Definition at line 140 of file pxa168_eth.c.
| #define ICR_TXEND_L (1 << 7) |
Definition at line 141 of file pxa168_eth.c.
| #define ICR_TXERR_H (1 << 10) |
Definition at line 143 of file pxa168_eth.c.
| #define ICR_TXERR_L (1 << 11) |
Definition at line 144 of file pxa168_eth.c.
| #define INT_CAUSE 0x0450 |
Definition at line 65 of file pxa168_eth.c.
| #define INT_MASK 0x0458 |
Definition at line 67 of file pxa168_eth.c.
| #define INT_W_CLEAR 0x0454 |
Definition at line 66 of file pxa168_eth.c.
| #define LINK_UP (1 << 3) |
Definition at line 167 of file pxa168_eth.c.
| #define NUM_RX_DESCS 64 |
Definition at line 155 of file pxa168_eth.c.
| #define NUM_TX_DESCS 64 |
Definition at line 156 of file pxa168_eth.c.
| #define PCR_EN (1 << 7) |
Definition at line 107 of file pxa168_eth.c.
| #define PCR_HS (1 << 12) |
Definition at line 106 of file pxa168_eth.c.
| #define PCR_PM (1 << 0) |
Definition at line 108 of file pxa168_eth.c.
| #define PCXR_2BSM (1 << 28) |
Definition at line 111 of file pxa168_eth.c.
| #define PCXR_DSCP_EN (1 << 21) |
Definition at line 112 of file pxa168_eth.c.
| #define PCXR_FLP (1 << 11) |
Definition at line 117 of file pxa168_eth.c.
| #define PCXR_MFL_1518 (0 << 14) |
Definition at line 113 of file pxa168_eth.c.
| #define PCXR_MFL_1536 (1 << 14) |
Definition at line 114 of file pxa168_eth.c.
| #define PCXR_MFL_2048 (2 << 14) |
Definition at line 115 of file pxa168_eth.c.
| #define PCXR_MFL_64K (3 << 14) |
Definition at line 116 of file pxa168_eth.c.
| #define PCXR_PRIO_TX_OFF 3 |
Definition at line 118 of file pxa168_eth.c.
| #define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF) |
Definition at line 119 of file pxa168_eth.c.
| #define PHY_ADDRESS 0x0000 |
Definition at line 56 of file pxa168_eth.c.
| #define PHY_WAIT_ITERATIONS 10 |
Definition at line 78 of file pxa168_eth.c.
| #define PORT_COMMAND 0x0410 |
Definition at line 60 of file pxa168_eth.c.
| #define PORT_CONFIG 0x0400 |
Definition at line 58 of file pxa168_eth.c.
| #define PORT_CONFIG_EXT 0x0408 |
Definition at line 59 of file pxa168_eth.c.
| #define PORT_SPEED_100 (1 << 0) |
Definition at line 164 of file pxa168_eth.c.
| #define PORT_STATUS 0x0418 |
Definition at line 61 of file pxa168_eth.c.
| #define PXA168_ETH_PHY_ADDR_DEFAULT 0 |
Definition at line 80 of file pxa168_eth.c.
| #define pxa168_eth_resume NULL |
Definition at line 1632 of file pxa168_eth.c.
| #define pxa168_eth_suspend NULL |
Definition at line 1633 of file pxa168_eth.c.
| #define RX_EN_INT (1 << 23) |
Definition at line 85 of file pxa168_eth.c.
| #define RX_ERROR (1 << 15) |
Definition at line 88 of file pxa168_eth.c.
| #define RX_FIRST_DESC (1 << 17) |
Definition at line 86 of file pxa168_eth.c.
| #define RX_LAST_DESC (1 << 16) |
Definition at line 87 of file pxa168_eth.c.
| #define SDCR_BLMR (1 << 6) |
Definition at line 127 of file pxa168_eth.c.
| #define SDCR_BLMT (1 << 7) |
Definition at line 128 of file pxa168_eth.c.
| #define SDCR_BSZ1 (0 << SDCR_BSZ_OFF) |
Definition at line 126 of file pxa168_eth.c.
| #define SDCR_BSZ2 (1 << SDCR_BSZ_OFF) |
Definition at line 125 of file pxa168_eth.c.
| #define SDCR_BSZ4 (2 << SDCR_BSZ_OFF) |
Definition at line 124 of file pxa168_eth.c.
| #define SDCR_BSZ8 (3 << SDCR_BSZ_OFF) |
Definition at line 123 of file pxa168_eth.c.
| #define SDCR_BSZ_OFF 12 |
Definition at line 122 of file pxa168_eth.c.
| #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) |
Definition at line 131 of file pxa168_eth.c.
| #define SDCR_RC_OFF 2 |
Definition at line 130 of file pxa168_eth.c.
| #define SDCR_RIFB (1 << 9) |
Definition at line 129 of file pxa168_eth.c.
| #define SDMA_CMD 0x0448 |
Definition at line 64 of file pxa168_eth.c.
| #define SDMA_CMD_AR (1 << 15) |
Definition at line 102 of file pxa168_eth.c.
| #define SDMA_CMD_AT (1 << 31) |
Definition at line 99 of file pxa168_eth.c.
| #define SDMA_CMD_ERD (1 << 7) |
Definition at line 103 of file pxa168_eth.c.
| #define SDMA_CMD_TXDH (1 << 23) |
Definition at line 101 of file pxa168_eth.c.
| #define SDMA_CMD_TXDL (1 << 24) |
Definition at line 100 of file pxa168_eth.c.
| #define SDMA_CONFIG 0x0440 |
Definition at line 63 of file pxa168_eth.c.
| #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) |
Definition at line 176 of file pxa168_eth.c.
| #define SMI 0x0010 |
Definition at line 57 of file pxa168_eth.c.
Definition at line 73 of file pxa168_eth.c.
Definition at line 76 of file pxa168_eth.c.
Definition at line 75 of file pxa168_eth.c.
Definition at line 74 of file pxa168_eth.c.
| #define TX_EN_INT (1 << 23) |
Definition at line 91 of file pxa168_eth.c.
| #define TX_ERROR (1 << 15) |
Definition at line 96 of file pxa168_eth.c.
| #define TX_FIRST_DESC (1 << 17) |
Definition at line 94 of file pxa168_eth.c.
| #define TX_GEN_CRC (1 << 22) |
Definition at line 92 of file pxa168_eth.c.
| #define TX_LAST_DESC (1 << 16) |
Definition at line 95 of file pxa168_eth.c.
| #define TX_ZERO_PADDING (1 << 18) |
Definition at line 93 of file pxa168_eth.c.
| #define WORK_LINK (1 << 0) |
Definition at line 170 of file pxa168_eth.c.
| #define WORK_TX_DONE (1 << 1) |
Definition at line 171 of file pxa168_eth.c.
| enum hash_table_entry |
Definition at line 258 of file pxa168_eth.c.
| MODULE_ALIAS | ( | "platform:pxa168_eth" | ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| module_platform_driver | ( | pxa168_eth_driver | ) |
1.8.2