#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <mach/dma.h>
#include <linux/platform_data/mtd-nand-pxa3xx.h>

Data Structures
struct	pxa3xx_nand_host

struct	pxa3xx_nand_info

Macros
#define	CHIP_DELAY_TIMEOUT (2 * HZ/10)

#define	NAND_STOP_DELAY (2 * HZ/50)

#define	PAGE_CHUNK_SIZE (2048)

#define	NDCR (0x00) /* Control register */

#define	NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */

#define	NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */

#define	NDSR (0x14) /* Status Register */

#define	NDPCR (0x18) /* Page Count Register */

#define	NDBDR0 (0x1C) /* Bad Block Register 0 */

#define	NDBDR1 (0x20) /* Bad Block Register 1 */

#define	NDDB (0x40) /* Data Buffer */

#define	NDCB0 (0x48) /* Command Buffer0 */

#define	NDCB1 (0x4C) /* Command Buffer1 */

#define	NDCB2 (0x50) /* Command Buffer2 */

#define	NDCR_SPARE_EN (0x1 << 31)

#define	NDCR_ECC_EN (0x1 << 30)

#define	NDCR_DMA_EN (0x1 << 29)

#define	NDCR_ND_RUN (0x1 << 28)

#define	NDCR_DWIDTH_C (0x1 << 27)

#define	NDCR_DWIDTH_M (0x1 << 26)

#define	NDCR_PAGE_SZ (0x1 << 24)

#define	NDCR_NCSX (0x1 << 23)

#define	NDCR_ND_MODE (0x3 << 21)

#define	NDCR_NAND_MODE (0x0)

#define	NDCR_CLR_PG_CNT (0x1 << 20)

#define	NDCR_STOP_ON_UNCOR (0x1 << 19)

#define	NDCR_RD_ID_CNT_MASK (0x7 << 16)

#define	NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)

#define	NDCR_RA_START (0x1 << 15)

#define	NDCR_PG_PER_BLK (0x1 << 14)

#define	NDCR_ND_ARB_EN (0x1 << 12)

#define	NDCR_INT_MASK (0xFFF)

#define	NDSR_MASK (0xfff)

#define	NDSR_RDY (0x1 << 12)

#define	NDSR_FLASH_RDY (0x1 << 11)

#define	NDSR_CS0_PAGED (0x1 << 10)

#define	NDSR_CS1_PAGED (0x1 << 9)

#define	NDSR_CS0_CMDD (0x1 << 8)

#define	NDSR_CS1_CMDD (0x1 << 7)

#define	NDSR_CS0_BBD (0x1 << 6)

#define	NDSR_CS1_BBD (0x1 << 5)

#define	NDSR_DBERR (0x1 << 4)

#define	NDSR_SBERR (0x1 << 3)

#define	NDSR_WRDREQ (0x1 << 2)

#define	NDSR_RDDREQ (0x1 << 1)

#define	NDSR_WRCMDREQ (0x1)

#define	NDCB0_ST_ROW_EN (0x1 << 26)

#define	NDCB0_AUTO_RS (0x1 << 25)

#define	NDCB0_CSEL (0x1 << 24)

#define	NDCB0_CMD_TYPE_MASK (0x7 << 21)

#define	NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)

#define	NDCB0_NC (0x1 << 20)

#define	NDCB0_DBC (0x1 << 19)

#define	NDCB0_ADDR_CYC_MASK (0x7 << 16)

#define	NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)

#define	NDCB0_CMD2_MASK (0xff << 8)

#define	NDCB0_CMD1_MASK (0xff)

#define	NDCB0_ADDR_CYC_SHIFT (16)

#define	nand_writel(info, off, val) __raw_writel((val), (info)->mmio_base + (off))

#define	nand_readl(info, off) __raw_readl((info)->mmio_base + (off))

#define	DEFAULT_FLASH_TYPE (&builtin_flash_types[0])

#define	NDTR0_tCH(c) (min((c), 7) << 19)

#define	NDTR0_tCS(c) (min((c), 7) << 16)

#define	NDTR0_tWH(c) (min((c), 7) << 11)

#define	NDTR0_tWP(c) (min((c), 7) << 8)

#define	NDTR0_tRH(c) (min((c), 7) << 3)

#define	NDTR0_tRP(c) (min((c), 7) << 0)

#define	NDTR1_tR(c) (min((c), 65535) << 16)

#define	NDTR1_tWHR(c) (min((c), 15) << 4)

#define	NDTR1_tAR(c) (min((c), 15) << 0)

#define	ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)

#define	MAX_BUFF_SIZE PAGE_SIZE

#define	pxa3xx_nand_suspend NULL

#define	pxa3xx_nand_resume NULL

Enumerations
enum	{ ERR_NONE = 0, ERR_DMABUSERR = -1, ERR_SENDCMD = -2, ERR_DBERR = -3, ERR_BBERR = -4, ERR_SBERR = -5 }

enum	{ STATE_IDLE = 0, STATE_PREPARED, STATE_CMD_HANDLE, STATE_DMA_READING, STATE_DMA_WRITING, STATE_DMA_DONE, STATE_PIO_READING, STATE_PIO_WRITING, STATE_CMD_DONE, STATE_READY }

Functions
	module_param (use_dma, bool, 0444)

	MODULE_PARM_DESC (use_dma,"enable DMA for data transferring to/from NAND HW")

	module_platform_driver (pxa3xx_nand_driver)

	MODULE_LICENSE ("GPL")

	MODULE_DESCRIPTION ("PXA3xx NAND controller driver")

Variables
const char *	mtd_names [] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL}

Macro Definition Documentation

#define CHIP_DELAY_TIMEOUT (2 * HZ/10)

Definition at line 31 of file pxa3xx_nand.c.

#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])

Definition at line 231 of file pxa3xx_nand.c.

#define MAX_BUFF_SIZE PAGE_SIZE

Definition at line 879 of file pxa3xx_nand.c.

#define nand_readl	(	info,
		off
	)	__raw_readl((info)->mmio_base + (off))

Definition at line 100 of file pxa3xx_nand.c.

#define NAND_STOP_DELAY (2 * HZ/50)

Definition at line 32 of file pxa3xx_nand.c.

#define nand_writel	(	info,
		off,
		val
	)	__raw_writel((val), (info)->mmio_base + (off))

Definition at line 97 of file pxa3xx_nand.c.

#define NDBDR0 (0x1C) /* Bad Block Register 0 */

Definition at line 41 of file pxa3xx_nand.c.

#define NDBDR1 (0x20) /* Bad Block Register 1 */

Definition at line 42 of file pxa3xx_nand.c.

#define NDCB0 (0x48) /* Command Buffer0 */

Definition at line 44 of file pxa3xx_nand.c.

#define NDCB0_ADDR_CYC ( x ) (((x) << 16) & NDCB0_ADDR_CYC_MASK)

Definition at line 91 of file pxa3xx_nand.c.

#define NDCB0_ADDR_CYC_MASK (0x7 << 16)

Definition at line 90 of file pxa3xx_nand.c.

#define NDCB0_ADDR_CYC_SHIFT (16)

Definition at line 94 of file pxa3xx_nand.c.

#define NDCB0_AUTO_RS (0x1 << 25)

Definition at line 84 of file pxa3xx_nand.c.

#define NDCB0_CMD1_MASK (0xff)

Definition at line 93 of file pxa3xx_nand.c.

#define NDCB0_CMD2_MASK (0xff << 8)

Definition at line 92 of file pxa3xx_nand.c.

#define NDCB0_CMD_TYPE ( x ) (((x) << 21) & NDCB0_CMD_TYPE_MASK)

Definition at line 87 of file pxa3xx_nand.c.

#define NDCB0_CMD_TYPE_MASK (0x7 << 21)

Definition at line 86 of file pxa3xx_nand.c.

#define NDCB0_CSEL (0x1 << 24)

Definition at line 85 of file pxa3xx_nand.c.

#define NDCB0_DBC (0x1 << 19)

Definition at line 89 of file pxa3xx_nand.c.

#define NDCB0_NC (0x1 << 20)

Definition at line 88 of file pxa3xx_nand.c.

#define NDCB0_ST_ROW_EN (0x1 << 26)

Definition at line 83 of file pxa3xx_nand.c.

#define NDCB1 (0x4C) /* Command Buffer1 */

Definition at line 45 of file pxa3xx_nand.c.

#define NDCB2 (0x50) /* Command Buffer2 */

Definition at line 46 of file pxa3xx_nand.c.

#define NDCR (0x00) /* Control register */

Definition at line 36 of file pxa3xx_nand.c.

#define NDCR_CLR_PG_CNT (0x1 << 20)

Definition at line 58 of file pxa3xx_nand.c.

#define NDCR_DMA_EN (0x1 << 29)

Definition at line 50 of file pxa3xx_nand.c.

#define NDCR_DWIDTH_C (0x1 << 27)

Definition at line 52 of file pxa3xx_nand.c.

#define NDCR_DWIDTH_M (0x1 << 26)

Definition at line 53 of file pxa3xx_nand.c.

#define NDCR_ECC_EN (0x1 << 30)

Definition at line 49 of file pxa3xx_nand.c.

#define NDCR_INT_MASK (0xFFF)

Definition at line 66 of file pxa3xx_nand.c.

#define NDCR_NAND_MODE (0x0)

Definition at line 57 of file pxa3xx_nand.c.

#define NDCR_NCSX (0x1 << 23)

Definition at line 55 of file pxa3xx_nand.c.

#define NDCR_ND_ARB_EN (0x1 << 12)

Definition at line 65 of file pxa3xx_nand.c.

#define NDCR_ND_MODE (0x3 << 21)

Definition at line 56 of file pxa3xx_nand.c.

#define NDCR_ND_RUN (0x1 << 28)

Definition at line 51 of file pxa3xx_nand.c.

#define NDCR_PAGE_SZ (0x1 << 24)

Definition at line 54 of file pxa3xx_nand.c.

#define NDCR_PG_PER_BLK (0x1 << 14)

Definition at line 64 of file pxa3xx_nand.c.

#define NDCR_RA_START (0x1 << 15)

Definition at line 63 of file pxa3xx_nand.c.

#define NDCR_RD_ID_CNT ( x ) (((x) << 16) & NDCR_RD_ID_CNT_MASK)

Definition at line 61 of file pxa3xx_nand.c.

#define NDCR_RD_ID_CNT_MASK (0x7 << 16)

Definition at line 60 of file pxa3xx_nand.c.

#define NDCR_SPARE_EN (0x1 << 31)

Definition at line 48 of file pxa3xx_nand.c.

#define NDCR_STOP_ON_UNCOR (0x1 << 19)

Definition at line 59 of file pxa3xx_nand.c.

#define NDDB (0x40) /* Data Buffer */

Definition at line 43 of file pxa3xx_nand.c.

#define NDPCR (0x18) /* Page Count Register */

Definition at line 40 of file pxa3xx_nand.c.

#define NDSR (0x14) /* Status Register */

Definition at line 39 of file pxa3xx_nand.c.

#define NDSR_CS0_BBD (0x1 << 6)

Definition at line 75 of file pxa3xx_nand.c.

#define NDSR_CS0_CMDD (0x1 << 8)

Definition at line 73 of file pxa3xx_nand.c.

#define NDSR_CS0_PAGED (0x1 << 10)

Definition at line 71 of file pxa3xx_nand.c.

#define NDSR_CS1_BBD (0x1 << 5)

Definition at line 76 of file pxa3xx_nand.c.

#define NDSR_CS1_CMDD (0x1 << 7)

Definition at line 74 of file pxa3xx_nand.c.

#define NDSR_CS1_PAGED (0x1 << 9)

Definition at line 72 of file pxa3xx_nand.c.

#define NDSR_DBERR (0x1 << 4)

Definition at line 77 of file pxa3xx_nand.c.

#define NDSR_FLASH_RDY (0x1 << 11)

Definition at line 70 of file pxa3xx_nand.c.

#define NDSR_MASK (0xfff)

Definition at line 68 of file pxa3xx_nand.c.

#define NDSR_RDDREQ (0x1 << 1)

Definition at line 80 of file pxa3xx_nand.c.

#define NDSR_RDY (0x1 << 12)

Definition at line 69 of file pxa3xx_nand.c.

#define NDSR_SBERR (0x1 << 3)

Definition at line 78 of file pxa3xx_nand.c.

#define NDSR_WRCMDREQ (0x1)

Definition at line 81 of file pxa3xx_nand.c.

#define NDSR_WRDREQ (0x1 << 2)

Definition at line 79 of file pxa3xx_nand.c.

#define NDTR0_tCH ( c ) (min((c), 7) << 19)

Definition at line 235 of file pxa3xx_nand.c.

#define NDTR0_tCS ( c ) (min((c), 7) << 16)

Definition at line 236 of file pxa3xx_nand.c.

#define NDTR0_tRH ( c ) (min((c), 7) << 3)

Definition at line 239 of file pxa3xx_nand.c.

#define NDTR0_tRP ( c ) (min((c), 7) << 0)

Definition at line 240 of file pxa3xx_nand.c.

#define NDTR0_tWH ( c ) (min((c), 7) << 11)

Definition at line 237 of file pxa3xx_nand.c.

#define NDTR0_tWP ( c ) (min((c), 7) << 8)

Definition at line 238 of file pxa3xx_nand.c.

#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */

Definition at line 37 of file pxa3xx_nand.c.

#define NDTR1_tAR ( c ) (min((c), 15) << 0)

Definition at line 244 of file pxa3xx_nand.c.

#define NDTR1_tR ( c ) (min((c), 65535) << 16)

Definition at line 242 of file pxa3xx_nand.c.

#define NDTR1_tWHR ( c ) (min((c), 15) << 4)

Definition at line 243 of file pxa3xx_nand.c.

#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */

Definition at line 38 of file pxa3xx_nand.c.

#define ns2cycle	(	ns,
		clk
	)	(int)((ns) * (clk / 1000000) / 1000)

Definition at line 247 of file pxa3xx_nand.c.

#define PAGE_CHUNK_SIZE (2048)

Definition at line 33 of file pxa3xx_nand.c.

#define pxa3xx_nand_resume NULL

Definition at line 1353 of file pxa3xx_nand.c.

#define pxa3xx_nand_suspend NULL

Definition at line 1352 of file pxa3xx_nand.c.

Enumeration Type Documentation

anonymous enum

Enumerator:

ERR_NONE
ERR_DMABUSERR
ERR_SENDCMD
ERR_DBERR
ERR_BBERR
ERR_SBERR

Definition at line 104 of file pxa3xx_nand.c.

anonymous enum

Enumerator:

STATE_IDLE
STATE_PREPARED
STATE_CMD_HANDLE
STATE_DMA_READING
STATE_DMA_WRITING
STATE_DMA_DONE
STATE_PIO_READING
STATE_PIO_WRITING
STATE_CMD_DONE
STATE_READY

Definition at line 113 of file pxa3xx_nand.c.

Function Documentation

MODULE_DESCRIPTION ( "PXA3xx NAND controller driver" )

MODULE_LICENSE ( "GPL" )

module_param	(	use_dma	,
		bool	,
		0444
	)

MODULE_PARM_DESC	(	use_dma	,
		"enable DMA for data transferring to/from NAND HW"
	)

module_platform_driver ( pxa3xx_nand_driver )

Variable Documentation

const char* mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL}

Definition at line 233 of file pxa3xx_nand.c.

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation