Data Structures
struct	crb_128M_2M_sub_block_map

struct	crb_128M_2M_block_map

struct	crb_addr_pair

struct	qla8xxx_minidump_entry_hdr

struct	qla8xxx_minidump_entry_crb

struct	qla8xxx_minidump_entry_cache

struct	qla8xxx_minidump_entry_rdocm

struct	qla8xxx_minidump_entry_rdmem

struct	qla8xxx_minidump_entry_rdrom

struct	qla8xxx_minidump_entry_mux

struct	qla8xxx_minidump_entry_queue

Macros
#define	PHAN_INITIALIZE_FAILED 0xffff

#define	PHAN_INITIALIZE_COMPLETE 0xff01

#define	PHAN_INITIALIZE_ACK 0xf00f

#define	PHAN_PEG_RCV_INITIALIZED 0xff01

#define	QLA82XX_CRB_BASE (QLA82XX_CAM_RAM(0x200))

#define	QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X))

#define	CRB_CMDPEG_STATE QLA82XX_REG(0x50)

#define	CRB_RCVPEG_STATE QLA82XX_REG(0x13c)

#define	CRB_DMA_SHIFT QLA82XX_REG(0xcc)

#define	CRB_TEMP_STATE QLA82XX_REG(0x1b4)

#define	CRB_CMDPEG_CHECK_RETRY_COUNT 60

#define	CRB_CMDPEG_CHECK_DELAY 500

#define	qla82xx_get_temp_val(x) ((x) >> 16)

#define	qla82xx_get_temp_state(x) ((x) & 0xffff)

#define	qla82xx_encode_temp(val, state) (((val) << 16) \| (state))

#define	CRB_NIU_XG_PAUSE_CTL_P0 0x1

#define	CRB_NIU_XG_PAUSE_CTL_P1 0x8

#define	QLA82XX_HW_H0_CH_HUB_ADR 0x05

#define	QLA82XX_HW_H1_CH_HUB_ADR 0x0E

#define	QLA82XX_HW_H2_CH_HUB_ADR 0x03

#define	QLA82XX_HW_H3_CH_HUB_ADR 0x01

#define	QLA82XX_HW_H4_CH_HUB_ADR 0x06

#define	QLA82XX_HW_H5_CH_HUB_ADR 0x07

#define	QLA82XX_HW_H6_CH_HUB_ADR 0x08

#define	QLA82XX_HW_MN_CRB_AGT_ADR 0x15

#define	QLA82XX_HW_MS_CRB_AGT_ADR 0x25

#define	QLA82XX_HW_PS_CRB_AGT_ADR 0x73

#define	QLA82XX_HW_QMS_CRB_AGT_ADR 0x00

#define	QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b

#define	QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01

#define	QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02

#define	QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03

#define	QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04

#define	QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58

#define	QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59

#define	QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a

#define	QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a

#define	QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c

#define	QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f

#define	QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12

#define	QLA82XX_HW_SMB_CRB_AGT_ADR 0x18

#define	QLA82XX_HW_NIU_CRB_AGT_ADR 0x31

#define	QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19

#define	QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29

#define	QLA82XX_HW_SN_CRB_AGT_ADR 0x10

#define	QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20

#define	QLA82XX_HW_LPC_CRB_AGT_ADR 0x22

#define	QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21

#define	QLA82XX_HW_QM_CRB_AGT_ADR 0x66

#define	QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60

#define	QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61

#define	QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62

#define	QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63

#define	QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09

#define	QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d

#define	QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e

#define	QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11

#define	QLA82XX_HW_PH_CRB_AGT_ADR 0x1A

#define	QLA82XX_HW_SRE_CRB_AGT_ADR 0x50

#define	QLA82XX_HW_EG_CRB_AGT_ADR 0x51

#define	QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08

#define	QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40

#define	QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41

#define	QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42

#define	QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43

#define	QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44

#define	QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45

#define	QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46

#define	QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47

#define	QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48

#define	QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49

#define	QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a

#define	QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b

#define	QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40

#define	QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41

#define	QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42

#define	QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43

#define	QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44

#define	QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45

#define	QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46

#define	QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46

#define	QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47

#define	QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48

#define	QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49

#define	QLA82XX_HW_NCM_CRB_AGT_ADR 0x16

#define	QLA82XX_HW_TMR_CRB_AGT_ADR 0x17

#define	QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05

#define	QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06

#define	QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07

#define	QLA82XX_HW_PX_MAP_CRB_PH 0

#define	QLA82XX_HW_PX_MAP_CRB_PS 1

#define	QLA82XX_HW_PX_MAP_CRB_MN 2

#define	QLA82XX_HW_PX_MAP_CRB_MS 3

#define	QLA82XX_HW_PX_MAP_CRB_SRE 5

#define	QLA82XX_HW_PX_MAP_CRB_NIU 6

#define	QLA82XX_HW_PX_MAP_CRB_QMN 7

#define	QLA82XX_HW_PX_MAP_CRB_SQN0 8

#define	QLA82XX_HW_PX_MAP_CRB_SQN1 9

#define	QLA82XX_HW_PX_MAP_CRB_SQN2 10

#define	QLA82XX_HW_PX_MAP_CRB_SQN3 11

#define	QLA82XX_HW_PX_MAP_CRB_QMS 12

#define	QLA82XX_HW_PX_MAP_CRB_SQS0 13

#define	QLA82XX_HW_PX_MAP_CRB_SQS1 14

#define	QLA82XX_HW_PX_MAP_CRB_SQS2 15

#define	QLA82XX_HW_PX_MAP_CRB_SQS3 16

#define	QLA82XX_HW_PX_MAP_CRB_PGN0 17

#define	QLA82XX_HW_PX_MAP_CRB_PGN1 18

#define	QLA82XX_HW_PX_MAP_CRB_PGN2 19

#define	QLA82XX_HW_PX_MAP_CRB_PGN3 20

#define	QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2

#define	QLA82XX_HW_PX_MAP_CRB_PGND 21

#define	QLA82XX_HW_PX_MAP_CRB_PGNI 22

#define	QLA82XX_HW_PX_MAP_CRB_PGS0 23

#define	QLA82XX_HW_PX_MAP_CRB_PGS1 24

#define	QLA82XX_HW_PX_MAP_CRB_PGS2 25

#define	QLA82XX_HW_PX_MAP_CRB_PGS3 26

#define	QLA82XX_HW_PX_MAP_CRB_PGSD 27

#define	QLA82XX_HW_PX_MAP_CRB_PGSI 28

#define	QLA82XX_HW_PX_MAP_CRB_SN 29

#define	QLA82XX_HW_PX_MAP_CRB_EG 31

#define	QLA82XX_HW_PX_MAP_CRB_PH2 32

#define	QLA82XX_HW_PX_MAP_CRB_PS2 33

#define	QLA82XX_HW_PX_MAP_CRB_CAM 34

#define	QLA82XX_HW_PX_MAP_CRB_CAS0 35

#define	QLA82XX_HW_PX_MAP_CRB_CAS1 36

#define	QLA82XX_HW_PX_MAP_CRB_CAS2 37

#define	QLA82XX_HW_PX_MAP_CRB_C2C0 38

#define	QLA82XX_HW_PX_MAP_CRB_C2C1 39

#define	QLA82XX_HW_PX_MAP_CRB_TIMR 40

#define	QLA82XX_HW_PX_MAP_CRB_RPMX1 42

#define	QLA82XX_HW_PX_MAP_CRB_RPMX2 43

#define	QLA82XX_HW_PX_MAP_CRB_RPMX3 44

#define	QLA82XX_HW_PX_MAP_CRB_RPMX4 45

#define	QLA82XX_HW_PX_MAP_CRB_RPMX5 46

#define	QLA82XX_HW_PX_MAP_CRB_RPMX6 47

#define	QLA82XX_HW_PX_MAP_CRB_RPMX7 48

#define	QLA82XX_HW_PX_MAP_CRB_XDMA 49

#define	QLA82XX_HW_PX_MAP_CRB_I2Q 50

#define	QLA82XX_HW_PX_MAP_CRB_ROMUSB 51

#define	QLA82XX_HW_PX_MAP_CRB_CAS3 52

#define	QLA82XX_HW_PX_MAP_CRB_RPMX0 53

#define	QLA82XX_HW_PX_MAP_CRB_RPMX8 54

#define	QLA82XX_HW_PX_MAP_CRB_RPMX9 55

#define	QLA82XX_HW_PX_MAP_CRB_OCM0 56

#define	QLA82XX_HW_PX_MAP_CRB_OCM1 57

#define	QLA82XX_HW_PX_MAP_CRB_SMB 58

#define	QLA82XX_HW_PX_MAP_CRB_I2C0 59

#define	QLA82XX_HW_PX_MAP_CRB_I2C1 60

#define	QLA82XX_HW_PX_MAP_CRB_LPC 61

#define	QLA82XX_HW_PX_MAP_CRB_PGNC 62

#define	QLA82XX_HW_PX_MAP_CRB_PGR0 63

#define	QLA82XX_HW_PX_MAP_CRB_PGR1 4

#define	QLA82XX_HW_PX_MAP_CRB_PGR2 30

#define	QLA82XX_HW_PX_MAP_CRB_PGR3 41

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_MN

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PH

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_MS

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PS

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SS

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_QMS

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SMB

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_NIU

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SRE

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_EG

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_QMN

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGND

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_CAM

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_SN

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1

#define	QLA82XX_HW_CRB_HUB_AGT_ADR_LPC

#define	ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)

#define	QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)

#define	QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)

#define	QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)

#define	QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)

#define	QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)

#define	QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)

#define	QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)

#define	QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)

#define	ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)

#define	QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)

#define	QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)

#define	ROM_LOCK_DRIVER 0x0d417340

#define	QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */

#define	QLA82XX_PCI_CRB_WINDOW(A)

#define	QLA82XX_CRB_C2C_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)

#define	QLA82XX_CRB_C2C_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)

#define	QLA82XX_CRB_C2C_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)

#define	QLA82XX_CRB_CAM QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)

#define	QLA82XX_CRB_CASPER QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)

#define	QLA82XX_CRB_CASPER_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)

#define	QLA82XX_CRB_CASPER_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)

#define	QLA82XX_CRB_CASPER_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)

#define	QLA82XX_CRB_DDR_MD QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)

#define	QLA82XX_CRB_DDR_NET QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)

#define	QLA82XX_CRB_EPG QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)

#define	QLA82XX_CRB_I2Q QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)

#define	QLA82XX_CRB_NIU QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)

#define	QLA82XX_CRB_PCIX_HOST QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)

#define	QLA82XX_CRB_PCIX_HOST2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)

#define	QLA82XX_CRB_PCIX_MD QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)

#define	QLA82XX_CRB_PCIE QLA82XX_CRB_PCIX_MD

#define	QLA82XX_CRB_PCIE2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)

#define	QLA82XX_CRB_PEG_MD_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)

#define	QLA82XX_CRB_PEG_MD_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)

#define	QLA82XX_CRB_PEG_MD_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)

#define	QLA82XX_CRB_PEG_MD_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)

#define	QLA82XX_CRB_PEG_MD_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)

#define	QLA82XX_CRB_PEG_MD_D QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)

#define	QLA82XX_CRB_PEG_MD_I QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)

#define	QLA82XX_CRB_PEG_NET_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)

#define	QLA82XX_CRB_PEG_NET_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)

#define	QLA82XX_CRB_PEG_NET_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)

#define	QLA82XX_CRB_PEG_NET_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)

#define	QLA82XX_CRB_PEG_NET_4 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)

#define	QLA82XX_CRB_PEG_NET_D QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)

#define	QLA82XX_CRB_PEG_NET_I QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)

#define	QLA82XX_CRB_PQM_MD QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)

#define	QLA82XX_CRB_PQM_NET QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)

#define	QLA82XX_CRB_QDR_MD QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)

#define	QLA82XX_CRB_QDR_NET QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)

#define	QLA82XX_CRB_ROMUSB QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)

#define	QLA82XX_CRB_RPMX_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)

#define	QLA82XX_CRB_RPMX_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)

#define	QLA82XX_CRB_RPMX_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)

#define	QLA82XX_CRB_RPMX_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)

#define	QLA82XX_CRB_RPMX_4 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)

#define	QLA82XX_CRB_RPMX_5 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)

#define	QLA82XX_CRB_RPMX_6 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)

#define	QLA82XX_CRB_RPMX_7 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)

#define	QLA82XX_CRB_SQM_MD_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)

#define	QLA82XX_CRB_SQM_MD_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)

#define	QLA82XX_CRB_SQM_MD_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)

#define	QLA82XX_CRB_SQM_MD_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)

#define	QLA82XX_CRB_SQM_NET_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)

#define	QLA82XX_CRB_SQM_NET_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)

#define	QLA82XX_CRB_SQM_NET_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)

#define	QLA82XX_CRB_SQM_NET_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)

#define	QLA82XX_CRB_SRE QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)

#define	QLA82XX_CRB_TIMER QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)

#define	QLA82XX_CRB_XDMA QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)

#define	QLA82XX_CRB_I2C0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)

#define	QLA82XX_CRB_I2C1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)

#define	QLA82XX_CRB_OCM0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)

#define	QLA82XX_CRB_SMB QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)

#define	QLA82XX_CRB_MAX QLA82XX_PCI_CRB_WINDOW(64)

#define	QLA8XXX_ADDR_DDR_NET (0x0000000000000000ULL)

#define	QLA8XXX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)

#define	QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)

#define	QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)

#define	QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)

#define	QLA8XXX_ADDR_OCM0 (0x0000000200000000ULL)

#define	QLA8XXX_ADDR_OCM0_MAX (0x00000002000fffffULL)

#define	QLA8XXX_ADDR_OCM1 (0x0000000200400000ULL)

#define	QLA8XXX_ADDR_OCM1_MAX (0x00000002004fffffULL)

#define	QLA8XXX_ADDR_QDR_NET (0x0000000300000000ULL)

#define	QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)

#define	QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)

#define	QLA8XXX_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)

#define	QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000

#define	QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000

#define	QLA82XX_PCI_CAMQM (unsigned long)0x04800000

#define	QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff

#define	QLA82XX_PCI_DDR_NET (unsigned long)0x00000000

#define	QLA82XX_PCI_QDR_NET (unsigned long)0x04000000

#define	QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff

#define	QLA8XXX_ADDR_IN_RANGE(addr, low, high) (((addr) <= (high)) && ((addr) >= (low)))

#define	MIU_CONTROL (0x000)

#define	MIU_TAG (0x004)

#define	MIU_TEST_AGT_CTRL (0x090)

#define	MIU_TEST_AGT_ADDR_LO (0x094)

#define	MIU_TEST_AGT_ADDR_HI (0x098)

#define	MIU_TEST_AGT_WRDATA_LO (0x0a0)

#define	MIU_TEST_AGT_WRDATA_HI (0x0a4)

#define	MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))

#define	MIU_TEST_AGT_RDDATA_LO (0x0a8)

#define	MIU_TEST_AGT_RDDATA_HI (0x0ac)

#define	MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))

#define	MIU_TEST_AGT_ADDR_MASK 0xfffffff8

#define	MIU_TEST_AGT_UPPER_ADDR(off) (0)

#define	MIU_TA_CTL_START 1

#define	MIU_TA_CTL_ENABLE 2

#define	MIU_TA_CTL_WRITE 4

#define	MIU_TA_CTL_BUSY 8

#define	MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE \| MIU_TA_CTL_ENABLE)

#define	MIU_TA_CTL_WRITE_START

#define	MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START \| MIU_TA_CTL_ENABLE)

#define	QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)

#define	QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg))

#define	QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))

#define	QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))

#define	QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))

#define	QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))

#define	QLA82XX_CAM_RAM_DB1 (QLA82XX_CAM_RAM(0x1b0))

#define	QLA82XX_CAM_RAM_DB2 (QLA82XX_CAM_RAM(0x1b4))

#define	HALT_STATUS_UNRECOVERABLE 0x80000000

#define	HALT_STATUS_RECOVERABLE 0x40000000

#define	QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))

#define	QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))

#define	QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))

#define	QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))

#define	QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))

#define	QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg))

#define	QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))

#define	QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))

#define	QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))

#define	QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))

#define	QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))

#define	QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))

#define	QLA8XXX_DEV_COLD 1

#define	QLA8XXX_DEV_INITIALIZING 2

#define	QLA8XXX_DEV_READY 3

#define	QLA8XXX_DEV_NEED_RESET 4

#define	QLA8XXX_DEV_NEED_QUIESCENT 5

#define	QLA8XXX_DEV_FAILED 6

#define	QLA8XXX_DEV_QUIESCENT 7

#define	MAX_STATES 8 /* Increment if new state added */

#define	QLA82XX_IDC_VERSION 0x1

#define	ROM_DEV_INIT_TIMEOUT 30

#define	ROM_DRV_RESET_ACK_TIMEOUT 10

#define	PCIE_SETUP_FUNCTION (0x12040)

#define	PCIE_SETUP_FUNCTION2 (0x12048)

#define	QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg))

#define	QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg))

#define	PCIE_SEM2_LOCK (0x1c010) /* Flash lock */

#define	PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */

#define	PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */

#define	PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */

#define	PCIE_SEM7_LOCK (0x1c038) /* crb win lock */

#define	PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/

#define	QLA82XX_MSIX_TBL_SPACE 8192

#define	QLA82XX_PCI_REG_MSIX_TBL 0x44

#define	QLA82XX_PCI_MSIX_CONTROL 0x40

#define	ADDR_ERROR ((unsigned long) 0xffffffff)

#define	MAX_CTL_CHECK 1000

#define	QLA82XX_FWERROR_CODE(code) ((code >> 8) & 0x1fffff)

#define	PCIX_TARGET_STATUS (0x10118)

#define	PCIX_TARGET_STATUS_F1 (0x10160)

#define	PCIX_TARGET_STATUS_F2 (0x10164)

#define	PCIX_TARGET_STATUS_F3 (0x10168)

#define	PCIX_TARGET_STATUS_F4 (0x10360)

#define	PCIX_TARGET_STATUS_F5 (0x10364)

#define	PCIX_TARGET_STATUS_F6 (0x10368)

#define	PCIX_TARGET_STATUS_F7 (0x1036c)

#define	PCIX_TARGET_MASK (0x10128)

#define	PCIX_TARGET_MASK_F1 (0x10170)

#define	PCIX_TARGET_MASK_F2 (0x10174)

#define	PCIX_TARGET_MASK_F3 (0x10178)

#define	PCIX_TARGET_MASK_F4 (0x10370)

#define	PCIX_TARGET_MASK_F5 (0x10374)

#define	PCIX_TARGET_MASK_F6 (0x10378)

#define	PCIX_TARGET_MASK_F7 (0x1037c)

#define	PCIX_MSI_F0 (0x13000)

#define	PCIX_MSI_F1 (0x13004)

#define	PCIX_MSI_F2 (0x13008)

#define	PCIX_MSI_F3 (0x1300c)

#define	PCIX_MSI_F4 (0x13010)

#define	PCIX_MSI_F5 (0x13014)

#define	PCIX_MSI_F6 (0x13018)

#define	PCIX_MSI_F7 (0x1301c)

#define	PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))

#define	PCIX_INT_VECTOR (0x10100)

#define	PCIX_INT_MASK (0x10104)

#define	PCIE_MISCCFG_RC (0x1206c)

#define	ISR_INT_TARGET_STATUS (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))

#define	ISR_INT_TARGET_STATUS_F1 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))

#define	ISR_INT_TARGET_STATUS_F2 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))

#define	ISR_INT_TARGET_STATUS_F3 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))

#define	ISR_INT_TARGET_STATUS_F4 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))

#define	ISR_INT_TARGET_STATUS_F5 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))

#define	ISR_INT_TARGET_STATUS_F6 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))

#define	ISR_INT_TARGET_STATUS_F7 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))

#define	ISR_INT_TARGET_MASK (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))

#define	ISR_INT_TARGET_MASK_F1 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))

#define	ISR_INT_TARGET_MASK_F2 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))

#define	ISR_INT_TARGET_MASK_F3 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))

#define	ISR_INT_TARGET_MASK_F4 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))

#define	ISR_INT_TARGET_MASK_F5 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))

#define	ISR_INT_TARGET_MASK_F6 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))

#define	ISR_INT_TARGET_MASK_F7 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))

#define	ISR_INT_VECTOR (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))

#define	ISR_INT_MASK (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))

#define	ISR_INT_STATE_REG (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))

#define	ISR_MSI_INT_TRIGGER(FUNC) (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))

#define	ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)

#define	ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)

#define	PCIX_INT_VECTOR_BIT_F0 0x0080

#define	PCIX_INT_VECTOR_BIT_F1 0x0100

#define	PCIX_INT_VECTOR_BIT_F2 0x0200

#define	PCIX_INT_VECTOR_BIT_F3 0x0400

#define	PCIX_INT_VECTOR_BIT_F4 0x0800

#define	PCIX_INT_VECTOR_BIT_F5 0x1000

#define	PCIX_INT_VECTOR_BIT_F6 0x2000

#define	PCIX_INT_VECTOR_BIT_F7 0x4000

#define	QLA82XX_LEGACY_INTR_CONFIG

#define	QLA82XX_BDINFO_MAGIC 0x12345678

#define	FW_SIZE_OFFSET (0x3e840c)

#define	MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)

#define	MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)

#define	QLA8XXX_RDNOP 0

#define	QLA8XXX_RDCRB 1

#define	QLA8XXX_RDMUX 2

#define	QLA8XXX_QUEUE 3

#define	QLA8XXX_BOARD 4

#define	QLA8XXX_RDOCM 6

#define	QLA8XXX_PREGS 7

#define	QLA8XXX_L1DTG 8

#define	QLA8XXX_L1ITG 9

#define	QLA8XXX_L1DAT 11

#define	QLA8XXX_L1INS 12

#define	QLA8XXX_L2DTG 21

#define	QLA8XXX_L2ITG 22

#define	QLA8XXX_L2DAT 23

#define	QLA8XXX_L2INS 24

#define	QLA83XX_POLLRD 35

#define	QLA83XX_RDMUX2 36

#define	QLA83XX_POLLRDMWR 37

#define	QLA8XXX_RDROM 71

#define	QLA8XXX_RDMEM 72

#define	QLA8XXX_CNTRL 98

#define	QLA83XX_TLHDR 99

#define	QLA8XXX_RDEND 255

#define	QLA8XXX_DBG_OPCODE_WR 0x01

#define	QLA8XXX_DBG_OPCODE_RW 0x02

#define	QLA8XXX_DBG_OPCODE_AND 0x04

#define	QLA8XXX_DBG_OPCODE_OR 0x08

#define	QLA8XXX_DBG_OPCODE_POLL 0x10

#define	QLA8XXX_DBG_OPCODE_RDSTATE 0x20

#define	QLA8XXX_DBG_OPCODE_WRSTATE 0x40

#define	QLA8XXX_DBG_OPCODE_MDSTATE 0x80

#define	QLA8XXX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */

#define	QLA8XXX_DBG_SIZE_ERR_FLAG

#define	MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129

#define	RQST_TMPLT_SIZE 0x0

#define	RQST_TMPLT 0x1

#define	MD_DIRECT_ROM_WINDOW 0x42110030

#define	MD_DIRECT_ROM_READ_BASE 0x42150000

#define	MD_MIU_TEST_AGT_CTRL 0x41000090

#define	MD_MIU_TEST_AGT_ADDR_LO 0x41000094

#define	MD_MIU_TEST_AGT_ADDR_HI 0x41000098

#define	MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0

#define	MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4

#define	MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0

#define	MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4

#define	MD_MIU_TEST_AGT_RDDATA_LO 0x410000A8

#define	MD_MIU_TEST_AGT_RDDATA_HI 0x410000AC

#define	MD_MIU_TEST_AGT_RDDATA_ULO 0x410000B8

#define	MD_MIU_TEST_AGT_RDDATA_UHI 0x410000BC

Enumerations
enum	{ QLA82XX_TEMP_NORMAL = 0x1, QLA82XX_TEMP_WARN, QLA82XX_TEMP_PANIC }

enum	qla_regs { QLA8XXX_PEG_HALT_STATUS1 = 0, QLA8XXX_PEG_HALT_STATUS2, QLA8XXX_PEG_ALIVE_COUNTER, QLA8XXX_CRB_DRV_ACTIVE, QLA8XXX_CRB_DEV_STATE, QLA8XXX_CRB_DRV_STATE, QLA8XXX_CRB_DRV_SCRATCH, QLA8XXX_CRB_DEV_PART_INFO, QLA8XXX_CRB_DRV_IDC_VERSION, QLA8XXX_FW_VERSION_MAJOR, QLA8XXX_FW_VERSION_MINOR, QLA8XXX_FW_VERSION_SUB, QLA8XXX_CRB_CMDPEG_STATE, QLA8XXX_CRB_TEMP_STATE }

Macro Definition Documentation

#define ADDR_ERROR ((unsigned long) 0xffffffff)

Definition at line 669 of file ql4_nx.h.

#define CRB_CMDPEG_CHECK_DELAY 500

Definition at line 29 of file ql4_nx.h.

#define CRB_CMDPEG_CHECK_RETRY_COUNT 60

Definition at line 28 of file ql4_nx.h.

#define CRB_CMDPEG_STATE QLA82XX_REG(0x50)

Definition at line 24 of file ql4_nx.h.

#define CRB_DMA_SHIFT QLA82XX_REG(0xcc)

Definition at line 26 of file ql4_nx.h.

#define CRB_NIU_XG_PAUSE_CTL_P0 0x1

Definition at line 44 of file ql4_nx.h.

#define CRB_NIU_XG_PAUSE_CTL_P1 0x8

Definition at line 45 of file ql4_nx.h.

#define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)

Definition at line 25 of file ql4_nx.h.

#define CRB_TEMP_STATE QLA82XX_REG(0x1b4)

Definition at line 27 of file ql4_nx.h.

#define FW_SIZE_OFFSET (0x3e840c)

Definition at line 834 of file ql4_nx.h.

#define HALT_STATUS_RECOVERABLE 0x40000000

Definition at line 567 of file ql4_nx.h.

#define HALT_STATUS_UNRECOVERABLE 0x80000000

Definition at line 566 of file ql4_nx.h.

#define ISR_INT_MASK (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))

Definition at line 758 of file ql4_nx.h.

#define ISR_INT_STATE_REG (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))

Definition at line 759 of file ql4_nx.h.

#define ISR_INT_TARGET_MASK (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))

Definition at line 740 of file ql4_nx.h.

#define ISR_INT_TARGET_MASK_F1 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))

Definition at line 742 of file ql4_nx.h.

#define ISR_INT_TARGET_MASK_F2 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))

Definition at line 744 of file ql4_nx.h.

#define ISR_INT_TARGET_MASK_F3 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))

Definition at line 746 of file ql4_nx.h.

#define ISR_INT_TARGET_MASK_F4 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))

Definition at line 748 of file ql4_nx.h.

#define ISR_INT_TARGET_MASK_F5 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))

Definition at line 750 of file ql4_nx.h.

#define ISR_INT_TARGET_MASK_F6 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))

Definition at line 752 of file ql4_nx.h.

#define ISR_INT_TARGET_MASK_F7 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))

Definition at line 754 of file ql4_nx.h.

#define ISR_INT_TARGET_STATUS (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))

Definition at line 723 of file ql4_nx.h.

#define ISR_INT_TARGET_STATUS_F1 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))

Definition at line 725 of file ql4_nx.h.

#define ISR_INT_TARGET_STATUS_F2 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))

Definition at line 727 of file ql4_nx.h.

#define ISR_INT_TARGET_STATUS_F3 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))

Definition at line 729 of file ql4_nx.h.

#define ISR_INT_TARGET_STATUS_F4 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))

Definition at line 731 of file ql4_nx.h.

#define ISR_INT_TARGET_STATUS_F5 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))

Definition at line 733 of file ql4_nx.h.

#define ISR_INT_TARGET_STATUS_F6 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))

Definition at line 735 of file ql4_nx.h.

#define ISR_INT_TARGET_STATUS_F7 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))

Definition at line 737 of file ql4_nx.h.

#define ISR_INT_VECTOR (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))

Definition at line 757 of file ql4_nx.h.

#define ISR_IS_LEGACY_INTR_IDLE ( VAL ) (((VAL) & 0x300) == 0)

Definition at line 764 of file ql4_nx.h.

#define ISR_IS_LEGACY_INTR_TRIGGERED ( VAL ) (((VAL) & 0x300) == 0x200)

Definition at line 765 of file ql4_nx.h.

#define ISR_MSI_INT_TRIGGER ( FUNC ) (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))

Definition at line 761 of file ql4_nx.h.

#define MAX_CTL_CHECK 1000

Definition at line 670 of file ql4_nx.h.

#define MAX_STATES 8 /* Increment if new state added */

Definition at line 627 of file ql4_nx.h.

#define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129

Definition at line 1007 of file ql4_nx.h.

#define MD_DIRECT_ROM_READ_BASE 0x42150000

Definition at line 1011 of file ql4_nx.h.

#define MD_DIRECT_ROM_WINDOW 0x42110030

Definition at line 1010 of file ql4_nx.h.

#define MD_MIU_TEST_AGT_ADDR_HI 0x41000098

Definition at line 1014 of file ql4_nx.h.

#define MD_MIU_TEST_AGT_ADDR_LO 0x41000094

Definition at line 1013 of file ql4_nx.h.

#define MD_MIU_TEST_AGT_CTRL 0x41000090

Definition at line 1012 of file ql4_nx.h.

#define MD_MIU_TEST_AGT_RDDATA_HI 0x410000AC

Definition at line 1022 of file ql4_nx.h.

#define MD_MIU_TEST_AGT_RDDATA_LO 0x410000A8

Definition at line 1021 of file ql4_nx.h.

#define MD_MIU_TEST_AGT_RDDATA_UHI 0x410000BC

Definition at line 1024 of file ql4_nx.h.

#define MD_MIU_TEST_AGT_RDDATA_ULO 0x410000B8

Definition at line 1023 of file ql4_nx.h.

#define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4

Definition at line 1017 of file ql4_nx.h.

#define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0

Definition at line 1016 of file ql4_nx.h.

#define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4

Definition at line 1019 of file ql4_nx.h.

#define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0

Definition at line 1018 of file ql4_nx.h.

#define MIU_CONTROL (0x000)

Definition at line 530 of file ql4_nx.h.

#define MIU_TA_CTL_BUSY 8

Definition at line 548 of file ql4_nx.h.

#define MIU_TA_CTL_ENABLE 2

Definition at line 546 of file ql4_nx.h.

#define MIU_TA_CTL_START 1

Definition at line 545 of file ql4_nx.h.

#define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)

Definition at line 553 of file ql4_nx.h.

#define MIU_TA_CTL_WRITE 4

Definition at line 547 of file ql4_nx.h.

#define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)

Definition at line 550 of file ql4_nx.h.

#define MIU_TA_CTL_WRITE_START

Value:

(MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE |\

MIU_TA_CTL_START)

Definition at line 551 of file ql4_nx.h.

#define MIU_TAG (0x004)

Definition at line 531 of file ql4_nx.h.

#define MIU_TEST_AGT_ADDR_HI (0x098)

Definition at line 534 of file ql4_nx.h.

#define MIU_TEST_AGT_ADDR_LO (0x094)

Definition at line 533 of file ql4_nx.h.

#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8

Definition at line 541 of file ql4_nx.h.

#define MIU_TEST_AGT_CTRL (0x090)

Definition at line 532 of file ql4_nx.h.

#define MIU_TEST_AGT_RDDATA ( i ) (0x0a8+(4*(i)))

Definition at line 540 of file ql4_nx.h.

#define MIU_TEST_AGT_RDDATA_HI (0x0ac)

Definition at line 539 of file ql4_nx.h.

#define MIU_TEST_AGT_RDDATA_LO (0x0a8)

Definition at line 538 of file ql4_nx.h.

#define MIU_TEST_AGT_UPPER_ADDR ( off ) (0)

Definition at line 542 of file ql4_nx.h.

#define MIU_TEST_AGT_WRDATA ( i ) (0x0a0+(4*(i)))

Definition at line 537 of file ql4_nx.h.

#define MIU_TEST_AGT_WRDATA_HI (0x0a4)

Definition at line 536 of file ql4_nx.h.

#define MIU_TEST_AGT_WRDATA_LO (0x0a0)

Definition at line 535 of file ql4_nx.h.

#define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)

Definition at line 838 of file ql4_nx.h.

#define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)

Definition at line 837 of file ql4_nx.h.

#define PCIE_MISCCFG_RC (0x1206c)

Definition at line 720 of file ql4_nx.h.

#define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */

Definition at line 639 of file ql4_nx.h.

#define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */

Definition at line 640 of file ql4_nx.h.

#define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */

Definition at line 641 of file ql4_nx.h.

#define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */

Definition at line 642 of file ql4_nx.h.

#define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */

Definition at line 643 of file ql4_nx.h.

#define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/

Definition at line 644 of file ql4_nx.h.

#define PCIE_SETUP_FUNCTION (0x12040)

Definition at line 633 of file ql4_nx.h.

#define PCIE_SETUP_FUNCTION2 (0x12048)

Definition at line 634 of file ql4_nx.h.

#define PCIX_INT_MASK (0x10104)

Definition at line 715 of file ql4_nx.h.

#define PCIX_INT_VECTOR (0x10100)

Definition at line 714 of file ql4_nx.h.

#define PCIX_INT_VECTOR_BIT_F0 0x0080

Definition at line 770 of file ql4_nx.h.

#define PCIX_INT_VECTOR_BIT_F1 0x0100

Definition at line 771 of file ql4_nx.h.

#define PCIX_INT_VECTOR_BIT_F2 0x0200

Definition at line 772 of file ql4_nx.h.

#define PCIX_INT_VECTOR_BIT_F3 0x0400

Definition at line 773 of file ql4_nx.h.

#define PCIX_INT_VECTOR_BIT_F4 0x0800

Definition at line 774 of file ql4_nx.h.

#define PCIX_INT_VECTOR_BIT_F5 0x1000

Definition at line 775 of file ql4_nx.h.

#define PCIX_INT_VECTOR_BIT_F6 0x2000

Definition at line 776 of file ql4_nx.h.

#define PCIX_INT_VECTOR_BIT_F7 0x4000

Definition at line 777 of file ql4_nx.h.

#define PCIX_MSI_F ( FUNC ) (0x13000 + ((FUNC) * 4))

Definition at line 709 of file ql4_nx.h.

#define PCIX_MSI_F0 (0x13000)

Definition at line 701 of file ql4_nx.h.

#define PCIX_MSI_F1 (0x13004)

Definition at line 702 of file ql4_nx.h.

#define PCIX_MSI_F2 (0x13008)

Definition at line 703 of file ql4_nx.h.

#define PCIX_MSI_F3 (0x1300c)

Definition at line 704 of file ql4_nx.h.

#define PCIX_MSI_F4 (0x13010)

Definition at line 705 of file ql4_nx.h.

#define PCIX_MSI_F5 (0x13014)

Definition at line 706 of file ql4_nx.h.

#define PCIX_MSI_F6 (0x13018)

Definition at line 707 of file ql4_nx.h.

#define PCIX_MSI_F7 (0x1301c)

Definition at line 708 of file ql4_nx.h.

#define PCIX_TARGET_MASK (0x10128)

Definition at line 689 of file ql4_nx.h.

#define PCIX_TARGET_MASK_F1 (0x10170)

Definition at line 690 of file ql4_nx.h.

#define PCIX_TARGET_MASK_F2 (0x10174)

Definition at line 691 of file ql4_nx.h.

#define PCIX_TARGET_MASK_F3 (0x10178)

Definition at line 692 of file ql4_nx.h.

#define PCIX_TARGET_MASK_F4 (0x10370)

Definition at line 693 of file ql4_nx.h.

#define PCIX_TARGET_MASK_F5 (0x10374)

Definition at line 694 of file ql4_nx.h.

#define PCIX_TARGET_MASK_F6 (0x10378)

Definition at line 695 of file ql4_nx.h.

#define PCIX_TARGET_MASK_F7 (0x1037c)

Definition at line 696 of file ql4_nx.h.

#define PCIX_TARGET_STATUS (0x10118)

Definition at line 680 of file ql4_nx.h.

#define PCIX_TARGET_STATUS_F1 (0x10160)

Definition at line 681 of file ql4_nx.h.

#define PCIX_TARGET_STATUS_F2 (0x10164)

Definition at line 682 of file ql4_nx.h.

#define PCIX_TARGET_STATUS_F3 (0x10168)

Definition at line 683 of file ql4_nx.h.

#define PCIX_TARGET_STATUS_F4 (0x10360)

Definition at line 684 of file ql4_nx.h.

#define PCIX_TARGET_STATUS_F5 (0x10364)

Definition at line 685 of file ql4_nx.h.

#define PCIX_TARGET_STATUS_F6 (0x10368)

Definition at line 686 of file ql4_nx.h.

#define PCIX_TARGET_STATUS_F7 (0x1036c)

Definition at line 687 of file ql4_nx.h.

#define PHAN_INITIALIZE_ACK 0xf00f

Definition at line 18 of file ql4_nx.h.

#define PHAN_INITIALIZE_COMPLETE 0xff01

Definition at line 15 of file ql4_nx.h.

#define PHAN_INITIALIZE_FAILED 0xffff

Definition at line 14 of file ql4_nx.h.

#define PHAN_PEG_RCV_INITIALIZED 0xff01

Definition at line 19 of file ql4_nx.h.

#define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)

Definition at line 504 of file ql4_nx.h.

#define QLA82XX_BDINFO_MAGIC 0x12345678

Definition at line 833 of file ql4_nx.h.

#define QLA82XX_CAM_RAM ( reg ) (QLA82XX_CAM_RAM_BASE + (reg))

Definition at line 557 of file ql4_nx.h.

#define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)

Definition at line 556 of file ql4_nx.h.

#define QLA82XX_CAM_RAM_DB1 (QLA82XX_CAM_RAM(0x1b0))

Definition at line 563 of file ql4_nx.h.

#define QLA82XX_CAM_RAM_DB2 (QLA82XX_CAM_RAM(0x1b4))

Definition at line 564 of file ql4_nx.h.

#define QLA82XX_CRB_BASE (QLA82XX_CAM_RAM(0x200))

Definition at line 22 of file ql4_nx.h.

#define QLA82XX_CRB_C2C_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)

Definition at line 365 of file ql4_nx.h.

#define QLA82XX_CRB_C2C_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)

Definition at line 367 of file ql4_nx.h.

#define QLA82XX_CRB_C2C_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)

Definition at line 369 of file ql4_nx.h.

#define QLA82XX_CRB_CAM QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)

Definition at line 371 of file ql4_nx.h.

#define QLA82XX_CRB_CASPER QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)

Definition at line 373 of file ql4_nx.h.

#define QLA82XX_CRB_CASPER_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)

Definition at line 375 of file ql4_nx.h.

#define QLA82XX_CRB_CASPER_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)

Definition at line 377 of file ql4_nx.h.

#define QLA82XX_CRB_CASPER_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)

Definition at line 379 of file ql4_nx.h.

#define QLA82XX_CRB_DDR_MD QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)

Definition at line 381 of file ql4_nx.h.

#define QLA82XX_CRB_DDR_NET QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)

Definition at line 383 of file ql4_nx.h.

#define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))

Definition at line 582 of file ql4_nx.h.

#define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))

Definition at line 579 of file ql4_nx.h.

#define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))

Definition at line 578 of file ql4_nx.h.

#define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))

Definition at line 583 of file ql4_nx.h.

#define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))

Definition at line 581 of file ql4_nx.h.

#define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))

Definition at line 580 of file ql4_nx.h.

#define QLA82XX_CRB_EPG QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)

Definition at line 385 of file ql4_nx.h.

#define QLA82XX_CRB_I2C0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)

Definition at line 479 of file ql4_nx.h.

#define QLA82XX_CRB_I2C1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)

Definition at line 481 of file ql4_nx.h.

#define QLA82XX_CRB_I2Q QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)

Definition at line 387 of file ql4_nx.h.

#define QLA82XX_CRB_MAX QLA82XX_PCI_CRB_WINDOW(64)

Definition at line 488 of file ql4_nx.h.

#define QLA82XX_CRB_NIU QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)

Definition at line 389 of file ql4_nx.h.

#define QLA82XX_CRB_OCM0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)

Definition at line 483 of file ql4_nx.h.

#define QLA82XX_CRB_PCIE QLA82XX_CRB_PCIX_MD

Definition at line 398 of file ql4_nx.h.

#define QLA82XX_CRB_PCIE2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)

Definition at line 400 of file ql4_nx.h.

#define QLA82XX_CRB_PCIX_HOST QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)

Definition at line 392 of file ql4_nx.h.

#define QLA82XX_CRB_PCIX_HOST2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)

Definition at line 394 of file ql4_nx.h.

#define QLA82XX_CRB_PCIX_MD QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)

Definition at line 396 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_MD_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)

Definition at line 403 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_MD_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)

Definition at line 405 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_MD_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)

Definition at line 407 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_MD_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)

Definition at line 411 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_MD_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)

Definition at line 411 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_MD_D QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)

Definition at line 413 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_MD_I QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)

Definition at line 415 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_NET_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)

Definition at line 417 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_NET_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)

Definition at line 419 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_NET_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)

Definition at line 421 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_NET_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)

Definition at line 423 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_NET_4 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)

Definition at line 425 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_NET_D QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)

Definition at line 427 of file ql4_nx.h.

#define QLA82XX_CRB_PEG_NET_I QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)

Definition at line 429 of file ql4_nx.h.

#define QLA82XX_CRB_PQM_MD QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)

Definition at line 431 of file ql4_nx.h.

#define QLA82XX_CRB_PQM_NET QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)

Definition at line 433 of file ql4_nx.h.

#define QLA82XX_CRB_QDR_MD QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)

Definition at line 435 of file ql4_nx.h.

#define QLA82XX_CRB_QDR_NET QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)

Definition at line 437 of file ql4_nx.h.

#define QLA82XX_CRB_ROMUSB QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)

Definition at line 439 of file ql4_nx.h.

#define QLA82XX_CRB_RPMX_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)

Definition at line 441 of file ql4_nx.h.

#define QLA82XX_CRB_RPMX_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)

Definition at line 443 of file ql4_nx.h.

#define QLA82XX_CRB_RPMX_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)

Definition at line 445 of file ql4_nx.h.

#define QLA82XX_CRB_RPMX_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)

Definition at line 447 of file ql4_nx.h.

#define QLA82XX_CRB_RPMX_4 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)

Definition at line 449 of file ql4_nx.h.

#define QLA82XX_CRB_RPMX_5 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)

Definition at line 451 of file ql4_nx.h.

#define QLA82XX_CRB_RPMX_6 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)

Definition at line 453 of file ql4_nx.h.

#define QLA82XX_CRB_RPMX_7 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)

Definition at line 455 of file ql4_nx.h.

#define QLA82XX_CRB_SMB QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)

Definition at line 485 of file ql4_nx.h.

#define QLA82XX_CRB_SQM_MD_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)

Definition at line 457 of file ql4_nx.h.

#define QLA82XX_CRB_SQM_MD_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)

Definition at line 459 of file ql4_nx.h.

#define QLA82XX_CRB_SQM_MD_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)

Definition at line 461 of file ql4_nx.h.

#define QLA82XX_CRB_SQM_MD_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)

Definition at line 463 of file ql4_nx.h.

#define QLA82XX_CRB_SQM_NET_0 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)

Definition at line 465 of file ql4_nx.h.

#define QLA82XX_CRB_SQM_NET_1 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)

Definition at line 467 of file ql4_nx.h.

#define QLA82XX_CRB_SQM_NET_2 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)

Definition at line 469 of file ql4_nx.h.

#define QLA82XX_CRB_SQM_NET_3 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)

Definition at line 471 of file ql4_nx.h.

#define QLA82XX_CRB_SRE QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)

Definition at line 473 of file ql4_nx.h.

#define QLA82XX_CRB_TIMER QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)

Definition at line 475 of file ql4_nx.h.

#define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))

Definition at line 571 of file ql4_nx.h.

#define QLA82XX_CRB_XDMA QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)

Definition at line 477 of file ql4_nx.h.

#define qla82xx_encode_temp	(	val,
		state
	)	(((val) << 16) \| (state))

Definition at line 33 of file ql4_nx.h.

#define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))

Definition at line 572 of file ql4_nx.h.

#define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))

Definition at line 573 of file ql4_nx.h.

#define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))

Definition at line 574 of file ql4_nx.h.

#define QLA82XX_FWERROR_CODE ( code ) ((code >> 8) & 0x1fffff)

Definition at line 671 of file ql4_nx.h.

#define qla82xx_get_temp_state ( x ) ((x) & 0xffff)

Definition at line 32 of file ql4_nx.h.

#define qla82xx_get_temp_val ( x ) ((x) >> 16)

Definition at line 31 of file ql4_nx.h.

#define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58

Definition at line 67 of file ql4_nx.h.

#define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59

Definition at line 68 of file ql4_nx.h.

#define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a

Definition at line 69 of file ql4_nx.h.

#define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46

Definition at line 126 of file ql4_nx.h.

#define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47

Definition at line 127 of file ql4_nx.h.

#define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48

Definition at line 128 of file ql4_nx.h.

#define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49

Definition at line 129 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_C2C0_CRB_AGT_ADR)

Definition at line 229 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_C2C1_CRB_AGT_ADR)

Definition at line 231 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM

Value:

((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \

QLA82XX_HW_NCM_CRB_AGT_ADR)

Definition at line 325 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_CAS0_CRB_AGT_ADR)

Definition at line 275 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_CAS1_CRB_AGT_ADR)

Definition at line 277 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_CAS2_CRB_AGT_ADR)

Definition at line 279 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_CAS3_CRB_AGT_ADR)

Definition at line 281 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_EG

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_EG_CRB_AGT_ADR)

Definition at line 253 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0

Value:

((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \

QLA82XX_HW_I2C0_CRB_AGT_ADR)

Definition at line 246 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1

Value:

((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \

QLA82XX_HW_I2C1_CRB_AGT_ADR)

Definition at line 248 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q

Value:

((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \

QLA82XX_HW_I2Q_CRB_AGT_ADR)

Definition at line 333 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC

Value:

((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \

QLA82XX_HW_LPC_CRB_AGT_ADR)

Definition at line 341 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_MN

Value:

((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \

QLA82XX_HW_MN_CRB_AGT_ADR)

Definition at line 207 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_MS

Value:

((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \

QLA82XX_HW_MS_CRB_AGT_ADR)

Definition at line 211 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU

Value:

((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \

QLA82XX_HW_NIU_CRB_AGT_ADR)

Definition at line 244 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0

Value:

((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \

QLA82XX_HW_OCM0_CRB_AGT_ADR)

Definition at line 337 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1

Value:

((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \

QLA82XX_HW_OCM1_CRB_AGT_ADR)

Definition at line 339 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGN0_CRB_AGT_ADR)

Definition at line 288 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGN1_CRB_AGT_ADR)

Definition at line 290 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGN2_CRB_AGT_ADR)

Definition at line 292 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGN3_CRB_AGT_ADR)

Definition at line 294 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGN4_CRB_AGT_ADR)

Definition at line 296 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGNC_CRB_AGT_ADR)

Definition at line 299 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGND_CRB_AGT_ADR)

Definition at line 286 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGNI_CRB_AGT_ADR)

Definition at line 284 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGR0_CRB_AGT_ADR)

Definition at line 301 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGR1_CRB_AGT_ADR)

Definition at line 303 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGR2_CRB_AGT_ADR)

Definition at line 305 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3

Value:

((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGR3_CRB_AGT_ADR)

Definition at line 307 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0

Value:

((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGS0_CRB_AGT_ADR)

Definition at line 314 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1

Value:

((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGS1_CRB_AGT_ADR)

Definition at line 316 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2

Value:

((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGS2_CRB_AGT_ADR)

Definition at line 318 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3

Value:

((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGS3_CRB_AGT_ADR)

Definition at line 320 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC

Value:

((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGSC_CRB_AGT_ADR)

Definition at line 322 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD

Value:

((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGSD_CRB_AGT_ADR)

Definition at line 312 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI

Value:

((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \

QLA82XX_HW_PEGSI_CRB_AGT_ADR)

Definition at line 310 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PH

Value:

((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \

QLA82XX_HW_PH_CRB_AGT_ADR)

Definition at line 209 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_PS

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_PS_CRB_AGT_ADR)

Definition at line 213 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_QM_CRB_AGT_ADR)

Definition at line 257 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_QMS_CRB_AGT_ADR)

Definition at line 219 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB

Value:

((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \

QLA82XX_HW_ROMUSB_CRB_AGT_ADR)

Definition at line 335 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_RPMX0_CRB_AGT_ADR)

Definition at line 255 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_RPMX1_CRB_AGT_ADR)

Definition at line 267 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_RPMX2_CRB_AGT_ADR)

Definition at line 233 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_RPMX3_CRB_AGT_ADR)

Definition at line 217 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_RPMX4_CRB_AGT_ADR)

Definition at line 235 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_RPMX5_CRB_AGT_ADR)

Definition at line 269 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_RPMX6_CRB_AGT_ADR)

Definition at line 271 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_RPMX7_CRB_AGT_ADR)

Definition at line 237 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_RPMX8_CRB_AGT_ADR)

Definition at line 273 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_RPMX9_CRB_AGT_ADR)

Definition at line 239 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_SMB_CRB_AGT_ADR)

Definition at line 241 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SN

Value:

((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \

QLA82XX_HW_SN_CRB_AGT_ADR)

Definition at line 331 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_SQG0_CRB_AGT_ADR)

Definition at line 259 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_SQG1_CRB_AGT_ADR)

Definition at line 261 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_SQG2_CRB_AGT_ADR)

Definition at line 263 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_SQG3_CRB_AGT_ADR)

Definition at line 265 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_SQGS0_CRB_AGT_ADR)

Definition at line 221 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_SQGS1_CRB_AGT_ADR)

Definition at line 223 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_SQGS2_CRB_AGT_ADR)

Definition at line 225 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_SQGS3_CRB_AGT_ADR)

Definition at line 227 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE

Value:

((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \

QLA82XX_HW_SRE_CRB_AGT_ADR)

Definition at line 251 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_SS

Value:

((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \

QLA82XX_HW_SS_CRB_AGT_ADR)

Definition at line 215 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR

Value:

((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \

QLA82XX_HW_TMR_CRB_AGT_ADR)

Definition at line 327 of file ql4_nx.h.

#define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA

Value:

((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \

QLA82XX_HW_XDMA_CRB_AGT_ADR)

Definition at line 329 of file ql4_nx.h.

#define QLA82XX_HW_EG_CRB_AGT_ADR 0x51

Definition at line 98 of file ql4_nx.h.

#define QLA82XX_HW_H0_CH_HUB_ADR 0x05

Definition at line 47 of file ql4_nx.h.

#define QLA82XX_HW_H1_CH_HUB_ADR 0x0E

Definition at line 48 of file ql4_nx.h.

#define QLA82XX_HW_H2_CH_HUB_ADR 0x03

Definition at line 49 of file ql4_nx.h.

#define QLA82XX_HW_H3_CH_HUB_ADR 0x01

Definition at line 50 of file ql4_nx.h.

#define QLA82XX_HW_H4_CH_HUB_ADR 0x06

Definition at line 51 of file ql4_nx.h.

#define QLA82XX_HW_H5_CH_HUB_ADR 0x07

Definition at line 52 of file ql4_nx.h.

#define QLA82XX_HW_H6_CH_HUB_ADR 0x08

Definition at line 53 of file ql4_nx.h.

#define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19

Definition at line 78 of file ql4_nx.h.

#define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29

Definition at line 79 of file ql4_nx.h.

#define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20

Definition at line 82 of file ql4_nx.h.

#define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22

Definition at line 83 of file ql4_nx.h.

#define QLA82XX_HW_MN_CRB_AGT_ADR 0x15

Definition at line 56 of file ql4_nx.h.

#define QLA82XX_HW_MS_CRB_AGT_ADR 0x25

Definition at line 57 of file ql4_nx.h.

#define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16

Definition at line 130 of file ql4_nx.h.

#define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31

Definition at line 77 of file ql4_nx.h.

#define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06

Definition at line 133 of file ql4_nx.h.

#define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07

Definition at line 134 of file ql4_nx.h.

#define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40

Definition at line 102 of file ql4_nx.h.

#define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41

Definition at line 103 of file ql4_nx.h.

#define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42

Definition at line 104 of file ql4_nx.h.

#define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43

Definition at line 105 of file ql4_nx.h.

#define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b

Definition at line 113 of file ql4_nx.h.

#define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46

Definition at line 108 of file ql4_nx.h.

#define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45

Definition at line 107 of file ql4_nx.h.

#define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44

Definition at line 106 of file ql4_nx.h.

#define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47

Definition at line 109 of file ql4_nx.h.

#define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48

Definition at line 110 of file ql4_nx.h.

#define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49

Definition at line 111 of file ql4_nx.h.

#define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a

Definition at line 112 of file ql4_nx.h.

#define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40

Definition at line 116 of file ql4_nx.h.

#define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41

Definition at line 117 of file ql4_nx.h.

#define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42

Definition at line 118 of file ql4_nx.h.

#define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43

Definition at line 119 of file ql4_nx.h.

#define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46

Definition at line 123 of file ql4_nx.h.

#define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45

Definition at line 122 of file ql4_nx.h.

#define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44

Definition at line 121 of file ql4_nx.h.

#define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A

Definition at line 96 of file ql4_nx.h.

#define QLA82XX_HW_PS_CRB_AGT_ADR 0x73

Definition at line 60 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_C2C0 38

Definition at line 175 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_C2C1 39

Definition at line 176 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_CAM 34

Definition at line 171 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_CAS0 35

Definition at line 172 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_CAS1 36

Definition at line 173 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_CAS2 37

Definition at line 174 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_CAS3 52

Definition at line 188 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_EG 31

Definition at line 168 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_I2C0 59

Definition at line 195 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_I2C1 60

Definition at line 196 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_I2Q 50

Definition at line 186 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_LPC 61

Definition at line 197 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_MN 2

Definition at line 140 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_MS 3

Definition at line 141 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_NIU 6

Definition at line 143 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_OCM0 56

Definition at line 192 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_OCM1 57

Definition at line 193 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGN0 17

Definition at line 154 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGN1 18

Definition at line 155 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGN2 19

Definition at line 156 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGN3 20

Definition at line 157 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2

Definition at line 158 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGNC 62

Definition at line 198 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGND 21

Definition at line 159 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGNI 22

Definition at line 160 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGR0 63

Definition at line 199 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGR1 4

Definition at line 200 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGR2 30

Definition at line 201 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGR3 41

Definition at line 202 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGS0 23

Definition at line 161 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGS1 24

Definition at line 162 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGS2 25

Definition at line 163 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGS3 26

Definition at line 164 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGSD 27

Definition at line 165 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PGSI 28

Definition at line 166 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PH 0

Definition at line 138 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PH2 32

Definition at line 169 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PS 1

Definition at line 139 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_PS2 33

Definition at line 170 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_QMN 7

Definition at line 144 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_QMS 12

Definition at line 149 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51

Definition at line 187 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_RPMX0 53

Definition at line 189 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_RPMX1 42

Definition at line 178 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_RPMX2 43

Definition at line 179 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_RPMX3 44

Definition at line 180 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_RPMX4 45

Definition at line 181 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_RPMX5 46

Definition at line 182 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_RPMX6 47

Definition at line 183 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_RPMX7 48

Definition at line 184 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_RPMX8 54

Definition at line 190 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_RPMX9 55

Definition at line 191 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_SMB 58

Definition at line 194 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_SN 29

Definition at line 167 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_SQN0 8

Definition at line 145 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_SQN1 9

Definition at line 146 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_SQN2 10

Definition at line 147 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_SQN3 11

Definition at line 148 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_SQS0 13

Definition at line 150 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_SQS1 14

Definition at line 151 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_SQS2 15

Definition at line 152 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_SQS3 16

Definition at line 153 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_SRE 5

Definition at line 142 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_TIMR 40

Definition at line 177 of file ql4_nx.h.

#define QLA82XX_HW_PX_MAP_CRB_XDMA 49

Definition at line 185 of file ql4_nx.h.

#define QLA82XX_HW_QM_CRB_AGT_ADR 0x66

Definition at line 85 of file ql4_nx.h.

#define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00

Definition at line 61 of file ql4_nx.h.

#define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21

Definition at line 84 of file ql4_nx.h.

#define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08

Definition at line 99 of file ql4_nx.h.

#define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09

Definition at line 90 of file ql4_nx.h.

#define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a

Definition at line 70 of file ql4_nx.h.

#define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b

Definition at line 62 of file ql4_nx.h.

#define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c

Definition at line 71 of file ql4_nx.h.

#define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d

Definition at line 91 of file ql4_nx.h.

#define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e

Definition at line 92 of file ql4_nx.h.

#define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f

Definition at line 72 of file ql4_nx.h.

#define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11

Definition at line 93 of file ql4_nx.h.

#define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12

Definition at line 73 of file ql4_nx.h.

#define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18

Definition at line 74 of file ql4_nx.h.

#define QLA82XX_HW_SN_CRB_AGT_ADR 0x10

Definition at line 81 of file ql4_nx.h.

#define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60

Definition at line 86 of file ql4_nx.h.

#define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61

Definition at line 87 of file ql4_nx.h.

#define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62

Definition at line 88 of file ql4_nx.h.

#define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63

Definition at line 89 of file ql4_nx.h.

#define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01

Definition at line 63 of file ql4_nx.h.

#define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02

Definition at line 64 of file ql4_nx.h.

#define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03

Definition at line 65 of file ql4_nx.h.

#define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04

Definition at line 66 of file ql4_nx.h.

#define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50

Definition at line 97 of file ql4_nx.h.

#define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17

Definition at line 131 of file ql4_nx.h.

#define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05

Definition at line 132 of file ql4_nx.h.

#define QLA82XX_IDC_VERSION 0x1

Definition at line 629 of file ql4_nx.h.

#define QLA82XX_LEGACY_INTR_CONFIG

Definition at line 781 of file ql4_nx.h.

#define QLA82XX_MSIX_TBL_SPACE 8192

Definition at line 649 of file ql4_nx.h.

#define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)

Definition at line 502 of file ql4_nx.h.

#define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)

Definition at line 511 of file ql4_nx.h.

#define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)

Definition at line 503 of file ql4_nx.h.

#define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)

Definition at line 512 of file ql4_nx.h.

#define QLA82XX_PCI_CAMQM (unsigned long)0x04800000

Definition at line 517 of file ql4_nx.h.

#define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff

Definition at line 518 of file ql4_nx.h.

#define QLA82XX_PCI_CRB_WINDOW ( A )

Value:

(QLA82XX_PCI_CRBSPACE + \

(A)*QLA82XX_PCI_CRB_WINDOWSIZE)

Definition at line 362 of file ql4_nx.h.

#define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */

Definition at line 361 of file ql4_nx.h.

#define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000

Definition at line 515 of file ql4_nx.h.

#define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000

Definition at line 519 of file ql4_nx.h.

#define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000

Definition at line 516 of file ql4_nx.h.

#define QLA82XX_PCI_MSIX_CONTROL 0x40

Definition at line 651 of file ql4_nx.h.

#define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000

Definition at line 520 of file ql4_nx.h.

#define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff

Definition at line 521 of file ql4_nx.h.

#define QLA82XX_PCI_REG_MSIX_TBL 0x44

Definition at line 650 of file ql4_nx.h.

#define QLA82XX_PCIE_REG ( reg ) (QLA82XX_CRB_PCIE + (reg))

Definition at line 575 of file ql4_nx.h.

#define QLA82XX_PCIX_PS2_REG ( reg ) (QLA82XX_CRB_PCIE2 + (reg))

Definition at line 637 of file ql4_nx.h.

#define QLA82XX_PCIX_PS_REG ( reg ) (QLA82XX_CRB_PCIX_MD + (reg))

Definition at line 636 of file ql4_nx.h.

#define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))

Definition at line 562 of file ql4_nx.h.

#define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))

Definition at line 560 of file ql4_nx.h.

#define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))

Definition at line 561 of file ql4_nx.h.

#define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))

Definition at line 559 of file ql4_nx.h.

#define QLA82XX_REG ( X ) (QLA82XX_CRB_BASE+(X))

Definition at line 23 of file ql4_nx.h.

#define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))

Definition at line 570 of file ql4_nx.h.

#define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)

Definition at line 356 of file ql4_nx.h.

#define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)

Definition at line 345 of file ql4_nx.h.

#define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)

Definition at line 346 of file ql4_nx.h.

#define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)

Definition at line 347 of file ql4_nx.h.

#define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)

Definition at line 350 of file ql4_nx.h.

#define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)

Definition at line 348 of file ql4_nx.h.

#define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)

Definition at line 351 of file ql4_nx.h.

#define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)

Definition at line 355 of file ql4_nx.h.

#define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)

Definition at line 352 of file ql4_nx.h.

#define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)

Definition at line 349 of file ql4_nx.h.

#define QLA83XX_POLLRD 35

Definition at line 858 of file ql4_nx.h.

#define QLA83XX_POLLRDMWR 37

Definition at line 860 of file ql4_nx.h.

#define QLA83XX_RDMUX2 36

Definition at line 859 of file ql4_nx.h.

#define QLA83XX_TLHDR 99

Definition at line 864 of file ql4_nx.h.

#define QLA8XXX_ADDR_DDR_NET (0x0000000000000000ULL)

Definition at line 495 of file ql4_nx.h.

#define QLA8XXX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)

Definition at line 496 of file ql4_nx.h.

#define QLA8XXX_ADDR_IN_RANGE	(	addr,
		low,
		high
	)	(((addr) <= (high)) && ((addr) >= (low)))

Definition at line 524 of file ql4_nx.h.

#define QLA8XXX_ADDR_OCM0 (0x0000000200000000ULL)

Definition at line 505 of file ql4_nx.h.

#define QLA8XXX_ADDR_OCM0_MAX (0x00000002000fffffULL)

Definition at line 506 of file ql4_nx.h.

#define QLA8XXX_ADDR_OCM1 (0x0000000200400000ULL)

Definition at line 507 of file ql4_nx.h.

#define QLA8XXX_ADDR_OCM1_MAX (0x00000002004fffffULL)

Definition at line 508 of file ql4_nx.h.

#define QLA8XXX_ADDR_QDR_NET (0x0000000300000000ULL)

Definition at line 509 of file ql4_nx.h.

#define QLA8XXX_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)

Definition at line 513 of file ql4_nx.h.

#define QLA8XXX_BOARD 4

Definition at line 847 of file ql4_nx.h.

#define QLA8XXX_CNTRL 98

Definition at line 863 of file ql4_nx.h.

#define QLA8XXX_DBG_OPCODE_AND 0x04

Definition at line 872 of file ql4_nx.h.

#define QLA8XXX_DBG_OPCODE_MDSTATE 0x80

Definition at line 877 of file ql4_nx.h.

#define QLA8XXX_DBG_OPCODE_OR 0x08

Definition at line 873 of file ql4_nx.h.

#define QLA8XXX_DBG_OPCODE_POLL 0x10

Definition at line 874 of file ql4_nx.h.

#define QLA8XXX_DBG_OPCODE_RDSTATE 0x20

Definition at line 875 of file ql4_nx.h.

#define QLA8XXX_DBG_OPCODE_RW 0x02

Definition at line 871 of file ql4_nx.h.

#define QLA8XXX_DBG_OPCODE_WR 0x01

Definition at line 870 of file ql4_nx.h.

#define QLA8XXX_DBG_OPCODE_WRSTATE 0x40

Definition at line 876 of file ql4_nx.h.

#define QLA8XXX_DBG_SIZE_ERR_FLAG

Value:

0x40 /* Entry vs Capture size

* mismatch */

Definition at line 881 of file ql4_nx.h.

#define QLA8XXX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */

Definition at line 880 of file ql4_nx.h.

#define QLA8XXX_DEV_COLD 1

Definition at line 620 of file ql4_nx.h.

#define QLA8XXX_DEV_FAILED 6

Definition at line 625 of file ql4_nx.h.

#define QLA8XXX_DEV_INITIALIZING 2

Definition at line 621 of file ql4_nx.h.

#define QLA8XXX_DEV_NEED_QUIESCENT 5

Definition at line 624 of file ql4_nx.h.

#define QLA8XXX_DEV_NEED_RESET 4

Definition at line 623 of file ql4_nx.h.

#define QLA8XXX_DEV_QUIESCENT 7

Definition at line 626 of file ql4_nx.h.

#define QLA8XXX_DEV_READY 3

Definition at line 622 of file ql4_nx.h.

#define QLA8XXX_L1DAT 11

Definition at line 852 of file ql4_nx.h.

#define QLA8XXX_L1DTG 8

Definition at line 850 of file ql4_nx.h.

#define QLA8XXX_L1INS 12

Definition at line 853 of file ql4_nx.h.

#define QLA8XXX_L1ITG 9

Definition at line 851 of file ql4_nx.h.

#define QLA8XXX_L2DAT 23

Definition at line 856 of file ql4_nx.h.

#define QLA8XXX_L2DTG 21

Definition at line 854 of file ql4_nx.h.

#define QLA8XXX_L2INS 24

Definition at line 857 of file ql4_nx.h.

#define QLA8XXX_L2ITG 22

Definition at line 855 of file ql4_nx.h.

#define QLA8XXX_PREGS 7

Definition at line 849 of file ql4_nx.h.

#define QLA8XXX_QUEUE 3

Definition at line 846 of file ql4_nx.h.

#define QLA8XXX_RDCRB 1

Definition at line 844 of file ql4_nx.h.

#define QLA8XXX_RDEND 255

Definition at line 865 of file ql4_nx.h.

#define QLA8XXX_RDMEM 72

Definition at line 862 of file ql4_nx.h.

#define QLA8XXX_RDMUX 2

Definition at line 845 of file ql4_nx.h.

#define QLA8XXX_RDNOP 0

Definition at line 843 of file ql4_nx.h.

#define QLA8XXX_RDOCM 6

Definition at line 848 of file ql4_nx.h.

#define QLA8XXX_RDROM 71

Definition at line 861 of file ql4_nx.h.

#define ROM_DEV_INIT_TIMEOUT 30

Definition at line 630 of file ql4_nx.h.

#define ROM_DRV_RESET_ACK_TIMEOUT 10

Definition at line 631 of file ql4_nx.h.

#define ROM_LOCK_DRIVER 0x0d417340

Definition at line 359 of file ql4_nx.h.

#define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)

Definition at line 344 of file ql4_nx.h.

#define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)

Definition at line 354 of file ql4_nx.h.

#define RQST_TMPLT 0x1

Definition at line 1009 of file ql4_nx.h.

#define RQST_TMPLT_SIZE 0x0

Definition at line 1008 of file ql4_nx.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

QLA82XX_TEMP_NORMAL
QLA82XX_TEMP_WARN
QLA82XX_TEMP_PANIC

Definition at line 38 of file ql4_nx.h.

enum qla_regs

Enumerator:

QLA8XXX_PEG_HALT_STATUS1
QLA8XXX_PEG_HALT_STATUS2
QLA8XXX_PEG_ALIVE_COUNTER
QLA8XXX_CRB_DRV_ACTIVE
QLA8XXX_CRB_DEV_STATE
QLA8XXX_CRB_DRV_STATE
QLA8XXX_CRB_DRV_SCRATCH
QLA8XXX_CRB_DEV_PART_INFO
QLA8XXX_CRB_DRV_IDC_VERSION
QLA8XXX_FW_VERSION_MAJOR
QLA8XXX_FW_VERSION_MINOR
QLA8XXX_FW_VERSION_SUB
QLA8XXX_CRB_CMDPEG_STATE
QLA8XXX_CRB_TEMP_STATE

Definition at line 585 of file ql4_nx.h.

Data Structures

Macros

Enumerations

Macro Definition Documentation

Enumeration Type Documentation