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Data Structures | Macros | Enumerations
qlcnic_hdr.h File Reference
#include <linux/kernel.h>
#include <linux/types.h>

Go to the source code of this file.

Data Structures

struct  qlcnic_legacy_intr_set
 
struct  crb_128M_2M_sub_block_map
 
struct  crb_128M_2M_block_map
 

Macros

#define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR   0x67
 
#define BIT_0   0x1
 
#define BIT_1   0x2
 
#define BIT_2   0x4
 
#define BIT_3   0x8
 
#define BIT_4   0x10
 
#define BIT_5   0x20
 
#define BIT_6   0x40
 
#define BIT_7   0x80
 
#define BIT_8   0x100
 
#define BIT_9   0x200
 
#define BIT_10   0x400
 
#define BIT_11   0x800
 
#define BIT_12   0x1000
 
#define BIT_13   0x2000
 
#define BIT_14   0x4000
 
#define BIT_15   0x8000
 
#define BIT_16   0x10000
 
#define BIT_17   0x20000
 
#define BIT_18   0x40000
 
#define BIT_19   0x80000
 
#define BIT_20   0x100000
 
#define BIT_21   0x200000
 
#define BIT_22   0x400000
 
#define BIT_23   0x800000
 
#define BIT_24   0x1000000
 
#define BIT_25   0x2000000
 
#define BIT_26   0x4000000
 
#define BIT_27   0x8000000
 
#define BIT_28   0x10000000
 
#define BIT_29   0x20000000
 
#define BIT_30   0x40000000
 
#define BIT_31   0x80000000
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_MN   ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MN_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PH   ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_PH_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_MS   ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MS_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PS   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_PS_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SS   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SS_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX3_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMS   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_QMS_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS0   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS0_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS1   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS1_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS2   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS2_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS3   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS3_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C0   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C0_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C1   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C1_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX2_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX4_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX7_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX9_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SMB   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SMB_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_NIU   ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_NIU_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0   ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C0_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1   ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C1_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SRE   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SRE_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_EG   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_EG_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX0_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMN   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_QM_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG0_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG1_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG2_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG3_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX1_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX5_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX6_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX8_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS0   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS0_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS1   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS1_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS2   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS2_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS3   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS3_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNI_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGND   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGND_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN0_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN1_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN2_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN3_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN4_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNC_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR0   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR0_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR1   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR1_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR2   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR2_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR3   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR3_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSI_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSD   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSD_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS0_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS1_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS2_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS3_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSC   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSC_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAM   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_NCM_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_TMR_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_XDMA_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SN   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_SN_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_I2Q_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_ROMUSB_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM0_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM1   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM1_CRB_AGT_ADR)
 
#define QLCNIC_HW_CRB_HUB_AGT_ADR_LPC   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_LPC_CRB_AGT_ADR)
 
#define QLCNIC_SRE_MISC   (QLCNIC_CRB_SRE + 0x0002c)
 
#define QLCNIC_I2Q_CLR_PCI_HI   (QLCNIC_CRB_I2Q + 0x00034)
 
#define ROMUSB_GLB   (QLCNIC_CRB_ROMUSB + 0x00000)
 
#define ROMUSB_ROM   (QLCNIC_CRB_ROMUSB + 0x10000)
 
#define QLCNIC_ROMUSB_GLB_STATUS   (ROMUSB_GLB + 0x0004)
 
#define QLCNIC_ROMUSB_GLB_SW_RESET   (ROMUSB_GLB + 0x0008)
 
#define QLCNIC_ROMUSB_GLB_PAD_GPIO_I   (ROMUSB_GLB + 0x000c)
 
#define QLCNIC_ROMUSB_GLB_CAS_RST   (ROMUSB_GLB + 0x0038)
 
#define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL   (ROMUSB_GLB + 0x0044)
 
#define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE   (ROMUSB_GLB + 0x005c)
 
#define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL   (ROMUSB_GLB + 0x00A8)
 
#define QLCNIC_ROMUSB_GPIO(n)   (ROMUSB_GLB + 0x60 + (4 * (n)))
 
#define QLCNIC_ROMUSB_ROM_INSTR_OPCODE   (ROMUSB_ROM + 0x0004)
 
#define QLCNIC_ROMUSB_ROM_ADDRESS   (ROMUSB_ROM + 0x0008)
 
#define QLCNIC_ROMUSB_ROM_WDATA   (ROMUSB_ROM + 0x000c)
 
#define QLCNIC_ROMUSB_ROM_ABYTE_CNT   (ROMUSB_ROM + 0x0010)
 
#define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT   (ROMUSB_ROM + 0x0014)
 
#define QLCNIC_ROMUSB_ROM_RDATA   (ROMUSB_ROM + 0x0018)
 
#define ROM_LOCK_DRIVER   0x0d417340
 
#define QLCNIC_PCI_CRB_WINDOWSIZE   0x00100000
 
#define QLCNIC_PCI_CRB_WINDOW(A)   (QLCNIC_PCI_CRBSPACE + (A)*QLCNIC_PCI_CRB_WINDOWSIZE)
 
#define QLCNIC_CRB_NIU   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_NIU)
 
#define QLCNIC_CRB_SRE   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE)
 
#define QLCNIC_CRB_ROMUSB   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB)
 
#define QLCNIC_CRB_EPG   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_EG)
 
#define QLCNIC_CRB_I2Q   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q)
 
#define QLCNIC_CRB_TIMER   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_TIMR)
 
#define QLCNIC_CRB_I2C0   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0)
 
#define QLCNIC_CRB_SMB   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB)
 
#define QLCNIC_CRB_MAX   QLCNIC_PCI_CRB_WINDOW(64)
 
#define QLCNIC_CRB_PCIX_HOST   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH)
 
#define QLCNIC_CRB_PCIX_HOST2   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH2)
 
#define QLCNIC_CRB_PEG_NET_0   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN0)
 
#define QLCNIC_CRB_PEG_NET_1   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN1)
 
#define QLCNIC_CRB_PEG_NET_2   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN2)
 
#define QLCNIC_CRB_PEG_NET_3   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN3)
 
#define QLCNIC_CRB_PEG_NET_4   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SQS2)
 
#define QLCNIC_CRB_PEG_NET_D   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGND)
 
#define QLCNIC_CRB_PEG_NET_I   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGNI)
 
#define QLCNIC_CRB_DDR_NET   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_MN)
 
#define QLCNIC_CRB_QDR_NET   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SN)
 
#define QLCNIC_CRB_PCIX_MD   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PS)
 
#define QLCNIC_CRB_PCIE   QLCNIC_CRB_PCIX_MD
 
#define ISR_INT_VECTOR   (QLCNIC_PCIX_PS_REG(PCIX_INT_VECTOR))
 
#define ISR_INT_MASK   (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))
 
#define ISR_INT_MASK_SLOW   (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))
 
#define ISR_INT_TARGET_STATUS   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS))
 
#define ISR_INT_TARGET_MASK   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK))
 
#define ISR_INT_TARGET_STATUS_F1   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
 
#define ISR_INT_TARGET_MASK_F1   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
 
#define ISR_INT_TARGET_STATUS_F2   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
 
#define ISR_INT_TARGET_MASK_F2   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
 
#define ISR_INT_TARGET_STATUS_F3   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
 
#define ISR_INT_TARGET_MASK_F3   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
 
#define ISR_INT_TARGET_STATUS_F4   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
 
#define ISR_INT_TARGET_MASK_F4   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
 
#define ISR_INT_TARGET_STATUS_F5   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
 
#define ISR_INT_TARGET_MASK_F5   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
 
#define ISR_INT_TARGET_STATUS_F6   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
 
#define ISR_INT_TARGET_MASK_F6   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
 
#define ISR_INT_TARGET_STATUS_F7   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
 
#define ISR_INT_TARGET_MASK_F7   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
 
#define QLCNIC_PCI_MN_2M   (0)
 
#define QLCNIC_PCI_MS_2M   (0x80000)
 
#define QLCNIC_PCI_OCM0_2M   (0x000c0000UL)
 
#define QLCNIC_PCI_CRBSPACE   (0x06000000UL)
 
#define QLCNIC_PCI_CAMQM   (0x04800000UL)
 
#define QLCNIC_PCI_CAMQM_END   (0x04800800UL)
 
#define QLCNIC_PCI_2MB_SIZE   (0x00200000UL)
 
#define QLCNIC_PCI_CAMQM_2M_BASE   (0x000ff800UL)
 
#define QLCNIC_CRB_CAM   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_CAM)
 
#define QLCNIC_ADDR_DDR_NET   (0x0000000000000000ULL)
 
#define QLCNIC_ADDR_DDR_NET_MAX   (0x000000000fffffffULL)
 
#define QLCNIC_ADDR_OCM0   (0x0000000200000000ULL)
 
#define QLCNIC_ADDR_OCM0_MAX   (0x00000002000fffffULL)
 
#define QLCNIC_ADDR_OCM1   (0x0000000200400000ULL)
 
#define QLCNIC_ADDR_OCM1_MAX   (0x00000002004fffffULL)
 
#define QLCNIC_ADDR_QDR_NET   (0x0000000300000000ULL)
 
#define QLCNIC_ADDR_QDR_NET_MAX   (0x0000000307ffffffULL)
 
#define QLCNIC_MIU_CONTROL   (0x000)
 
#define QLCNIC_MIU_MN_CONTROL   (QLCNIC_CRB_DDR_NET+QLCNIC_MIU_CONTROL)
 
#define QLCNIC_NIU_PHY_WAITLEN   200000
 
#define QLCNIC_NIU_PHY_WAITMAX   50
 
#define QLCNIC_NIU_MAX_GBE_PORTS   4
 
#define QLCNIC_NIU_MAX_XG_PORTS   2
 
#define QLCNIC_NIU_MODE   (QLCNIC_CRB_NIU + 0x00000)
 
#define QLCNIC_NIU_GB_PAUSE_CTL   (QLCNIC_CRB_NIU + 0x0030c)
 
#define QLCNIC_NIU_XG_PAUSE_CTL   (QLCNIC_CRB_NIU + 0x00098)
 
#define QLCNIC_NIU_GB_MAC_CONFIG_0(I)   (QLCNIC_CRB_NIU + 0x30000 + (I)*0x10000)
 
#define QLCNIC_NIU_GB_MAC_CONFIG_1(I)   (QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000)
 
#define TEST_AGT_CTRL   (0x00)
 
#define TA_CTL_START   BIT_0
 
#define TA_CTL_ENABLE   BIT_1
 
#define TA_CTL_WRITE   BIT_2
 
#define TA_CTL_BUSY   BIT_3
 
#define MIU_TEST_AGT_BASE   (0x90)
 
#define MIU_TEST_AGT_ADDR_LO   (0x04)
 
#define MIU_TEST_AGT_ADDR_HI   (0x08)
 
#define MIU_TEST_AGT_WRDATA_LO   (0x10)
 
#define MIU_TEST_AGT_WRDATA_HI   (0x14)
 
#define MIU_TEST_AGT_WRDATA_UPPER_LO   (0x20)
 
#define MIU_TEST_AGT_WRDATA_UPPER_HI   (0x24)
 
#define MIU_TEST_AGT_WRDATA(i)   (0x10+(0x10*((i)>>1))+(4*((i)&1)))
 
#define MIU_TEST_AGT_RDDATA_LO   (0x18)
 
#define MIU_TEST_AGT_RDDATA_HI   (0x1c)
 
#define MIU_TEST_AGT_RDDATA_UPPER_LO   (0x28)
 
#define MIU_TEST_AGT_RDDATA_UPPER_HI   (0x2c)
 
#define MIU_TEST_AGT_RDDATA(i)   (0x18+(0x10*((i)>>1))+(4*((i)&1)))
 
#define MIU_TEST_AGT_ADDR_MASK   0xfffffff8
 
#define MIU_TEST_AGT_UPPER_ADDR(off)   (0)
 
#define SIU_TEST_AGT_BASE   (0x60)
 
#define SIU_TEST_AGT_ADDR_LO   (0x04)
 
#define SIU_TEST_AGT_ADDR_HI   (0x18)
 
#define SIU_TEST_AGT_WRDATA_LO   (0x08)
 
#define SIU_TEST_AGT_WRDATA_HI   (0x0c)
 
#define SIU_TEST_AGT_WRDATA(i)   (0x08+(4*(i)))
 
#define SIU_TEST_AGT_RDDATA_LO   (0x10)
 
#define SIU_TEST_AGT_RDDATA_HI   (0x14)
 
#define SIU_TEST_AGT_RDDATA(i)   (0x10+(4*(i)))
 
#define SIU_TEST_AGT_ADDR_MASK   0x3ffff8
 
#define SIU_TEST_AGT_UPPER_ADDR(off)   ((off)>>22)
 
#define XG_LINK_UP   0x10
 
#define XG_LINK_DOWN   0x20
 
#define XG_LINK_UP_P3P   0x01
 
#define XG_LINK_DOWN_P3P   0x02
 
#define XG_LINK_STATE_P3P_MASK   0xf
 
#define XG_LINK_STATE_P3P(pcifn, val)   (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3P_MASK)
 
#define P3P_LINK_SPEED_MHZ   100
 
#define P3P_LINK_SPEED_MASK   0xff
 
#define P3P_LINK_SPEED_REG(pcifn)   (CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4))
 
#define P3P_LINK_SPEED_VAL(pcifn, reg)   (((reg) >> (8 * ((pcifn) & 0x3))) & P3P_LINK_SPEED_MASK)
 
#define QLCNIC_CAM_RAM_BASE   (QLCNIC_CRB_CAM + 0x02000)
 
#define QLCNIC_CAM_RAM(reg)   (QLCNIC_CAM_RAM_BASE + (reg))
 
#define QLCNIC_FW_VERSION_MAJOR   (QLCNIC_CAM_RAM(0x150))
 
#define QLCNIC_FW_VERSION_MINOR   (QLCNIC_CAM_RAM(0x154))
 
#define QLCNIC_FW_VERSION_SUB   (QLCNIC_CAM_RAM(0x158))
 
#define QLCNIC_ROM_LOCK_ID   (QLCNIC_CAM_RAM(0x100))
 
#define QLCNIC_PHY_LOCK_ID   (QLCNIC_CAM_RAM(0x120))
 
#define QLCNIC_CRB_WIN_LOCK_ID   (QLCNIC_CAM_RAM(0x124))
 
#define NIC_CRB_BASE   (QLCNIC_CAM_RAM(0x200))
 
#define NIC_CRB_BASE_2   (QLCNIC_CAM_RAM(0x700))
 
#define QLCNIC_REG(X)   (NIC_CRB_BASE+(X))
 
#define QLCNIC_REG_2(X)   (NIC_CRB_BASE_2+(X))
 
#define QLCNIC_CDRP_CRB_OFFSET   (QLCNIC_REG(0x18))
 
#define QLCNIC_ARG1_CRB_OFFSET   (QLCNIC_REG(0x1c))
 
#define QLCNIC_ARG2_CRB_OFFSET   (QLCNIC_REG(0x20))
 
#define QLCNIC_ARG3_CRB_OFFSET   (QLCNIC_REG(0x24))
 
#define QLCNIC_SIGN_CRB_OFFSET   (QLCNIC_REG(0x28))
 
#define CRB_CMDPEG_STATE   (QLCNIC_REG(0x50))
 
#define CRB_RCVPEG_STATE   (QLCNIC_REG(0x13c))
 
#define CRB_XG_STATE_P3P   (QLCNIC_REG(0x98))
 
#define CRB_PF_LINK_SPEED_1   (QLCNIC_REG(0xe8))
 
#define CRB_PF_LINK_SPEED_2   (QLCNIC_REG(0xec))
 
#define CRB_TEMP_STATE   (QLCNIC_REG(0x1b4))
 
#define CRB_V2P_0   (QLCNIC_REG(0x290))
 
#define CRB_V2P(port)   (CRB_V2P_0+((port)*4))
 
#define CRB_DRIVER_VERSION   (QLCNIC_REG(0x2a0))
 
#define CRB_FW_CAPABILITIES_1   (QLCNIC_CAM_RAM(0x128))
 
#define CRB_FW_CAPABILITIES_2   (QLCNIC_CAM_RAM(0x12c))
 
#define CRB_MAC_BLOCK_START   (QLCNIC_CAM_RAM(0x1c0))
 
#define qlcnic_get_temp_val(x)   ((x) >> 16)
 
#define qlcnic_get_temp_state(x)   ((x) & 0xffff)
 
#define qlcnic_encode_temp(val, state)   (((val) << 16) | (state))
 
#define PHY_LOCK_DRIVER   0x44524956
 
#define PCIX_PS_OP_ADDR_LO   (0x10000)
 
#define PCIX_PS_OP_ADDR_HI   (0x10004)
 
#define PCIX_INT_VECTOR   (0x10100)
 
#define PCIX_INT_MASK   (0x10104)
 
#define PCIX_OCM_WINDOW   (0x10800)
 
#define PCIX_OCM_WINDOW_REG(func)   (PCIX_OCM_WINDOW + 0x4 * (func))
 
#define PCIX_TARGET_STATUS   (0x10118)
 
#define PCIX_TARGET_STATUS_F1   (0x10160)
 
#define PCIX_TARGET_STATUS_F2   (0x10164)
 
#define PCIX_TARGET_STATUS_F3   (0x10168)
 
#define PCIX_TARGET_STATUS_F4   (0x10360)
 
#define PCIX_TARGET_STATUS_F5   (0x10364)
 
#define PCIX_TARGET_STATUS_F6   (0x10368)
 
#define PCIX_TARGET_STATUS_F7   (0x1036c)
 
#define PCIX_TARGET_MASK   (0x10128)
 
#define PCIX_TARGET_MASK_F1   (0x10170)
 
#define PCIX_TARGET_MASK_F2   (0x10174)
 
#define PCIX_TARGET_MASK_F3   (0x10178)
 
#define PCIX_TARGET_MASK_F4   (0x10370)
 
#define PCIX_TARGET_MASK_F5   (0x10374)
 
#define PCIX_TARGET_MASK_F6   (0x10378)
 
#define PCIX_TARGET_MASK_F7   (0x1037c)
 
#define PCIX_MSI_F(i)   (0x13000+((i)*4))
 
#define QLCNIC_PCIX_PH_REG(reg)   (QLCNIC_CRB_PCIE + (reg))
 
#define QLCNIC_PCIX_PS_REG(reg)   (QLCNIC_CRB_PCIX_MD + (reg))
 
#define QLCNIC_PCIE_REG(reg)   (QLCNIC_CRB_PCIE + (reg))
 
#define PCIE_SEM0_LOCK   (0x1c000)
 
#define PCIE_SEM0_UNLOCK   (0x1c004)
 
#define PCIE_SEM_LOCK(N)   (PCIE_SEM0_LOCK + 8*(N))
 
#define PCIE_SEM_UNLOCK(N)   (PCIE_SEM0_UNLOCK + 8*(N))
 
#define PCIE_SETUP_FUNCTION   (0x12040)
 
#define PCIE_SETUP_FUNCTION2   (0x12048)
 
#define PCIE_MISCCFG_RC   (0x1206c)
 
#define PCIE_TGT_SPLIT_CHICKEN   (0x12080)
 
#define PCIE_CHICKEN3   (0x120c8)
 
#define ISR_INT_STATE_REG   (QLCNIC_PCIX_PS_REG(PCIE_MISCCFG_RC))
 
#define PCIE_MAX_MASTER_SPLIT   (0x14048)
 
#define QLCNIC_PORT_MODE_NONE   0
 
#define QLCNIC_PORT_MODE_XG   1
 
#define QLCNIC_PORT_MODE_GB   2
 
#define QLCNIC_PORT_MODE_802_3_AP   3
 
#define QLCNIC_PORT_MODE_AUTO_NEG   4
 
#define QLCNIC_PORT_MODE_AUTO_NEG_1G   5
 
#define QLCNIC_PORT_MODE_AUTO_NEG_XG   6
 
#define QLCNIC_PORT_MODE_ADDR   (QLCNIC_CAM_RAM(0x24))
 
#define QLCNIC_WOL_PORT_MODE   (QLCNIC_CAM_RAM(0x198))
 
#define QLCNIC_WOL_CONFIG_NV   (QLCNIC_CAM_RAM(0x184))
 
#define QLCNIC_WOL_CONFIG   (QLCNIC_CAM_RAM(0x188))
 
#define QLCNIC_PEG_TUNE_MN_PRESENT   0x1
 
#define QLCNIC_PEG_TUNE_CAPABILITY   (QLCNIC_CAM_RAM(0x02c))
 
#define QLCNIC_DMA_WATCHDOG_CTRL   (QLCNIC_CAM_RAM(0x14))
 
#define QLCNIC_PEG_ALIVE_COUNTER   (QLCNIC_CAM_RAM(0xb0))
 
#define QLCNIC_PEG_HALT_STATUS1   (QLCNIC_CAM_RAM(0xa8))
 
#define QLCNIC_PEG_HALT_STATUS2   (QLCNIC_CAM_RAM(0xac))
 
#define QLCNIC_CRB_DRV_ACTIVE   (QLCNIC_CAM_RAM(0x138))
 
#define QLCNIC_CRB_DEV_STATE   (QLCNIC_CAM_RAM(0x140))
 
#define QLCNIC_CRB_DRV_STATE   (QLCNIC_CAM_RAM(0x144))
 
#define QLCNIC_CRB_DRV_SCRATCH   (QLCNIC_CAM_RAM(0x148))
 
#define QLCNIC_CRB_DEV_PARTITION_INFO   (QLCNIC_CAM_RAM(0x14c))
 
#define QLCNIC_CRB_DRV_IDC_VER   (QLCNIC_CAM_RAM(0x174))
 
#define QLCNIC_CRB_DEV_NPAR_STATE   (QLCNIC_CAM_RAM(0x19c))
 
#define QLCNIC_ROM_DEV_INIT_TIMEOUT   (0x3e885c)
 
#define QLCNIC_ROM_DRV_RESET_TIMEOUT   (0x3e8860)
 
#define QLCNIC_DEV_COLD   0x1
 
#define QLCNIC_DEV_INITIALIZING   0x2
 
#define QLCNIC_DEV_READY   0x3
 
#define QLCNIC_DEV_NEED_RESET   0x4
 
#define QLCNIC_DEV_NEED_QUISCENT   0x5
 
#define QLCNIC_DEV_FAILED   0x6
 
#define QLCNIC_DEV_QUISCENT   0x7
 
#define QLCNIC_DEV_BADBAD   0xbad0bad0
 
#define QLCNIC_DEV_NPAR_NON_OPER   0 /* NON Operational */
 
#define QLCNIC_DEV_NPAR_OPER   1 /* NPAR Operational */
 
#define QLCNIC_DEV_NPAR_OPER_TIMEO   30 /* Operational time out */
 
#define QLC_DEV_CHECK_ACTIVE(VAL, FN)   ((VAL) & (1 << (FN * 4)))
 
#define QLC_DEV_SET_REF_CNT(VAL, FN)   ((VAL) |= (1 << (FN * 4)))
 
#define QLC_DEV_CLR_REF_CNT(VAL, FN)   ((VAL) &= ~(1 << (FN * 4)))
 
#define QLC_DEV_SET_RST_RDY(VAL, FN)   ((VAL) |= (1 << (FN * 4)))
 
#define QLC_DEV_SET_QSCNT_RDY(VAL, FN)   ((VAL) |= (2 << (FN * 4)))
 
#define QLC_DEV_CLR_RST_QSCNT(VAL, FN)   ((VAL) &= ~(3 << (FN * 4)))
 
#define QLC_DEV_GET_DRV(VAL, FN)   (0xf & ((VAL) >> (FN * 4)))
 
#define QLC_DEV_SET_DRV(VAL, FN)   ((VAL) << (FN * 4))
 
#define QLCNIC_TYPE_NIC   1
 
#define QLCNIC_TYPE_FCOE   2
 
#define QLCNIC_TYPE_ISCSI   3
 
#define QLCNIC_RCODE_DRIVER_INFO   0x20000000
 
#define QLCNIC_RCODE_DRIVER_CAN_RELOAD   BIT_30
 
#define QLCNIC_RCODE_FATAL_ERROR   BIT_31
 
#define QLCNIC_FWERROR_PEGNUM(code)   ((code) & 0xff)
 
#define QLCNIC_FWERROR_CODE(code)   ((code >> 8) & 0x1fffff)
 
#define QLCNIC_FWERROR_FAN_FAILURE   0x16
 
#define FW_POLL_DELAY   (1 * HZ)
 
#define FW_FAIL_THRESH   2
 
#define QLCNIC_RESET_TIMEOUT_SECS   10
 
#define QLCNIC_INIT_TIMEOUT_SECS   30
 
#define QLCNIC_RCVPEG_CHECK_RETRY_COUNT   2000
 
#define QLCNIC_RCVPEG_CHECK_DELAY   10
 
#define QLCNIC_CMDPEG_CHECK_RETRY_COUNT   60
 
#define QLCNIC_CMDPEG_CHECK_DELAY   500
 
#define QLCNIC_HEARTBEAT_PERIOD_MSECS   200
 
#define QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT   45
 
#define ISR_MSI_INT_TRIGGER(FUNC)   (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
 
#define ISR_LEGACY_INT_TRIGGERED(VAL)   (((VAL) & 0x300) == 0x200)
 
#define PCIX_INT_VECTOR_BIT_F0   0x0080
 
#define PCIX_INT_VECTOR_BIT_F1   0x0100
 
#define PCIX_INT_VECTOR_BIT_F2   0x0200
 
#define PCIX_INT_VECTOR_BIT_F3   0x0400
 
#define PCIX_INT_VECTOR_BIT_F4   0x0800
 
#define PCIX_INT_VECTOR_BIT_F5   0x1000
 
#define PCIX_INT_VECTOR_BIT_F6   0x2000
 
#define PCIX_INT_VECTOR_BIT_F7   0x4000
 
#define QLCNIC_FW_API   0x1b216c
 
#define QLCNIC_DRV_OP_MODE   0x1b2170
 
#define QLCNIC_MSIX_BASE   0x132110
 
#define QLCNIC_MAX_PCI_FUNC   8
 
#define QLCNIC_MAX_VLAN_FILTERS   64
 
#define MIU_TEST_CTR   0x41000090
 
#define MIU_TEST_ADDR_LO   0x41000094
 
#define MIU_TEST_ADDR_HI   0x41000098
 
#define FLASH_ROM_WINDOW   0x42110030
 
#define FLASH_ROM_DATA   0x42150000
 
#define QLCNIC_FW_DUMP_REG1   0x00130060
 
#define QLCNIC_FW_DUMP_REG2   0x001e0000
 
#define QLCNIC_FLASH_SEM2_LK   0x0013C010
 
#define QLCNIC_FLASH_SEM2_ULK   0x0013C014
 
#define QLCNIC_FLASH_LOCK_ID   0x001B2100
 
#define QLCNIC_RD_DUMP_REG(addr, bar0, data)
 
#define QLCNIC_WR_DUMP_REG(addr, bar0, data)
 
#define QLC_DEV_DRV_DEFAULT   0x11111111
 
#define LSB(x)   ((uint8_t)(x))
 
#define MSB(x)   ((uint8_t)((uint16_t)(x) >> 8))
 
#define LSW(x)   ((uint16_t)((uint32_t)(x)))
 
#define MSW(x)   ((uint16_t)((uint32_t)(x) >> 16))
 
#define LSD(x)   ((uint32_t)((uint64_t)(x)))
 
#define MSD(x)   ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
 
#define QLCNIC_LEGACY_INTR_CONFIG
 
#define _qlcnic_crb_get_bit(var, bit)   ((var >> bit) & 0x1)
 
#define qlcnic_gb_rx_flowctl(config_word)   ((config_word) |= 1 << 5)
 
#define qlcnic_gb_get_rx_flowctl(config_word)   _qlcnic_crb_get_bit((config_word), 5)
 
#define qlcnic_gb_unset_rx_flowctl(config_word)   ((config_word) &= ~(1 << 5))
 
#define qlcnic_gb_set_gb0_mask(config_word)   ((config_word) |= 1 << 0)
 
#define qlcnic_gb_set_gb1_mask(config_word)   ((config_word) |= 1 << 2)
 
#define qlcnic_gb_set_gb2_mask(config_word)   ((config_word) |= 1 << 4)
 
#define qlcnic_gb_set_gb3_mask(config_word)   ((config_word) |= 1 << 6)
 
#define qlcnic_gb_get_gb0_mask(config_word)   _qlcnic_crb_get_bit((config_word), 0)
 
#define qlcnic_gb_get_gb1_mask(config_word)   _qlcnic_crb_get_bit((config_word), 2)
 
#define qlcnic_gb_get_gb2_mask(config_word)   _qlcnic_crb_get_bit((config_word), 4)
 
#define qlcnic_gb_get_gb3_mask(config_word)   _qlcnic_crb_get_bit((config_word), 6)
 
#define qlcnic_gb_unset_gb0_mask(config_word)   ((config_word) &= ~(1 << 0))
 
#define qlcnic_gb_unset_gb1_mask(config_word)   ((config_word) &= ~(1 << 2))
 
#define qlcnic_gb_unset_gb2_mask(config_word)   ((config_word) &= ~(1 << 4))
 
#define qlcnic_gb_unset_gb3_mask(config_word)   ((config_word) &= ~(1 << 6))
 
#define qlcnic_xg_set_xg0_mask(config_word)   ((config_word) |= 1 << 0)
 
#define qlcnic_xg_set_xg1_mask(config_word)   ((config_word) |= 1 << 3)
 
#define qlcnic_xg_get_xg0_mask(config_word)   _qlcnic_crb_get_bit((config_word), 0)
 
#define qlcnic_xg_get_xg1_mask(config_word)   _qlcnic_crb_get_bit((config_word), 3)
 
#define qlcnic_xg_unset_xg0_mask(config_word)   ((config_word) &= ~(1 << 0))
 
#define qlcnic_xg_unset_xg1_mask(config_word)   ((config_word) &= ~(1 << 3))
 
#define QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG   4
 
#define QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS   17
 
#define qlcnic_get_phy_speed(config_word)   (((config_word) >> 14) & 0x03)
 
#define qlcnic_set_phy_speed(config_word, val)   ((config_word) |= ((val & 0x03) << 14))
 
#define qlcnic_set_phy_duplex(config_word)   ((config_word) |= 1 << 13)
 
#define qlcnic_clear_phy_duplex(config_word)   ((config_word) &= ~(1 << 13))
 
#define qlcnic_get_phy_link(config_word)   _qlcnic_crb_get_bit(config_word, 10)
 
#define qlcnic_get_phy_duplex(config_word)   _qlcnic_crb_get_bit(config_word, 13)
 
#define QLCNIC_NIU_NON_PROMISC_MODE   0
 
#define QLCNIC_NIU_PROMISC_MODE   1
 
#define QLCNIC_NIU_ALLMULTI_MODE   2
 

Enumerations

enum  {
  QLCNIC_HW_H0_CH_HUB_ADR = 0x05, QLCNIC_HW_H1_CH_HUB_ADR = 0x0E, QLCNIC_HW_H2_CH_HUB_ADR = 0x03, QLCNIC_HW_H3_CH_HUB_ADR = 0x01,
  QLCNIC_HW_H4_CH_HUB_ADR = 0x06, QLCNIC_HW_H5_CH_HUB_ADR = 0x07, QLCNIC_HW_H6_CH_HUB_ADR = 0x08
}
 
enum  { QLCNIC_HW_MN_CRB_AGT_ADR = 0x15, QLCNIC_HW_MS_CRB_AGT_ADR = 0x25 }
 
enum  {
  QLCNIC_HW_PS_CRB_AGT_ADR = 0x73, QLCNIC_HW_SS_CRB_AGT_ADR = 0x20, QLCNIC_HW_RPMX3_CRB_AGT_ADR = 0x0b, QLCNIC_HW_QMS_CRB_AGT_ADR = 0x00,
  QLCNIC_HW_SQGS0_CRB_AGT_ADR = 0x01, QLCNIC_HW_SQGS1_CRB_AGT_ADR = 0x02, QLCNIC_HW_SQGS2_CRB_AGT_ADR = 0x03, QLCNIC_HW_SQGS3_CRB_AGT_ADR = 0x04,
  QLCNIC_HW_C2C0_CRB_AGT_ADR = 0x58, QLCNIC_HW_C2C1_CRB_AGT_ADR = 0x59, QLCNIC_HW_C2C2_CRB_AGT_ADR = 0x5a, QLCNIC_HW_RPMX2_CRB_AGT_ADR = 0x0a,
  QLCNIC_HW_RPMX4_CRB_AGT_ADR = 0x0c, QLCNIC_HW_RPMX7_CRB_AGT_ADR = 0x0f, QLCNIC_HW_RPMX9_CRB_AGT_ADR = 0x12, QLCNIC_HW_SMB_CRB_AGT_ADR = 0x18
}
 
enum  {
  QLCNIC_HW_NIU_CRB_AGT_ADR = 0x31, QLCNIC_HW_I2C0_CRB_AGT_ADR = 0x19, QLCNIC_HW_I2C1_CRB_AGT_ADR = 0x29, QLCNIC_HW_SN_CRB_AGT_ADR = 0x10,
  QLCNIC_HW_I2Q_CRB_AGT_ADR = 0x20, QLCNIC_HW_LPC_CRB_AGT_ADR = 0x22, QLCNIC_HW_ROMUSB_CRB_AGT_ADR = 0x21, QLCNIC_HW_QM_CRB_AGT_ADR = 0x66,
  QLCNIC_HW_SQG0_CRB_AGT_ADR = 0x60, QLCNIC_HW_SQG1_CRB_AGT_ADR = 0x61, QLCNIC_HW_SQG2_CRB_AGT_ADR = 0x62, QLCNIC_HW_SQG3_CRB_AGT_ADR = 0x63,
  QLCNIC_HW_RPMX1_CRB_AGT_ADR = 0x09, QLCNIC_HW_RPMX5_CRB_AGT_ADR = 0x0d, QLCNIC_HW_RPMX6_CRB_AGT_ADR = 0x0e, QLCNIC_HW_RPMX8_CRB_AGT_ADR = 0x11
}
 
enum  { QLCNIC_HW_PH_CRB_AGT_ADR = 0x1A, QLCNIC_HW_SRE_CRB_AGT_ADR = 0x50, QLCNIC_HW_EG_CRB_AGT_ADR = 0x51, QLCNIC_HW_RPMX0_CRB_AGT_ADR = 0x08 }
 
enum  {
  QLCNIC_HW_PEGN0_CRB_AGT_ADR = 0x40, QLCNIC_HW_PEGN1_CRB_AGT_ADR, QLCNIC_HW_PEGN2_CRB_AGT_ADR, QLCNIC_HW_PEGN3_CRB_AGT_ADR,
  QLCNIC_HW_PEGNI_CRB_AGT_ADR, QLCNIC_HW_PEGND_CRB_AGT_ADR, QLCNIC_HW_PEGNC_CRB_AGT_ADR, QLCNIC_HW_PEGR0_CRB_AGT_ADR,
  QLCNIC_HW_PEGR1_CRB_AGT_ADR, QLCNIC_HW_PEGR2_CRB_AGT_ADR, QLCNIC_HW_PEGR3_CRB_AGT_ADR, QLCNIC_HW_PEGN4_CRB_AGT_ADR
}
 
enum  {
  QLCNIC_HW_PEGS0_CRB_AGT_ADR = 0x40, QLCNIC_HW_PEGS1_CRB_AGT_ADR, QLCNIC_HW_PEGS2_CRB_AGT_ADR, QLCNIC_HW_PEGS3_CRB_AGT_ADR,
  QLCNIC_HW_PEGSI_CRB_AGT_ADR, QLCNIC_HW_PEGSD_CRB_AGT_ADR, QLCNIC_HW_PEGSC_CRB_AGT_ADR
}
 
enum  {
  QLCNIC_HW_CAS0_CRB_AGT_ADR = 0x46, QLCNIC_HW_CAS1_CRB_AGT_ADR = 0x47, QLCNIC_HW_CAS2_CRB_AGT_ADR = 0x48, QLCNIC_HW_CAS3_CRB_AGT_ADR = 0x49,
  QLCNIC_HW_NCM_CRB_AGT_ADR = 0x16, QLCNIC_HW_TMR_CRB_AGT_ADR = 0x17, QLCNIC_HW_XDMA_CRB_AGT_ADR = 0x05, QLCNIC_HW_OCM0_CRB_AGT_ADR = 0x06,
  QLCNIC_HW_OCM1_CRB_AGT_ADR = 0x07
}
 
enum  {
  QLCNIC_HW_PX_MAP_CRB_PH = 0, QLCNIC_HW_PX_MAP_CRB_PS, QLCNIC_HW_PX_MAP_CRB_MN, QLCNIC_HW_PX_MAP_CRB_MS,
  QLCNIC_HW_PX_MAP_CRB_PGR1, QLCNIC_HW_PX_MAP_CRB_SRE, QLCNIC_HW_PX_MAP_CRB_NIU, QLCNIC_HW_PX_MAP_CRB_QMN,
  QLCNIC_HW_PX_MAP_CRB_SQN0, QLCNIC_HW_PX_MAP_CRB_SQN1, QLCNIC_HW_PX_MAP_CRB_SQN2, QLCNIC_HW_PX_MAP_CRB_SQN3,
  QLCNIC_HW_PX_MAP_CRB_QMS, QLCNIC_HW_PX_MAP_CRB_SQS0, QLCNIC_HW_PX_MAP_CRB_SQS1, QLCNIC_HW_PX_MAP_CRB_SQS2,
  QLCNIC_HW_PX_MAP_CRB_SQS3, QLCNIC_HW_PX_MAP_CRB_PGN0, QLCNIC_HW_PX_MAP_CRB_PGN1, QLCNIC_HW_PX_MAP_CRB_PGN2,
  QLCNIC_HW_PX_MAP_CRB_PGN3, QLCNIC_HW_PX_MAP_CRB_PGND, QLCNIC_HW_PX_MAP_CRB_PGNI, QLCNIC_HW_PX_MAP_CRB_PGS0,
  QLCNIC_HW_PX_MAP_CRB_PGS1, QLCNIC_HW_PX_MAP_CRB_PGS2, QLCNIC_HW_PX_MAP_CRB_PGS3, QLCNIC_HW_PX_MAP_CRB_PGSD,
  QLCNIC_HW_PX_MAP_CRB_PGSI, QLCNIC_HW_PX_MAP_CRB_SN, QLCNIC_HW_PX_MAP_CRB_PGR2, QLCNIC_HW_PX_MAP_CRB_EG,
  QLCNIC_HW_PX_MAP_CRB_PH2, QLCNIC_HW_PX_MAP_CRB_PS2, QLCNIC_HW_PX_MAP_CRB_CAM, QLCNIC_HW_PX_MAP_CRB_CAS0,
  QLCNIC_HW_PX_MAP_CRB_CAS1, QLCNIC_HW_PX_MAP_CRB_CAS2, QLCNIC_HW_PX_MAP_CRB_C2C0, QLCNIC_HW_PX_MAP_CRB_C2C1,
  QLCNIC_HW_PX_MAP_CRB_TIMR, QLCNIC_HW_PX_MAP_CRB_PGR3, QLCNIC_HW_PX_MAP_CRB_RPMX1, QLCNIC_HW_PX_MAP_CRB_RPMX2,
  QLCNIC_HW_PX_MAP_CRB_RPMX3, QLCNIC_HW_PX_MAP_CRB_RPMX4, QLCNIC_HW_PX_MAP_CRB_RPMX5, QLCNIC_HW_PX_MAP_CRB_RPMX6,
  QLCNIC_HW_PX_MAP_CRB_RPMX7, QLCNIC_HW_PX_MAP_CRB_XDMA, QLCNIC_HW_PX_MAP_CRB_I2Q, QLCNIC_HW_PX_MAP_CRB_ROMUSB,
  QLCNIC_HW_PX_MAP_CRB_CAS3, QLCNIC_HW_PX_MAP_CRB_RPMX0, QLCNIC_HW_PX_MAP_CRB_RPMX8, QLCNIC_HW_PX_MAP_CRB_RPMX9,
  QLCNIC_HW_PX_MAP_CRB_OCM0, QLCNIC_HW_PX_MAP_CRB_OCM1, QLCNIC_HW_PX_MAP_CRB_SMB, QLCNIC_HW_PX_MAP_CRB_I2C0,
  QLCNIC_HW_PX_MAP_CRB_I2C1, QLCNIC_HW_PX_MAP_CRB_LPC, QLCNIC_HW_PX_MAP_CRB_PGNC, QLCNIC_HW_PX_MAP_CRB_PGR0
}
 
enum  { QLCNIC_TEMP_NORMAL = 0x1, QLCNIC_TEMP_WARN, QLCNIC_TEMP_PANIC }
 
enum  { QLCNIC_MGMT_FUNC = 0, QLCNIC_PRIV_FUNC = 1, QLCNIC_NON_PRIV_FUNC = 2 }
 
enum  { QLCNIC_PORT_DEFAULTS = 0, QLCNIC_ADD_VLAN = 1, QLCNIC_DEL_VLAN = 2 }
 

Macro Definition Documentation

#define _qlcnic_crb_get_bit (   var,
  bit 
)    ((var >> bit) & 0x1)

Definition at line 888 of file qlcnic_hdr.h.

#define BIT_0   0x1

Definition at line 194 of file qlcnic_hdr.h.

#define BIT_1   0x2

Definition at line 195 of file qlcnic_hdr.h.

#define BIT_10   0x400

Definition at line 204 of file qlcnic_hdr.h.

#define BIT_11   0x800

Definition at line 205 of file qlcnic_hdr.h.

#define BIT_12   0x1000

Definition at line 206 of file qlcnic_hdr.h.

#define BIT_13   0x2000

Definition at line 207 of file qlcnic_hdr.h.

#define BIT_14   0x4000

Definition at line 208 of file qlcnic_hdr.h.

#define BIT_15   0x8000

Definition at line 209 of file qlcnic_hdr.h.

#define BIT_16   0x10000

Definition at line 210 of file qlcnic_hdr.h.

#define BIT_17   0x20000

Definition at line 211 of file qlcnic_hdr.h.

#define BIT_18   0x40000

Definition at line 212 of file qlcnic_hdr.h.

#define BIT_19   0x80000

Definition at line 213 of file qlcnic_hdr.h.

#define BIT_2   0x4

Definition at line 196 of file qlcnic_hdr.h.

#define BIT_20   0x100000

Definition at line 214 of file qlcnic_hdr.h.

#define BIT_21   0x200000

Definition at line 215 of file qlcnic_hdr.h.

#define BIT_22   0x400000

Definition at line 216 of file qlcnic_hdr.h.

#define BIT_23   0x800000

Definition at line 217 of file qlcnic_hdr.h.

#define BIT_24   0x1000000

Definition at line 218 of file qlcnic_hdr.h.

#define BIT_25   0x2000000

Definition at line 219 of file qlcnic_hdr.h.

#define BIT_26   0x4000000

Definition at line 220 of file qlcnic_hdr.h.

#define BIT_27   0x8000000

Definition at line 221 of file qlcnic_hdr.h.

#define BIT_28   0x10000000

Definition at line 222 of file qlcnic_hdr.h.

#define BIT_29   0x20000000

Definition at line 223 of file qlcnic_hdr.h.

#define BIT_3   0x8

Definition at line 197 of file qlcnic_hdr.h.

#define BIT_30   0x40000000

Definition at line 224 of file qlcnic_hdr.h.

#define BIT_31   0x80000000

Definition at line 225 of file qlcnic_hdr.h.

#define BIT_4   0x10

Definition at line 198 of file qlcnic_hdr.h.

#define BIT_5   0x20

Definition at line 199 of file qlcnic_hdr.h.

#define BIT_6   0x40

Definition at line 200 of file qlcnic_hdr.h.

#define BIT_7   0x80

Definition at line 201 of file qlcnic_hdr.h.

#define BIT_8   0x100

Definition at line 202 of file qlcnic_hdr.h.

#define BIT_9   0x200

Definition at line 203 of file qlcnic_hdr.h.

#define CRB_CMDPEG_STATE   (QLCNIC_REG(0x50))

Definition at line 577 of file qlcnic_hdr.h.

#define CRB_DRIVER_VERSION   (QLCNIC_REG(0x2a0))

Definition at line 588 of file qlcnic_hdr.h.

#define CRB_FW_CAPABILITIES_1   (QLCNIC_CAM_RAM(0x128))

Definition at line 590 of file qlcnic_hdr.h.

#define CRB_FW_CAPABILITIES_2   (QLCNIC_CAM_RAM(0x12c))

Definition at line 591 of file qlcnic_hdr.h.

#define CRB_MAC_BLOCK_START   (QLCNIC_CAM_RAM(0x1c0))

Definition at line 592 of file qlcnic_hdr.h.

#define CRB_PF_LINK_SPEED_1   (QLCNIC_REG(0xe8))

Definition at line 581 of file qlcnic_hdr.h.

#define CRB_PF_LINK_SPEED_2   (QLCNIC_REG(0xec))

Definition at line 582 of file qlcnic_hdr.h.

#define CRB_RCVPEG_STATE   (QLCNIC_REG(0x13c))

Definition at line 578 of file qlcnic_hdr.h.

#define CRB_TEMP_STATE   (QLCNIC_REG(0x1b4))

Definition at line 584 of file qlcnic_hdr.h.

#define CRB_V2P (   port)    (CRB_V2P_0+((port)*4))

Definition at line 587 of file qlcnic_hdr.h.

#define CRB_V2P_0   (QLCNIC_REG(0x290))

Definition at line 586 of file qlcnic_hdr.h.

#define CRB_XG_STATE_P3P   (QLCNIC_REG(0x98))

Definition at line 580 of file qlcnic_hdr.h.

#define FLASH_ROM_DATA   0x42150000

Definition at line 780 of file qlcnic_hdr.h.

#define FLASH_ROM_WINDOW   0x42110030

Definition at line 779 of file qlcnic_hdr.h.

#define FW_FAIL_THRESH   2

Definition at line 736 of file qlcnic_hdr.h.

#define FW_POLL_DELAY   (1 * HZ)

Definition at line 735 of file qlcnic_hdr.h.

#define ISR_INT_MASK   (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))

Definition at line 433 of file qlcnic_hdr.h.

#define ISR_INT_MASK_SLOW   (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))

Definition at line 434 of file qlcnic_hdr.h.

#define ISR_INT_STATE_REG   (QLCNIC_PCIX_PS_REG(PCIE_MISCCFG_RC))

Definition at line 665 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_MASK   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK))

Definition at line 436 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_MASK_F1   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F1))

Definition at line 438 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_MASK_F2   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F2))

Definition at line 440 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_MASK_F3   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F3))

Definition at line 442 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_MASK_F4   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F4))

Definition at line 444 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_MASK_F5   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F5))

Definition at line 446 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_MASK_F6   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F6))

Definition at line 448 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_MASK_F7   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F7))

Definition at line 450 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_STATUS   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS))

Definition at line 435 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_STATUS_F1   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))

Definition at line 437 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_STATUS_F2   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))

Definition at line 439 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_STATUS_F3   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))

Definition at line 441 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_STATUS_F4   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))

Definition at line 443 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_STATUS_F5   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))

Definition at line 445 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_STATUS_F6   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))

Definition at line 447 of file qlcnic_hdr.h.

#define ISR_INT_TARGET_STATUS_F7   (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))

Definition at line 449 of file qlcnic_hdr.h.

#define ISR_INT_VECTOR   (QLCNIC_PCIX_PS_REG(PCIX_INT_VECTOR))

Definition at line 432 of file qlcnic_hdr.h.

#define ISR_LEGACY_INT_TRIGGERED (   VAL)    (((VAL) & 0x300) == 0x200)

Definition at line 748 of file qlcnic_hdr.h.

#define ISR_MSI_INT_TRIGGER (   FUNC)    (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC)))

Definition at line 747 of file qlcnic_hdr.h.

#define LSB (   x)    ((uint8_t)(x))

Definition at line 826 of file qlcnic_hdr.h.

#define LSD (   x)    ((uint32_t)((uint64_t)(x)))

Definition at line 832 of file qlcnic_hdr.h.

#define LSW (   x)    ((uint16_t)((uint32_t)(x)))

Definition at line 829 of file qlcnic_hdr.h.

#define MIU_TEST_ADDR_HI   0x41000098

Definition at line 778 of file qlcnic_hdr.h.

#define MIU_TEST_ADDR_LO   0x41000094

Definition at line 777 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_ADDR_HI   (0x08)

Definition at line 508 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_ADDR_LO   (0x04)

Definition at line 507 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_ADDR_MASK   0xfffffff8

Definition at line 520 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_BASE   (0x90)

Definition at line 505 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_RDDATA (   i)    (0x18+(0x10*((i)>>1))+(4*((i)&1)))

Definition at line 518 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_RDDATA_HI   (0x1c)

Definition at line 515 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_RDDATA_LO   (0x18)

Definition at line 514 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_RDDATA_UPPER_HI   (0x2c)

Definition at line 517 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_RDDATA_UPPER_LO   (0x28)

Definition at line 516 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_UPPER_ADDR (   off)    (0)

Definition at line 521 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_WRDATA (   i)    (0x10+(0x10*((i)>>1))+(4*((i)&1)))

Definition at line 513 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_WRDATA_HI   (0x14)

Definition at line 510 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_WRDATA_LO   (0x10)

Definition at line 509 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_WRDATA_UPPER_HI   (0x24)

Definition at line 512 of file qlcnic_hdr.h.

#define MIU_TEST_AGT_WRDATA_UPPER_LO   (0x20)

Definition at line 511 of file qlcnic_hdr.h.

#define MIU_TEST_CTR   0x41000090

Definition at line 776 of file qlcnic_hdr.h.

#define MSB (   x)    ((uint8_t)((uint16_t)(x) >> 8))

Definition at line 827 of file qlcnic_hdr.h.

#define MSD (   x)    ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))

Definition at line 833 of file qlcnic_hdr.h.

#define MSW (   x)    ((uint16_t)((uint32_t)(x) >> 16))

Definition at line 830 of file qlcnic_hdr.h.

#define NIC_CRB_BASE   (QLCNIC_CAM_RAM(0x200))

Definition at line 566 of file qlcnic_hdr.h.

#define NIC_CRB_BASE_2   (QLCNIC_CAM_RAM(0x700))

Definition at line 567 of file qlcnic_hdr.h.

#define P3P_LINK_SPEED_MASK   0xff

Definition at line 551 of file qlcnic_hdr.h.

#define P3P_LINK_SPEED_MHZ   100

Definition at line 550 of file qlcnic_hdr.h.

#define P3P_LINK_SPEED_REG (   pcifn)    (CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4))

Definition at line 552 of file qlcnic_hdr.h.

#define P3P_LINK_SPEED_VAL (   pcifn,
  reg 
)    (((reg) >> (8 * ((pcifn) & 0x3))) & P3P_LINK_SPEED_MASK)

Definition at line 554 of file qlcnic_hdr.h.

#define PCIE_CHICKEN3   (0x120c8)

Definition at line 663 of file qlcnic_hdr.h.

#define PCIE_MAX_MASTER_SPLIT   (0x14048)

Definition at line 666 of file qlcnic_hdr.h.

#define PCIE_MISCCFG_RC   (0x1206c)

Definition at line 661 of file qlcnic_hdr.h.

#define PCIE_SEM0_LOCK   (0x1c000)

Definition at line 654 of file qlcnic_hdr.h.

#define PCIE_SEM0_UNLOCK   (0x1c004)

Definition at line 655 of file qlcnic_hdr.h.

#define PCIE_SEM_LOCK (   N)    (PCIE_SEM0_LOCK + 8*(N))

Definition at line 656 of file qlcnic_hdr.h.

#define PCIE_SEM_UNLOCK (   N)    (PCIE_SEM0_UNLOCK + 8*(N))

Definition at line 657 of file qlcnic_hdr.h.

#define PCIE_SETUP_FUNCTION   (0x12040)

Definition at line 659 of file qlcnic_hdr.h.

#define PCIE_SETUP_FUNCTION2   (0x12048)

Definition at line 660 of file qlcnic_hdr.h.

#define PCIE_TGT_SPLIT_CHICKEN   (0x12080)

Definition at line 662 of file qlcnic_hdr.h.

#define PCIX_INT_MASK   (0x10104)

Definition at line 625 of file qlcnic_hdr.h.

#define PCIX_INT_VECTOR   (0x10100)

Definition at line 624 of file qlcnic_hdr.h.

#define PCIX_INT_VECTOR_BIT_F0   0x0080

Definition at line 753 of file qlcnic_hdr.h.

#define PCIX_INT_VECTOR_BIT_F1   0x0100

Definition at line 754 of file qlcnic_hdr.h.

#define PCIX_INT_VECTOR_BIT_F2   0x0200

Definition at line 755 of file qlcnic_hdr.h.

#define PCIX_INT_VECTOR_BIT_F3   0x0400

Definition at line 756 of file qlcnic_hdr.h.

#define PCIX_INT_VECTOR_BIT_F4   0x0800

Definition at line 757 of file qlcnic_hdr.h.

#define PCIX_INT_VECTOR_BIT_F5   0x1000

Definition at line 758 of file qlcnic_hdr.h.

#define PCIX_INT_VECTOR_BIT_F6   0x2000

Definition at line 759 of file qlcnic_hdr.h.

#define PCIX_INT_VECTOR_BIT_F7   0x4000

Definition at line 760 of file qlcnic_hdr.h.

#define PCIX_MSI_F (   i)    (0x13000+((i)*4))

Definition at line 648 of file qlcnic_hdr.h.

#define PCIX_OCM_WINDOW   (0x10800)

Definition at line 627 of file qlcnic_hdr.h.

#define PCIX_OCM_WINDOW_REG (   func)    (PCIX_OCM_WINDOW + 0x4 * (func))

Definition at line 628 of file qlcnic_hdr.h.

#define PCIX_PS_OP_ADDR_HI   (0x10004)

Definition at line 622 of file qlcnic_hdr.h.

#define PCIX_PS_OP_ADDR_LO   (0x10000)

Definition at line 620 of file qlcnic_hdr.h.

#define PCIX_TARGET_MASK   (0x10128)

Definition at line 639 of file qlcnic_hdr.h.

#define PCIX_TARGET_MASK_F1   (0x10170)

Definition at line 640 of file qlcnic_hdr.h.

#define PCIX_TARGET_MASK_F2   (0x10174)

Definition at line 641 of file qlcnic_hdr.h.

#define PCIX_TARGET_MASK_F3   (0x10178)

Definition at line 642 of file qlcnic_hdr.h.

#define PCIX_TARGET_MASK_F4   (0x10370)

Definition at line 643 of file qlcnic_hdr.h.

#define PCIX_TARGET_MASK_F5   (0x10374)

Definition at line 644 of file qlcnic_hdr.h.

#define PCIX_TARGET_MASK_F6   (0x10378)

Definition at line 645 of file qlcnic_hdr.h.

#define PCIX_TARGET_MASK_F7   (0x1037c)

Definition at line 646 of file qlcnic_hdr.h.

#define PCIX_TARGET_STATUS   (0x10118)

Definition at line 630 of file qlcnic_hdr.h.

#define PCIX_TARGET_STATUS_F1   (0x10160)

Definition at line 631 of file qlcnic_hdr.h.

#define PCIX_TARGET_STATUS_F2   (0x10164)

Definition at line 632 of file qlcnic_hdr.h.

#define PCIX_TARGET_STATUS_F3   (0x10168)

Definition at line 633 of file qlcnic_hdr.h.

#define PCIX_TARGET_STATUS_F4   (0x10360)

Definition at line 634 of file qlcnic_hdr.h.

#define PCIX_TARGET_STATUS_F5   (0x10364)

Definition at line 635 of file qlcnic_hdr.h.

#define PCIX_TARGET_STATUS_F6   (0x10368)

Definition at line 636 of file qlcnic_hdr.h.

#define PCIX_TARGET_STATUS_F7   (0x1036c)

Definition at line 637 of file qlcnic_hdr.h.

#define PHY_LOCK_DRIVER   0x44524956

Definition at line 617 of file qlcnic_hdr.h.

#define QLC_DEV_CHECK_ACTIVE (   VAL,
  FN 
)    ((VAL) & (1 << (FN * 4)))

Definition at line 714 of file qlcnic_hdr.h.

#define QLC_DEV_CLR_REF_CNT (   VAL,
  FN 
)    ((VAL) &= ~(1 << (FN * 4)))

Definition at line 716 of file qlcnic_hdr.h.

#define QLC_DEV_CLR_RST_QSCNT (   VAL,
  FN 
)    ((VAL) &= ~(3 << (FN * 4)))

Definition at line 719 of file qlcnic_hdr.h.

#define QLC_DEV_DRV_DEFAULT   0x11111111

Definition at line 824 of file qlcnic_hdr.h.

#define QLC_DEV_GET_DRV (   VAL,
  FN 
)    (0xf & ((VAL) >> (FN * 4)))

Definition at line 721 of file qlcnic_hdr.h.

#define QLC_DEV_SET_DRV (   VAL,
  FN 
)    ((VAL) << (FN * 4))

Definition at line 722 of file qlcnic_hdr.h.

#define QLC_DEV_SET_QSCNT_RDY (   VAL,
  FN 
)    ((VAL) |= (2 << (FN * 4)))

Definition at line 718 of file qlcnic_hdr.h.

#define QLC_DEV_SET_REF_CNT (   VAL,
  FN 
)    ((VAL) |= (1 << (FN * 4)))

Definition at line 715 of file qlcnic_hdr.h.

#define QLC_DEV_SET_RST_RDY (   VAL,
  FN 
)    ((VAL) |= (1 << (FN * 4)))

Definition at line 717 of file qlcnic_hdr.h.

#define QLCNIC_ADDR_DDR_NET   (0x0000000000000000ULL)

Definition at line 463 of file qlcnic_hdr.h.

#define QLCNIC_ADDR_DDR_NET_MAX   (0x000000000fffffffULL)

Definition at line 464 of file qlcnic_hdr.h.

#define QLCNIC_ADDR_OCM0   (0x0000000200000000ULL)

Definition at line 465 of file qlcnic_hdr.h.

#define QLCNIC_ADDR_OCM0_MAX   (0x00000002000fffffULL)

Definition at line 466 of file qlcnic_hdr.h.

#define QLCNIC_ADDR_OCM1   (0x0000000200400000ULL)

Definition at line 467 of file qlcnic_hdr.h.

#define QLCNIC_ADDR_OCM1_MAX   (0x00000002004fffffULL)

Definition at line 468 of file qlcnic_hdr.h.

#define QLCNIC_ADDR_QDR_NET   (0x0000000300000000ULL)

Definition at line 469 of file qlcnic_hdr.h.

#define QLCNIC_ADDR_QDR_NET_MAX   (0x0000000307ffffffULL)

Definition at line 470 of file qlcnic_hdr.h.

#define QLCNIC_ARG1_CRB_OFFSET   (QLCNIC_REG(0x1c))

Definition at line 572 of file qlcnic_hdr.h.

#define QLCNIC_ARG2_CRB_OFFSET   (QLCNIC_REG(0x20))

Definition at line 573 of file qlcnic_hdr.h.

#define QLCNIC_ARG3_CRB_OFFSET   (QLCNIC_REG(0x24))

Definition at line 574 of file qlcnic_hdr.h.

#define QLCNIC_CAM_RAM (   reg)    (QLCNIC_CAM_RAM_BASE + (reg))

Definition at line 558 of file qlcnic_hdr.h.

#define QLCNIC_CAM_RAM_BASE   (QLCNIC_CRB_CAM + 0x02000)

Definition at line 557 of file qlcnic_hdr.h.

#define QLCNIC_CDRP_CRB_OFFSET   (QLCNIC_REG(0x18))

Definition at line 571 of file qlcnic_hdr.h.

#define qlcnic_clear_phy_duplex (   config_word)    ((config_word) &= ~(1 << 13))

Definition at line 1012 of file qlcnic_hdr.h.

#define QLCNIC_CMDPEG_CHECK_DELAY   500

Definition at line 743 of file qlcnic_hdr.h.

#define QLCNIC_CMDPEG_CHECK_RETRY_COUNT   60

Definition at line 742 of file qlcnic_hdr.h.

#define QLCNIC_CRB_CAM   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_CAM)

Definition at line 461 of file qlcnic_hdr.h.

#define QLCNIC_CRB_DDR_NET   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_MN)

Definition at line 426 of file qlcnic_hdr.h.

#define QLCNIC_CRB_DEV_NPAR_STATE   (QLCNIC_CAM_RAM(0x19c))

Definition at line 695 of file qlcnic_hdr.h.

#define QLCNIC_CRB_DEV_PARTITION_INFO   (QLCNIC_CAM_RAM(0x14c))

Definition at line 693 of file qlcnic_hdr.h.

#define QLCNIC_CRB_DEV_STATE   (QLCNIC_CAM_RAM(0x140))

Definition at line 689 of file qlcnic_hdr.h.

#define QLCNIC_CRB_DRV_ACTIVE   (QLCNIC_CAM_RAM(0x138))

Definition at line 688 of file qlcnic_hdr.h.

#define QLCNIC_CRB_DRV_IDC_VER   (QLCNIC_CAM_RAM(0x174))

Definition at line 694 of file qlcnic_hdr.h.

#define QLCNIC_CRB_DRV_SCRATCH   (QLCNIC_CAM_RAM(0x148))

Definition at line 692 of file qlcnic_hdr.h.

#define QLCNIC_CRB_DRV_STATE   (QLCNIC_CAM_RAM(0x144))

Definition at line 691 of file qlcnic_hdr.h.

#define QLCNIC_CRB_EPG   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_EG)

Definition at line 410 of file qlcnic_hdr.h.

#define QLCNIC_CRB_I2C0   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0)

Definition at line 413 of file qlcnic_hdr.h.

#define QLCNIC_CRB_I2Q   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q)

Definition at line 411 of file qlcnic_hdr.h.

#define QLCNIC_CRB_MAX   QLCNIC_PCI_CRB_WINDOW(64)

Definition at line 415 of file qlcnic_hdr.h.

#define QLCNIC_CRB_NIU   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_NIU)

Definition at line 406 of file qlcnic_hdr.h.

#define QLCNIC_CRB_PCIE   QLCNIC_CRB_PCIX_MD

Definition at line 430 of file qlcnic_hdr.h.

#define QLCNIC_CRB_PCIX_HOST   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH)

Definition at line 417 of file qlcnic_hdr.h.

#define QLCNIC_CRB_PCIX_HOST2   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH2)

Definition at line 418 of file qlcnic_hdr.h.

#define QLCNIC_CRB_PCIX_MD   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PS)

Definition at line 429 of file qlcnic_hdr.h.

#define QLCNIC_CRB_PEG_NET_0   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN0)

Definition at line 419 of file qlcnic_hdr.h.

#define QLCNIC_CRB_PEG_NET_1   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN1)

Definition at line 420 of file qlcnic_hdr.h.

#define QLCNIC_CRB_PEG_NET_2   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN2)

Definition at line 421 of file qlcnic_hdr.h.

#define QLCNIC_CRB_PEG_NET_3   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN3)

Definition at line 422 of file qlcnic_hdr.h.

#define QLCNIC_CRB_PEG_NET_4   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SQS2)

Definition at line 423 of file qlcnic_hdr.h.

#define QLCNIC_CRB_PEG_NET_D   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGND)

Definition at line 424 of file qlcnic_hdr.h.

#define QLCNIC_CRB_PEG_NET_I   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGNI)

Definition at line 425 of file qlcnic_hdr.h.

#define QLCNIC_CRB_QDR_NET   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SN)

Definition at line 427 of file qlcnic_hdr.h.

#define QLCNIC_CRB_ROMUSB   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB)

Definition at line 408 of file qlcnic_hdr.h.

#define QLCNIC_CRB_SMB   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB)

Definition at line 414 of file qlcnic_hdr.h.

#define QLCNIC_CRB_SRE   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE)

Definition at line 407 of file qlcnic_hdr.h.

#define QLCNIC_CRB_TIMER   QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_TIMR)

Definition at line 412 of file qlcnic_hdr.h.

#define QLCNIC_CRB_WIN_LOCK_ID   (QLCNIC_CAM_RAM(0x124))

Definition at line 564 of file qlcnic_hdr.h.

#define QLCNIC_DEV_BADBAD   0xbad0bad0

Definition at line 708 of file qlcnic_hdr.h.

#define QLCNIC_DEV_COLD   0x1

Definition at line 700 of file qlcnic_hdr.h.

#define QLCNIC_DEV_FAILED   0x6

Definition at line 705 of file qlcnic_hdr.h.

#define QLCNIC_DEV_INITIALIZING   0x2

Definition at line 701 of file qlcnic_hdr.h.

#define QLCNIC_DEV_NEED_QUISCENT   0x5

Definition at line 704 of file qlcnic_hdr.h.

#define QLCNIC_DEV_NEED_RESET   0x4

Definition at line 703 of file qlcnic_hdr.h.

#define QLCNIC_DEV_NPAR_NON_OPER   0 /* NON Operational */

Definition at line 710 of file qlcnic_hdr.h.

#define QLCNIC_DEV_NPAR_OPER   1 /* NPAR Operational */

Definition at line 711 of file qlcnic_hdr.h.

#define QLCNIC_DEV_NPAR_OPER_TIMEO   30 /* Operational time out */

Definition at line 712 of file qlcnic_hdr.h.

#define QLCNIC_DEV_QUISCENT   0x7

Definition at line 706 of file qlcnic_hdr.h.

#define QLCNIC_DEV_READY   0x3

Definition at line 702 of file qlcnic_hdr.h.

#define QLCNIC_DMA_WATCHDOG_CTRL   (QLCNIC_CAM_RAM(0x14))

Definition at line 684 of file qlcnic_hdr.h.

#define QLCNIC_DRV_OP_MODE   0x1b2170

Definition at line 770 of file qlcnic_hdr.h.

#define qlcnic_encode_temp (   val,
  state 
)    (((val) << 16) | (state))

Definition at line 604 of file qlcnic_hdr.h.

#define QLCNIC_FLASH_LOCK_ID   0x001B2100

Definition at line 793 of file qlcnic_hdr.h.

#define QLCNIC_FLASH_SEM2_LK   0x0013C010

Definition at line 791 of file qlcnic_hdr.h.

#define QLCNIC_FLASH_SEM2_ULK   0x0013C014

Definition at line 792 of file qlcnic_hdr.h.

#define QLCNIC_FW_API   0x1b216c

Definition at line 769 of file qlcnic_hdr.h.

#define QLCNIC_FW_DUMP_REG1   0x00130060

Definition at line 789 of file qlcnic_hdr.h.

#define QLCNIC_FW_DUMP_REG2   0x001e0000

Definition at line 790 of file qlcnic_hdr.h.

#define QLCNIC_FW_VERSION_MAJOR   (QLCNIC_CAM_RAM(0x150))

Definition at line 559 of file qlcnic_hdr.h.

#define QLCNIC_FW_VERSION_MINOR   (QLCNIC_CAM_RAM(0x154))

Definition at line 560 of file qlcnic_hdr.h.

#define QLCNIC_FW_VERSION_SUB   (QLCNIC_CAM_RAM(0x158))

Definition at line 561 of file qlcnic_hdr.h.

#define QLCNIC_FWERROR_CODE (   code)    ((code >> 8) & 0x1fffff)

Definition at line 732 of file qlcnic_hdr.h.

#define QLCNIC_FWERROR_FAN_FAILURE   0x16

Definition at line 733 of file qlcnic_hdr.h.

#define QLCNIC_FWERROR_PEGNUM (   code)    ((code) & 0xff)

Definition at line 731 of file qlcnic_hdr.h.

#define qlcnic_gb_get_gb0_mask (   config_word)    _qlcnic_crb_get_bit((config_word), 0)

Definition at line 926 of file qlcnic_hdr.h.

#define qlcnic_gb_get_gb1_mask (   config_word)    _qlcnic_crb_get_bit((config_word), 2)

Definition at line 928 of file qlcnic_hdr.h.

#define qlcnic_gb_get_gb2_mask (   config_word)    _qlcnic_crb_get_bit((config_word), 4)

Definition at line 930 of file qlcnic_hdr.h.

#define qlcnic_gb_get_gb3_mask (   config_word)    _qlcnic_crb_get_bit((config_word), 6)

Definition at line 932 of file qlcnic_hdr.h.

#define qlcnic_gb_get_rx_flowctl (   config_word)    _qlcnic_crb_get_bit((config_word), 5)

Definition at line 908 of file qlcnic_hdr.h.

#define qlcnic_gb_rx_flowctl (   config_word)    ((config_word) |= 1 << 5)

Definition at line 906 of file qlcnic_hdr.h.

#define qlcnic_gb_set_gb0_mask (   config_word)    ((config_word) |= 1 << 0)

Definition at line 917 of file qlcnic_hdr.h.

#define qlcnic_gb_set_gb1_mask (   config_word)    ((config_word) |= 1 << 2)

Definition at line 919 of file qlcnic_hdr.h.

#define qlcnic_gb_set_gb2_mask (   config_word)    ((config_word) |= 1 << 4)

Definition at line 921 of file qlcnic_hdr.h.

#define qlcnic_gb_set_gb3_mask (   config_word)    ((config_word) |= 1 << 6)

Definition at line 923 of file qlcnic_hdr.h.

#define qlcnic_gb_unset_gb0_mask (   config_word)    ((config_word) &= ~(1 << 0))

Definition at line 935 of file qlcnic_hdr.h.

#define qlcnic_gb_unset_gb1_mask (   config_word)    ((config_word) &= ~(1 << 2))

Definition at line 937 of file qlcnic_hdr.h.

#define qlcnic_gb_unset_gb2_mask (   config_word)    ((config_word) &= ~(1 << 4))

Definition at line 939 of file qlcnic_hdr.h.

#define qlcnic_gb_unset_gb3_mask (   config_word)    ((config_word) &= ~(1 << 6))

Definition at line 941 of file qlcnic_hdr.h.

#define qlcnic_gb_unset_rx_flowctl (   config_word)    ((config_word) &= ~(1 << 5))

Definition at line 910 of file qlcnic_hdr.h.

#define qlcnic_get_phy_duplex (   config_word)    _qlcnic_crb_get_bit(config_word, 13)

Definition at line 1017 of file qlcnic_hdr.h.

#define qlcnic_get_phy_link (   config_word)    _qlcnic_crb_get_bit(config_word, 10)

Definition at line 1015 of file qlcnic_hdr.h.

#define qlcnic_get_phy_speed (   config_word)    (((config_word) >> 14) & 0x03)

Definition at line 1006 of file qlcnic_hdr.h.

#define qlcnic_get_temp_state (   x)    ((x) & 0xffff)

Definition at line 603 of file qlcnic_hdr.h.

#define qlcnic_get_temp_val (   x)    ((x) >> 16)

Definition at line 602 of file qlcnic_hdr.h.

#define QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT   45

Definition at line 745 of file qlcnic_hdr.h.

#define QLCNIC_HEARTBEAT_PERIOD_MSECS   200

Definition at line 744 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C0   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C0_CRB_AGT_ADR)

Definition at line 252 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C1   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C1_CRB_AGT_ADR)

Definition at line 254 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAM   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_NCM_CRB_AGT_ADR)

Definition at line 347 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS0   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS0_CRB_AGT_ADR)

Definition at line 298 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS1   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS1_CRB_AGT_ADR)

Definition at line 300 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS2   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS2_CRB_AGT_ADR)

Definition at line 302 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS3   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS3_CRB_AGT_ADR)

Definition at line 304 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_EG   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_EG_CRB_AGT_ADR)

Definition at line 276 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0   ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C0_CRB_AGT_ADR)

Definition at line 269 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1   ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C1_CRB_AGT_ADR)

Definition at line 271 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_I2Q_CRB_AGT_ADR)

Definition at line 355 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_LPC   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_LPC_CRB_AGT_ADR)

Definition at line 363 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_MN   ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MN_CRB_AGT_ADR)

Definition at line 229 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_MS   ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MS_CRB_AGT_ADR)

Definition at line 233 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_NIU   ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_NIU_CRB_AGT_ADR)

Definition at line 267 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM0_CRB_AGT_ADR)

Definition at line 359 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM1   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM1_CRB_AGT_ADR)

Definition at line 361 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN0_CRB_AGT_ADR)

Definition at line 311 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN1_CRB_AGT_ADR)

Definition at line 313 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN2_CRB_AGT_ADR)

Definition at line 315 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN3_CRB_AGT_ADR)

Definition at line 317 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN4_CRB_AGT_ADR)

Definition at line 319 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNC_CRB_AGT_ADR)

Definition at line 321 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGND   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGND_CRB_AGT_ADR)

Definition at line 309 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNI_CRB_AGT_ADR)

Definition at line 307 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR0   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR0_CRB_AGT_ADR)

Definition at line 323 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR1   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR1_CRB_AGT_ADR)

Definition at line 325 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR2   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR2_CRB_AGT_ADR)

Definition at line 327 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR3   ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR3_CRB_AGT_ADR)

Definition at line 329 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS0_CRB_AGT_ADR)

Definition at line 336 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS1_CRB_AGT_ADR)

Definition at line 338 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS2_CRB_AGT_ADR)

Definition at line 340 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS3_CRB_AGT_ADR)

Definition at line 342 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSC   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSC_CRB_AGT_ADR)

Definition at line 344 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSD   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSD_CRB_AGT_ADR)

Definition at line 334 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI   ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSI_CRB_AGT_ADR)

Definition at line 332 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PH   ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_PH_CRB_AGT_ADR)

Definition at line 231 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PS   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_PS_CRB_AGT_ADR)

Definition at line 236 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMN   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_QM_CRB_AGT_ADR)

Definition at line 280 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMS   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_QMS_CRB_AGT_ADR)

Definition at line 242 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_ROMUSB_CRB_AGT_ADR)

Definition at line 357 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX0_CRB_AGT_ADR)

Definition at line 278 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX1_CRB_AGT_ADR)

Definition at line 290 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX2_CRB_AGT_ADR)

Definition at line 256 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX3_CRB_AGT_ADR)

Definition at line 240 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX4_CRB_AGT_ADR)

Definition at line 258 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX5_CRB_AGT_ADR)

Definition at line 292 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX6_CRB_AGT_ADR)

Definition at line 294 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX7_CRB_AGT_ADR)

Definition at line 260 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX8_CRB_AGT_ADR)

Definition at line 296 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX9_CRB_AGT_ADR)

Definition at line 262 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SMB   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SMB_CRB_AGT_ADR)

Definition at line 264 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SN   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_SN_CRB_AGT_ADR)

Definition at line 353 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG0_CRB_AGT_ADR)

Definition at line 282 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG1_CRB_AGT_ADR)

Definition at line 284 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG2_CRB_AGT_ADR)

Definition at line 286 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG3_CRB_AGT_ADR)

Definition at line 288 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS0   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS0_CRB_AGT_ADR)

Definition at line 244 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS1   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS1_CRB_AGT_ADR)

Definition at line 246 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS2   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS2_CRB_AGT_ADR)

Definition at line 248 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS3   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS3_CRB_AGT_ADR)

Definition at line 250 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SRE   ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SRE_CRB_AGT_ADR)

Definition at line 274 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SS   ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SS_CRB_AGT_ADR)

Definition at line 238 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_TMR_CRB_AGT_ADR)

Definition at line 349 of file qlcnic_hdr.h.

#define QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA   ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_XDMA_CRB_AGT_ADR)

Definition at line 351 of file qlcnic_hdr.h.

#define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR   0x67

Definition at line 124 of file qlcnic_hdr.h.

#define QLCNIC_I2Q_CLR_PCI_HI   (QLCNIC_CRB_I2Q + 0x00034)

Definition at line 368 of file qlcnic_hdr.h.

#define QLCNIC_INIT_TIMEOUT_SECS   30

Definition at line 739 of file qlcnic_hdr.h.

#define QLCNIC_LEGACY_INTR_CONFIG

Definition at line 835 of file qlcnic_hdr.h.

#define QLCNIC_MAX_PCI_FUNC   8

Definition at line 772 of file qlcnic_hdr.h.

#define QLCNIC_MAX_VLAN_FILTERS   64

Definition at line 773 of file qlcnic_hdr.h.

#define QLCNIC_MIU_CONTROL   (0x000)

Definition at line 475 of file qlcnic_hdr.h.

#define QLCNIC_MIU_MN_CONTROL   (QLCNIC_CRB_DDR_NET+QLCNIC_MIU_CONTROL)

Definition at line 476 of file qlcnic_hdr.h.

#define QLCNIC_MSIX_BASE   0x132110

Definition at line 771 of file qlcnic_hdr.h.

#define QLCNIC_NIU_ALLMULTI_MODE   2

Definition at line 1022 of file qlcnic_hdr.h.

#define QLCNIC_NIU_GB_MAC_CONFIG_0 (   I)    (QLCNIC_CRB_NIU + 0x30000 + (I)*0x10000)

Definition at line 489 of file qlcnic_hdr.h.

#define QLCNIC_NIU_GB_MAC_CONFIG_1 (   I)    (QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000)

Definition at line 491 of file qlcnic_hdr.h.

#define QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG   4

Definition at line 984 of file qlcnic_hdr.h.

#define QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS   17

Definition at line 985 of file qlcnic_hdr.h.

#define QLCNIC_NIU_GB_PAUSE_CTL   (QLCNIC_CRB_NIU + 0x0030c)

Definition at line 486 of file qlcnic_hdr.h.

#define QLCNIC_NIU_MAX_GBE_PORTS   4

Definition at line 482 of file qlcnic_hdr.h.

#define QLCNIC_NIU_MAX_XG_PORTS   2

Definition at line 483 of file qlcnic_hdr.h.

#define QLCNIC_NIU_MODE   (QLCNIC_CRB_NIU + 0x00000)

Definition at line 485 of file qlcnic_hdr.h.

#define QLCNIC_NIU_NON_PROMISC_MODE   0

Definition at line 1020 of file qlcnic_hdr.h.

#define QLCNIC_NIU_PHY_WAITLEN   200000

Definition at line 479 of file qlcnic_hdr.h.

#define QLCNIC_NIU_PHY_WAITMAX   50

Definition at line 481 of file qlcnic_hdr.h.

#define QLCNIC_NIU_PROMISC_MODE   1

Definition at line 1021 of file qlcnic_hdr.h.

#define QLCNIC_NIU_XG_PAUSE_CTL   (QLCNIC_CRB_NIU + 0x00098)

Definition at line 487 of file qlcnic_hdr.h.

#define QLCNIC_PCI_2MB_SIZE   (0x00200000UL)

Definition at line 458 of file qlcnic_hdr.h.

#define QLCNIC_PCI_CAMQM   (0x04800000UL)

Definition at line 456 of file qlcnic_hdr.h.

#define QLCNIC_PCI_CAMQM_2M_BASE   (0x000ff800UL)

Definition at line 459 of file qlcnic_hdr.h.

#define QLCNIC_PCI_CAMQM_END   (0x04800800UL)

Definition at line 457 of file qlcnic_hdr.h.

#define QLCNIC_PCI_CRB_WINDOW (   A)    (QLCNIC_PCI_CRBSPACE + (A)*QLCNIC_PCI_CRB_WINDOWSIZE)

Definition at line 403 of file qlcnic_hdr.h.

#define QLCNIC_PCI_CRB_WINDOWSIZE   0x00100000

Definition at line 402 of file qlcnic_hdr.h.

#define QLCNIC_PCI_CRBSPACE   (0x06000000UL)

Definition at line 455 of file qlcnic_hdr.h.

#define QLCNIC_PCI_MN_2M   (0)

Definition at line 452 of file qlcnic_hdr.h.

#define QLCNIC_PCI_MS_2M   (0x80000)

Definition at line 453 of file qlcnic_hdr.h.

#define QLCNIC_PCI_OCM0_2M   (0x000c0000UL)

Definition at line 454 of file qlcnic_hdr.h.

#define QLCNIC_PCIE_REG (   reg)    (QLCNIC_CRB_PCIE + (reg))

Definition at line 652 of file qlcnic_hdr.h.

#define QLCNIC_PCIX_PH_REG (   reg)    (QLCNIC_CRB_PCIE + (reg))

Definition at line 650 of file qlcnic_hdr.h.

#define QLCNIC_PCIX_PS_REG (   reg)    (QLCNIC_CRB_PCIX_MD + (reg))

Definition at line 651 of file qlcnic_hdr.h.

#define QLCNIC_PEG_ALIVE_COUNTER   (QLCNIC_CAM_RAM(0xb0))

Definition at line 685 of file qlcnic_hdr.h.

#define QLCNIC_PEG_HALT_STATUS1   (QLCNIC_CAM_RAM(0xa8))

Definition at line 686 of file qlcnic_hdr.h.

#define QLCNIC_PEG_HALT_STATUS2   (QLCNIC_CAM_RAM(0xac))

Definition at line 687 of file qlcnic_hdr.h.

#define QLCNIC_PEG_TUNE_CAPABILITY   (QLCNIC_CAM_RAM(0x02c))

Definition at line 682 of file qlcnic_hdr.h.

#define QLCNIC_PEG_TUNE_MN_PRESENT   0x1

Definition at line 681 of file qlcnic_hdr.h.

#define QLCNIC_PHY_LOCK_ID   (QLCNIC_CAM_RAM(0x120))

Definition at line 563 of file qlcnic_hdr.h.

#define QLCNIC_PORT_MODE_802_3_AP   3

Definition at line 671 of file qlcnic_hdr.h.

#define QLCNIC_PORT_MODE_ADDR   (QLCNIC_CAM_RAM(0x24))

Definition at line 675 of file qlcnic_hdr.h.

#define QLCNIC_PORT_MODE_AUTO_NEG   4

Definition at line 672 of file qlcnic_hdr.h.

#define QLCNIC_PORT_MODE_AUTO_NEG_1G   5

Definition at line 673 of file qlcnic_hdr.h.

#define QLCNIC_PORT_MODE_AUTO_NEG_XG   6

Definition at line 674 of file qlcnic_hdr.h.

#define QLCNIC_PORT_MODE_GB   2

Definition at line 670 of file qlcnic_hdr.h.

#define QLCNIC_PORT_MODE_NONE   0

Definition at line 668 of file qlcnic_hdr.h.

#define QLCNIC_PORT_MODE_XG   1

Definition at line 669 of file qlcnic_hdr.h.

#define QLCNIC_RCODE_DRIVER_CAN_RELOAD   BIT_30

Definition at line 729 of file qlcnic_hdr.h.

#define QLCNIC_RCODE_DRIVER_INFO   0x20000000

Definition at line 728 of file qlcnic_hdr.h.

#define QLCNIC_RCODE_FATAL_ERROR   BIT_31

Definition at line 730 of file qlcnic_hdr.h.

#define QLCNIC_RCVPEG_CHECK_DELAY   10

Definition at line 741 of file qlcnic_hdr.h.

#define QLCNIC_RCVPEG_CHECK_RETRY_COUNT   2000

Definition at line 740 of file qlcnic_hdr.h.

#define QLCNIC_RD_DUMP_REG (   addr,
  bar0,
  data 
)
Value:
do { \
writel((addr & 0xFFFF0000), (void *) (bar0 + \
QLCNIC_FW_DUMP_REG1)); \
readl((void *) (bar0 + QLCNIC_FW_DUMP_REG1)); \
*data = readl((void *) (bar0 + QLCNIC_FW_DUMP_REG2 + \
LSW(addr))); \
} while (0)

Definition at line 795 of file qlcnic_hdr.h.

#define QLCNIC_REG (   X)    (NIC_CRB_BASE+(X))

Definition at line 568 of file qlcnic_hdr.h.

#define QLCNIC_REG_2 (   X)    (NIC_CRB_BASE_2+(X))

Definition at line 569 of file qlcnic_hdr.h.

#define QLCNIC_RESET_TIMEOUT_SECS   10

Definition at line 738 of file qlcnic_hdr.h.

#define QLCNIC_ROM_DEV_INIT_TIMEOUT   (0x3e885c)

Definition at line 696 of file qlcnic_hdr.h.

#define QLCNIC_ROM_DRV_RESET_TIMEOUT   (0x3e8860)

Definition at line 697 of file qlcnic_hdr.h.

#define QLCNIC_ROM_LOCK_ID   (QLCNIC_CAM_RAM(0x100))

Definition at line 562 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_GLB_CAS_RST   (ROMUSB_GLB + 0x0038)

Definition at line 376 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL   (ROMUSB_GLB + 0x00A8)

Definition at line 379 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_GLB_PAD_GPIO_I   (ROMUSB_GLB + 0x000c)

Definition at line 375 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE   (ROMUSB_GLB + 0x005c)

Definition at line 378 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_GLB_STATUS   (ROMUSB_GLB + 0x0004)

Definition at line 373 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_GLB_SW_RESET   (ROMUSB_GLB + 0x0008)

Definition at line 374 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL   (ROMUSB_GLB + 0x0044)

Definition at line 377 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_GPIO (   n)    (ROMUSB_GLB + 0x60 + (4 * (n)))

Definition at line 381 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_ROM_ABYTE_CNT   (ROMUSB_ROM + 0x0010)

Definition at line 386 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_ROM_ADDRESS   (ROMUSB_ROM + 0x0008)

Definition at line 384 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT   (ROMUSB_ROM + 0x0014)

Definition at line 387 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_ROM_INSTR_OPCODE   (ROMUSB_ROM + 0x0004)

Definition at line 383 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_ROM_RDATA   (ROMUSB_ROM + 0x0018)

Definition at line 388 of file qlcnic_hdr.h.

#define QLCNIC_ROMUSB_ROM_WDATA   (ROMUSB_ROM + 0x000c)

Definition at line 385 of file qlcnic_hdr.h.

#define qlcnic_set_phy_duplex (   config_word)    ((config_word) |= 1 << 13)

Definition at line 1010 of file qlcnic_hdr.h.

#define qlcnic_set_phy_speed (   config_word,
  val 
)    ((config_word) |= ((val & 0x03) << 14))

Definition at line 1008 of file qlcnic_hdr.h.

#define QLCNIC_SIGN_CRB_OFFSET   (QLCNIC_REG(0x28))

Definition at line 575 of file qlcnic_hdr.h.

#define QLCNIC_SRE_MISC   (QLCNIC_CRB_SRE + 0x0002c)

Definition at line 366 of file qlcnic_hdr.h.

#define QLCNIC_TYPE_FCOE   2

Definition at line 725 of file qlcnic_hdr.h.

#define QLCNIC_TYPE_ISCSI   3

Definition at line 726 of file qlcnic_hdr.h.

#define QLCNIC_TYPE_NIC   1

Definition at line 724 of file qlcnic_hdr.h.

#define QLCNIC_WOL_CONFIG   (QLCNIC_CAM_RAM(0x188))

Definition at line 679 of file qlcnic_hdr.h.

#define QLCNIC_WOL_CONFIG_NV   (QLCNIC_CAM_RAM(0x184))

Definition at line 678 of file qlcnic_hdr.h.

#define QLCNIC_WOL_PORT_MODE   (QLCNIC_CAM_RAM(0x198))

Definition at line 676 of file qlcnic_hdr.h.

#define QLCNIC_WR_DUMP_REG (   addr,
  bar0,
  data 
)
Value:
do { \
writel((addr & 0xFFFF0000), (void *) (bar0 + \
QLCNIC_FW_DUMP_REG1)); \
readl((void *) (bar0 + QLCNIC_FW_DUMP_REG1)); \
writel(data, (void *) (bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr)));\
readl((void *) (bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr))); \
} while (0)

Definition at line 803 of file qlcnic_hdr.h.

#define qlcnic_xg_get_xg0_mask (   config_word)    _qlcnic_crb_get_bit((config_word), 0)

Definition at line 960 of file qlcnic_hdr.h.

#define qlcnic_xg_get_xg1_mask (   config_word)    _qlcnic_crb_get_bit((config_word), 3)

Definition at line 962 of file qlcnic_hdr.h.

#define qlcnic_xg_set_xg0_mask (   config_word)    ((config_word) |= 1 << 0)

Definition at line 955 of file qlcnic_hdr.h.

#define qlcnic_xg_set_xg1_mask (   config_word)    ((config_word) |= 1 << 3)

Definition at line 957 of file qlcnic_hdr.h.

#define qlcnic_xg_unset_xg0_mask (   config_word)    ((config_word) &= ~(1 << 0))

Definition at line 965 of file qlcnic_hdr.h.

#define qlcnic_xg_unset_xg1_mask (   config_word)    ((config_word) &= ~(1 << 3))

Definition at line 967 of file qlcnic_hdr.h.

#define ROM_LOCK_DRIVER   0x0d417340

Definition at line 391 of file qlcnic_hdr.h.

#define ROMUSB_GLB   (QLCNIC_CRB_ROMUSB + 0x00000)

Definition at line 370 of file qlcnic_hdr.h.

#define ROMUSB_ROM   (QLCNIC_CRB_ROMUSB + 0x10000)

Definition at line 371 of file qlcnic_hdr.h.

#define SIU_TEST_AGT_ADDR_HI   (0x18)

Definition at line 529 of file qlcnic_hdr.h.

#define SIU_TEST_AGT_ADDR_LO   (0x04)

Definition at line 528 of file qlcnic_hdr.h.

#define SIU_TEST_AGT_ADDR_MASK   0x3ffff8

Definition at line 537 of file qlcnic_hdr.h.

#define SIU_TEST_AGT_BASE   (0x60)

Definition at line 526 of file qlcnic_hdr.h.

#define SIU_TEST_AGT_RDDATA (   i)    (0x10+(4*(i)))

Definition at line 535 of file qlcnic_hdr.h.

#define SIU_TEST_AGT_RDDATA_HI   (0x14)

Definition at line 534 of file qlcnic_hdr.h.

#define SIU_TEST_AGT_RDDATA_LO   (0x10)

Definition at line 533 of file qlcnic_hdr.h.

#define SIU_TEST_AGT_UPPER_ADDR (   off)    ((off)>>22)

Definition at line 538 of file qlcnic_hdr.h.

#define SIU_TEST_AGT_WRDATA (   i)    (0x08+(4*(i)))

Definition at line 532 of file qlcnic_hdr.h.

#define SIU_TEST_AGT_WRDATA_HI   (0x0c)

Definition at line 531 of file qlcnic_hdr.h.

#define SIU_TEST_AGT_WRDATA_LO   (0x08)

Definition at line 530 of file qlcnic_hdr.h.

#define TA_CTL_BUSY   BIT_3

Definition at line 500 of file qlcnic_hdr.h.

#define TA_CTL_ENABLE   BIT_1

Definition at line 498 of file qlcnic_hdr.h.

#define TA_CTL_START   BIT_0

Definition at line 497 of file qlcnic_hdr.h.

#define TA_CTL_WRITE   BIT_2

Definition at line 499 of file qlcnic_hdr.h.

#define TEST_AGT_CTRL   (0x00)

Definition at line 495 of file qlcnic_hdr.h.

#define XG_LINK_DOWN   0x20

Definition at line 542 of file qlcnic_hdr.h.

#define XG_LINK_DOWN_P3P   0x02

Definition at line 545 of file qlcnic_hdr.h.

#define XG_LINK_STATE_P3P (   pcifn,
  val 
)    (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3P_MASK)

Definition at line 547 of file qlcnic_hdr.h.

#define XG_LINK_STATE_P3P_MASK   0xf

Definition at line 546 of file qlcnic_hdr.h.

#define XG_LINK_UP   0x10

Definition at line 541 of file qlcnic_hdr.h.

#define XG_LINK_UP_P3P   0x01

Definition at line 544 of file qlcnic_hdr.h.

Enumeration Type Documentation

anonymous enum
Enumerator:
QLCNIC_HW_H0_CH_HUB_ADR 
QLCNIC_HW_H1_CH_HUB_ADR 
QLCNIC_HW_H2_CH_HUB_ADR 
QLCNIC_HW_H3_CH_HUB_ADR 
QLCNIC_HW_H4_CH_HUB_ADR 
QLCNIC_HW_H5_CH_HUB_ADR 
QLCNIC_HW_H6_CH_HUB_ADR 

Definition at line 18 of file qlcnic_hdr.h.

anonymous enum
Enumerator:
QLCNIC_HW_MN_CRB_AGT_ADR 
QLCNIC_HW_MS_CRB_AGT_ADR 

Definition at line 29 of file qlcnic_hdr.h.

anonymous enum
Enumerator:
QLCNIC_HW_PS_CRB_AGT_ADR 
QLCNIC_HW_SS_CRB_AGT_ADR 
QLCNIC_HW_RPMX3_CRB_AGT_ADR 
QLCNIC_HW_QMS_CRB_AGT_ADR 
QLCNIC_HW_SQGS0_CRB_AGT_ADR 
QLCNIC_HW_SQGS1_CRB_AGT_ADR 
QLCNIC_HW_SQGS2_CRB_AGT_ADR 
QLCNIC_HW_SQGS3_CRB_AGT_ADR 
QLCNIC_HW_C2C0_CRB_AGT_ADR 
QLCNIC_HW_C2C1_CRB_AGT_ADR 
QLCNIC_HW_C2C2_CRB_AGT_ADR 
QLCNIC_HW_RPMX2_CRB_AGT_ADR 
QLCNIC_HW_RPMX4_CRB_AGT_ADR 
QLCNIC_HW_RPMX7_CRB_AGT_ADR 
QLCNIC_HW_RPMX9_CRB_AGT_ADR 
QLCNIC_HW_SMB_CRB_AGT_ADR 

Definition at line 35 of file qlcnic_hdr.h.

anonymous enum
Enumerator:
QLCNIC_HW_NIU_CRB_AGT_ADR 
QLCNIC_HW_I2C0_CRB_AGT_ADR 
QLCNIC_HW_I2C1_CRB_AGT_ADR 
QLCNIC_HW_SN_CRB_AGT_ADR 
QLCNIC_HW_I2Q_CRB_AGT_ADR 
QLCNIC_HW_LPC_CRB_AGT_ADR 
QLCNIC_HW_ROMUSB_CRB_AGT_ADR 
QLCNIC_HW_QM_CRB_AGT_ADR 
QLCNIC_HW_SQG0_CRB_AGT_ADR 
QLCNIC_HW_SQG1_CRB_AGT_ADR 
QLCNIC_HW_SQG2_CRB_AGT_ADR 
QLCNIC_HW_SQG3_CRB_AGT_ADR 
QLCNIC_HW_RPMX1_CRB_AGT_ADR 
QLCNIC_HW_RPMX5_CRB_AGT_ADR 
QLCNIC_HW_RPMX6_CRB_AGT_ADR 
QLCNIC_HW_RPMX8_CRB_AGT_ADR 

Definition at line 55 of file qlcnic_hdr.h.

anonymous enum
Enumerator:
QLCNIC_HW_PH_CRB_AGT_ADR 
QLCNIC_HW_SRE_CRB_AGT_ADR 
QLCNIC_HW_EG_CRB_AGT_ADR 
QLCNIC_HW_RPMX0_CRB_AGT_ADR 

Definition at line 76 of file qlcnic_hdr.h.

anonymous enum
Enumerator:
QLCNIC_HW_PEGN0_CRB_AGT_ADR 
QLCNIC_HW_PEGN1_CRB_AGT_ADR 
QLCNIC_HW_PEGN2_CRB_AGT_ADR 
QLCNIC_HW_PEGN3_CRB_AGT_ADR 
QLCNIC_HW_PEGNI_CRB_AGT_ADR 
QLCNIC_HW_PEGND_CRB_AGT_ADR 
QLCNIC_HW_PEGNC_CRB_AGT_ADR 
QLCNIC_HW_PEGR0_CRB_AGT_ADR 
QLCNIC_HW_PEGR1_CRB_AGT_ADR 
QLCNIC_HW_PEGR2_CRB_AGT_ADR 
QLCNIC_HW_PEGR3_CRB_AGT_ADR 
QLCNIC_HW_PEGN4_CRB_AGT_ADR 

Definition at line 84 of file qlcnic_hdr.h.

anonymous enum
Enumerator:
QLCNIC_HW_PEGS0_CRB_AGT_ADR 
QLCNIC_HW_PEGS1_CRB_AGT_ADR 
QLCNIC_HW_PEGS2_CRB_AGT_ADR 
QLCNIC_HW_PEGS3_CRB_AGT_ADR 
QLCNIC_HW_PEGSI_CRB_AGT_ADR 
QLCNIC_HW_PEGSD_CRB_AGT_ADR 
QLCNIC_HW_PEGSC_CRB_AGT_ADR 

Definition at line 100 of file qlcnic_hdr.h.

anonymous enum
Enumerator:
QLCNIC_HW_CAS0_CRB_AGT_ADR 
QLCNIC_HW_CAS1_CRB_AGT_ADR 
QLCNIC_HW_CAS2_CRB_AGT_ADR 
QLCNIC_HW_CAS3_CRB_AGT_ADR 
QLCNIC_HW_NCM_CRB_AGT_ADR 
QLCNIC_HW_TMR_CRB_AGT_ADR 
QLCNIC_HW_XDMA_CRB_AGT_ADR 
QLCNIC_HW_OCM0_CRB_AGT_ADR 
QLCNIC_HW_OCM1_CRB_AGT_ADR 

Definition at line 111 of file qlcnic_hdr.h.

anonymous enum
Enumerator:
QLCNIC_HW_PX_MAP_CRB_PH 
QLCNIC_HW_PX_MAP_CRB_PS 
QLCNIC_HW_PX_MAP_CRB_MN 
QLCNIC_HW_PX_MAP_CRB_MS 
QLCNIC_HW_PX_MAP_CRB_PGR1 
QLCNIC_HW_PX_MAP_CRB_SRE 
QLCNIC_HW_PX_MAP_CRB_NIU 
QLCNIC_HW_PX_MAP_CRB_QMN 
QLCNIC_HW_PX_MAP_CRB_SQN0 
QLCNIC_HW_PX_MAP_CRB_SQN1 
QLCNIC_HW_PX_MAP_CRB_SQN2 
QLCNIC_HW_PX_MAP_CRB_SQN3 
QLCNIC_HW_PX_MAP_CRB_QMS 
QLCNIC_HW_PX_MAP_CRB_SQS0 
QLCNIC_HW_PX_MAP_CRB_SQS1 
QLCNIC_HW_PX_MAP_CRB_SQS2 
QLCNIC_HW_PX_MAP_CRB_SQS3 
QLCNIC_HW_PX_MAP_CRB_PGN0 
QLCNIC_HW_PX_MAP_CRB_PGN1 
QLCNIC_HW_PX_MAP_CRB_PGN2 
QLCNIC_HW_PX_MAP_CRB_PGN3 
QLCNIC_HW_PX_MAP_CRB_PGND 
QLCNIC_HW_PX_MAP_CRB_PGNI 
QLCNIC_HW_PX_MAP_CRB_PGS0 
QLCNIC_HW_PX_MAP_CRB_PGS1 
QLCNIC_HW_PX_MAP_CRB_PGS2 
QLCNIC_HW_PX_MAP_CRB_PGS3 
QLCNIC_HW_PX_MAP_CRB_PGSD 
QLCNIC_HW_PX_MAP_CRB_PGSI 
QLCNIC_HW_PX_MAP_CRB_SN 
QLCNIC_HW_PX_MAP_CRB_PGR2 
QLCNIC_HW_PX_MAP_CRB_EG 
QLCNIC_HW_PX_MAP_CRB_PH2 
QLCNIC_HW_PX_MAP_CRB_PS2 
QLCNIC_HW_PX_MAP_CRB_CAM 
QLCNIC_HW_PX_MAP_CRB_CAS0 
QLCNIC_HW_PX_MAP_CRB_CAS1 
QLCNIC_HW_PX_MAP_CRB_CAS2 
QLCNIC_HW_PX_MAP_CRB_C2C0 
QLCNIC_HW_PX_MAP_CRB_C2C1 
QLCNIC_HW_PX_MAP_CRB_TIMR 
QLCNIC_HW_PX_MAP_CRB_PGR3 
QLCNIC_HW_PX_MAP_CRB_RPMX1 
QLCNIC_HW_PX_MAP_CRB_RPMX2 
QLCNIC_HW_PX_MAP_CRB_RPMX3 
QLCNIC_HW_PX_MAP_CRB_RPMX4 
QLCNIC_HW_PX_MAP_CRB_RPMX5 
QLCNIC_HW_PX_MAP_CRB_RPMX6 
QLCNIC_HW_PX_MAP_CRB_RPMX7 
QLCNIC_HW_PX_MAP_CRB_XDMA 
QLCNIC_HW_PX_MAP_CRB_I2Q 
QLCNIC_HW_PX_MAP_CRB_ROMUSB 
QLCNIC_HW_PX_MAP_CRB_CAS3 
QLCNIC_HW_PX_MAP_CRB_RPMX0 
QLCNIC_HW_PX_MAP_CRB_RPMX8 
QLCNIC_HW_PX_MAP_CRB_RPMX9 
QLCNIC_HW_PX_MAP_CRB_OCM0 
QLCNIC_HW_PX_MAP_CRB_OCM1 
QLCNIC_HW_PX_MAP_CRB_SMB 
QLCNIC_HW_PX_MAP_CRB_I2C0 
QLCNIC_HW_PX_MAP_CRB_I2C1 
QLCNIC_HW_PX_MAP_CRB_LPC 
QLCNIC_HW_PX_MAP_CRB_PGNC 
QLCNIC_HW_PX_MAP_CRB_PGR0 

Definition at line 127 of file qlcnic_hdr.h.

anonymous enum
Enumerator:
QLCNIC_TEMP_NORMAL 
QLCNIC_TEMP_WARN 
QLCNIC_TEMP_PANIC 

Definition at line 609 of file qlcnic_hdr.h.

anonymous enum
Enumerator:
QLCNIC_MGMT_FUNC 
QLCNIC_PRIV_FUNC 
QLCNIC_NON_PRIV_FUNC 

Definition at line 812 of file qlcnic_hdr.h.

anonymous enum
Enumerator:
QLCNIC_PORT_DEFAULTS 
QLCNIC_ADD_VLAN 
QLCNIC_DEL_VLAN 

Definition at line 818 of file qlcnic_hdr.h.

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