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r8192E_hw.h File Reference

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Macros

#define RTL8187_REQT_READ   0xc0
 
#define RTL8187_REQT_WRITE   0x40
 
#define RTL8187_REQ_GET_REGS   0x05
 
#define RTL8187_REQ_SET_REGS   0x05
 
#define MAX_TX_URB   5
 
#define MAX_RX_URB   16
 
#define RX_URB_SIZE   9100
 
#define BB_ANTATTEN_CHAN14   0x0c
 
#define BB_ANTENNA_B   0x40
 
#define BB_HOST_BANG   (1<<30)
 
#define BB_HOST_BANG_EN   (1<<2)
 
#define BB_HOST_BANG_CLK   (1<<1)
 
#define BB_HOST_BANG_RW   (1<<3)
 
#define BB_HOST_BANG_DATA   1
 
#define RTL8190_EEPROM_ID   0x8129
 
#define EEPROM_VID   0x02
 
#define EEPROM_DID   0x04
 
#define EEPROM_NODE_ADDRESS_BYTE_0   0x0C
 
#define EEPROM_TxPowerDiff   0x1F
 
#define EEPROM_PwDiff   0x21
 
#define EEPROM_CrystalCap   0x22
 
#define EEPROM_TxPwIndex_CCK_V1   0x29
 
#define EEPROM_TxPwIndex_OFDM_24G_V1   0x2C
 
#define EEPROM_TxPwIndex_Ver   0x27
 
#define EEPROM_Default_TxPowerDiff   0x0
 
#define EEPROM_Default_ThermalMeter   0x77
 
#define EEPROM_Default_AntTxPowerDiff   0x0
 
#define EEPROM_Default_TxPwDiff_CrystalCap   0x5
 
#define EEPROM_Default_PwDiff   0x4
 
#define EEPROM_Default_CrystalCap   0x5
 
#define EEPROM_Default_TxPower   0x1010
 
#define EEPROM_ICVersion_ChannelPlan   0x7C
 
#define EEPROM_Customer_ID   0x7B
 
#define EEPROM_RFInd_PowerDiff   0x28
 
#define EEPROM_ThermalMeter   0x29
 
#define EEPROM_TxPwDiff_CrystalCap   0x2A
 
#define EEPROM_TxPwIndex_CCK   0x2C
 
#define EEPROM_TxPwIndex_OFDM_24G   0x3A
 
#define EEPROM_Default_TxPowerLevel   0x10
 
#define EEPROM_IC_VER   0x7d
 
#define EEPROM_CRC   0x7e
 
#define EEPROM_CID_DEFAULT   0x0
 
#define EEPROM_CID_CAMEO   0x1
 
#define EEPROM_CID_RUNTOP   0x2
 
#define EEPROM_CID_Senao   0x3
 
#define EEPROM_CID_TOSHIBA   0x4
 
#define EEPROM_CID_NetCore   0x5
 
#define EEPROM_CID_Nettronix   0x6
 
#define EEPROM_CID_Pronet   0x7
 
#define EEPROM_CID_DLINK   0x8
 
#define EEPROM_CID_WHQL   0xFE
 
#define MXDMA2_16bytes   0x000
 
#define MXDMA2_32bytes   0x001
 
#define MXDMA2_64bytes   0x010
 
#define MXDMA2_128bytes   0x011
 
#define MXDMA2_256bytes   0x100
 
#define MXDMA2_512bytes   0x101
 
#define MXDMA2_1024bytes   0x110
 
#define MXDMA2_NoLimit   0x7
 
#define MULRW_SHIFT   3
 
#define MXDMA2_RX_SHIFT   4
 
#define MXDMA2_TX_SHIFT   0
 
#define EPROM_CMD_RESERVED_MASK   BIT5
 
#define EPROM_CMD_9356SEL   BIT4
 
#define EPROM_CMD_OPERATING_MODE_SHIFT   6
 
#define EPROM_CMD_OPERATING_MODE_MASK   ((1<<7)|(1<<6))
 
#define EPROM_CMD_CONFIG   0x3
 
#define EPROM_CMD_NORMAL   0
 
#define EPROM_CMD_LOAD   1
 
#define EPROM_CMD_PROGRAM   2
 
#define EPROM_CS_SHIFT   3
 
#define EPROM_CK_SHIFT   2
 
#define EPROM_W_SHIFT   1
 
#define EPROM_R_SHIFT   0
 
#define AFR_CardBEn   (1<<0)
 
#define AFR_CLKRUN_SEL   (1<<1)
 
#define AFR_FuncRegEn   (1<<2)
 
#define BB_GLOBAL_RESET_BIT   0x1
 
#define CR_RST   0x10
 
#define CR_RE   0x08
 
#define CR_TE   0x04
 
#define CR_MulRW   0x01
 
#define RCR_FILTER_MASK
 
#define RCR_ONLYERLPKT   BIT31
 
#define RCR_ENCS2   BIT30
 
#define RCR_ENCS1   BIT29
 
#define RCR_ENMBID   BIT27
 
#define RCR_ACKTXBW   (BIT24|BIT25)
 
#define RCR_CBSSID   BIT23
 
#define RCR_APWRMGT   BIT22
 
#define RCR_ADD3   BIT21
 
#define RCR_AMF   BIT20
 
#define RCR_ACF   BIT19
 
#define RCR_ADF   BIT18
 
#define RCR_RXFTH   BIT13
 
#define RCR_AICV   BIT12
 
#define RCR_ACRC32   BIT5
 
#define RCR_AB   BIT3
 
#define RCR_AM   BIT2
 
#define RCR_APM   BIT1
 
#define RCR_AAP   BIT0
 
#define RCR_MXDMA_OFFSET   8
 
#define RCR_FIFO_OFFSET   13
 
#define AC_PARAM_TXOP_LIMIT_OFFSET   16
 
#define AC_PARAM_ECW_MAX_OFFSET   12
 
#define AC_PARAM_ECW_MIN_OFFSET   8
 
#define AC_PARAM_AIFS_OFFSET   0
 
#define BCN_TCFG_CW_SHIFT   8
 
#define BCN_TCFG_IFS   0
 
#define BCN_DRV_EARLY_INT_SWBCN_SHIFT   8
 
#define BCN_DRV_EARLY_INT_TIME_SHIFT   0
 
#define CAM_CM_SecCAMPolling   BIT31
 
#define CAM_CM_SecCAMClr   BIT30
 
#define CAM_CM_SecCAMWE   BIT16
 
#define CAM_VALID   BIT15
 
#define CAM_NOTVALID   0x0000
 
#define CAM_USEDK   BIT5
 
#define CAM_NONE   0x0
 
#define CAM_WEP40   0x01
 
#define CAM_TKIP   0x02
 
#define CAM_AES   0x04
 
#define CAM_WEP104   0x05
 
#define TOTAL_CAM_ENTRY   32
 
#define CAM_CONFIG_USEDK   true
 
#define CAM_CONFIG_NO_USEDK   false
 
#define CAM_WRITE   BIT16
 
#define CAM_READ   0x00000000
 
#define CAM_POLLINIG   BIT31
 
#define SCR_UseDK   0x01
 
#define SCR_TxUseDK   BIT0
 
#define SCR_RxUseDK   BIT1
 
#define SCR_TxEncEnable   BIT2
 
#define SCR_RxDecEnable   BIT3
 
#define SCR_SKByA2   BIT4
 
#define SCR_NoSKMC   BIT5
 
#define IMR8190_DISABLED   0x0
 
#define IMR_ATIMEND   BIT28
 
#define IMR_TBDOK   BIT27
 
#define IMR_TBDER   BIT26
 
#define IMR_TXFOVW   BIT15
 
#define IMR_TIMEOUT0   BIT14
 
#define IMR_BcnInt   BIT13
 
#define IMR_RXFOVW   BIT12
 
#define IMR_RDU   BIT11
 
#define IMR_RXCMDOK   BIT10
 
#define IMR_BDOK   BIT9
 
#define IMR_HIGHDOK   BIT8
 
#define IMR_COMDOK   BIT7
 
#define IMR_MGNTDOK   BIT6
 
#define IMR_HCCADOK   BIT5
 
#define IMR_BKDOK   BIT4
 
#define IMR_BEDOK   BIT3
 
#define IMR_VIDOK   BIT2
 
#define IMR_VODOK   BIT1
 
#define IMR_ROK   BIT0
 
#define TPPoll_BKQ   BIT0
 
#define TPPoll_BEQ   BIT1
 
#define TPPoll_VIQ   BIT2
 
#define TPPoll_VOQ   BIT3
 
#define TPPoll_BQ   BIT4
 
#define TPPoll_CQ   BIT5
 
#define TPPoll_MQ   BIT6
 
#define TPPoll_HQ   BIT7
 
#define TPPoll_HCCAQ   BIT8
 
#define TPPoll_StopBK   BIT9
 
#define TPPoll_StopBE   BIT10
 
#define TPPoll_StopVI   BIT11
 
#define TPPoll_StopVO   BIT12
 
#define TPPoll_StopMgt   BIT13
 
#define TPPoll_StopHigh   BIT14
 
#define TPPoll_StopHCCA   BIT15
 
#define TPPoll_SHIFT   8
 
#define PSR_GEN   0x0
 
#define PSR_CPU   0x1
 
#define CPU_CCK_LOOPBACK   0x00030000
 
#define CPU_GEN_SYSTEM_RESET   0x00000001
 
#define CPU_GEN_FIRMWARE_RESET   0x00000008
 
#define CPU_GEN_BOOT_RDY   0x00000010
 
#define CPU_GEN_FIRM_RDY   0x00000020
 
#define CPU_GEN_PUT_CODE_OK   0x00000080
 
#define CPU_GEN_BB_RST   0x00000100
 
#define CPU_GEN_PWR_STB_CPU   0x00000004
 
#define CPU_GEN_NO_LOOPBACK_MSK   0xFFF8FFFF
 
#define CPU_GEN_NO_LOOPBACK_SET   0x00080000
 
#define CPU_GEN_GPIO_UART   0x00007000
 
#define AcmHw_HwEn   BIT0
 
#define AcmHw_BeqEn   BIT1
 
#define AcmHw_ViqEn   BIT2
 
#define AcmHw_VoqEn   BIT3
 
#define AcmHw_BeqStatus   BIT4
 
#define AcmHw_ViqStatus   BIT5
 
#define AcmHw_VoqStatus   BIT6
 
#define AcmFw_BeqStatus   BIT0
 
#define AcmFw_ViqStatus   BIT1
 
#define AcmFw_VoqStatus   BIT2
 
#define BW_OPMODE_11J   BIT0
 
#define BW_OPMODE_5G   BIT1
 
#define BW_OPMODE_20MHZ   BIT2
 
#define MSR_LINK_MASK   ((1<<0)|(1<<1))
 
#define MSR_LINK_MANAGED   2
 
#define MSR_LINK_NONE   0
 
#define MSR_LINK_SHIFT   0
 
#define MSR_LINK_ADHOC   1
 
#define MSR_LINK_MASTER   3
 
#define MSR_LINK_ENEDCA   (1<<4)
 
#define MSR_NOLINK   0x00
 
#define MSR_ADHOC   0x01
 
#define MSR_INFRA   0x02
 
#define MSR_AP   0x03
 
#define RETRY_LIMIT_SHORT_SHIFT   8
 
#define RETRY_LIMIT_LONG_SHIFT   0
 
#define RRSR_RSC_OFFSET   21
 
#define RRSR_SHORT_OFFSET   23
 
#define RRSR_RSC_DUPLICATE   0x600000
 
#define RRSR_RSC_UPSUBCHNL   0x400000
 
#define RRSR_RSC_LOWSUBCHNL   0x200000
 
#define RRSR_SHORT   0x800000
 
#define RRSR_1M   BIT0
 
#define RRSR_2M   BIT1
 
#define RRSR_5_5M   BIT2
 
#define RRSR_11M   BIT3
 
#define RRSR_6M   BIT4
 
#define RRSR_9M   BIT5
 
#define RRSR_12M   BIT6
 
#define RRSR_18M   BIT7
 
#define RRSR_24M   BIT8
 
#define RRSR_36M   BIT9
 
#define RRSR_48M   BIT10
 
#define RRSR_54M   BIT11
 
#define RRSR_MCS0   BIT12
 
#define RRSR_MCS1   BIT13
 
#define RRSR_MCS2   BIT14
 
#define RRSR_MCS3   BIT15
 
#define RRSR_MCS4   BIT16
 
#define RRSR_MCS5   BIT17
 
#define RRSR_MCS6   BIT18
 
#define RRSR_MCS7   BIT19
 
#define BRSR_AckShortPmb   BIT23
 
#define RATR_1M   0x00000001
 
#define RATR_2M   0x00000002
 
#define RATR_55M   0x00000004
 
#define RATR_11M   0x00000008
 
#define RATR_6M   0x00000010
 
#define RATR_9M   0x00000020
 
#define RATR_12M   0x00000040
 
#define RATR_18M   0x00000080
 
#define RATR_24M   0x00000100
 
#define RATR_36M   0x00000200
 
#define RATR_48M   0x00000400
 
#define RATR_54M   0x00000800
 
#define RATR_MCS0   0x00001000
 
#define RATR_MCS1   0x00002000
 
#define RATR_MCS2   0x00004000
 
#define RATR_MCS3   0x00008000
 
#define RATR_MCS4   0x00010000
 
#define RATR_MCS5   0x00020000
 
#define RATR_MCS6   0x00040000
 
#define RATR_MCS7   0x00080000
 
#define RATR_MCS8   0x00100000
 
#define RATR_MCS9   0x00200000
 
#define RATR_MCS10   0x00400000
 
#define RATR_MCS11   0x00800000
 
#define RATR_MCS12   0x01000000
 
#define RATR_MCS13   0x02000000
 
#define RATR_MCS14   0x04000000
 
#define RATR_MCS15   0x08000000
 
#define RATE_ALL_CCK   (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
 
#define RATE_ALL_OFDM_AG
 
#define RATE_ALL_OFDM_1SS
 
#define RATE_ALL_OFDM_2SS
 
#define GPI   0x108
 
#define GPO   0x109
 
#define GPE   0x10a
 
#define HWSET_MAX_SIZE_92S   128
 
#define ANAPAR_FOR_8192PciE   0x17
 

Enumerations

enum  baseband_config { BaseBand_Config_PHY_REG = 0, BaseBand_Config_AGC_TAB = 1 }
 
enum  _RTL8192Pci_HW {
  MAC0 = 0x000, MAC1 = 0x001, MAC2 = 0x002, MAC3 = 0x003,
  MAC4 = 0x004, MAC5 = 0x005, PCIF = 0x009, PMR = 0x00c,
  EPROM_CMD = 0x00e, AFR = 0x010, ANAPAR = 0x17, BB_GLOBAL_RESET = 0x020,
  BSSIDR = 0x02E, CMDR = 0x037, SIFS = 0x03E, TCR = 0x040,
  RCR = 0x044, SLOT_TIME = 0x049, ACK_TIMEOUT = 0x04c, PIFS_TIME = 0x04d,
  USTIME = 0x04e, EDCAPARA_BE = 0x050, EDCAPARA_BK = 0x054, EDCAPARA_VO = 0x058,
  EDCAPARA_VI = 0x05C, RFPC = 0x05F, CWRR = 0x060, BCN_TCFG = 0x062,
  BCN_INTERVAL = 0x070, ATIMWND = 0x072, BCN_DRV_EARLY_INT = 0x074, BCN_DMATIME = 0x076,
  BCN_ERR_THRESH = 0x078, RWCAM = 0x0A0, WCAMI = 0x0A4, RCAMO = 0x0A8,
  SECR = 0x0B0, SWREGULATOR = 0x0BD, INTA_MASK = 0x0f4, ISR = 0x0f8,
  TPPoll = 0x0fd, PSR = 0x0ff, CPU_GEN = 0x100, BB_RESET = 0x101,
  LED1Cfg = 0x154, LED0Cfg = 0x155, AcmAvg = 0x170, AcmHwCtrl = 0x171,
  AcmFwCtrl = 0x172, VOAdmTime = 0x174, VIAdmTime = 0x178, BEAdmTime = 0x17C,
  RQPN1 = 0x180, RQPN2 = 0x184, RQPN3 = 0x188, QPRR = 0x1E0,
  QPNR = 0x1F0, BQDA = 0x200, HQDA = 0x204, CQDA = 0x208,
  MQDA = 0x20C, HCCAQDA = 0x210, VOQDA = 0x214, VIQDA = 0x218,
  BEQDA = 0x21C, BKQDA = 0x220, RCQDA = 0x224, RDQDA = 0x228,
  MAR0 = 0x240, MAR4 = 0x244, CCX_PERIOD = 0x250, CLM_RESULT = 0x251,
  NHM_PERIOD = 0x252, NHM_THRESHOLD0 = 0x253, NHM_THRESHOLD1 = 0x254, NHM_THRESHOLD2 = 0x255,
  NHM_THRESHOLD3 = 0x256, NHM_THRESHOLD4 = 0x257, NHM_THRESHOLD5 = 0x258, NHM_THRESHOLD6 = 0x259,
  MCTRL = 0x25A, NHM_RPI_COUNTER0 = 0x264, NHM_RPI_COUNTER1 = 0x265, NHM_RPI_COUNTER2 = 0x266,
  NHM_RPI_COUNTER3 = 0x267, NHM_RPI_COUNTER4 = 0x268, NHM_RPI_COUNTER5 = 0x269, NHM_RPI_COUNTER6 = 0x26A,
  NHM_RPI_COUNTER7 = 0x26B, WFCRC0 = 0x2f0, WFCRC1 = 0x2f4, WFCRC2 = 0x2f8,
  BW_OPMODE = 0x300, IC_VERRSION = 0x301, MSR = 0x303, RETRY_LIMIT = 0x304,
  TSFR = 0x308, RRSR = 0x310, UFWP = 0x318, RATR0 = 0x320,
  DRIVER_RSSI = 0x32c, MCS_TXAGC = 0x340, CCK_TXAGC = 0x348, MacBlkCtrl = 0x403
}
 

Macro Definition Documentation

#define AC_PARAM_AIFS_OFFSET   0

Definition at line 177 of file r8192E_hw.h.

#define AC_PARAM_ECW_MAX_OFFSET   12

Definition at line 175 of file r8192E_hw.h.

#define AC_PARAM_ECW_MIN_OFFSET   8

Definition at line 176 of file r8192E_hw.h.

#define AC_PARAM_TXOP_LIMIT_OFFSET   16

Definition at line 174 of file r8192E_hw.h.

#define AcmFw_BeqStatus   BIT0

Definition at line 293 of file r8192E_hw.h.

#define AcmFw_ViqStatus   BIT1

Definition at line 294 of file r8192E_hw.h.

#define AcmFw_VoqStatus   BIT2

Definition at line 295 of file r8192E_hw.h.

#define AcmHw_BeqEn   BIT1

Definition at line 286 of file r8192E_hw.h.

#define AcmHw_BeqStatus   BIT4

Definition at line 289 of file r8192E_hw.h.

#define AcmHw_HwEn   BIT0

Definition at line 285 of file r8192E_hw.h.

#define AcmHw_ViqEn   BIT2

Definition at line 287 of file r8192E_hw.h.

#define AcmHw_ViqStatus   BIT5

Definition at line 290 of file r8192E_hw.h.

#define AcmHw_VoqEn   BIT3

Definition at line 288 of file r8192E_hw.h.

#define AcmHw_VoqStatus   BIT6

Definition at line 291 of file r8192E_hw.h.

#define AFR_CardBEn   (1<<0)

Definition at line 128 of file r8192E_hw.h.

#define AFR_CLKRUN_SEL   (1<<1)

Definition at line 129 of file r8192E_hw.h.

#define AFR_FuncRegEn   (1<<2)

Definition at line 130 of file r8192E_hw.h.

#define ANAPAR_FOR_8192PciE   0x17

Definition at line 451 of file r8192E_hw.h.

#define BB_ANTATTEN_CHAN14   0x0c

Definition at line 38 of file r8192E_hw.h.

#define BB_ANTENNA_B   0x40

Definition at line 39 of file r8192E_hw.h.

#define BB_GLOBAL_RESET_BIT   0x1

Definition at line 133 of file r8192E_hw.h.

#define BB_HOST_BANG   (1<<30)

Definition at line 41 of file r8192E_hw.h.

#define BB_HOST_BANG_CLK   (1<<1)

Definition at line 43 of file r8192E_hw.h.

#define BB_HOST_BANG_DATA   1

Definition at line 45 of file r8192E_hw.h.

#define BB_HOST_BANG_EN   (1<<2)

Definition at line 42 of file r8192E_hw.h.

#define BB_HOST_BANG_RW   (1<<3)

Definition at line 44 of file r8192E_hw.h.

#define BCN_DRV_EARLY_INT_SWBCN_SHIFT   8

Definition at line 186 of file r8192E_hw.h.

#define BCN_DRV_EARLY_INT_TIME_SHIFT   0

Definition at line 187 of file r8192E_hw.h.

#define BCN_TCFG_CW_SHIFT   8

Definition at line 181 of file r8192E_hw.h.

#define BCN_TCFG_IFS   0

Definition at line 182 of file r8192E_hw.h.

#define BRSR_AckShortPmb   BIT23

Definition at line 395 of file r8192E_hw.h.

#define BW_OPMODE_11J   BIT0

Definition at line 346 of file r8192E_hw.h.

#define BW_OPMODE_20MHZ   BIT2

Definition at line 348 of file r8192E_hw.h.

#define BW_OPMODE_5G   BIT1

Definition at line 347 of file r8192E_hw.h.

#define CAM_AES   0x04

Definition at line 201 of file r8192E_hw.h.

#define CAM_CM_SecCAMClr   BIT30

Definition at line 192 of file r8192E_hw.h.

#define CAM_CM_SecCAMPolling   BIT31

Definition at line 191 of file r8192E_hw.h.

#define CAM_CM_SecCAMWE   BIT16

Definition at line 193 of file r8192E_hw.h.

#define CAM_CONFIG_NO_USEDK   false

Definition at line 207 of file r8192E_hw.h.

#define CAM_CONFIG_USEDK   true

Definition at line 206 of file r8192E_hw.h.

#define CAM_NONE   0x0

Definition at line 198 of file r8192E_hw.h.

#define CAM_NOTVALID   0x0000

Definition at line 195 of file r8192E_hw.h.

#define CAM_POLLINIG   BIT31

Definition at line 210 of file r8192E_hw.h.

#define CAM_READ   0x00000000

Definition at line 209 of file r8192E_hw.h.

#define CAM_TKIP   0x02

Definition at line 200 of file r8192E_hw.h.

#define CAM_USEDK   BIT5

Definition at line 196 of file r8192E_hw.h.

#define CAM_VALID   BIT15

Definition at line 194 of file r8192E_hw.h.

#define CAM_WEP104   0x05

Definition at line 202 of file r8192E_hw.h.

#define CAM_WEP40   0x01

Definition at line 199 of file r8192E_hw.h.

#define CAM_WRITE   BIT16

Definition at line 208 of file r8192E_hw.h.

#define CPU_CCK_LOOPBACK   0x00030000

Definition at line 268 of file r8192E_hw.h.

#define CPU_GEN_BB_RST   0x00000100

Definition at line 274 of file r8192E_hw.h.

#define CPU_GEN_BOOT_RDY   0x00000010

Definition at line 271 of file r8192E_hw.h.

#define CPU_GEN_FIRM_RDY   0x00000020

Definition at line 272 of file r8192E_hw.h.

#define CPU_GEN_FIRMWARE_RESET   0x00000008

Definition at line 270 of file r8192E_hw.h.

#define CPU_GEN_GPIO_UART   0x00007000

Definition at line 278 of file r8192E_hw.h.

#define CPU_GEN_NO_LOOPBACK_MSK   0xFFF8FFFF

Definition at line 276 of file r8192E_hw.h.

#define CPU_GEN_NO_LOOPBACK_SET   0x00080000

Definition at line 277 of file r8192E_hw.h.

#define CPU_GEN_PUT_CODE_OK   0x00000080

Definition at line 273 of file r8192E_hw.h.

#define CPU_GEN_PWR_STB_CPU   0x00000004

Definition at line 275 of file r8192E_hw.h.

#define CPU_GEN_SYSTEM_RESET   0x00000001

Definition at line 269 of file r8192E_hw.h.

#define CR_MulRW   0x01

Definition at line 140 of file r8192E_hw.h.

#define CR_RE   0x08

Definition at line 138 of file r8192E_hw.h.

#define CR_RST   0x10

Definition at line 137 of file r8192E_hw.h.

#define CR_TE   0x04

Definition at line 139 of file r8192E_hw.h.

#define EEPROM_CID_CAMEO   0x1

Definition at line 83 of file r8192E_hw.h.

#define EEPROM_CID_DEFAULT   0x0

Definition at line 82 of file r8192E_hw.h.

#define EEPROM_CID_DLINK   0x8

Definition at line 90 of file r8192E_hw.h.

#define EEPROM_CID_NetCore   0x5

Definition at line 87 of file r8192E_hw.h.

#define EEPROM_CID_Nettronix   0x6

Definition at line 88 of file r8192E_hw.h.

#define EEPROM_CID_Pronet   0x7

Definition at line 89 of file r8192E_hw.h.

#define EEPROM_CID_RUNTOP   0x2

Definition at line 84 of file r8192E_hw.h.

#define EEPROM_CID_Senao   0x3

Definition at line 85 of file r8192E_hw.h.

#define EEPROM_CID_TOSHIBA   0x4

Definition at line 86 of file r8192E_hw.h.

#define EEPROM_CID_WHQL   0xFE

Definition at line 91 of file r8192E_hw.h.

#define EEPROM_CRC   0x7e

Definition at line 80 of file r8192E_hw.h.

#define EEPROM_CrystalCap   0x22

Definition at line 56 of file r8192E_hw.h.

#define EEPROM_Customer_ID   0x7B

Definition at line 72 of file r8192E_hw.h.

#define EEPROM_Default_AntTxPowerDiff   0x0

Definition at line 66 of file r8192E_hw.h.

#define EEPROM_Default_CrystalCap   0x5

Definition at line 69 of file r8192E_hw.h.

#define EEPROM_Default_PwDiff   0x4

Definition at line 68 of file r8192E_hw.h.

#define EEPROM_Default_ThermalMeter   0x77

Definition at line 65 of file r8192E_hw.h.

#define EEPROM_Default_TxPower   0x1010

Definition at line 70 of file r8192E_hw.h.

#define EEPROM_Default_TxPowerDiff   0x0

Definition at line 64 of file r8192E_hw.h.

#define EEPROM_Default_TxPowerLevel   0x10

Definition at line 78 of file r8192E_hw.h.

#define EEPROM_Default_TxPwDiff_CrystalCap   0x5

Definition at line 67 of file r8192E_hw.h.

#define EEPROM_DID   0x04

Definition at line 49 of file r8192E_hw.h.

#define EEPROM_IC_VER   0x7d

Definition at line 79 of file r8192E_hw.h.

#define EEPROM_ICVersion_ChannelPlan   0x7C

Definition at line 71 of file r8192E_hw.h.

#define EEPROM_NODE_ADDRESS_BYTE_0   0x0C

Definition at line 50 of file r8192E_hw.h.

#define EEPROM_PwDiff   0x21

Definition at line 55 of file r8192E_hw.h.

#define EEPROM_RFInd_PowerDiff   0x28

Definition at line 73 of file r8192E_hw.h.

#define EEPROM_ThermalMeter   0x29

Definition at line 74 of file r8192E_hw.h.

#define EEPROM_TxPowerDiff   0x1F

Definition at line 52 of file r8192E_hw.h.

#define EEPROM_TxPwDiff_CrystalCap   0x2A

Definition at line 75 of file r8192E_hw.h.

#define EEPROM_TxPwIndex_CCK   0x2C

Definition at line 76 of file r8192E_hw.h.

#define EEPROM_TxPwIndex_CCK_V1   0x29

Definition at line 60 of file r8192E_hw.h.

#define EEPROM_TxPwIndex_OFDM_24G   0x3A

Definition at line 77 of file r8192E_hw.h.

#define EEPROM_TxPwIndex_OFDM_24G_V1   0x2C

Definition at line 61 of file r8192E_hw.h.

#define EEPROM_TxPwIndex_Ver   0x27

Definition at line 62 of file r8192E_hw.h.

#define EEPROM_VID   0x02

Definition at line 48 of file r8192E_hw.h.

#define EPROM_CK_SHIFT   2

Definition at line 123 of file r8192E_hw.h.

#define EPROM_CMD_9356SEL   BIT4

Definition at line 115 of file r8192E_hw.h.

#define EPROM_CMD_CONFIG   0x3

Definition at line 118 of file r8192E_hw.h.

#define EPROM_CMD_LOAD   1

Definition at line 120 of file r8192E_hw.h.

#define EPROM_CMD_NORMAL   0

Definition at line 119 of file r8192E_hw.h.

#define EPROM_CMD_OPERATING_MODE_MASK   ((1<<7)|(1<<6))

Definition at line 117 of file r8192E_hw.h.

#define EPROM_CMD_OPERATING_MODE_SHIFT   6

Definition at line 116 of file r8192E_hw.h.

#define EPROM_CMD_PROGRAM   2

Definition at line 121 of file r8192E_hw.h.

#define EPROM_CMD_RESERVED_MASK   BIT5

Definition at line 114 of file r8192E_hw.h.

#define EPROM_CS_SHIFT   3

Definition at line 122 of file r8192E_hw.h.

#define EPROM_R_SHIFT   0

Definition at line 125 of file r8192E_hw.h.

#define EPROM_W_SHIFT   1

Definition at line 124 of file r8192E_hw.h.

#define GPE   0x10a

Definition at line 447 of file r8192E_hw.h.

#define GPI   0x108

Definition at line 445 of file r8192E_hw.h.

#define GPO   0x109

Definition at line 446 of file r8192E_hw.h.

#define HWSET_MAX_SIZE_92S   128

Definition at line 449 of file r8192E_hw.h.

#define IMR8190_DISABLED   0x0

Definition at line 223 of file r8192E_hw.h.

#define IMR_ATIMEND   BIT28

Definition at line 224 of file r8192E_hw.h.

#define IMR_BcnInt   BIT13

Definition at line 229 of file r8192E_hw.h.

#define IMR_BDOK   BIT9

Definition at line 233 of file r8192E_hw.h.

#define IMR_BEDOK   BIT3

Definition at line 239 of file r8192E_hw.h.

#define IMR_BKDOK   BIT4

Definition at line 238 of file r8192E_hw.h.

#define IMR_COMDOK   BIT7

Definition at line 235 of file r8192E_hw.h.

#define IMR_HCCADOK   BIT5

Definition at line 237 of file r8192E_hw.h.

#define IMR_HIGHDOK   BIT8

Definition at line 234 of file r8192E_hw.h.

#define IMR_MGNTDOK   BIT6

Definition at line 236 of file r8192E_hw.h.

#define IMR_RDU   BIT11

Definition at line 231 of file r8192E_hw.h.

#define IMR_ROK   BIT0

Definition at line 242 of file r8192E_hw.h.

#define IMR_RXCMDOK   BIT10

Definition at line 232 of file r8192E_hw.h.

#define IMR_RXFOVW   BIT12

Definition at line 230 of file r8192E_hw.h.

#define IMR_TBDER   BIT26

Definition at line 226 of file r8192E_hw.h.

#define IMR_TBDOK   BIT27

Definition at line 225 of file r8192E_hw.h.

#define IMR_TIMEOUT0   BIT14

Definition at line 228 of file r8192E_hw.h.

#define IMR_TXFOVW   BIT15

Definition at line 227 of file r8192E_hw.h.

#define IMR_VIDOK   BIT2

Definition at line 240 of file r8192E_hw.h.

#define IMR_VODOK   BIT1

Definition at line 241 of file r8192E_hw.h.

#define MAX_RX_URB   16

Definition at line 35 of file r8192E_hw.h.

#define MAX_TX_URB   5

Definition at line 34 of file r8192E_hw.h.

#define MSR_ADHOC   0x01

Definition at line 360 of file r8192E_hw.h.

#define MSR_AP   0x03

Definition at line 362 of file r8192E_hw.h.

#define MSR_INFRA   0x02

Definition at line 361 of file r8192E_hw.h.

#define MSR_LINK_ADHOC   1

Definition at line 355 of file r8192E_hw.h.

#define MSR_LINK_ENEDCA   (1<<4)

Definition at line 357 of file r8192E_hw.h.

#define MSR_LINK_MANAGED   2

Definition at line 352 of file r8192E_hw.h.

#define MSR_LINK_MASK   ((1<<0)|(1<<1))

Definition at line 351 of file r8192E_hw.h.

#define MSR_LINK_MASTER   3

Definition at line 356 of file r8192E_hw.h.

#define MSR_LINK_NONE   0

Definition at line 353 of file r8192E_hw.h.

#define MSR_LINK_SHIFT   0

Definition at line 354 of file r8192E_hw.h.

#define MSR_NOLINK   0x00

Definition at line 359 of file r8192E_hw.h.

#define MULRW_SHIFT   3

Definition at line 109 of file r8192E_hw.h.

#define MXDMA2_1024bytes   0x110

Definition at line 106 of file r8192E_hw.h.

#define MXDMA2_128bytes   0x011

Definition at line 103 of file r8192E_hw.h.

#define MXDMA2_16bytes   0x000

Definition at line 100 of file r8192E_hw.h.

#define MXDMA2_256bytes   0x100

Definition at line 104 of file r8192E_hw.h.

#define MXDMA2_32bytes   0x001

Definition at line 101 of file r8192E_hw.h.

#define MXDMA2_512bytes   0x101

Definition at line 105 of file r8192E_hw.h.

#define MXDMA2_64bytes   0x010

Definition at line 102 of file r8192E_hw.h.

#define MXDMA2_NoLimit   0x7

Definition at line 107 of file r8192E_hw.h.

#define MXDMA2_RX_SHIFT   4

Definition at line 110 of file r8192E_hw.h.

#define MXDMA2_TX_SHIFT   0

Definition at line 111 of file r8192E_hw.h.

#define PSR_CPU   0x1

Definition at line 265 of file r8192E_hw.h.

#define PSR_GEN   0x0

Definition at line 264 of file r8192E_hw.h.

#define RATE_ALL_CCK   (RATR_1M | RATR_2M | RATR_55M | RATR_11M)

Definition at line 426 of file r8192E_hw.h.

#define RATE_ALL_OFDM_1SS
Value:
RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
RATR_MCS6 | RATR_MCS7)

Definition at line 429 of file r8192E_hw.h.

#define RATE_ALL_OFDM_2SS
Value:
RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
RATR_MCS14|RATR_MCS15)

Definition at line 432 of file r8192E_hw.h.

#define RATE_ALL_OFDM_AG
Value:

Definition at line 427 of file r8192E_hw.h.

#define RATR_11M   0x00000008

Definition at line 401 of file r8192E_hw.h.

#define RATR_12M   0x00000040

Definition at line 404 of file r8192E_hw.h.

#define RATR_18M   0x00000080

Definition at line 405 of file r8192E_hw.h.

#define RATR_1M   0x00000001

Definition at line 398 of file r8192E_hw.h.

#define RATR_24M   0x00000100

Definition at line 406 of file r8192E_hw.h.

#define RATR_2M   0x00000002

Definition at line 399 of file r8192E_hw.h.

#define RATR_36M   0x00000200

Definition at line 407 of file r8192E_hw.h.

#define RATR_48M   0x00000400

Definition at line 408 of file r8192E_hw.h.

#define RATR_54M   0x00000800

Definition at line 409 of file r8192E_hw.h.

#define RATR_55M   0x00000004

Definition at line 400 of file r8192E_hw.h.

#define RATR_6M   0x00000010

Definition at line 402 of file r8192E_hw.h.

#define RATR_9M   0x00000020

Definition at line 403 of file r8192E_hw.h.

#define RATR_MCS0   0x00001000

Definition at line 410 of file r8192E_hw.h.

#define RATR_MCS1   0x00002000

Definition at line 411 of file r8192E_hw.h.

#define RATR_MCS10   0x00400000

Definition at line 420 of file r8192E_hw.h.

#define RATR_MCS11   0x00800000

Definition at line 421 of file r8192E_hw.h.

#define RATR_MCS12   0x01000000

Definition at line 422 of file r8192E_hw.h.

#define RATR_MCS13   0x02000000

Definition at line 423 of file r8192E_hw.h.

#define RATR_MCS14   0x04000000

Definition at line 424 of file r8192E_hw.h.

#define RATR_MCS15   0x08000000

Definition at line 425 of file r8192E_hw.h.

#define RATR_MCS2   0x00004000

Definition at line 412 of file r8192E_hw.h.

#define RATR_MCS3   0x00008000

Definition at line 413 of file r8192E_hw.h.

#define RATR_MCS4   0x00010000

Definition at line 414 of file r8192E_hw.h.

#define RATR_MCS5   0x00020000

Definition at line 415 of file r8192E_hw.h.

#define RATR_MCS6   0x00040000

Definition at line 416 of file r8192E_hw.h.

#define RATR_MCS7   0x00080000

Definition at line 417 of file r8192E_hw.h.

#define RATR_MCS8   0x00100000

Definition at line 418 of file r8192E_hw.h.

#define RATR_MCS9   0x00200000

Definition at line 419 of file r8192E_hw.h.

#define RCR_AAP   BIT0

Definition at line 163 of file r8192E_hw.h.

#define RCR_AB   BIT3

Definition at line 160 of file r8192E_hw.h.

#define RCR_ACF   BIT19

Definition at line 155 of file r8192E_hw.h.

#define RCR_ACKTXBW   (BIT24|BIT25)

Definition at line 150 of file r8192E_hw.h.

#define RCR_ACRC32   BIT5

Definition at line 159 of file r8192E_hw.h.

#define RCR_ADD3   BIT21

Definition at line 153 of file r8192E_hw.h.

#define RCR_ADF   BIT18

Definition at line 156 of file r8192E_hw.h.

#define RCR_AICV   BIT12

Definition at line 158 of file r8192E_hw.h.

#define RCR_AM   BIT2

Definition at line 161 of file r8192E_hw.h.

#define RCR_AMF   BIT20

Definition at line 154 of file r8192E_hw.h.

#define RCR_APM   BIT1

Definition at line 162 of file r8192E_hw.h.

#define RCR_APWRMGT   BIT22

Definition at line 152 of file r8192E_hw.h.

#define RCR_CBSSID   BIT23

Definition at line 151 of file r8192E_hw.h.

#define RCR_ENCS1   BIT29

Definition at line 148 of file r8192E_hw.h.

#define RCR_ENCS2   BIT30

Definition at line 147 of file r8192E_hw.h.

#define RCR_ENMBID   BIT27

Definition at line 149 of file r8192E_hw.h.

#define RCR_FIFO_OFFSET   13

Definition at line 165 of file r8192E_hw.h.

#define RCR_FILTER_MASK
Value:
(BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23)

Definition at line 144 of file r8192E_hw.h.

#define RCR_MXDMA_OFFSET   8

Definition at line 164 of file r8192E_hw.h.

#define RCR_ONLYERLPKT   BIT31

Definition at line 146 of file r8192E_hw.h.

#define RCR_RXFTH   BIT13

Definition at line 157 of file r8192E_hw.h.

#define RETRY_LIMIT_LONG_SHIFT   0

Definition at line 366 of file r8192E_hw.h.

#define RETRY_LIMIT_SHORT_SHIFT   8

Definition at line 365 of file r8192E_hw.h.

#define RRSR_11M   BIT3

Definition at line 378 of file r8192E_hw.h.

#define RRSR_12M   BIT6

Definition at line 381 of file r8192E_hw.h.

#define RRSR_18M   BIT7

Definition at line 382 of file r8192E_hw.h.

#define RRSR_1M   BIT0

Definition at line 375 of file r8192E_hw.h.

#define RRSR_24M   BIT8

Definition at line 383 of file r8192E_hw.h.

#define RRSR_2M   BIT1

Definition at line 376 of file r8192E_hw.h.

#define RRSR_36M   BIT9

Definition at line 384 of file r8192E_hw.h.

#define RRSR_48M   BIT10

Definition at line 385 of file r8192E_hw.h.

#define RRSR_54M   BIT11

Definition at line 386 of file r8192E_hw.h.

#define RRSR_5_5M   BIT2

Definition at line 377 of file r8192E_hw.h.

#define RRSR_6M   BIT4

Definition at line 379 of file r8192E_hw.h.

#define RRSR_9M   BIT5

Definition at line 380 of file r8192E_hw.h.

#define RRSR_MCS0   BIT12

Definition at line 387 of file r8192E_hw.h.

#define RRSR_MCS1   BIT13

Definition at line 388 of file r8192E_hw.h.

#define RRSR_MCS2   BIT14

Definition at line 389 of file r8192E_hw.h.

#define RRSR_MCS3   BIT15

Definition at line 390 of file r8192E_hw.h.

#define RRSR_MCS4   BIT16

Definition at line 391 of file r8192E_hw.h.

#define RRSR_MCS5   BIT17

Definition at line 392 of file r8192E_hw.h.

#define RRSR_MCS6   BIT18

Definition at line 393 of file r8192E_hw.h.

#define RRSR_MCS7   BIT19

Definition at line 394 of file r8192E_hw.h.

#define RRSR_RSC_DUPLICATE   0x600000

Definition at line 371 of file r8192E_hw.h.

#define RRSR_RSC_LOWSUBCHNL   0x200000

Definition at line 373 of file r8192E_hw.h.

#define RRSR_RSC_OFFSET   21

Definition at line 369 of file r8192E_hw.h.

#define RRSR_RSC_UPSUBCHNL   0x400000

Definition at line 372 of file r8192E_hw.h.

#define RRSR_SHORT   0x800000

Definition at line 374 of file r8192E_hw.h.

#define RRSR_SHORT_OFFSET   23

Definition at line 370 of file r8192E_hw.h.

#define RTL8187_REQ_GET_REGS   0x05

Definition at line 31 of file r8192E_hw.h.

#define RTL8187_REQ_SET_REGS   0x05

Definition at line 32 of file r8192E_hw.h.

#define RTL8187_REQT_READ   0xc0

Definition at line 29 of file r8192E_hw.h.

#define RTL8187_REQT_WRITE   0x40

Definition at line 30 of file r8192E_hw.h.

#define RTL8190_EEPROM_ID   0x8129

Definition at line 47 of file r8192E_hw.h.

#define RX_URB_SIZE   9100

Definition at line 36 of file r8192E_hw.h.

#define SCR_NoSKMC   BIT5

Definition at line 220 of file r8192E_hw.h.

#define SCR_RxDecEnable   BIT3

Definition at line 218 of file r8192E_hw.h.

#define SCR_RxUseDK   BIT1

Definition at line 216 of file r8192E_hw.h.

#define SCR_SKByA2   BIT4

Definition at line 219 of file r8192E_hw.h.

#define SCR_TxEncEnable   BIT2

Definition at line 217 of file r8192E_hw.h.

#define SCR_TxUseDK   BIT0

Definition at line 215 of file r8192E_hw.h.

#define SCR_UseDK   0x01

Definition at line 211 of file r8192E_hw.h.

#define TOTAL_CAM_ENTRY   32

Definition at line 204 of file r8192E_hw.h.

#define TPPoll_BEQ   BIT1

Definition at line 246 of file r8192E_hw.h.

#define TPPoll_BKQ   BIT0

Definition at line 245 of file r8192E_hw.h.

#define TPPoll_BQ   BIT4

Definition at line 249 of file r8192E_hw.h.

#define TPPoll_CQ   BIT5

Definition at line 250 of file r8192E_hw.h.

#define TPPoll_HCCAQ   BIT8

Definition at line 253 of file r8192E_hw.h.

#define TPPoll_HQ   BIT7

Definition at line 252 of file r8192E_hw.h.

#define TPPoll_MQ   BIT6

Definition at line 251 of file r8192E_hw.h.

#define TPPoll_SHIFT   8

Definition at line 261 of file r8192E_hw.h.

#define TPPoll_StopBE   BIT10

Definition at line 255 of file r8192E_hw.h.

#define TPPoll_StopBK   BIT9

Definition at line 254 of file r8192E_hw.h.

#define TPPoll_StopHCCA   BIT15

Definition at line 260 of file r8192E_hw.h.

#define TPPoll_StopHigh   BIT14

Definition at line 259 of file r8192E_hw.h.

#define TPPoll_StopMgt   BIT13

Definition at line 258 of file r8192E_hw.h.

#define TPPoll_StopVI   BIT11

Definition at line 256 of file r8192E_hw.h.

#define TPPoll_StopVO   BIT12

Definition at line 257 of file r8192E_hw.h.

#define TPPoll_VIQ   BIT2

Definition at line 247 of file r8192E_hw.h.

#define TPPoll_VOQ   BIT3

Definition at line 248 of file r8192E_hw.h.

Enumeration Type Documentation

Enumerator:
MAC0 
MAC1 
MAC2 
MAC3 
MAC4 
MAC5 
PCIF 
PMR 
EPROM_CMD 
AFR 
ANAPAR 
BB_GLOBAL_RESET 
BSSIDR 
CMDR 
SIFS 
TCR 
RCR 
SLOT_TIME 
ACK_TIMEOUT 
PIFS_TIME 
USTIME 
EDCAPARA_BE 
EDCAPARA_BK 
EDCAPARA_VO 
EDCAPARA_VI 
RFPC 
CWRR 
BCN_TCFG 
BCN_INTERVAL 
ATIMWND 
BCN_DRV_EARLY_INT 
BCN_DMATIME 
BCN_ERR_THRESH 
RWCAM 
WCAMI 
RCAMO 
SECR 
SWREGULATOR 
INTA_MASK 
ISR 
TPPoll 
PSR 
CPU_GEN 
BB_RESET 
LED1Cfg 
LED0Cfg 
AcmAvg 
AcmHwCtrl 
AcmFwCtrl 
VOAdmTime 
VIAdmTime 
BEAdmTime 
RQPN1 
RQPN2 
RQPN3 
QPRR 
QPNR 
BQDA 
HQDA 
CQDA 
MQDA 
HCCAQDA 
VOQDA 
VIQDA 
BEQDA 
BKQDA 
RCQDA 
RDQDA 
MAR0 
MAR4 
CCX_PERIOD 
CLM_RESULT 
NHM_PERIOD 
NHM_THRESHOLD0 
NHM_THRESHOLD1 
NHM_THRESHOLD2 
NHM_THRESHOLD3 
NHM_THRESHOLD4 
NHM_THRESHOLD5 
NHM_THRESHOLD6 
MCTRL 
NHM_RPI_COUNTER0 
NHM_RPI_COUNTER1 
NHM_RPI_COUNTER2 
NHM_RPI_COUNTER3 
NHM_RPI_COUNTER4 
NHM_RPI_COUNTER5 
NHM_RPI_COUNTER6 
NHM_RPI_COUNTER7 
WFCRC0 
WFCRC1 
WFCRC2 
BW_OPMODE 
IC_VERRSION 
MSR 
RETRY_LIMIT 
TSFR 
RRSR 
UFWP 
RATR0 
DRIVER_RSSI 
MCS_TXAGC 
CCK_TXAGC 
MacBlkCtrl 

Definition at line 92 of file r8192E_hw.h.

Enumerator:
BaseBand_Config_PHY_REG 
BaseBand_Config_AGC_TAB 

Definition at line 24 of file r8192E_hw.h.