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r8192U_dm.h
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1 /*****************************************************************************
2  * Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved.
3  *
4  * Module: Hal819xUsbDM.h (RTL8192 Header H File)
5  *
6  *
7  * Note: For dynamic control definition constant structure.
8  *
9  *
10  * Export:
11  *
12  * Abbrev:
13  *
14  * History:
15  * Data Who Remark
16  * 10/04/2007 MHC Create initial version.
17  *
18  *****************************************************************************/
19  /* Check to see if the file has been included already. */
20 #ifndef __R8192UDM_H__
21 #define __R8192UDM_H__
22 
23 
24 /*--------------------------Define Parameters-------------------------------*/
25 #define DM_DIG_THRESH_HIGH 40
26 #define DM_DIG_THRESH_LOW 35
27 
28 #define DM_DIG_HIGH_PWR_THRESH_HIGH 75
29 #define DM_DIG_HIGH_PWR_THRESH_LOW 70
30 
31 #define BW_AUTO_SWITCH_HIGH_LOW 25
32 #define BW_AUTO_SWITCH_LOW_HIGH 30
33 
34 #define DM_check_fsync_time_interval 500
35 
36 
37 #define DM_DIG_BACKOFF 12
38 #define DM_DIG_MAX 0x36
39 #define DM_DIG_MIN 0x1c
40 #define DM_DIG_MIN_Netcore 0x12
41 
42 #define RxPathSelection_SS_TH_low 30
43 #define RxPathSelection_diff_TH 18
44 
45 #define RateAdaptiveTH_High 50
46 #define RateAdaptiveTH_Low_20M 30
47 #define RateAdaptiveTH_Low_40M 10
48 #define VeryLowRSSI 15
49 #define CTSToSelfTHVal 30
50 
51 //defined by vivi, for tx power track
52 #define E_FOR_TX_POWER_TRACK 300
53 //Dynamic Tx Power Control Threshold
54 #define TX_POWER_NEAR_FIELD_THRESH_HIGH 68
55 #define TX_POWER_NEAR_FIELD_THRESH_LOW 62
56 //added by amy for atheros AP
57 #define TX_POWER_ATHEROAP_THRESH_HIGH 78
58 #define TX_POWER_ATHEROAP_THRESH_LOW 72
59 
60 //defined by vivi, for showing on UI
61 #define Current_Tx_Rate_Reg 0x1b8
62 #define Initial_Tx_Rate_Reg 0x1b9
63 #define Tx_Retry_Count_Reg 0x1ac
64 #define RegC38_TH 20
65 /*--------------------------Define Parameters-------------------------------*/
66 
67 
68 /*------------------------------Define structure----------------------------*/
69 /* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */
70 typedef struct _dynamic_initial_gain_threshold_
71 {
72  u8 dig_enable_flag;
73  u8 dig_algorithm;
74  u8 dbg_mode;
75  u8 dig_algorithm_switch;
76 
77  long rssi_low_thresh;
78  long rssi_high_thresh;
79 
80  long rssi_high_power_lowthresh;
81  long rssi_high_power_highthresh;
82 
83  u8 dig_state;
84  u8 dig_highpwr_state;
85  u8 cur_connect_state;
86  u8 pre_connect_state;
87 
88  u8 curpd_thstate;
89  u8 prepd_thstate;
90  u8 curcs_ratio_state;
91  u8 precs_ratio_state;
92 
93  u32 pre_ig_value;
94  u32 cur_ig_value;
95 
96  u8 backoff_val;
97  u8 rx_gain_range_max;
98  u8 rx_gain_range_min;
99  bool initialgain_lowerbound_state;
100 
101  long rssi_val;
102 }dig_t;
103 
104 typedef enum tag_dynamic_init_gain_state_definition
105 {
106  DM_STA_DIG_OFF = 0,
107  DM_STA_DIG_ON,
108  DM_STA_DIG_MAX
109 }dm_dig_sta_e;
110 
111 
112 /* 2007/10/08 MH Define RATR state. */
113 typedef enum tag_dynamic_ratr_state_definition
114 {
115  DM_RATR_STA_HIGH = 0,
116  DM_RATR_STA_MIDDLE = 1,
117  DM_RATR_STA_LOW = 2,
118  DM_RATR_STA_MAX
119 }dm_ratr_sta_e;
120 
121 /* 2007/10/11 MH Define DIG operation type. */
122 typedef enum tag_dynamic_init_gain_operation_type_definition
123 {
124  DIG_TYPE_THRESH_HIGH = 0,
125  DIG_TYPE_THRESH_LOW = 1,
126  DIG_TYPE_THRESH_HIGHPWR_HIGH = 2,
127  DIG_TYPE_THRESH_HIGHPWR_LOW = 3,
128  DIG_TYPE_DBG_MODE = 4,
129  DIG_TYPE_RSSI = 5,
130  DIG_TYPE_ALGORITHM = 6,
131  DIG_TYPE_BACKOFF = 7,
132  DIG_TYPE_PWDB_FACTOR = 8,
133  DIG_TYPE_RX_GAIN_MIN = 9,
134  DIG_TYPE_RX_GAIN_MAX = 10,
135  DIG_TYPE_ENABLE = 20,
136  DIG_TYPE_DISABLE = 30,
137  DIG_OP_TYPE_MAX
138 }dm_dig_op_e;
139 
140 typedef enum tag_dig_algorithm_definition
141 {
142  DIG_ALGO_BY_FALSE_ALARM = 0,
143  DIG_ALGO_BY_RSSI = 1,
144  DIG_ALGO_MAX
145 }dm_dig_alg_e;
146 
147 typedef enum tag_dig_dbgmode_definition
148 {
149  DIG_DBG_OFF = 0,
150  DIG_DBG_ON = 1,
151  DIG_DBG_MAX
152 }dm_dig_dbg_e;
153 
154 typedef enum tag_dig_connect_definition
155 {
156  DIG_DISCONNECT = 0,
157  DIG_CONNECT = 1,
158  DIG_CONNECT_MAX
159 }dm_dig_connect_e;
160 
161 typedef enum tag_dig_packetdetection_threshold_definition
162 {
163  DIG_PD_AT_LOW_POWER = 0,
164  DIG_PD_AT_NORMAL_POWER = 1,
165  DIG_PD_AT_HIGH_POWER = 2,
166  DIG_PD_MAX
167 }dm_dig_pd_th_e;
168 
169 typedef enum tag_dig_cck_cs_ratio_state_definition
170 {
171  DIG_CS_RATIO_LOWER = 0,
172  DIG_CS_RATIO_HIGHER = 1,
173  DIG_CS_MAX
174 }dm_dig_cs_ratio_e;
175 typedef struct _Dynamic_Rx_Path_Selection_
176 {
177  u8 Enable;
178  u8 DbgMode;
179  u8 cck_method;
180  u8 cck_Rx_path;
181 
182  u8 SS_TH_low;
183  u8 diff_TH;
184  u8 disabledRF;
185  u8 reserved;
186 
187  u8 rf_rssi[4];
188  u8 rf_enable_rssi_th[4];
189  long cck_pwdb_sta[4];
190 }DRxPathSel;
191 
192 typedef enum tag_CCK_Rx_Path_Method_Definition
193 {
194  CCK_Rx_Version_1 = 0,
195  CCK_Rx_Version_2= 1,
196  CCK_Rx_Version_MAX
197 }DM_CCK_Rx_Path_Method;
198 
199 typedef enum tag_DM_DbgMode_Definition
200 {
201  DM_DBG_OFF = 0,
202  DM_DBG_ON = 1,
203  DM_DBG_MAX
204 }DM_DBG_E;
205 
206 typedef struct tag_Tx_Config_Cmd_Format
207 {
208  u32 Op; /* Command packet type. */
209  u32 Length; /* Command packet length. */
210  u32 Value;
211 }DCMD_TXCMD_T, *PDCMD_TXCMD_T;
212 /*------------------------------Define structure----------------------------*/
213 
214 
215 /*------------------------Export global variable----------------------------*/
216 extern dig_t dm_digtable;
217 extern u8 dm_shadow[16][256];
218 extern DRxPathSel DM_RxPathSelTable;
219 /*------------------------Export global variable----------------------------*/
220 
221 
222 /*------------------------Export Marco Definition---------------------------*/
223 
224 /*------------------------Export Marco Definition---------------------------*/
225 
226 
227 /*--------------------------Exported Function prototype---------------------*/
228 extern void init_hal_dm(struct net_device *dev);
229 extern void deinit_hal_dm(struct net_device *dev);
230 
231 extern void hal_dm_watchdog(struct net_device *dev);
232 
233 extern void init_rate_adaptive(struct net_device *dev);
234 extern void dm_txpower_trackingcallback(struct work_struct *work);
235 extern void dm_restore_dynamic_mechanism_state(struct net_device *dev);
236 extern void dm_backup_dynamic_mechanism_state(struct net_device *dev);
237 extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
238  u32 dm_type, u32 dm_value);
239 extern void dm_force_tx_fw_info(struct net_device *dev,u32 force_type, u32 force_value);
240 extern void dm_init_edca_turbo(struct net_device *dev);
241 extern void dm_rf_operation_test_callback(unsigned long data);
242 extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
243 extern void dm_fsync_timer_callback(unsigned long data);
244 extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
245 extern void dm_shadow_init(struct net_device *dev);
246 extern void dm_initialize_txpower_tracking(struct net_device *dev);
247 /*--------------------------Exported Function prototype---------------------*/
248 
249 
250 #endif /*__R8192UDM_H__ */
251 
252 
253 /* End of r8192U_dm.h */
254 
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