#include "r300_reg.h"
#include "r500_reg.h"
#include "r600_reg.h"
#include "evergreen_reg.h"
#include "ni_reg.h"
#include "si_reg.h"

Macros
#define	RADEON_MC_AGP_LOCATION 0x014c

#define	RADEON_MC_AGP_START_MASK 0x0000FFFF

#define	RADEON_MC_AGP_START_SHIFT 0

#define	RADEON_MC_AGP_TOP_MASK 0xFFFF0000

#define	RADEON_MC_AGP_TOP_SHIFT 16

#define	RADEON_MC_FB_LOCATION 0x0148

#define	RADEON_MC_FB_START_MASK 0x0000FFFF

#define	RADEON_MC_FB_START_SHIFT 0

#define	RADEON_MC_FB_TOP_MASK 0xFFFF0000

#define	RADEON_MC_FB_TOP_SHIFT 16

#define	RADEON_AGP_BASE_2 0x015c /* r200+ only */

#define	RADEON_AGP_BASE 0x0170

#define	ATI_DATATYPE_VQ 0

#define	ATI_DATATYPE_CI4 1

#define	ATI_DATATYPE_CI8 2

#define	ATI_DATATYPE_ARGB1555 3

#define	ATI_DATATYPE_RGB565 4

#define	ATI_DATATYPE_RGB888 5

#define	ATI_DATATYPE_ARGB8888 6

#define	ATI_DATATYPE_RGB332 7

#define	ATI_DATATYPE_Y8 8

#define	ATI_DATATYPE_RGB8 9

#define	ATI_DATATYPE_CI16 10

#define	ATI_DATATYPE_VYUY_422 11

#define	ATI_DATATYPE_YVYU_422 12

#define	ATI_DATATYPE_AYUV_444 14

#define	ATI_DATATYPE_ARGB4444 15

#define	RADEON_ADAPTER_ID 0x0f2c /* PCI */

#define	RADEON_AGP_BASE 0x0170

#define	RADEON_AGP_CNTL 0x0174

#define	RADEON_AGP_APER_SIZE_256MB (0x00 << 0)

#define	RADEON_AGP_APER_SIZE_128MB (0x20 << 0)

#define	RADEON_AGP_APER_SIZE_64MB (0x30 << 0)

#define	RADEON_AGP_APER_SIZE_32MB (0x38 << 0)

#define	RADEON_AGP_APER_SIZE_16MB (0x3c << 0)

#define	RADEON_AGP_APER_SIZE_8MB (0x3e << 0)

#define	RADEON_AGP_APER_SIZE_4MB (0x3f << 0)

#define	RADEON_AGP_APER_SIZE_MASK (0x3f << 0)

#define	RADEON_STATUS_PCI_CONFIG 0x06

#define	RADEON_CAP_LIST 0x100000

#define	RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/

#define	RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */

#define	RADEON_CAP_ID_NULL 0x00 /* End of capability list */

#define	RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */

#define	RADEON_CAP_ID_EXP 0x10 /* PCI Express */

#define	RADEON_AGP_COMMAND 0x0f60 /* PCI */

#define	RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/

#define	RADEON_AGP_ENABLE (1<<8)

#define	RADEON_AGP_PLL_CNTL 0x000b /* PLL */

#define	RADEON_AGP_STATUS 0x0f5c /* PCI */

#define	RADEON_AGP_1X_MODE 0x01

#define	RADEON_AGP_2X_MODE 0x02

#define	RADEON_AGP_4X_MODE 0x04

#define	RADEON_AGP_FW_MODE 0x10

#define	RADEON_AGP_MODE_MASK 0x17

#define	RADEON_AGPv3_MODE 0x08

#define	RADEON_AGPv3_4X_MODE 0x01

#define	RADEON_AGPv3_8X_MODE 0x02

#define	RADEON_ATTRDR 0x03c1 /* VGA */

#define	RADEON_ATTRDW 0x03c0 /* VGA */

#define	RADEON_ATTRX 0x03c0 /* VGA */

#define	RADEON_AUX_SC_CNTL 0x1660

#define	RADEON_AUX1_SC_EN (1 << 0)

#define	RADEON_AUX1_SC_MODE_OR (0 << 1)

#define	RADEON_AUX1_SC_MODE_NAND (1 << 1)

#define	RADEON_AUX2_SC_EN (1 << 2)

#define	RADEON_AUX2_SC_MODE_OR (0 << 3)

#define	RADEON_AUX2_SC_MODE_NAND (1 << 3)

#define	RADEON_AUX3_SC_EN (1 << 4)

#define	RADEON_AUX3_SC_MODE_OR (0 << 5)

#define	RADEON_AUX3_SC_MODE_NAND (1 << 5)

#define	RADEON_AUX1_SC_BOTTOM 0x1670

#define	RADEON_AUX1_SC_LEFT 0x1664

#define	RADEON_AUX1_SC_RIGHT 0x1668

#define	RADEON_AUX1_SC_TOP 0x166c

#define	RADEON_AUX2_SC_BOTTOM 0x1680

#define	RADEON_AUX2_SC_LEFT 0x1674

#define	RADEON_AUX2_SC_RIGHT 0x1678

#define	RADEON_AUX2_SC_TOP 0x167c

#define	RADEON_AUX3_SC_BOTTOM 0x1690

#define	RADEON_AUX3_SC_LEFT 0x1684

#define	RADEON_AUX3_SC_RIGHT 0x1688

#define	RADEON_AUX3_SC_TOP 0x168c

#define	RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8

#define	RADEON_AUX_WINDOW_VERT_CNTL 0x02dc

#define	RADEON_BASE_CODE 0x0f0b

#define	RADEON_BIOS_0_SCRATCH 0x0010

#define	RADEON_FP_PANEL_SCALABLE (1 << 16)

#define	RADEON_FP_PANEL_SCALE_EN (1 << 17)

#define	RADEON_FP_CHIP_SCALE_EN (1 << 18)

#define	RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)

#define	RADEON_DISPLAY_ROT_MASK (3 << 28)

#define	RADEON_DISPLAY_ROT_00 (0 << 28)

#define	RADEON_DISPLAY_ROT_90 (1 << 28)

#define	RADEON_DISPLAY_ROT_180 (2 << 28)

#define	RADEON_DISPLAY_ROT_270 (3 << 28)

#define	RADEON_BIOS_1_SCRATCH 0x0014

#define	RADEON_BIOS_2_SCRATCH 0x0018

#define	RADEON_BIOS_3_SCRATCH 0x001c

#define	RADEON_BIOS_4_SCRATCH 0x0020

#define	RADEON_CRT1_ATTACHED_MASK (3 << 0)

#define	RADEON_CRT1_ATTACHED_MONO (1 << 0)

#define	RADEON_CRT1_ATTACHED_COLOR (2 << 0)

#define	RADEON_LCD1_ATTACHED (1 << 2)

#define	RADEON_DFP1_ATTACHED (1 << 3)

#define	RADEON_TV1_ATTACHED_MASK (3 << 4)

#define	RADEON_TV1_ATTACHED_COMP (1 << 4)

#define	RADEON_TV1_ATTACHED_SVIDEO (2 << 4)

#define	RADEON_CRT2_ATTACHED_MASK (3 << 8)

#define	RADEON_CRT2_ATTACHED_MONO (1 << 8)

#define	RADEON_CRT2_ATTACHED_COLOR (2 << 8)

#define	RADEON_DFP2_ATTACHED (1 << 11)

#define	RADEON_BIOS_5_SCRATCH 0x0024

#define	RADEON_LCD1_ON (1 << 0)

#define	RADEON_CRT1_ON (1 << 1)

#define	RADEON_TV1_ON (1 << 2)

#define	RADEON_DFP1_ON (1 << 3)

#define	RADEON_CRT2_ON (1 << 5)

#define	RADEON_CV1_ON (1 << 6)

#define	RADEON_DFP2_ON (1 << 7)

#define	RADEON_LCD1_CRTC_MASK (1 << 8)

#define	RADEON_LCD1_CRTC_SHIFT 8

#define	RADEON_CRT1_CRTC_MASK (1 << 9)

#define	RADEON_CRT1_CRTC_SHIFT 9

#define	RADEON_TV1_CRTC_MASK (1 << 10)

#define	RADEON_TV1_CRTC_SHIFT 10

#define	RADEON_DFP1_CRTC_MASK (1 << 11)

#define	RADEON_DFP1_CRTC_SHIFT 11

#define	RADEON_CRT2_CRTC_MASK (1 << 12)

#define	RADEON_CRT2_CRTC_SHIFT 12

#define	RADEON_CV1_CRTC_MASK (1 << 13)

#define	RADEON_CV1_CRTC_SHIFT 13

#define	RADEON_DFP2_CRTC_MASK (1 << 14)

#define	RADEON_DFP2_CRTC_SHIFT 14

#define	RADEON_ACC_REQ_LCD1 (1 << 16)

#define	RADEON_ACC_REQ_CRT1 (1 << 17)

#define	RADEON_ACC_REQ_TV1 (1 << 18)

#define	RADEON_ACC_REQ_DFP1 (1 << 19)

#define	RADEON_ACC_REQ_CRT2 (1 << 21)

#define	RADEON_ACC_REQ_TV2 (1 << 22)

#define	RADEON_ACC_REQ_DFP2 (1 << 23)

#define	RADEON_BIOS_6_SCRATCH 0x0028

#define	RADEON_ACC_MODE_CHANGE (1 << 2)

#define	RADEON_EXT_DESKTOP_MODE (1 << 3)

#define	RADEON_LCD_DPMS_ON (1 << 20)

#define	RADEON_CRT_DPMS_ON (1 << 21)

#define	RADEON_TV_DPMS_ON (1 << 22)

#define	RADEON_DFP_DPMS_ON (1 << 23)

#define	RADEON_DPMS_MASK (3 << 24)

#define	RADEON_DPMS_ON (0 << 24)

#define	RADEON_DPMS_STANDBY (1 << 24)

#define	RADEON_DPMS_SUSPEND (2 << 24)

#define	RADEON_DPMS_OFF (3 << 24)

#define	RADEON_SCREEN_BLANKING (1 << 26)

#define	RADEON_DRIVER_CRITICAL (1 << 27)

#define	RADEON_DISPLAY_SWITCHING_DIS (1 << 30)

#define	RADEON_BIOS_7_SCRATCH 0x002c

#define	RADEON_SYS_HOTKEY (1 << 10)

#define	RADEON_DRV_LOADED (1 << 12)

#define	RADEON_BIOS_ROM 0x0f30 /* PCI */

#define	RADEON_BIST 0x0f0f /* PCI */

#define	RADEON_BRUSH_DATA0 0x1480

#define	RADEON_BRUSH_DATA1 0x1484

#define	RADEON_BRUSH_DATA10 0x14a8

#define	RADEON_BRUSH_DATA11 0x14ac

#define	RADEON_BRUSH_DATA12 0x14b0

#define	RADEON_BRUSH_DATA13 0x14b4

#define	RADEON_BRUSH_DATA14 0x14b8

#define	RADEON_BRUSH_DATA15 0x14bc

#define	RADEON_BRUSH_DATA16 0x14c0

#define	RADEON_BRUSH_DATA17 0x14c4

#define	RADEON_BRUSH_DATA18 0x14c8

#define	RADEON_BRUSH_DATA19 0x14cc

#define	RADEON_BRUSH_DATA2 0x1488

#define	RADEON_BRUSH_DATA20 0x14d0

#define	RADEON_BRUSH_DATA21 0x14d4

#define	RADEON_BRUSH_DATA22 0x14d8

#define	RADEON_BRUSH_DATA23 0x14dc

#define	RADEON_BRUSH_DATA24 0x14e0

#define	RADEON_BRUSH_DATA25 0x14e4

#define	RADEON_BRUSH_DATA26 0x14e8

#define	RADEON_BRUSH_DATA27 0x14ec

#define	RADEON_BRUSH_DATA28 0x14f0

#define	RADEON_BRUSH_DATA29 0x14f4

#define	RADEON_BRUSH_DATA3 0x148c

#define	RADEON_BRUSH_DATA30 0x14f8

#define	RADEON_BRUSH_DATA31 0x14fc

#define	RADEON_BRUSH_DATA32 0x1500

#define	RADEON_BRUSH_DATA33 0x1504

#define	RADEON_BRUSH_DATA34 0x1508

#define	RADEON_BRUSH_DATA35 0x150c

#define	RADEON_BRUSH_DATA36 0x1510

#define	RADEON_BRUSH_DATA37 0x1514

#define	RADEON_BRUSH_DATA38 0x1518

#define	RADEON_BRUSH_DATA39 0x151c

#define	RADEON_BRUSH_DATA4 0x1490

#define	RADEON_BRUSH_DATA40 0x1520

#define	RADEON_BRUSH_DATA41 0x1524

#define	RADEON_BRUSH_DATA42 0x1528

#define	RADEON_BRUSH_DATA43 0x152c

#define	RADEON_BRUSH_DATA44 0x1530

#define	RADEON_BRUSH_DATA45 0x1534

#define	RADEON_BRUSH_DATA46 0x1538

#define	RADEON_BRUSH_DATA47 0x153c

#define	RADEON_BRUSH_DATA48 0x1540

#define	RADEON_BRUSH_DATA49 0x1544

#define	RADEON_BRUSH_DATA5 0x1494

#define	RADEON_BRUSH_DATA50 0x1548

#define	RADEON_BRUSH_DATA51 0x154c

#define	RADEON_BRUSH_DATA52 0x1550

#define	RADEON_BRUSH_DATA53 0x1554

#define	RADEON_BRUSH_DATA54 0x1558

#define	RADEON_BRUSH_DATA55 0x155c

#define	RADEON_BRUSH_DATA56 0x1560

#define	RADEON_BRUSH_DATA57 0x1564

#define	RADEON_BRUSH_DATA58 0x1568

#define	RADEON_BRUSH_DATA59 0x156c

#define	RADEON_BRUSH_DATA6 0x1498

#define	RADEON_BRUSH_DATA60 0x1570

#define	RADEON_BRUSH_DATA61 0x1574

#define	RADEON_BRUSH_DATA62 0x1578

#define	RADEON_BRUSH_DATA63 0x157c

#define	RADEON_BRUSH_DATA7 0x149c

#define	RADEON_BRUSH_DATA8 0x14a0

#define	RADEON_BRUSH_DATA9 0x14a4

#define	RADEON_BRUSH_SCALE 0x1470

#define	RADEON_BRUSH_Y_X 0x1474

#define	RADEON_BUS_CNTL 0x0030

#define	RADEON_BUS_MASTER_DIS (1 << 6)

#define	RADEON_BUS_BIOS_DIS_ROM (1 << 12)

#define	RS600_BUS_MASTER_DIS (1 << 14)

#define	RS600_MSI_REARM (1 << 20) /* rs600/rs690/rs740 */

#define	RADEON_BUS_RD_DISCARD_EN (1 << 24)

#define	RADEON_BUS_RD_ABORT_EN (1 << 25)

#define	RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)

#define	RADEON_BUS_WRT_BURST (1 << 29)

#define	RADEON_BUS_READ_BURST (1 << 30)

#define	RADEON_BUS_CNTL1 0x0034

#define	RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)

#define	RV370_BUS_CNTL 0x004c

#define	RV370_BUS_BIOS_DIS_ROM (1 << 2)

#define	RADEON_MSI_REARM_EN 0x0160

#define	RV370_MSI_REARM_EN (1 << 0)

#define	RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */

#define	RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0

#define	RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7

#define	RADEON_PCIE_LC_LINK_WIDTH_X0 0

#define	RADEON_PCIE_LC_LINK_WIDTH_X1 1

#define	RADEON_PCIE_LC_LINK_WIDTH_X2 2

#define	RADEON_PCIE_LC_LINK_WIDTH_X4 3

#define	RADEON_PCIE_LC_LINK_WIDTH_X8 4

#define	RADEON_PCIE_LC_LINK_WIDTH_X12 5

#define	RADEON_PCIE_LC_LINK_WIDTH_X16 6

#define	RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4

#define	RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70

#define	RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)

#define	RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)

#define	RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)

#define	R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)

#define	R600_PCIE_LC_RENEGOTIATION_SUPPORT (1 << 9)

#define	R600_PCIE_LC_RENEGOTIATE_EN (1 << 10)

#define	R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11)

#define	R600_PCIE_LC_UPCONFIGURE_SUPPORT (1 << 12)

#define	R600_PCIE_LC_UPCONFIGURE_DIS (1 << 13)

#define	R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c

#define	R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c

#define	RADEON_CACHE_CNTL 0x1724

#define	RADEON_CACHE_LINE 0x0f0c /* PCI */

#define	RADEON_CAPABILITIES_ID 0x0f50 /* PCI */

#define	RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */

#define	RADEON_CLK_PIN_CNTL 0x0001 /* PLL */

#define	RADEON_DONT_USE_XTALIN (1 << 4)

#define	RADEON_SCLK_DYN_START_CNTL (1 << 15)

#define	RADEON_CLOCK_CNTL_DATA 0x000c

#define	RADEON_CLOCK_CNTL_INDEX 0x0008

#define	RADEON_PLL_WR_EN (1 << 7)

#define	RADEON_PLL_DIV_SEL (3 << 8)

#define	RADEON_PLL2_DIV_SEL_MASK (~(3 << 8))

#define	RADEON_CLK_PWRMGT_CNTL 0x0014

#define	RADEON_ENGIN_DYNCLK_MODE (1 << 12)

#define	RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)

#define	RADEON_ACTIVE_HILO_LAT_SHIFT 13

#define	RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)

#define	RADEON_MC_BUSY (1 << 16)

#define	RADEON_DLL_READY (1 << 19)

#define	RADEON_CG_NO1_DEBUG_0 (1 << 24)

#define	RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)

#define	RADEON_DYN_STOP_MODE_MASK (7 << 21)

#define	RADEON_TVPLL_PWRMGT_OFF (1 << 30)

#define	RADEON_TVCLK_TURNOFF (1 << 31)

#define	RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */

#define	RADEON_PM_MODE_SEL (1 << 13)

#define	RADEON_TCL_BYPASS_DISABLE (1 << 20)

#define	RADEON_CLR_CMP_CLR_3D 0x1a24

#define	RADEON_CLR_CMP_CLR_DST 0x15c8

#define	RADEON_CLR_CMP_CLR_SRC 0x15c4

#define	RADEON_CLR_CMP_CNTL 0x15c0

#define	RADEON_SRC_CMP_EQ_COLOR (4 << 0)

#define	RADEON_SRC_CMP_NEQ_COLOR (5 << 0)

#define	RADEON_CLR_CMP_SRC_SOURCE (1 << 24)

#define	RADEON_CLR_CMP_MASK 0x15cc

#define	RADEON_CLR_CMP_MSK 0xffffffff

#define	RADEON_CLR_CMP_MASK_3D 0x1A28

#define	RADEON_COMMAND 0x0f04 /* PCI */

#define	RADEON_COMPOSITE_SHADOW_ID 0x1a0c

#define	RADEON_CONFIG_APER_0_BASE 0x0100

#define	RADEON_CONFIG_APER_1_BASE 0x0104

#define	RADEON_CONFIG_APER_SIZE 0x0108

#define	RADEON_CONFIG_BONDS 0x00e8

#define	RADEON_CONFIG_CNTL 0x00e0

#define	RADEON_CFG_VGA_RAM_EN (1 << 8)

#define	RADEON_CFG_VGA_IO_DIS (1 << 9)

#define	RADEON_CFG_ATI_REV_A11 (0 << 16)

#define	RADEON_CFG_ATI_REV_A12 (1 << 16)

#define	RADEON_CFG_ATI_REV_A13 (2 << 16)

#define	RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)

#define	RADEON_CONFIG_MEMSIZE 0x00f8

#define	RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114

#define	RADEON_CONFIG_REG_1_BASE 0x010c

#define	RADEON_CONFIG_REG_APER_SIZE 0x0110

#define	RADEON_CONFIG_XSTRAP 0x00e4

#define	RADEON_CONSTANT_COLOR_C 0x1d34

#define	RADEON_CONSTANT_COLOR_MASK 0x00ffffff

#define	RADEON_CONSTANT_COLOR_ONE 0x00ffffff

#define	RADEON_CONSTANT_COLOR_ZERO 0x00000000

#define	RADEON_CRC_CMDFIFO_ADDR 0x0740

#define	RADEON_CRC_CMDFIFO_DOUT 0x0744

#define	RADEON_GRPH_BUFFER_CNTL 0x02f0

#define	RADEON_GRPH_START_REQ_MASK (0x7f)

#define	RADEON_GRPH_START_REQ_SHIFT 0

#define	RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)

#define	RADEON_GRPH_STOP_REQ_SHIFT 8

#define	RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)

#define	RADEON_GRPH_CRITICAL_POINT_SHIFT 16

#define	RADEON_GRPH_CRITICAL_CNTL (1<<28)

#define	RADEON_GRPH_BUFFER_SIZE (1<<29)

#define	RADEON_GRPH_CRITICAL_AT_SOF (1<<30)

#define	RADEON_GRPH_STOP_CNTL (1<<31)

#define	RADEON_GRPH2_BUFFER_CNTL 0x03f0

#define	RADEON_GRPH2_START_REQ_MASK (0x7f)

#define	RADEON_GRPH2_START_REQ_SHIFT 0

#define	RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)

#define	RADEON_GRPH2_STOP_REQ_SHIFT 8

#define	RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)

#define	RADEON_GRPH2_CRITICAL_POINT_SHIFT 16

#define	RADEON_GRPH2_CRITICAL_CNTL (1<<28)

#define	RADEON_GRPH2_BUFFER_SIZE (1<<29)

#define	RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)

#define	RADEON_GRPH2_STOP_CNTL (1<<31)

#define	RADEON_CRTC_CRNT_FRAME 0x0214

#define	RADEON_CRTC_EXT_CNTL 0x0054

#define	RADEON_CRTC_VGA_XOVERSCAN (1 << 0)

#define	RADEON_VGA_ATI_LINEAR (1 << 3)

#define	RADEON_XCRT_CNT_EN (1 << 6)

#define	RADEON_CRTC_HSYNC_DIS (1 << 8)

#define	RADEON_CRTC_VSYNC_DIS (1 << 9)

#define	RADEON_CRTC_DISPLAY_DIS (1 << 10)

#define	RADEON_CRTC_SYNC_TRISTAT (1 << 11)

#define	RADEON_CRTC_CRT_ON (1 << 15)

#define	RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055

#define	RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)

#define	RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)

#define	RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)

#define	RADEON_CRTC_GEN_CNTL 0x0050

#define	RADEON_CRTC_DBL_SCAN_EN (1 << 0)

#define	RADEON_CRTC_INTERLACE_EN (1 << 1)

#define	RADEON_CRTC_CSYNC_EN (1 << 4)

#define	RADEON_CRTC_ICON_EN (1 << 15)

#define	RADEON_CRTC_CUR_EN (1 << 16)

#define	RADEON_CRTC_VSTAT_MODE_MASK (3 << 17)

#define	RADEON_CRTC_CUR_MODE_MASK (7 << 20)

#define	RADEON_CRTC_CUR_MODE_SHIFT 20

#define	RADEON_CRTC_CUR_MODE_MONO 0

#define	RADEON_CRTC_CUR_MODE_24BPP 2

#define	RADEON_CRTC_EXT_DISP_EN (1 << 24)

#define	RADEON_CRTC_EN (1 << 25)

#define	RADEON_CRTC_DISP_REQ_EN_B (1 << 26)

#define	RADEON_CRTC2_GEN_CNTL 0x03f8

#define	RADEON_CRTC2_DBL_SCAN_EN (1 << 0)

#define	RADEON_CRTC2_INTERLACE_EN (1 << 1)

#define	RADEON_CRTC2_SYNC_TRISTAT (1 << 4)

#define	RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)

#define	RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)

#define	RADEON_CRTC2_CRT2_ON (1 << 7)

#define	RADEON_CRTC2_PIX_WIDTH_SHIFT 8

#define	RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)

#define	RADEON_CRTC2_ICON_EN (1 << 15)

#define	RADEON_CRTC2_CUR_EN (1 << 16)

#define	RADEON_CRTC2_CUR_MODE_MASK (7 << 20)

#define	RADEON_CRTC2_DISP_DIS (1 << 23)

#define	RADEON_CRTC2_EN (1 << 25)

#define	RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)

#define	RADEON_CRTC2_CSYNC_EN (1 << 27)

#define	RADEON_CRTC2_HSYNC_DIS (1 << 28)

#define	RADEON_CRTC2_VSYNC_DIS (1 << 29)

#define	RADEON_CRTC_MORE_CNTL 0x27c

#define	RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)

#define	RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)

#define	RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)

#define	RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)

#define	RADEON_CRTC_GUI_TRIG_VLINE 0x0218

#define	RADEON_CRTC_H_SYNC_STRT_WID 0x0204

#define	RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)

#define	RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)

#define	RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3

#define	RADEON_CRTC_H_SYNC_WID (0x3f << 16)

#define	RADEON_CRTC_H_SYNC_WID_SHIFT 16

#define	RADEON_CRTC_H_SYNC_POL (1 << 23)

#define	RADEON_CRTC2_H_SYNC_STRT_WID 0x0304

#define	RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)

#define	RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)

#define	RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3

#define	RADEON_CRTC2_H_SYNC_WID (0x3f << 16)

#define	RADEON_CRTC2_H_SYNC_WID_SHIFT 16

#define	RADEON_CRTC2_H_SYNC_POL (1 << 23)

#define	RADEON_CRTC_H_TOTAL_DISP 0x0200

#define	RADEON_CRTC_H_TOTAL (0x03ff << 0)

#define	RADEON_CRTC_H_TOTAL_SHIFT 0

#define	RADEON_CRTC_H_DISP (0x01ff << 16)

#define	RADEON_CRTC_H_DISP_SHIFT 16

#define	RADEON_CRTC2_H_TOTAL_DISP 0x0300

#define	RADEON_CRTC2_H_TOTAL (0x03ff << 0)

#define	RADEON_CRTC2_H_TOTAL_SHIFT 0

#define	RADEON_CRTC2_H_DISP (0x01ff << 16)

#define	RADEON_CRTC2_H_DISP_SHIFT 16

#define	RADEON_CRTC_OFFSET_RIGHT 0x0220

#define	RADEON_CRTC_OFFSET 0x0224

#define	RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)

#define	RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)

#define	RADEON_CRTC2_OFFSET 0x0324

#define	RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)

#define	RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)

#define	RADEON_CRTC_OFFSET_CNTL 0x0228

#define	RADEON_CRTC_TILE_LINE_SHIFT 0

#define	RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4

#define	R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)

#define	R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)

#define	R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)

#define	R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)

#define	R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)

#define	R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)

#define	R300_CRTC_X_Y_MODE_EN (1 << 9)

#define	R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)

#define	R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)

#define	R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)

#define	R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)

#define	R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)

#define	R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)

#define	R300_CRTC_MICRO_TILE_EN (1 << 13)

#define	R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)

#define	R300_CRTC_MACRO_TILE_EN (1 << 15)

#define	RADEON_CRTC_TILE_EN_RIGHT (1 << 14)

#define	RADEON_CRTC_TILE_EN (1 << 15)

#define	RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)

#define	RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)

#define	RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN (1 << 28)

#define	RADEON_CRTC_GUI_TRIG_OFFSET_RIGHT_EN (1 << 29)

#define	R300_CRTC_TILE_X0_Y0 0x0350

#define	R300_CRTC2_TILE_X0_Y0 0x0358

#define	RADEON_CRTC2_OFFSET_CNTL 0x0328

#define	RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)

#define	RADEON_CRTC2_TILE_EN (1 << 15)

#define	RADEON_CRTC_PITCH 0x022c

#define	RADEON_CRTC_PITCH__SHIFT 0

#define	RADEON_CRTC_PITCH__RIGHT_SHIFT 16

#define	RADEON_CRTC2_PITCH 0x032c

#define	RADEON_CRTC_STATUS 0x005c

#define	RADEON_CRTC_VBLANK_CUR (1 << 0)

#define	RADEON_CRTC_VBLANK_SAVE (1 << 1)

#define	RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)

#define	RADEON_CRTC2_STATUS 0x03fc

#define	RADEON_CRTC2_VBLANK_CUR (1 << 0)

#define	RADEON_CRTC2_VBLANK_SAVE (1 << 1)

#define	RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)

#define	RADEON_CRTC_V_SYNC_STRT_WID 0x020c

#define	RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)

#define	RADEON_CRTC_V_SYNC_STRT_SHIFT 0

#define	RADEON_CRTC_V_SYNC_WID (0x1f << 16)

#define	RADEON_CRTC_V_SYNC_WID_SHIFT 16

#define	RADEON_CRTC_V_SYNC_POL (1 << 23)

#define	RADEON_CRTC2_V_SYNC_STRT_WID 0x030c

#define	RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)

#define	RADEON_CRTC2_V_SYNC_STRT_SHIFT 0

#define	RADEON_CRTC2_V_SYNC_WID (0x1f << 16)

#define	RADEON_CRTC2_V_SYNC_WID_SHIFT 16

#define	RADEON_CRTC2_V_SYNC_POL (1 << 23)

#define	RADEON_CRTC_V_TOTAL_DISP 0x0208

#define	RADEON_CRTC_V_TOTAL (0x07ff << 0)

#define	RADEON_CRTC_V_TOTAL_SHIFT 0

#define	RADEON_CRTC_V_DISP (0x07ff << 16)

#define	RADEON_CRTC_V_DISP_SHIFT 16

#define	RADEON_CRTC2_V_TOTAL_DISP 0x0308

#define	RADEON_CRTC2_V_TOTAL (0x07ff << 0)

#define	RADEON_CRTC2_V_TOTAL_SHIFT 0

#define	RADEON_CRTC2_V_DISP (0x07ff << 16)

#define	RADEON_CRTC2_V_DISP_SHIFT 16

#define	RADEON_CRTC_VLINE_CRNT_VLINE 0x0210

#define	RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)

#define	RADEON_CRTC2_CRNT_FRAME 0x0314

#define	RADEON_CRTC2_GUI_TRIG_VLINE 0x0318

#define	RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310

#define	RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */

#define	RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */

#define	RADEON_CUR_CLR0 0x026c

#define	RADEON_CUR_CLR1 0x0270

#define	RADEON_CUR_HORZ_VERT_OFF 0x0268

#define	RADEON_CUR_HORZ_VERT_POSN 0x0264

#define	RADEON_CUR_OFFSET 0x0260

#define	RADEON_CUR_LOCK (1 << 31)

#define	RADEON_CUR2_CLR0 0x036c

#define	RADEON_CUR2_CLR1 0x0370

#define	RADEON_CUR2_HORZ_VERT_OFF 0x0368

#define	RADEON_CUR2_HORZ_VERT_POSN 0x0364

#define	RADEON_CUR2_OFFSET 0x0360

#define	RADEON_CUR2_LOCK (1 << 31)

#define	RADEON_DAC_CNTL 0x0058

#define	RADEON_DAC_RANGE_CNTL (3 << 0)

#define	RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)

#define	RADEON_DAC_RANGE_CNTL_MASK 0x03

#define	RADEON_DAC_BLANKING (1 << 2)

#define	RADEON_DAC_CMP_EN (1 << 3)

#define	RADEON_DAC_CMP_OUTPUT (1 << 7)

#define	RADEON_DAC_8BIT_EN (1 << 8)

#define	RADEON_DAC_TVO_EN (1 << 10)

#define	RADEON_DAC_VGA_ADR_EN (1 << 13)

#define	RADEON_DAC_PDWN (1 << 15)

#define	RADEON_DAC_MASK_ALL (0xff << 24)

#define	RADEON_DAC_CNTL2 0x007c

#define	RADEON_DAC2_TV_CLK_SEL (0 << 1)

#define	RADEON_DAC2_DAC_CLK_SEL (1 << 0)

#define	RADEON_DAC2_DAC2_CLK_SEL (1 << 1)

#define	RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)

#define	RADEON_DAC2_CMP_EN (1 << 7)

#define	RADEON_DAC2_CMP_OUT_R (1 << 8)

#define	RADEON_DAC2_CMP_OUT_G (1 << 9)

#define	RADEON_DAC2_CMP_OUT_B (1 << 10)

#define	RADEON_DAC2_CMP_OUTPUT (1 << 11)

#define	RADEON_DAC_EXT_CNTL 0x0280

#define	RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)

#define	RADEON_DAC2_FORCE_DATA_EN (1 << 1)

#define	RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)

#define	RADEON_DAC_FORCE_DATA_EN (1 << 5)

#define	RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)

#define	RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)

#define	RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)

#define	RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)

#define	RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)

#define	RADEON_DAC_FORCE_DATA_MASK 0x0003ff00

#define	RADEON_DAC_FORCE_DATA_SHIFT 8

#define	RADEON_DAC_MACRO_CNTL 0x0d04

#define	RADEON_DAC_PDWN_R (1 << 16)

#define	RADEON_DAC_PDWN_G (1 << 17)

#define	RADEON_DAC_PDWN_B (1 << 18)

#define	RADEON_DISP_PWR_MAN 0x0d08

#define	RADEON_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)

#define	RADEON_DISP_PWR_MAN_D3_CRTC2_EN (1 << 4)

#define	RADEON_DISP_PWR_MAN_DPMS_ON (0 << 8)

#define	RADEON_DISP_PWR_MAN_DPMS_STANDBY (1 << 8)

#define	RADEON_DISP_PWR_MAN_DPMS_SUSPEND (2 << 8)

#define	RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8)

#define	RADEON_DISP_D3_RST (1 << 16)

#define	RADEON_DISP_D3_REG_RST (1 << 17)

#define	RADEON_DISP_D3_GRPH_RST (1 << 18)

#define	RADEON_DISP_D3_SUBPIC_RST (1 << 19)

#define	RADEON_DISP_D3_OV0_RST (1 << 20)

#define	RADEON_DISP_D1D2_GRPH_RST (1 << 21)

#define	RADEON_DISP_D1D2_SUBPIC_RST (1 << 22)

#define	RADEON_DISP_D1D2_OV0_RST (1 << 23)

#define	RADEON_DIG_TMDS_ENABLE_RST (1 << 24)

#define	RADEON_TV_ENABLE_RST (1 << 25)

#define	RADEON_AUTO_PWRUP_EN (1 << 26)

#define	RADEON_TV_DAC_CNTL 0x088c

#define	RADEON_TV_DAC_NBLANK (1 << 0)

#define	RADEON_TV_DAC_NHOLD (1 << 1)

#define	RADEON_TV_DAC_PEDESTAL (1 << 2)

#define	RADEON_TV_MONITOR_DETECT_EN (1 << 4)

#define	RADEON_TV_DAC_CMPOUT (1 << 5)

#define	RADEON_TV_DAC_STD_MASK (3 << 8)

#define	RADEON_TV_DAC_STD_PAL (0 << 8)

#define	RADEON_TV_DAC_STD_NTSC (1 << 8)

#define	RADEON_TV_DAC_STD_PS2 (2 << 8)

#define	RADEON_TV_DAC_STD_RS343 (3 << 8)

#define	RADEON_TV_DAC_BGSLEEP (1 << 6)

#define	RADEON_TV_DAC_BGADJ_MASK (0xf << 16)

#define	RADEON_TV_DAC_BGADJ_SHIFT 16

#define	RADEON_TV_DAC_DACADJ_MASK (0xf << 20)

#define	RADEON_TV_DAC_DACADJ_SHIFT 20

#define	RADEON_TV_DAC_RDACPD (1 << 24)

#define	RADEON_TV_DAC_GDACPD (1 << 25)

#define	RADEON_TV_DAC_BDACPD (1 << 26)

#define	RADEON_TV_DAC_RDACDET (1 << 29)

#define	RADEON_TV_DAC_GDACDET (1 << 30)

#define	RADEON_TV_DAC_BDACDET (1 << 31)

#define	R420_TV_DAC_DACADJ_MASK (0x1f << 20)

#define	R420_TV_DAC_RDACPD (1 << 25)

#define	R420_TV_DAC_GDACPD (1 << 26)

#define	R420_TV_DAC_BDACPD (1 << 27)

#define	R420_TV_DAC_TVENABLE (1 << 28)

#define	RADEON_DISP_HW_DEBUG 0x0d14

#define	RADEON_CRT2_DISP1_SEL (1 << 5)

#define	RADEON_DISP_OUTPUT_CNTL 0x0d64

#define	RADEON_DISP_DAC_SOURCE_MASK 0x03

#define	RADEON_DISP_DAC2_SOURCE_MASK 0x0c

#define	RADEON_DISP_DAC_SOURCE_CRTC2 0x01

#define	RADEON_DISP_DAC_SOURCE_RMX 0x02

#define	RADEON_DISP_DAC_SOURCE_LTU 0x03

#define	RADEON_DISP_DAC2_SOURCE_CRTC2 0x04

#define	RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)

#define	RADEON_DISP_TVDAC_SOURCE_CRTC 0x0

#define	RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)

#define	RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)

#define	RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)

#define	RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)

#define	RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)

#define	RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)

#define	RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)

#define	RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */

#define	RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */

#define	RADEON_DISP_TV_OUT_CNTL 0x0d6c

#define	RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)

#define	RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)

#define	RADEON_DAC_CRC_SIG 0x02cc

#define	RADEON_DAC_DATA 0x03c9 /* VGA */

#define	RADEON_DAC_MASK 0x03c6 /* VGA */

#define	RADEON_DAC_R_INDEX 0x03c7 /* VGA */

#define	RADEON_DAC_W_INDEX 0x03c8 /* VGA */

#define	RADEON_DDA_CONFIG 0x02e0

#define	RADEON_DDA_ON_OFF 0x02e4

#define	RADEON_DEFAULT_OFFSET 0x16e0

#define	RADEON_DEFAULT_PITCH 0x16e4

#define	RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8

#define	RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)

#define	RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)

#define	RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820

#define	RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824

#define	RADEON_DEVICE_ID 0x0f02 /* PCI */

#define	RADEON_DISP_MISC_CNTL 0x0d00

#define	RADEON_SOFT_RESET_GRPH_PP (1 << 0)

#define	RADEON_DISP_MERGE_CNTL 0x0d60

#define	RADEON_DISP_ALPHA_MODE_MASK 0x03

#define	RADEON_DISP_ALPHA_MODE_KEY 0

#define	RADEON_DISP_ALPHA_MODE_PER_PIXEL 1

#define	RADEON_DISP_ALPHA_MODE_GLOBAL 2

#define	RADEON_DISP_RGB_OFFSET_EN (1 << 8)

#define	RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)

#define	RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)

#define	RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)

#define	RADEON_DISP2_MERGE_CNTL 0x0d68

#define	RADEON_DISP2_RGB_OFFSET_EN (1 << 8)

#define	RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80

#define	RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84

#define	RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88

#define	RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c

#define	RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90

#define	RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98

#define	RADEON_DP_BRUSH_BKGD_CLR 0x1478

#define	RADEON_DP_BRUSH_FRGD_CLR 0x147c

#define	RADEON_DP_CNTL 0x16c0

#define	RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)

#define	RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)

#define	RADEON_DP_DST_TILE_LINEAR (0 << 3)

#define	RADEON_DP_DST_TILE_MACRO (1 << 3)

#define	RADEON_DP_DST_TILE_MICRO (2 << 3)

#define	RADEON_DP_DST_TILE_BOTH (3 << 3)

#define	RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0

#define	RADEON_DST_Y_MAJOR (1 << 2)

#define	RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)

#define	RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)

#define	RADEON_DP_DATATYPE 0x16c4

#define	RADEON_HOST_BIG_ENDIAN_EN (1 << 29)

#define	RADEON_DP_GUI_MASTER_CNTL 0x146c

#define	RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)

#define	RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)

#define	RADEON_GMC_SRC_CLIPPING (1 << 2)

#define	RADEON_GMC_DST_CLIPPING (1 << 3)

#define	RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)

#define	RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)

#define	RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)

#define	RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)

#define	RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)

#define	RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)

#define	RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)

#define	RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)

#define	RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)

#define	RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)

#define	RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)

#define	RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)

#define	RADEON_GMC_BRUSH_NONE (15 << 4)

#define	RADEON_GMC_DST_8BPP_CI (2 << 8)

#define	RADEON_GMC_DST_15BPP (3 << 8)

#define	RADEON_GMC_DST_16BPP (4 << 8)

#define	RADEON_GMC_DST_24BPP (5 << 8)

#define	RADEON_GMC_DST_32BPP (6 << 8)

#define	RADEON_GMC_DST_8BPP_RGB (7 << 8)

#define	RADEON_GMC_DST_Y8 (8 << 8)

#define	RADEON_GMC_DST_RGB8 (9 << 8)

#define	RADEON_GMC_DST_VYUY (11 << 8)

#define	RADEON_GMC_DST_YVYU (12 << 8)

#define	RADEON_GMC_DST_AYUV444 (14 << 8)

#define	RADEON_GMC_DST_ARGB4444 (15 << 8)

#define	RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)

#define	RADEON_GMC_DST_DATATYPE_SHIFT 8

#define	RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)

#define	RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)

#define	RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)

#define	RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)

#define	RADEON_GMC_BYTE_PIX_ORDER (1 << 14)

#define	RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)

#define	RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)

#define	RADEON_GMC_CONVERSION_TEMP (1 << 15)

#define	RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)

#define	RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)

#define	RADEON_GMC_ROP3_MASK (0xff << 16)

#define	RADEON_DP_SRC_SOURCE_MASK (7 << 24)

#define	RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)

#define	RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)

#define	RADEON_GMC_3D_FCN_EN (1 << 27)

#define	RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)

#define	RADEON_GMC_AUX_CLIP_DIS (1 << 29)

#define	RADEON_GMC_WR_MSK_DIS (1 << 30)

#define	RADEON_GMC_LD_BRUSH_Y_X (1 << 31)

#define	RADEON_ROP3_ZERO 0x00000000

#define	RADEON_ROP3_DSa 0x00880000

#define	RADEON_ROP3_SDna 0x00440000

#define	RADEON_ROP3_S 0x00cc0000

#define	RADEON_ROP3_DSna 0x00220000

#define	RADEON_ROP3_D 0x00aa0000

#define	RADEON_ROP3_DSx 0x00660000

#define	RADEON_ROP3_DSo 0x00ee0000

#define	RADEON_ROP3_DSon 0x00110000

#define	RADEON_ROP3_DSxn 0x00990000

#define	RADEON_ROP3_Dn 0x00550000

#define	RADEON_ROP3_SDno 0x00dd0000

#define	RADEON_ROP3_Sn 0x00330000

#define	RADEON_ROP3_DSno 0x00bb0000

#define	RADEON_ROP3_DSan 0x00770000

#define	RADEON_ROP3_ONE 0x00ff0000

#define	RADEON_ROP3_DPa 0x00a00000

#define	RADEON_ROP3_PDna 0x00500000

#define	RADEON_ROP3_P 0x00f00000

#define	RADEON_ROP3_DPna 0x000a0000

#define	RADEON_ROP3_D 0x00aa0000

#define	RADEON_ROP3_DPx 0x005a0000

#define	RADEON_ROP3_DPo 0x00fa0000

#define	RADEON_ROP3_DPon 0x00050000

#define	RADEON_ROP3_PDxn 0x00a50000

#define	RADEON_ROP3_PDno 0x00f50000

#define	RADEON_ROP3_Pn 0x000f0000

#define	RADEON_ROP3_DPno 0x00af0000

#define	RADEON_ROP3_DPan 0x005f0000

#define	RADEON_DP_GUI_MASTER_CNTL_C 0x1c84

#define	RADEON_DP_MIX 0x16c8

#define	RADEON_DP_SRC_BKGD_CLR 0x15dc

#define	RADEON_DP_SRC_FRGD_CLR 0x15d8

#define	RADEON_DP_WRITE_MASK 0x16cc

#define	RADEON_DST_BRES_DEC 0x1630

#define	RADEON_DST_BRES_ERR 0x1628

#define	RADEON_DST_BRES_INC 0x162c

#define	RADEON_DST_BRES_LNTH 0x1634

#define	RADEON_DST_BRES_LNTH_SUB 0x1638

#define	RADEON_DST_HEIGHT 0x1410

#define	RADEON_DST_HEIGHT_WIDTH 0x143c

#define	RADEON_DST_HEIGHT_WIDTH_8 0x158c

#define	RADEON_DST_HEIGHT_WIDTH_BW 0x15b4

#define	RADEON_DST_HEIGHT_Y 0x15a0

#define	RADEON_DST_LINE_START 0x1600

#define	RADEON_DST_LINE_END 0x1604

#define	RADEON_DST_LINE_PATCOUNT 0x1608

#define	RADEON_BRES_CNTL_SHIFT 8

#define	RADEON_DST_OFFSET 0x1404

#define	RADEON_DST_PITCH 0x1408

#define	RADEON_DST_PITCH_OFFSET 0x142c

#define	RADEON_DST_PITCH_OFFSET_C 0x1c80

#define	RADEON_PITCH_SHIFT 21

#define	RADEON_DST_TILE_LINEAR (0 << 30)

#define	RADEON_DST_TILE_MACRO (1 << 30)

#define	RADEON_DST_TILE_MICRO (2 << 30)

#define	RADEON_DST_TILE_BOTH (3 << 30)

#define	RADEON_DST_WIDTH 0x140c

#define	RADEON_DST_WIDTH_HEIGHT 0x1598

#define	RADEON_DST_WIDTH_X 0x1588

#define	RADEON_DST_WIDTH_X_INCY 0x159c

#define	RADEON_DST_X 0x141c

#define	RADEON_DST_X_SUB 0x15a4

#define	RADEON_DST_X_Y 0x1594

#define	RADEON_DST_Y 0x1420

#define	RADEON_DST_Y_SUB 0x15a8

#define	RADEON_DST_Y_X 0x1438

#define	RADEON_FCP_CNTL 0x0910

#define	RADEON_FCP0_SRC_PCICLK 0

#define	RADEON_FCP0_SRC_PCLK 1

#define	RADEON_FCP0_SRC_PCLKb 2

#define	RADEON_FCP0_SRC_HREF 3

#define	RADEON_FCP0_SRC_GND 4

#define	RADEON_FCP0_SRC_HREFb 5

#define	RADEON_FLUSH_1 0x1704

#define	RADEON_FLUSH_2 0x1708

#define	RADEON_FLUSH_3 0x170c

#define	RADEON_FLUSH_4 0x1710

#define	RADEON_FLUSH_5 0x1714

#define	RADEON_FLUSH_6 0x1718

#define	RADEON_FLUSH_7 0x171c

#define	RADEON_FOG_3D_TABLE_START 0x1810

#define	RADEON_FOG_3D_TABLE_END 0x1814

#define	RADEON_FOG_3D_TABLE_DENSITY 0x181c

#define	RADEON_FOG_TABLE_INDEX 0x1a14

#define	RADEON_FOG_TABLE_DATA 0x1a18

#define	RADEON_FP_CRTC_H_TOTAL_DISP 0x0250

#define	RADEON_FP_CRTC_V_TOTAL_DISP 0x0254

#define	RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff

#define	RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000

#define	RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff

#define	RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000

#define	RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8

#define	RADEON_FP_H_SYNC_WID_MASK 0x003f0000

#define	RADEON_FP_V_SYNC_STRT_MASK 0x00000fff

#define	RADEON_FP_V_SYNC_WID_MASK 0x001f0000

#define	RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000

#define	RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010

#define	RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000

#define	RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010

#define	RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003

#define	RADEON_FP_H_SYNC_WID_SHIFT 0x00000010

#define	RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000

#define	RADEON_FP_V_SYNC_WID_SHIFT 0x00000010

#define	RADEON_FP_GEN_CNTL 0x0284

#define	RADEON_FP_FPON (1 << 0)

#define	RADEON_FP_BLANK_EN (1 << 1)

#define	RADEON_FP_TMDS_EN (1 << 2)

#define	RADEON_FP_PANEL_FORMAT (1 << 3)

#define	RADEON_FP_EN_TMDS (1 << 7)

#define	RADEON_FP_DETECT_SENSE (1 << 8)

#define	RADEON_FP_DETECT_INT_POL (1 << 9)

#define	R200_FP_SOURCE_SEL_MASK (3 << 10)

#define	R200_FP_SOURCE_SEL_CRTC1 (0 << 10)

#define	R200_FP_SOURCE_SEL_CRTC2 (1 << 10)

#define	R200_FP_SOURCE_SEL_RMX (2 << 10)

#define	R200_FP_SOURCE_SEL_TRANS (3 << 10)

#define	RADEON_FP_SEL_CRTC1 (0 << 13)

#define	RADEON_FP_SEL_CRTC2 (1 << 13)

#define	R300_HPD_SEL(x) ((x) << 13)

#define	RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)

#define	RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)

#define	RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)

#define	RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)

#define	RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)

#define	RADEON_FP_DFP_SYNC_SEL (1 << 21)

#define	RADEON_FP_CRTC_LOCK_8DOT (1 << 22)

#define	RADEON_FP_CRT_SYNC_SEL (1 << 23)

#define	RADEON_FP_USE_SHADOW_EN (1 << 24)

#define	RADEON_FP_CRT_SYNC_ALT (1 << 26)

#define	RADEON_FP2_GEN_CNTL 0x0288

#define	RADEON_FP2_BLANK_EN (1 << 1)

#define	RADEON_FP2_ON (1 << 2)

#define	RADEON_FP2_PANEL_FORMAT (1 << 3)

#define	RADEON_FP2_DETECT_SENSE (1 << 8)

#define	RADEON_FP2_DETECT_INT_POL (1 << 9)

#define	R200_FP2_SOURCE_SEL_MASK (3 << 10)

#define	R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)

#define	R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)

#define	R200_FP2_SOURCE_SEL_RMX (2 << 10)

#define	R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)

#define	RADEON_FP2_SRC_SEL_MASK (3 << 13)

#define	RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)

#define	RADEON_FP2_FP_POL (1 << 16)

#define	RADEON_FP2_LP_POL (1 << 17)

#define	RADEON_FP2_SCK_POL (1 << 18)

#define	RADEON_FP2_LCD_CNTL_MASK (7 << 19)

#define	RADEON_FP2_PAD_FLOP_EN (1 << 22)

#define	RADEON_FP2_CRC_EN (1 << 23)

#define	RADEON_FP2_CRC_READ_EN (1 << 24)

#define	RADEON_FP2_DVO_EN (1 << 25)

#define	RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)

#define	R200_FP2_DVO_RATE_SEL_SDR (1 << 27)

#define	R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)

#define	R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)

#define	RADEON_FP_H_SYNC_STRT_WID 0x02c4

#define	RADEON_FP_H2_SYNC_STRT_WID 0x03c4

#define	RADEON_FP_HORZ_STRETCH 0x028c

#define	RADEON_FP_HORZ2_STRETCH 0x038c

#define	RADEON_HORZ_STRETCH_RATIO_MASK 0xffff

#define	RADEON_HORZ_STRETCH_RATIO_MAX 4096

#define	RADEON_HORZ_PANEL_SIZE (0x1ff << 16)

#define	RADEON_HORZ_PANEL_SHIFT 16

#define	RADEON_HORZ_STRETCH_PIXREP (0 << 25)

#define	RADEON_HORZ_STRETCH_BLEND (1 << 26)

#define	RADEON_HORZ_STRETCH_ENABLE (1 << 25)

#define	RADEON_HORZ_AUTO_RATIO (1 << 27)

#define	RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)

#define	RADEON_HORZ_AUTO_RATIO_INC (1 << 31)

#define	RADEON_FP_HORZ_VERT_ACTIVE 0x0278

#define	RADEON_FP_V_SYNC_STRT_WID 0x02c8

#define	RADEON_FP_VERT_STRETCH 0x0290

#define	RADEON_FP_V2_SYNC_STRT_WID 0x03c8

#define	RADEON_FP_VERT2_STRETCH 0x0390

#define	RADEON_VERT_PANEL_SIZE (0xfff << 12)

#define	RADEON_VERT_PANEL_SHIFT 12

#define	RADEON_VERT_STRETCH_RATIO_MASK 0xfff

#define	RADEON_VERT_STRETCH_RATIO_SHIFT 0

#define	RADEON_VERT_STRETCH_RATIO_MAX 4096

#define	RADEON_VERT_STRETCH_ENABLE (1 << 25)

#define	RADEON_VERT_STRETCH_LINEREP (0 << 26)

#define	RADEON_VERT_STRETCH_BLEND (1 << 26)

#define	RADEON_VERT_AUTO_RATIO_EN (1 << 27)

#define	RADEON_VERT_AUTO_RATIO_INC (1 << 31)

#define	RADEON_VERT_STRETCH_RESERVED 0x71000000

#define	RS400_FP_2ND_GEN_CNTL 0x0384

#define	RS400_FP_2ND_ON (1 << 0)

#define	RS400_FP_2ND_BLANK_EN (1 << 1)

#define	RS400_TMDS_2ND_EN (1 << 2)

#define	RS400_PANEL_FORMAT_2ND (1 << 3)

#define	RS400_FP_2ND_EN_TMDS (1 << 7)

#define	RS400_FP_2ND_DETECT_SENSE (1 << 8)

#define	RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10)

#define	RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10)

#define	RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10)

#define	RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10)

#define	RS400_FP_2ND_DETECT_EN (1 << 12)

#define	RS400_HPD_2ND_SEL (1 << 13)

#define	RS400_FP2_2_GEN_CNTL 0x0388

#define	RS400_FP2_2_BLANK_EN (1 << 1)

#define	RS400_FP2_2_ON (1 << 2)

#define	RS400_FP2_2_PANEL_FORMAT (1 << 3)

#define	RS400_FP2_2_DETECT_SENSE (1 << 8)

#define	RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)

#define	RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)

#define	RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)

#define	RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)

#define	RS400_FP2_2_DVO2_EN (1 << 25)

#define	RS400_TMDS2_CNTL 0x0394

#define	RS400_TMDS2_TRANSMITTER_CNTL 0x03a4

#define	RS400_TMDS2_PLLEN (1 << 0)

#define	RS400_TMDS2_PLLRST (1 << 1)

#define	RADEON_GEN_INT_CNTL 0x0040

#define	RADEON_CRTC_VBLANK_MASK (1 << 0)

#define	RADEON_FP_DETECT_MASK (1 << 4)

#define	RADEON_CRTC2_VBLANK_MASK (1 << 9)

#define	RADEON_FP2_DETECT_MASK (1 << 10)

#define	RADEON_GUI_IDLE_MASK (1 << 19)

#define	RADEON_SW_INT_ENABLE (1 << 25)

#define	RADEON_GEN_INT_STATUS 0x0044

#define	AVIVO_DISPLAY_INT_STATUS (1 << 0)

#define	RADEON_CRTC_VBLANK_STAT (1 << 0)

#define	RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)

#define	RADEON_FP_DETECT_STAT (1 << 4)

#define	RADEON_FP_DETECT_STAT_ACK (1 << 4)

#define	RADEON_CRTC2_VBLANK_STAT (1 << 9)

#define	RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)

#define	RADEON_FP2_DETECT_STAT (1 << 10)

#define	RADEON_FP2_DETECT_STAT_ACK (1 << 10)

#define	RADEON_GUI_IDLE_STAT (1 << 19)

#define	RADEON_GUI_IDLE_STAT_ACK (1 << 19)

#define	RADEON_SW_INT_FIRE (1 << 26)

#define	RADEON_SW_INT_TEST (1 << 25)

#define	RADEON_SW_INT_TEST_ACK (1 << 25)

#define	RADEON_GENENB 0x03c3 /* VGA */

#define	RADEON_GENFC_RD 0x03ca /* VGA */

#define	RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */

#define	RADEON_GENMO_RD 0x03cc /* VGA */

#define	RADEON_GENMO_WT 0x03c2 /* VGA */

#define	RADEON_GENS0 0x03c2 /* VGA */

#define	RADEON_GENS1 0x03da /* VGA, 0x03ba */

#define	RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C / / DDC3 */

#define	RADEON_GPIO_MONIDB 0x006c

#define	RADEON_GPIO_CRT2_DDC 0x006c

#define	RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */

#define	RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */

#define	RADEON_GPIO_A_0 (1 << 0)

#define	RADEON_GPIO_A_1 (1 << 1)

#define	RADEON_GPIO_Y_0 (1 << 8)

#define	RADEON_GPIO_Y_1 (1 << 9)

#define	RADEON_GPIO_Y_SHIFT_0 8

#define	RADEON_GPIO_Y_SHIFT_1 9

#define	RADEON_GPIO_EN_0 (1 << 16)

#define	RADEON_GPIO_EN_1 (1 << 17)

#define	RADEON_GPIO_MASK_0 (1 << 24) /??/

#define	RADEON_GPIO_MASK_1 (1 << 25) /??/

#define	RADEON_GRPH8_DATA 0x03cf /* VGA */

#define	RADEON_GRPH8_IDX 0x03ce /* VGA */

#define	RADEON_GUI_SCRATCH_REG0 0x15e0

#define	RADEON_GUI_SCRATCH_REG1 0x15e4

#define	RADEON_GUI_SCRATCH_REG2 0x15e8

#define	RADEON_GUI_SCRATCH_REG3 0x15ec

#define	RADEON_GUI_SCRATCH_REG4 0x15f0

#define	RADEON_GUI_SCRATCH_REG5 0x15f4

#define	RADEON_HEADER 0x0f0e /* PCI */

#define	RADEON_HOST_DATA0 0x17c0

#define	RADEON_HOST_DATA1 0x17c4

#define	RADEON_HOST_DATA2 0x17c8

#define	RADEON_HOST_DATA3 0x17cc

#define	RADEON_HOST_DATA4 0x17d0

#define	RADEON_HOST_DATA5 0x17d4

#define	RADEON_HOST_DATA6 0x17d8

#define	RADEON_HOST_DATA7 0x17dc

#define	RADEON_HOST_DATA_LAST 0x17e0

#define	RADEON_HOST_PATH_CNTL 0x0130

#define	RADEON_HP_LIN_RD_CACHE_DIS (1 << 24)

#define	RADEON_HDP_READ_BUFFER_INVALIDATE (1 << 27)

#define	RADEON_HDP_SOFT_RESET (1 << 26)

#define	RADEON_HDP_APER_CNTL (1 << 23)

#define	RADEON_HTOTAL_CNTL 0x0009 /* PLL */

#define	RADEON_HTOT_CNTL_VGA_EN (1 << 28)

#define	RADEON_HTOTAL2_CNTL 0x002e /* PLL */

#define	RADEON_I2C_CNTL_0 0x0090

#define	RADEON_I2C_DONE (1 << 0)

#define	RADEON_I2C_NACK (1 << 1)

#define	RADEON_I2C_HALT (1 << 2)

#define	RADEON_I2C_SOFT_RST (1 << 5)

#define	RADEON_I2C_DRIVE_EN (1 << 6)

#define	RADEON_I2C_DRIVE_SEL (1 << 7)

#define	RADEON_I2C_START (1 << 8)

#define	RADEON_I2C_STOP (1 << 9)

#define	RADEON_I2C_RECEIVE (1 << 10)

#define	RADEON_I2C_ABORT (1 << 11)

#define	RADEON_I2C_GO (1 << 12)

#define	RADEON_I2C_PRESCALE_SHIFT 16

#define	RADEON_I2C_CNTL_1 0x0094

#define	RADEON_I2C_DATA_COUNT_SHIFT 0

#define	RADEON_I2C_ADDR_COUNT_SHIFT 4

#define	RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 8

#define	RADEON_I2C_SEL (1 << 16)

#define	RADEON_I2C_EN (1 << 17)

#define	RADEON_I2C_TIME_LIMIT_SHIFT 24

#define	RADEON_I2C_DATA 0x0098

#define	RADEON_DVI_I2C_CNTL_0 0x02e0

#define	R200_DVI_I2C_PIN_SEL(x) ((x) << 3)

#define	R200_SEL_DDC1 0 /* depends on asic */

#define	R200_SEL_DDC2 1 /* depends on asic */

#define	R200_SEL_DDC3 2 /* depends on asic */

#define	RADEON_SW_WANTS_TO_USE_DVI_I2C (1 << 13)

#define	RADEON_SW_CAN_USE_DVI_I2C (1 << 13)

#define	RADEON_SW_DONE_USING_DVI_I2C (1 << 14)

#define	RADEON_HW_NEEDS_DVI_I2C (1 << 14)

#define	RADEON_ABORT_HW_DVI_I2C (1 << 15)

#define	RADEON_HW_USING_DVI_I2C (1 << 15)

#define	RADEON_DVI_I2C_CNTL_1 0x02e4

#define	RADEON_DVI_I2C_DATA 0x02e8

#define	RADEON_INTERRUPT_LINE 0x0f3c /* PCI */

#define	RADEON_INTERRUPT_PIN 0x0f3d /* PCI */

#define	RADEON_IO_BASE 0x0f14 /* PCI */

#define	RADEON_LATENCY 0x0f0d /* PCI */

#define	RADEON_LEAD_BRES_DEC 0x1608

#define	RADEON_LEAD_BRES_LNTH 0x161c

#define	RADEON_LEAD_BRES_LNTH_SUB 0x1624

#define	RADEON_LVDS_GEN_CNTL 0x02d0

#define	RADEON_LVDS_ON (1 << 0)

#define	RADEON_LVDS_DISPLAY_DIS (1 << 1)

#define	RADEON_LVDS_PANEL_TYPE (1 << 2)

#define	RADEON_LVDS_PANEL_FORMAT (1 << 3)

#define	RADEON_LVDS_NO_FM (0 << 4)

#define	RADEON_LVDS_2_GREY (1 << 4)

#define	RADEON_LVDS_4_GREY (2 << 4)

#define	RADEON_LVDS_RST_FM (1 << 6)

#define	RADEON_LVDS_EN (1 << 7)

#define	RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8

#define	RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)

#define	RADEON_LVDS_BL_MOD_EN (1 << 16)

#define	RADEON_LVDS_BL_CLK_SEL (1 << 17)

#define	RADEON_LVDS_DIGON (1 << 18)

#define	RADEON_LVDS_BLON (1 << 19)

#define	RADEON_LVDS_FP_POL_LOW (1 << 20)

#define	RADEON_LVDS_LP_POL_LOW (1 << 21)

#define	RADEON_LVDS_DTM_POL_LOW (1 << 22)

#define	RADEON_LVDS_SEL_CRTC2 (1 << 23)

#define	RADEON_LVDS_FPDI_EN (1 << 27)

#define	RADEON_LVDS_HSYNC_DELAY_SHIFT 28

#define	RADEON_LVDS_PLL_CNTL 0x02d4

#define	RADEON_HSYNC_DELAY_SHIFT 28

#define	RADEON_HSYNC_DELAY_MASK (0xf << 28)

#define	RADEON_LVDS_PLL_EN (1 << 16)

#define	RADEON_LVDS_PLL_RESET (1 << 17)

#define	R300_LVDS_SRC_SEL_MASK (3 << 18)

#define	R300_LVDS_SRC_SEL_CRTC1 (0 << 18)

#define	R300_LVDS_SRC_SEL_CRTC2 (1 << 18)

#define	R300_LVDS_SRC_SEL_RMX (2 << 18)

#define	RADEON_LVDS_SS_GEN_CNTL 0x02ec

#define	RADEON_LVDS_PWRSEQ_DELAY1_SHIFT 16

#define	RADEON_LVDS_PWRSEQ_DELAY2_SHIFT 20

#define	RADEON_MAX_LATENCY 0x0f3f /* PCI */

#define	RADEON_DISPLAY_BASE_ADDR 0x23c

#define	RADEON_DISPLAY2_BASE_ADDR 0x33c

#define	RADEON_OV0_BASE_ADDR 0x43c

#define	RADEON_NB_TOM 0x15c

#define	R300_MC_INIT_MISC_LAT_TIMER 0x180

#define	R300_MC_DISP0R_INIT_LAT_SHIFT 8

#define	R300_MC_DISP0R_INIT_LAT_MASK 0xf

#define	R300_MC_DISP1R_INIT_LAT_SHIFT 12

#define	R300_MC_DISP1R_INIT_LAT_MASK 0xf

#define	RADEON_MCLK_CNTL 0x0012 /* PLL */

#define	RADEON_MCLKA_SRC_SEL_MASK 0x7

#define	RADEON_FORCEON_MCLKA (1 << 16)

#define	RADEON_FORCEON_MCLKB (1 << 17)

#define	RADEON_FORCEON_YCLKA (1 << 18)

#define	RADEON_FORCEON_YCLKB (1 << 19)

#define	RADEON_FORCEON_MC (1 << 20)

#define	RADEON_FORCEON_AIC (1 << 21)

#define	R300_DISABLE_MC_MCLKA (1 << 21)

#define	R300_DISABLE_MC_MCLKB (1 << 21)

#define	RADEON_MCLK_MISC 0x001f /* PLL */

#define	RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)

#define	RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)

#define	RADEON_MC_MCLK_DYN_ENABLE (1 << 14)

#define	RADEON_IO_MCLK_DYN_ENABLE (1 << 15)

#define	RADEON_GPIOPAD_MASK 0x0198

#define	RADEON_GPIOPAD_A 0x019c

#define	RADEON_GPIOPAD_EN 0x01a0

#define	RADEON_GPIOPAD_Y 0x01a4

#define	RADEON_MDGPIO_MASK 0x01a8

#define	RADEON_MDGPIO_A 0x01ac

#define	RADEON_MDGPIO_EN 0x01b0

#define	RADEON_MDGPIO_Y 0x01b4

#define	RADEON_MEM_ADDR_CONFIG 0x0148

#define	RADEON_MEM_BASE 0x0f10 /* PCI */

#define	RADEON_MEM_CNTL 0x0140

#define	RADEON_MEM_NUM_CHANNELS_MASK 0x01

#define	RADEON_MEM_USE_B_CH_ONLY (1 << 1)

#define	RV100_HALF_MODE (1 << 3)

#define	R300_MEM_NUM_CHANNELS_MASK 0x03

#define	R300_MEM_USE_CD_CH_ONLY (1 << 2)

#define	RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */

#define	RADEON_MEM_INIT_LAT_TIMER 0x0154

#define	RADEON_MEM_INTF_CNTL 0x014c

#define	RADEON_MEM_SDRAM_MODE_REG 0x0158

#define	RADEON_SDRAM_MODE_MASK 0xffff0000

#define	RADEON_B3MEM_RESET_MASK 0x6fffffff

#define	RADEON_MEM_CFG_TYPE_DDR (1 << 30)

#define	RADEON_MEM_STR_CNTL 0x0150

#define	RADEON_MEM_PWRUP_COMPL_A (1 << 0)

#define	RADEON_MEM_PWRUP_COMPL_B (1 << 1)

#define	R300_MEM_PWRUP_COMPL_C (1 << 2)

#define	R300_MEM_PWRUP_COMPL_D (1 << 3)

#define	RADEON_MEM_PWRUP_COMPLETE 0x03

#define	R300_MEM_PWRUP_COMPLETE 0x0f

#define	RADEON_MC_STATUS 0x0150

#define	RADEON_MC_IDLE (1 << 2)

#define	R300_MC_IDLE (1 << 4)

#define	RADEON_MEM_VGA_RP_SEL 0x003c

#define	RADEON_MEM_VGA_WP_SEL 0x0038

#define	RADEON_MIN_GRANT 0x0f3e /* PCI */

#define	RADEON_MM_DATA 0x0004

#define	RADEON_MM_INDEX 0x0000

#define	RADEON_MM_APER (1 << 31)

#define	RADEON_MPLL_CNTL 0x000e /* PLL */

#define	RADEON_MPP_TB_CONFIG 0x01c0 /* ? */

#define	RADEON_MPP_GP_CONFIG 0x01c8 /* ? */

#define	RADEON_SEPROM_CNTL1 0x01c0

#define	RADEON_SCK_PRESCALE_SHIFT 24

#define	RADEON_SCK_PRESCALE_MASK (0xff << 24)

#define	R300_MC_IND_INDEX 0x01f8

#define	R300_MC_IND_ADDR_MASK 0x3f

#define	R300_MC_IND_WR_EN (1 << 8)

#define	R300_MC_IND_DATA 0x01fc

#define	R300_MC_READ_CNTL_AB 0x017c

#define	R300_MEM_RBS_POSITION_A_MASK 0x03

#define	R300_MC_READ_CNTL_CD_mcind 0x24

#define	R300_MEM_RBS_POSITION_C_MASK 0x03

#define	RADEON_N_VIF_COUNT 0x0248

#define	RADEON_OV0_AUTO_FLIP_CNTL 0x0470

#define	RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007

#define	RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008

#define	RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010

#define	RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020

#define	RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040

#define	RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300

#define	RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000

#define	RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000

#define	RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000

#define	RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000

#define	RADEON_OV0_COLOUR_CNTL 0x04E0

#define	RADEON_OV0_DEINTERLACE_PATTERN 0x0474

#define	RADEON_OV0_EXCLUSIVE_HORZ 0x0408

#define	RADEON_EXCL_HORZ_START_MASK 0x000000ff

#define	RADEON_EXCL_HORZ_END_MASK 0x0000ff00

#define	RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000

#define	RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000

#define	RADEON_OV0_EXCLUSIVE_VERT 0x040C

#define	RADEON_EXCL_VERT_START_MASK 0x000003ff

#define	RADEON_EXCL_VERT_END_MASK 0x03ff0000

#define	RADEON_OV0_FILTER_CNTL 0x04A0

#define	RADEON_FILTER_PROGRAMMABLE_COEF 0x0

#define	RADEON_FILTER_HC_COEF_HORZ_Y 0x1

#define	RADEON_FILTER_HC_COEF_HORZ_UV 0x2

#define	RADEON_FILTER_HC_COEF_VERT_Y 0x4

#define	RADEON_FILTER_HC_COEF_VERT_UV 0x8

#define	RADEON_FILTER_HARDCODED_COEF 0xf

#define	RADEON_FILTER_COEF_MASK 0xf

#define	RADEON_OV0_FOUR_TAP_COEF_0 0x04B0

#define	RADEON_OV0_FOUR_TAP_COEF_1 0x04B4

#define	RADEON_OV0_FOUR_TAP_COEF_2 0x04B8

#define	RADEON_OV0_FOUR_TAP_COEF_3 0x04BC

#define	RADEON_OV0_FOUR_TAP_COEF_4 0x04C0

#define	RADEON_OV0_FLAG_CNTL 0x04DC

#define	RADEON_OV0_GAMMA_000_00F 0x0d40

#define	RADEON_OV0_GAMMA_010_01F 0x0d44

#define	RADEON_OV0_GAMMA_020_03F 0x0d48

#define	RADEON_OV0_GAMMA_040_07F 0x0d4c

#define	RADEON_OV0_GAMMA_080_0BF 0x0e00

#define	RADEON_OV0_GAMMA_0C0_0FF 0x0e04

#define	RADEON_OV0_GAMMA_100_13F 0x0e08

#define	RADEON_OV0_GAMMA_140_17F 0x0e0c

#define	RADEON_OV0_GAMMA_180_1BF 0x0e10

#define	RADEON_OV0_GAMMA_1C0_1FF 0x0e14

#define	RADEON_OV0_GAMMA_200_23F 0x0e18

#define	RADEON_OV0_GAMMA_240_27F 0x0e1c

#define	RADEON_OV0_GAMMA_280_2BF 0x0e20

#define	RADEON_OV0_GAMMA_2C0_2FF 0x0e24

#define	RADEON_OV0_GAMMA_300_33F 0x0e28

#define	RADEON_OV0_GAMMA_340_37F 0x0e2c

#define	RADEON_OV0_GAMMA_380_3BF 0x0d50

#define	RADEON_OV0_GAMMA_3C0_3FF 0x0d54

#define	RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC

#define	RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0

#define	RADEON_OV0_H_INC 0x0480

#define	RADEON_OV0_KEY_CNTL 0x04F4

#define	RADEON_VIDEO_KEY_FN_MASK 0x00000003L

#define	RADEON_VIDEO_KEY_FN_FALSE 0x00000000L

#define	RADEON_VIDEO_KEY_FN_TRUE 0x00000001L

#define	RADEON_VIDEO_KEY_FN_EQ 0x00000002L

#define	RADEON_VIDEO_KEY_FN_NE 0x00000003L

#define	RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L

#define	RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L

#define	RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L

#define	RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L

#define	RADEON_GRAPHIC_KEY_FN_NE 0x00000030L

#define	RADEON_CMP_MIX_MASK 0x00000100L

#define	RADEON_CMP_MIX_OR 0x00000000L

#define	RADEON_CMP_MIX_AND 0x00000100L

#define	RADEON_OV0_LIN_TRANS_A 0x0d20

#define	RADEON_OV0_LIN_TRANS_B 0x0d24

#define	RADEON_OV0_LIN_TRANS_C 0x0d28

#define	RADEON_OV0_LIN_TRANS_D 0x0d2c

#define	RADEON_OV0_LIN_TRANS_E 0x0d30

#define	RADEON_OV0_LIN_TRANS_F 0x0d34

#define	RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430

#define	RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL

#define	RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L

#define	RADEON_OV0_P1_H_ACCUM_INIT 0x0488

#define	RADEON_OV0_P1_V_ACCUM_INIT 0x0428

#define	RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L

#define	RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L

#define	RADEON_OV0_P1_X_START_END 0x0494

#define	RADEON_OV0_P2_X_START_END 0x0498

#define	RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434

#define	RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL

#define	RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L

#define	RADEON_OV0_P23_H_ACCUM_INIT 0x048C

#define	RADEON_OV0_P23_V_ACCUM_INIT 0x042C

#define	RADEON_OV0_P3_X_START_END 0x049C

#define	RADEON_OV0_REG_LOAD_CNTL 0x0410

#define	RADEON_REG_LD_CTL_LOCK 0x00000001L

#define	RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L

#define	RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L

#define	RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L

#define	RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L

#define	RADEON_OV0_SCALE_CNTL 0x0420

#define	RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L

#define	RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L

#define	RADEON_SCALER_SIGNED_UV 0x00000010L

#define	RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L

#define	RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L

#define	RADEON_SCALER_GAMMA_SEL_G22 0x00000020L

#define	RADEON_SCALER_GAMMA_SEL_G18 0x00000040L

#define	RADEON_SCALER_GAMMA_SEL_G14 0x00000060L

#define	RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L

#define	RADEON_SCALER_SURFAC_FORMAT 0x00000f00L

#define	RADEON_SCALER_SOURCE_15BPP 0x00000300L

#define	RADEON_SCALER_SOURCE_16BPP 0x00000400L

#define	RADEON_SCALER_SOURCE_32BPP 0x00000600L

#define	RADEON_SCALER_SOURCE_YUV9 0x00000900L

#define	RADEON_SCALER_SOURCE_YUV12 0x00000A00L

#define	RADEON_SCALER_SOURCE_VYUY422 0x00000B00L

#define	RADEON_SCALER_SOURCE_YVYU422 0x00000C00L

#define	RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L

#define	RADEON_SCALER_TEMPORAL_DEINT 0x00002000L

#define	RADEON_SCALER_CRTC_SEL 0x00004000L

#define	RADEON_SCALER_SMART_SWITCH 0x00008000L

#define	RADEON_SCALER_BURST_PER_PLANE 0x007F0000L

#define	RADEON_SCALER_DOUBLE_BUFFER 0x01000000L

#define	RADEON_SCALER_DIS_LIMIT 0x08000000L

#define	RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L

#define	RADEON_SCALER_INT_EMU 0x20000000L

#define	RADEON_SCALER_ENABLE 0x40000000L

#define	RADEON_SCALER_SOFT_RESET 0x80000000L

#define	RADEON_OV0_STEP_BY 0x0484

#define	RADEON_OV0_TEST 0x04F8

#define	RADEON_OV0_V_INC 0x0424

#define	RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460

#define	RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464

#define	RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440

#define	RADEON_VIF_BUF0_PITCH_SEL 0x00000001L

#define	RADEON_VIF_BUF0_TILE_ADRS 0x00000002L

#define	RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L

#define	RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L

#define	RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444

#define	RADEON_VIF_BUF1_PITCH_SEL 0x00000001L

#define	RADEON_VIF_BUF1_TILE_ADRS 0x00000002L

#define	RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L

#define	RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L

#define	RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448

#define	RADEON_VIF_BUF2_PITCH_SEL 0x00000001L

#define	RADEON_VIF_BUF2_TILE_ADRS 0x00000002L

#define	RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L

#define	RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L

#define	RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C

#define	RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450

#define	RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454

#define	RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8

#define	RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4

#define	RADEON_OV0_Y_X_START 0x0400

#define	RADEON_OV0_Y_X_END 0x0404

#define	RADEON_OV1_Y_X_START 0x0600

#define	RADEON_OV1_Y_X_END 0x0604

#define	RADEON_OVR_CLR 0x0230

#define	RADEON_OVR_WID_LEFT_RIGHT 0x0234

#define	RADEON_OVR_WID_TOP_BOTTOM 0x0238

#define	RADEON_OVR2_CLR 0x0330

#define	RADEON_OVR2_WID_LEFT_RIGHT 0x0334

#define	RADEON_OVR2_WID_TOP_BOTTOM 0x0338

#define	RADEON_CAP0_BUF0_OFFSET 0x0920

#define	RADEON_CAP0_BUF1_OFFSET 0x0924

#define	RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928

#define	RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C

#define	RADEON_CAP0_BUF_PITCH 0x0930

#define	RADEON_CAP0_V_WINDOW 0x0934

#define	RADEON_CAP0_H_WINDOW 0x0938

#define	RADEON_CAP0_VBI0_OFFSET 0x093C

#define	RADEON_CAP0_VBI1_OFFSET 0x0940

#define	RADEON_CAP0_VBI_V_WINDOW 0x0944

#define	RADEON_CAP0_VBI_H_WINDOW 0x0948

#define	RADEON_CAP0_PORT_MODE_CNTL 0x094C

#define	RADEON_CAP0_TRIG_CNTL 0x0950

#define	RADEON_CAP0_DEBUG 0x0954

#define	RADEON_CAP0_CONFIG 0x0958

#define	RADEON_CAP0_CONFIG_CONTINUOS 0x00000001

#define	RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002

#define	RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004

#define	RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008

#define	RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010

#define	RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020

#define	RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040

#define	RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080

#define	RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100

#define	RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200

#define	RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400

#define	RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800

#define	RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000

#define	RADEON_CAP0_CONFIG_VBI_EN 0x00002000

#define	RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000

#define	RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000

#define	RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000

#define	RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000

#define	RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000

#define	RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000

#define	RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000

#define	RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000

#define	RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000

#define	RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000

#define	RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000

#define	RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000

#define	RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000

#define	RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000

#define	RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000

#define	RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000

#define	RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000

#define	RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000

#define	RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000

#define	RADEON_CAP0_ANC_ODD_OFFSET 0x095C

#define	RADEON_CAP0_ANC_EVEN_OFFSET 0x0960

#define	RADEON_CAP0_ANC_H_WINDOW 0x0964

#define	RADEON_CAP0_VIDEO_SYNC_TEST 0x0968

#define	RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C

#define	RADEON_CAP0_BUF_STATUS 0x0970

#define	RADEON_CAP0_VBI2_OFFSET 0x0980

#define	RADEON_CAP0_VBI3_OFFSET 0x0984

#define	RADEON_CAP0_ANC2_OFFSET 0x0988

#define	RADEON_CAP0_ANC3_OFFSET 0x098C

#define	RADEON_VID_BUFFER_CONTROL 0x0900

#define	RADEON_CAP1_BUF0_OFFSET 0x0990

#define	RADEON_CAP1_BUF1_OFFSET 0x0994

#define	RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998

#define	RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C

#define	RADEON_CAP1_BUF_PITCH 0x09A0

#define	RADEON_CAP1_V_WINDOW 0x09A4

#define	RADEON_CAP1_H_WINDOW 0x09A8

#define	RADEON_CAP1_VBI_ODD_OFFSET 0x09AC

#define	RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0

#define	RADEON_CAP1_VBI_V_WINDOW 0x09B4

#define	RADEON_CAP1_VBI_H_WINDOW 0x09B8

#define	RADEON_CAP1_PORT_MODE_CNTL 0x09BC

#define	RADEON_CAP1_TRIG_CNTL 0x09C0

#define	RADEON_CAP1_DEBUG 0x09C4

#define	RADEON_CAP1_CONFIG 0x09C8

#define	RADEON_CAP1_ANC_ODD_OFFSET 0x09CC

#define	RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0

#define	RADEON_CAP1_ANC_H_WINDOW 0x09D4

#define	RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8

#define	RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC

#define	RADEON_CAP1_BUF_STATUS 0x09E0

#define	RADEON_CAP1_DWNSC_XRATIO 0x09E8

#define	RADEON_CAP1_XSHARPNESS 0x09EC

#define	RADEON_IDCT_RUNS 0x1F80

#define	RADEON_IDCT_LEVELS 0x1F84

#define	RADEON_IDCT_CONTROL 0x1FBC

#define	RADEON_IDCT_AUTH_CONTROL 0x1F88

#define	RADEON_IDCT_AUTH 0x1F8C

#define	RADEON_P2PLL_CNTL 0x002a /* P2PLL */

#define	RADEON_P2PLL_RESET (1 << 0)

#define	RADEON_P2PLL_SLEEP (1 << 1)

#define	RADEON_P2PLL_PVG_MASK (7 << 11)

#define	RADEON_P2PLL_PVG_SHIFT 11

#define	RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)

#define	RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)

#define	RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)

#define	RADEON_P2PLL_DIV_0 0x002c

#define	RADEON_P2PLL_FB0_DIV_MASK 0x07ff

#define	RADEON_P2PLL_POST0_DIV_MASK 0x00070000

#define	RADEON_P2PLL_REF_DIV 0x002B /* PLL */

#define	RADEON_P2PLL_REF_DIV_MASK 0x03ff

#define	RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */

#define	RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */

#define	R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)

#define	R300_PPLL_REF_DIV_ACC_SHIFT 18

#define	RADEON_PALETTE_DATA 0x00b4

#define	RADEON_PALETTE_30_DATA 0x00b8

#define	RADEON_PALETTE_INDEX 0x00b0

#define	RADEON_PCI_GART_PAGE 0x017c

#define	RADEON_PIXCLKS_CNTL 0x002d

#define	RADEON_PIX2CLK_SRC_SEL_MASK 0x03

#define	RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00

#define	RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01

#define	RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02

#define	RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03

#define	RADEON_PIX2CLK_ALWAYS_ONb (1<<6)

#define	RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)

#define	RADEON_PIXCLK_TV_SRC_SEL (1 << 8)

#define	RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)

#define	R300_DVOCLK_ALWAYS_ONb (1 << 10)

#define	RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)

#define	RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)

#define	RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)

#define	R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)

#define	RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)

#define	RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)

#define	R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)

#define	R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)

#define	R300_P2G2CLK_ALWAYS_ONb (1 << 18)

#define	R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)

#define	R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)

#define	RADEON_PLANE_3D_MASK_C 0x1d44

#define	RADEON_PLL_TEST_CNTL 0x0013 /* PLL */

#define	RADEON_PLL_MASK_READ_B (1 << 9)

#define	RADEON_PMI_CAP_ID 0x0f5c /* PCI */

#define	RADEON_PMI_DATA 0x0f63 /* PCI */

#define	RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */

#define	RADEON_PMI_PMC_REG 0x0f5e /* PCI */

#define	RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */

#define	RADEON_PMI_REGISTER 0x0f5c /* PCI */

#define	RADEON_PPLL_CNTL 0x0002 /* PLL */

#define	RADEON_PPLL_RESET (1 << 0)

#define	RADEON_PPLL_SLEEP (1 << 1)

#define	RADEON_PPLL_PVG_MASK (7 << 11)

#define	RADEON_PPLL_PVG_SHIFT 11

#define	RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)

#define	RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)

#define	RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)

#define	RADEON_PPLL_DIV_0 0x0004 /* PLL */

#define	RADEON_PPLL_DIV_1 0x0005 /* PLL */

#define	RADEON_PPLL_DIV_2 0x0006 /* PLL */

#define	RADEON_PPLL_DIV_3 0x0007 /* PLL */

#define	RADEON_PPLL_FB3_DIV_MASK 0x07ff

#define	RADEON_PPLL_POST3_DIV_MASK 0x00070000

#define	RADEON_PPLL_REF_DIV 0x0003 /* PLL */

#define	RADEON_PPLL_REF_DIV_MASK 0x03ff

#define	RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */

#define	RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */

#define	RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */

#define	RADEON_RBBM_GUICNTL 0x172c

#define	RADEON_HOST_DATA_SWAP_NONE (0 << 0)

#define	RADEON_HOST_DATA_SWAP_16BIT (1 << 0)

#define	RADEON_HOST_DATA_SWAP_32BIT (2 << 0)

#define	RADEON_HOST_DATA_SWAP_HDW (3 << 0)

#define	RADEON_RBBM_SOFT_RESET 0x00f0

#define	RADEON_SOFT_RESET_CP (1 << 0)

#define	RADEON_SOFT_RESET_HI (1 << 1)

#define	RADEON_SOFT_RESET_SE (1 << 2)

#define	RADEON_SOFT_RESET_RE (1 << 3)

#define	RADEON_SOFT_RESET_PP (1 << 4)

#define	RADEON_SOFT_RESET_E2 (1 << 5)

#define	RADEON_SOFT_RESET_RB (1 << 6)

#define	RADEON_SOFT_RESET_HDP (1 << 7)

#define	RADEON_RBBM_STATUS 0x0e40

#define	RADEON_RBBM_FIFOCNT_MASK 0x007f

#define	RADEON_RBBM_ACTIVE (1 << 31)

#define	RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c

#define	RADEON_RB2D_DC_FLUSH (3 << 0)

#define	RADEON_RB2D_DC_FREE (3 << 2)

#define	RADEON_RB2D_DC_FLUSH_ALL 0xf

#define	RADEON_RB2D_DC_BUSY (1 << 31)

#define	RADEON_RB2D_DSTCACHE_MODE 0x3428

#define	RADEON_DSTCACHE_CTLSTAT 0x1714

#define	RADEON_RB3D_ZCACHE_MODE 0x3250

#define	RADEON_RB3D_ZCACHE_CTLSTAT 0x3254

#define	RADEON_RB3D_ZC_FLUSH_ALL 0x5

#define	RADEON_RB3D_DSTCACHE_MODE 0x3258

#define	RADEON_RB3D_DC_CACHE_ENABLE (0)

#define	RADEON_RB3D_DC_2D_CACHE_DISABLE (1)

#define	RADEON_RB3D_DC_3D_CACHE_DISABLE (2)

#define	RADEON_RB3D_DC_CACHE_DISABLE (3)

#define	RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)

#define	RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)

#define	RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)

#define	RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)

#define	R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)

#define	R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)

#define	RADEON_RB3D_DC_FORCE_RMW (1 << 16)

#define	RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)

#define	RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)

#define	RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C

#define	RADEON_RB3D_DC_FLUSH (3 << 0)

#define	RADEON_RB3D_DC_FREE (3 << 2)

#define	RADEON_RB3D_DC_FLUSH_ALL 0xf

#define	RADEON_RB3D_DC_BUSY (1 << 31)

#define	RADEON_REG_BASE 0x0f18 /* PCI */

#define	RADEON_REGPROG_INF 0x0f09 /* PCI */

#define	RADEON_REVISION_ID 0x0f08 /* PCI */

#define	RADEON_SC_BOTTOM 0x164c

#define	RADEON_SC_BOTTOM_RIGHT 0x16f0

#define	RADEON_SC_BOTTOM_RIGHT_C 0x1c8c

#define	RADEON_SC_LEFT 0x1640

#define	RADEON_SC_RIGHT 0x1644

#define	RADEON_SC_TOP 0x1648

#define	RADEON_SC_TOP_LEFT 0x16ec

#define	RADEON_SC_TOP_LEFT_C 0x1c88

#define	RADEON_SC_SIGN_MASK_LO 0x8000

#define	RADEON_SC_SIGN_MASK_HI 0x80000000

#define	RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */

#define	RADEON_M_SPLL_REF_DIV_SHIFT 0

#define	RADEON_M_SPLL_REF_DIV_MASK 0xff

#define	RADEON_MPLL_FB_DIV_SHIFT 8

#define	RADEON_MPLL_FB_DIV_MASK 0xff

#define	RADEON_SPLL_FB_DIV_SHIFT 16

#define	RADEON_SPLL_FB_DIV_MASK 0xff

#define	RADEON_SPLL_CNTL 0x000c /* PLL */

#define	RADEON_SPLL_SLEEP (1 << 0)

#define	RADEON_SPLL_RESET (1 << 1)

#define	RADEON_SPLL_PCP_MASK 0x7

#define	RADEON_SPLL_PCP_SHIFT 8

#define	RADEON_SPLL_PVG_MASK 0x7

#define	RADEON_SPLL_PVG_SHIFT 11

#define	RADEON_SPLL_PDC_MASK 0x3

#define	RADEON_SPLL_PDC_SHIFT 14

#define	RADEON_SCLK_CNTL 0x000d /* PLL */

#define	RADEON_SCLK_SRC_SEL_MASK 0x0007

#define	RADEON_DYN_STOP_LAT_MASK 0x00007ff8

#define	RADEON_CP_MAX_DYN_STOP_LAT 0x0008

#define	RADEON_SCLK_FORCEON_MASK 0xffff8000

#define	RADEON_SCLK_FORCE_DISP2 (1<<15)

#define	RADEON_SCLK_FORCE_CP (1<<16)

#define	RADEON_SCLK_FORCE_HDP (1<<17)

#define	RADEON_SCLK_FORCE_DISP1 (1<<18)

#define	RADEON_SCLK_FORCE_TOP (1<<19)

#define	RADEON_SCLK_FORCE_E2 (1<<20)

#define	RADEON_SCLK_FORCE_SE (1<<21)

#define	RADEON_SCLK_FORCE_IDCT (1<<22)

#define	RADEON_SCLK_FORCE_VIP (1<<23)

#define	RADEON_SCLK_FORCE_RE (1<<24)

#define	RADEON_SCLK_FORCE_PB (1<<25)

#define	RADEON_SCLK_FORCE_TAM (1<<26)

#define	RADEON_SCLK_FORCE_TDM (1<<27)

#define	RADEON_SCLK_FORCE_RB (1<<28)

#define	RADEON_SCLK_FORCE_TV_SCLK (1<<29)

#define	RADEON_SCLK_FORCE_SUBPIC (1<<30)

#define	RADEON_SCLK_FORCE_OV0 (1<<31)

#define	R300_SCLK_FORCE_VAP (1<<21)

#define	R300_SCLK_FORCE_SR (1<<25)

#define	R300_SCLK_FORCE_PX (1<<26)

#define	R300_SCLK_FORCE_TX (1<<27)

#define	R300_SCLK_FORCE_US (1<<28)

#define	R300_SCLK_FORCE_SU (1<<30)

#define	R300_SCLK_CNTL2 0x1e /* PLL */

#define	R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)

#define	R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)

#define	R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)

#define	R300_SCLK_FORCE_TCL (1<<13)

#define	R300_SCLK_FORCE_CBA (1<<14)

#define	R300_SCLK_FORCE_GA (1<<15)

#define	RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */

#define	RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007

#define	RADEON_SCLK_MORE_FORCEON 0x0700

#define	RADEON_SDRAM_MODE_REG 0x0158

#define	RADEON_SEQ8_DATA 0x03c5 /* VGA */

#define	RADEON_SEQ8_IDX 0x03c4 /* VGA */

#define	RADEON_SNAPSHOT_F_COUNT 0x0244

#define	RADEON_SNAPSHOT_VH_COUNTS 0x0240

#define	RADEON_SNAPSHOT_VIF_COUNT 0x024c

#define	RADEON_SRC_OFFSET 0x15ac

#define	RADEON_SRC_PITCH 0x15b0

#define	RADEON_SRC_PITCH_OFFSET 0x1428

#define	RADEON_SRC_SC_BOTTOM 0x165c

#define	RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4

#define	RADEON_SRC_SC_RIGHT 0x1654

#define	RADEON_SRC_X 0x1414

#define	RADEON_SRC_X_Y 0x1590

#define	RADEON_SRC_Y 0x1418

#define	RADEON_SRC_Y_X 0x1434

#define	RADEON_STATUS 0x0f06 /* PCI */

#define	RADEON_SUBPIC_CNTL 0x0540 /* ? */

#define	RADEON_SUB_CLASS 0x0f0a /* PCI */

#define	RADEON_SURFACE_CNTL 0x0b00

#define	RADEON_SURF_TRANSLATION_DIS (1 << 8)

#define	RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)

#define	RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)

#define	RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)

#define	RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)

#define	RADEON_SURFACE0_INFO 0x0b0c

#define	RADEON_SURF_TILE_COLOR_MACRO (0 << 16)

#define	RADEON_SURF_TILE_COLOR_BOTH (1 << 16)

#define	RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)

#define	RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)

#define	R200_SURF_TILE_NONE (0 << 16)

#define	R200_SURF_TILE_COLOR_MACRO (1 << 16)

#define	R200_SURF_TILE_COLOR_MICRO (2 << 16)

#define	R200_SURF_TILE_COLOR_BOTH (3 << 16)

#define	R200_SURF_TILE_DEPTH_32BPP (4 << 16)

#define	R200_SURF_TILE_DEPTH_16BPP (5 << 16)

#define	R300_SURF_TILE_NONE (0 << 16)

#define	R300_SURF_TILE_COLOR_MACRO (1 << 16)

#define	R300_SURF_TILE_DEPTH_32BPP (2 << 16)

#define	RADEON_SURF_AP0_SWP_16BPP (1 << 20)

#define	RADEON_SURF_AP0_SWP_32BPP (1 << 21)

#define	RADEON_SURF_AP1_SWP_16BPP (1 << 22)

#define	RADEON_SURF_AP1_SWP_32BPP (1 << 23)

#define	RADEON_SURFACE0_LOWER_BOUND 0x0b04

#define	RADEON_SURFACE0_UPPER_BOUND 0x0b08

#define	RADEON_SURFACE1_INFO 0x0b1c

#define	RADEON_SURFACE1_LOWER_BOUND 0x0b14

#define	RADEON_SURFACE1_UPPER_BOUND 0x0b18

#define	RADEON_SURFACE2_INFO 0x0b2c

#define	RADEON_SURFACE2_LOWER_BOUND 0x0b24

#define	RADEON_SURFACE2_UPPER_BOUND 0x0b28

#define	RADEON_SURFACE3_INFO 0x0b3c

#define	RADEON_SURFACE3_LOWER_BOUND 0x0b34

#define	RADEON_SURFACE3_UPPER_BOUND 0x0b38

#define	RADEON_SURFACE4_INFO 0x0b4c

#define	RADEON_SURFACE4_LOWER_BOUND 0x0b44

#define	RADEON_SURFACE4_UPPER_BOUND 0x0b48

#define	RADEON_SURFACE5_INFO 0x0b5c

#define	RADEON_SURFACE5_LOWER_BOUND 0x0b54

#define	RADEON_SURFACE5_UPPER_BOUND 0x0b58

#define	RADEON_SURFACE6_INFO 0x0b6c

#define	RADEON_SURFACE6_LOWER_BOUND 0x0b64

#define	RADEON_SURFACE6_UPPER_BOUND 0x0b68

#define	RADEON_SURFACE7_INFO 0x0b7c

#define	RADEON_SURFACE7_LOWER_BOUND 0x0b74

#define	RADEON_SURFACE7_UPPER_BOUND 0x0b78

#define	RADEON_SW_SEMAPHORE 0x013c

#define	RADEON_TEST_DEBUG_CNTL 0x0120

#define	RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001

#define	RADEON_TEST_DEBUG_MUX 0x0124

#define	RADEON_TEST_DEBUG_OUT 0x012c

#define	RADEON_TMDS_PLL_CNTL 0x02a8

#define	RADEON_TMDS_TRANSMITTER_CNTL 0x02a4

#define	RADEON_TMDS_TRANSMITTER_PLLEN 1

#define	RADEON_TMDS_TRANSMITTER_PLLRST 2

#define	RADEON_TRAIL_BRES_DEC 0x1614

#define	RADEON_TRAIL_BRES_ERR 0x160c

#define	RADEON_TRAIL_BRES_INC 0x1610

#define	RADEON_TRAIL_X 0x1618

#define	RADEON_TRAIL_X_SUB 0x1620

#define	RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */

#define	RADEON_VCLK_SRC_SEL_MASK 0x03

#define	RADEON_VCLK_SRC_SEL_CPUCLK 0x00

#define	RADEON_VCLK_SRC_SEL_PSCANCLK 0x01

#define	RADEON_VCLK_SRC_SEL_BYTECLK 0x02

#define	RADEON_VCLK_SRC_SEL_PPLLCLK 0x03

#define	RADEON_PIXCLK_ALWAYS_ONb (1<<6)

#define	RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)

#define	R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)

#define	RADEON_VENDOR_ID 0x0f00 /* PCI */

#define	RADEON_VGA_DDA_CONFIG 0x02e8

#define	RADEON_VGA_DDA_ON_OFF 0x02ec

#define	RADEON_VID_BUFFER_CONTROL 0x0900

#define	RADEON_VIDEOMUX_CNTL 0x0190

#define	RADEON_VIPH_CH0_DATA 0x0c00

#define	RADEON_VIPH_CH1_DATA 0x0c04

#define	RADEON_VIPH_CH2_DATA 0x0c08

#define	RADEON_VIPH_CH3_DATA 0x0c0c

#define	RADEON_VIPH_CH0_ADDR 0x0c10

#define	RADEON_VIPH_CH1_ADDR 0x0c14

#define	RADEON_VIPH_CH2_ADDR 0x0c18

#define	RADEON_VIPH_CH3_ADDR 0x0c1c

#define	RADEON_VIPH_CH0_SBCNT 0x0c20

#define	RADEON_VIPH_CH1_SBCNT 0x0c24

#define	RADEON_VIPH_CH2_SBCNT 0x0c28

#define	RADEON_VIPH_CH3_SBCNT 0x0c2c

#define	RADEON_VIPH_CH0_ABCNT 0x0c30

#define	RADEON_VIPH_CH1_ABCNT 0x0c34

#define	RADEON_VIPH_CH2_ABCNT 0x0c38

#define	RADEON_VIPH_CH3_ABCNT 0x0c3c

#define	RADEON_VIPH_CONTROL 0x0c40

#define	RADEON_VIP_BUSY 0

#define	RADEON_VIP_IDLE 1

#define	RADEON_VIP_RESET 2

#define	RADEON_VIPH_EN (1 << 21)

#define	RADEON_VIPH_DV_LAT 0x0c44

#define	RADEON_VIPH_BM_CHUNK 0x0c48

#define	RADEON_VIPH_DV_INT 0x0c4c

#define	RADEON_VIPH_TIMEOUT_STAT 0x0c50

#define	RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010

#define	RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010

#define	RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000

#define	RADEON_VIPH_REG_DATA 0x0084

#define	RADEON_VIPH_REG_ADDR 0x0080

#define	RADEON_WAIT_UNTIL 0x1720

#define	RADEON_WAIT_CRTC_PFLIP (1 << 0)

#define	RADEON_WAIT_RE_CRTC_VLINE (1 << 1)

#define	RADEON_WAIT_FE_CRTC_VLINE (1 << 2)

#define	RADEON_WAIT_CRTC_VLINE (1 << 3)

#define	RADEON_WAIT_DMA_VID_IDLE (1 << 8)

#define	RADEON_WAIT_DMA_GUI_IDLE (1 << 9)

#define	RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */

#define	RADEON_WAIT_OV0_FLIP (1 << 11)

#define	RADEON_WAIT_AGP_FLUSH (1 << 13)

#define	RADEON_WAIT_2D_IDLE (1 << 14)

#define	RADEON_WAIT_3D_IDLE (1 << 15)

#define	RADEON_WAIT_2D_IDLECLEAN (1 << 16)

#define	RADEON_WAIT_3D_IDLECLEAN (1 << 17)

#define	RADEON_WAIT_HOST_IDLECLEAN (1 << 18)

#define	RADEON_CMDFIFO_ENTRIES_SHIFT 10

#define	RADEON_CMDFIFO_ENTRIES_MASK 0x7f

#define	RADEON_WAIT_VAP_IDLE (1 << 28)

#define	RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)

#define	RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)

#define	RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)

#define	RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */

#define	RADEON_XCLK_CNTL 0x000d /* PLL */

#define	RADEON_XDLL_CNTL 0x000c /* PLL */

#define	RADEON_XPLL_CNTL 0x000b /* PLL */

#define	RADEON_PP_BORDER_COLOR_0 0x1d40

#define	RADEON_PP_BORDER_COLOR_1 0x1d44

#define	RADEON_PP_BORDER_COLOR_2 0x1d48

#define	RADEON_PP_CNTL 0x1c38

#define	RADEON_STIPPLE_ENABLE (1 << 0)

#define	RADEON_SCISSOR_ENABLE (1 << 1)

#define	RADEON_PATTERN_ENABLE (1 << 2)

#define	RADEON_SHADOW_ENABLE (1 << 3)

#define	RADEON_TEX_ENABLE_MASK (0xf << 4)

#define	RADEON_TEX_0_ENABLE (1 << 4)

#define	RADEON_TEX_1_ENABLE (1 << 5)

#define	RADEON_TEX_2_ENABLE (1 << 6)

#define	RADEON_TEX_3_ENABLE (1 << 7)

#define	RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)

#define	RADEON_TEX_BLEND_0_ENABLE (1 << 12)

#define	RADEON_TEX_BLEND_1_ENABLE (1 << 13)

#define	RADEON_TEX_BLEND_2_ENABLE (1 << 14)

#define	RADEON_TEX_BLEND_3_ENABLE (1 << 15)

#define	RADEON_PLANAR_YUV_ENABLE (1 << 20)

#define	RADEON_SPECULAR_ENABLE (1 << 21)

#define	RADEON_FOG_ENABLE (1 << 22)

#define	RADEON_ALPHA_TEST_ENABLE (1 << 23)

#define	RADEON_ANTI_ALIAS_NONE (0 << 24)

#define	RADEON_ANTI_ALIAS_LINE (1 << 24)

#define	RADEON_ANTI_ALIAS_POLY (2 << 24)

#define	RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)

#define	RADEON_BUMP_MAP_ENABLE (1 << 26)

#define	RADEON_BUMPED_MAP_T0 (0 << 27)

#define	RADEON_BUMPED_MAP_T1 (1 << 27)

#define	RADEON_BUMPED_MAP_T2 (2 << 27)

#define	RADEON_TEX_3D_ENABLE_0 (1 << 29)

#define	RADEON_TEX_3D_ENABLE_1 (1 << 30)

#define	RADEON_MC_ENABLE (1 << 31)

#define	RADEON_PP_FOG_COLOR 0x1c18

#define	RADEON_FOG_COLOR_MASK 0x00ffffff

#define	RADEON_FOG_VERTEX (0 << 24)

#define	RADEON_FOG_TABLE (1 << 24)

#define	RADEON_FOG_USE_DEPTH (0 << 25)

#define	RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)

#define	RADEON_FOG_USE_SPEC_ALPHA (3 << 25)

#define	RADEON_PP_LUM_MATRIX 0x1d00

#define	RADEON_PP_MISC 0x1c14

#define	RADEON_REF_ALPHA_MASK 0x000000ff

#define	RADEON_ALPHA_TEST_FAIL (0 << 8)

#define	RADEON_ALPHA_TEST_LESS (1 << 8)

#define	RADEON_ALPHA_TEST_LEQUAL (2 << 8)

#define	RADEON_ALPHA_TEST_EQUAL (3 << 8)

#define	RADEON_ALPHA_TEST_GEQUAL (4 << 8)

#define	RADEON_ALPHA_TEST_GREATER (5 << 8)

#define	RADEON_ALPHA_TEST_NEQUAL (6 << 8)

#define	RADEON_ALPHA_TEST_PASS (7 << 8)

#define	RADEON_ALPHA_TEST_OP_MASK (7 << 8)

#define	RADEON_CHROMA_FUNC_FAIL (0 << 16)

#define	RADEON_CHROMA_FUNC_PASS (1 << 16)

#define	RADEON_CHROMA_FUNC_NEQUAL (2 << 16)

#define	RADEON_CHROMA_FUNC_EQUAL (3 << 16)

#define	RADEON_CHROMA_KEY_NEAREST (0 << 18)

#define	RADEON_CHROMA_KEY_ZERO (1 << 18)

#define	RADEON_SHADOW_ID_AUTO_INC (1 << 20)

#define	RADEON_SHADOW_FUNC_EQUAL (0 << 21)

#define	RADEON_SHADOW_FUNC_NEQUAL (1 << 21)

#define	RADEON_SHADOW_PASS_1 (0 << 22)

#define	RADEON_SHADOW_PASS_2 (1 << 22)

#define	RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)

#define	RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)

#define	RADEON_PP_ROT_MATRIX_0 0x1d58

#define	RADEON_PP_ROT_MATRIX_1 0x1d5c

#define	RADEON_PP_TXFILTER_0 0x1c54

#define	RADEON_PP_TXFILTER_1 0x1c6c

#define	RADEON_PP_TXFILTER_2 0x1c84

#define	RADEON_MAG_FILTER_NEAREST (0 << 0)

#define	RADEON_MAG_FILTER_LINEAR (1 << 0)

#define	RADEON_MAG_FILTER_MASK (1 << 0)

#define	RADEON_MIN_FILTER_NEAREST (0 << 1)

#define	RADEON_MIN_FILTER_LINEAR (1 << 1)

#define	RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)

#define	RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)

#define	RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)

#define	RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)

#define	RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)

#define	RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)

#define	RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)

#define	RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)

#define	RADEON_MIN_FILTER_MASK (15 << 1)

#define	RADEON_MAX_ANISO_1_TO_1 (0 << 5)

#define	RADEON_MAX_ANISO_2_TO_1 (1 << 5)

#define	RADEON_MAX_ANISO_4_TO_1 (2 << 5)

#define	RADEON_MAX_ANISO_8_TO_1 (3 << 5)

#define	RADEON_MAX_ANISO_16_TO_1 (4 << 5)

#define	RADEON_MAX_ANISO_MASK (7 << 5)

#define	RADEON_LOD_BIAS_MASK (0xff << 8)

#define	RADEON_LOD_BIAS_SHIFT 8

#define	RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)

#define	RADEON_MAX_MIP_LEVEL_SHIFT 16

#define	RADEON_YUV_TO_RGB (1 << 20)

#define	RADEON_YUV_TEMPERATURE_COOL (0 << 21)

#define	RADEON_YUV_TEMPERATURE_HOT (1 << 21)

#define	RADEON_YUV_TEMPERATURE_MASK (1 << 21)

#define	RADEON_WRAPEN_S (1 << 22)

#define	RADEON_CLAMP_S_WRAP (0 << 23)

#define	RADEON_CLAMP_S_MIRROR (1 << 23)

#define	RADEON_CLAMP_S_CLAMP_LAST (2 << 23)

#define	RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)

#define	RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)

#define	RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)

#define	RADEON_CLAMP_S_CLAMP_GL (6 << 23)

#define	RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)

#define	RADEON_CLAMP_S_MASK (7 << 23)

#define	RADEON_WRAPEN_T (1 << 26)

#define	RADEON_CLAMP_T_WRAP (0 << 27)

#define	RADEON_CLAMP_T_MIRROR (1 << 27)

#define	RADEON_CLAMP_T_CLAMP_LAST (2 << 27)

#define	RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)

#define	RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)

#define	RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)

#define	RADEON_CLAMP_T_CLAMP_GL (6 << 27)

#define	RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)

#define	RADEON_CLAMP_T_MASK (7 << 27)

#define	RADEON_BORDER_MODE_OGL (0 << 31)

#define	RADEON_BORDER_MODE_D3D (1 << 31)

#define	RADEON_PP_TXFORMAT_0 0x1c58

#define	RADEON_PP_TXFORMAT_1 0x1c70

#define	RADEON_PP_TXFORMAT_2 0x1c88

#define	RADEON_TXFORMAT_I8 (0 << 0)

#define	RADEON_TXFORMAT_AI88 (1 << 0)

#define	RADEON_TXFORMAT_RGB332 (2 << 0)

#define	RADEON_TXFORMAT_ARGB1555 (3 << 0)

#define	RADEON_TXFORMAT_RGB565 (4 << 0)

#define	RADEON_TXFORMAT_ARGB4444 (5 << 0)

#define	RADEON_TXFORMAT_ARGB8888 (6 << 0)

#define	RADEON_TXFORMAT_RGBA8888 (7 << 0)

#define	RADEON_TXFORMAT_Y8 (8 << 0)

#define	RADEON_TXFORMAT_VYUY422 (10 << 0)

#define	RADEON_TXFORMAT_YVYU422 (11 << 0)

#define	RADEON_TXFORMAT_DXT1 (12 << 0)

#define	RADEON_TXFORMAT_DXT23 (14 << 0)

#define	RADEON_TXFORMAT_DXT45 (15 << 0)

#define	RADEON_TXFORMAT_SHADOW16 (16 << 0)

#define	RADEON_TXFORMAT_SHADOW32 (17 << 0)

#define	RADEON_TXFORMAT_DUDV88 (18 << 0)

#define	RADEON_TXFORMAT_LDUDV655 (19 << 0)

#define	RADEON_TXFORMAT_LDUDUV8888 (20 << 0)

#define	RADEON_TXFORMAT_FORMAT_MASK (31 << 0)

#define	RADEON_TXFORMAT_FORMAT_SHIFT 0

#define	RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)

#define	RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)

#define	RADEON_TXFORMAT_NON_POWER2 (1 << 7)

#define	RADEON_TXFORMAT_WIDTH_MASK (15 << 8)

#define	RADEON_TXFORMAT_WIDTH_SHIFT 8

#define	RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)

#define	RADEON_TXFORMAT_HEIGHT_SHIFT 12

#define	RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)

#define	RADEON_TXFORMAT_F5_WIDTH_SHIFT 16

#define	RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)

#define	RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20

#define	RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)

#define	RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)

#define	RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)

#define	RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)

#define	RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)

#define	RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)

#define	RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)

#define	RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)

#define	RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)

#define	RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)

#define	RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)

#define	RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)

#define	RADEON_PP_CUBIC_FACES_0 0x1d24

#define	RADEON_PP_CUBIC_FACES_1 0x1d28

#define	RADEON_PP_CUBIC_FACES_2 0x1d2c

#define	RADEON_FACE_WIDTH_1_SHIFT 0

#define	RADEON_FACE_HEIGHT_1_SHIFT 4

#define	RADEON_FACE_WIDTH_1_MASK (0xf << 0)

#define	RADEON_FACE_HEIGHT_1_MASK (0xf << 4)

#define	RADEON_FACE_WIDTH_2_SHIFT 8

#define	RADEON_FACE_HEIGHT_2_SHIFT 12

#define	RADEON_FACE_WIDTH_2_MASK (0xf << 8)

#define	RADEON_FACE_HEIGHT_2_MASK (0xf << 12)

#define	RADEON_FACE_WIDTH_3_SHIFT 16

#define	RADEON_FACE_HEIGHT_3_SHIFT 20

#define	RADEON_FACE_WIDTH_3_MASK (0xf << 16)

#define	RADEON_FACE_HEIGHT_3_MASK (0xf << 20)

#define	RADEON_FACE_WIDTH_4_SHIFT 24

#define	RADEON_FACE_HEIGHT_4_SHIFT 28

#define	RADEON_FACE_WIDTH_4_MASK (0xf << 24)

#define	RADEON_FACE_HEIGHT_4_MASK (0xf << 28)

#define	RADEON_PP_TXOFFSET_0 0x1c5c

#define	RADEON_PP_TXOFFSET_1 0x1c74

#define	RADEON_PP_TXOFFSET_2 0x1c8c

#define	RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)

#define	RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)

#define	RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)

#define	RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)

#define	RADEON_TXO_MACRO_LINEAR (0 << 2)

#define	RADEON_TXO_MACRO_TILE (1 << 2)

#define	RADEON_TXO_MICRO_LINEAR (0 << 3)

#define	RADEON_TXO_MICRO_TILE_X2 (1 << 3)

#define	RADEON_TXO_MICRO_TILE_OPT (2 << 3)

#define	RADEON_TXO_OFFSET_MASK 0xffffffe0

#define	RADEON_TXO_OFFSET_SHIFT 5

#define	RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */

#define	RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4

#define	RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8

#define	RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc

#define	RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0

#define	RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00

#define	RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04

#define	RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08

#define	RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c

#define	RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10

#define	RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14

#define	RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18

#define	RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c

#define	RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20

#define	RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24

#define	RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */

#define	RADEON_PP_TEX_SIZE_1 0x1d0c

#define	RADEON_PP_TEX_SIZE_2 0x1d14

#define	RADEON_TEX_USIZE_MASK (0x7ff << 0)

#define	RADEON_TEX_USIZE_SHIFT 0

#define	RADEON_TEX_VSIZE_MASK (0x7ff << 16)

#define	RADEON_TEX_VSIZE_SHIFT 16

#define	RADEON_SIGNED_RGB_MASK (1 << 30)

#define	RADEON_SIGNED_RGB_SHIFT 30

#define	RADEON_SIGNED_ALPHA_MASK (1 << 31)

#define	RADEON_SIGNED_ALPHA_SHIFT 31

#define	RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */

#define	RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */

#define	RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */

#define	RADEON_PP_TXCBLEND_0 0x1c60

#define	RADEON_PP_TXCBLEND_1 0x1c78

#define	RADEON_PP_TXCBLEND_2 0x1c90

#define	RADEON_COLOR_ARG_A_SHIFT 0

#define	RADEON_COLOR_ARG_A_MASK (0x1f << 0)

#define	RADEON_COLOR_ARG_A_ZERO (0 << 0)

#define	RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)

#define	RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)

#define	RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)

#define	RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)

#define	RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)

#define	RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)

#define	RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)

#define	RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)

#define	RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)

#define	RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)

#define	RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)

#define	RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)

#define	RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)

#define	RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)

#define	RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)

#define	RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)

#define	RADEON_COLOR_ARG_B_SHIFT 5

#define	RADEON_COLOR_ARG_B_MASK (0x1f << 5)

#define	RADEON_COLOR_ARG_B_ZERO (0 << 5)

#define	RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)

#define	RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)

#define	RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)

#define	RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)

#define	RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)

#define	RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)

#define	RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)

#define	RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)

#define	RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)

#define	RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)

#define	RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)

#define	RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)

#define	RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)

#define	RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)

#define	RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)

#define	RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)

#define	RADEON_COLOR_ARG_C_SHIFT 10

#define	RADEON_COLOR_ARG_C_MASK (0x1f << 10)

#define	RADEON_COLOR_ARG_C_ZERO (0 << 10)

#define	RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)

#define	RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)

#define	RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)

#define	RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)

#define	RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)

#define	RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)

#define	RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)

#define	RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)

#define	RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)

#define	RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)

#define	RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)

#define	RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)

#define	RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)

#define	RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)

#define	RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)

#define	RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)

#define	RADEON_COMP_ARG_A (1 << 15)

#define	RADEON_COMP_ARG_A_SHIFT 15

#define	RADEON_COMP_ARG_B (1 << 16)

#define	RADEON_COMP_ARG_B_SHIFT 16

#define	RADEON_COMP_ARG_C (1 << 17)

#define	RADEON_COMP_ARG_C_SHIFT 17

#define	RADEON_BLEND_CTL_MASK (7 << 18)

#define	RADEON_BLEND_CTL_ADD (0 << 18)

#define	RADEON_BLEND_CTL_SUBTRACT (1 << 18)

#define	RADEON_BLEND_CTL_ADDSIGNED (2 << 18)

#define	RADEON_BLEND_CTL_BLEND (3 << 18)

#define	RADEON_BLEND_CTL_DOT3 (4 << 18)

#define	RADEON_SCALE_SHIFT 21

#define	RADEON_SCALE_MASK (3 << 21)

#define	RADEON_SCALE_1X (0 << 21)

#define	RADEON_SCALE_2X (1 << 21)

#define	RADEON_SCALE_4X (2 << 21)

#define	RADEON_CLAMP_TX (1 << 23)

#define	RADEON_T0_EQ_TCUR (1 << 24)

#define	RADEON_T1_EQ_TCUR (1 << 25)

#define	RADEON_T2_EQ_TCUR (1 << 26)

#define	RADEON_T3_EQ_TCUR (1 << 27)

#define	RADEON_COLOR_ARG_MASK 0x1f

#define	RADEON_COMP_ARG_SHIFT 15

#define	RADEON_PP_TXABLEND_0 0x1c64

#define	RADEON_PP_TXABLEND_1 0x1c7c

#define	RADEON_PP_TXABLEND_2 0x1c94

#define	RADEON_ALPHA_ARG_A_SHIFT 0

#define	RADEON_ALPHA_ARG_A_MASK (0xf << 0)

#define	RADEON_ALPHA_ARG_A_ZERO (0 << 0)

#define	RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)

#define	RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)

#define	RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)

#define	RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)

#define	RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)

#define	RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)

#define	RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)

#define	RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)

#define	RADEON_ALPHA_ARG_B_SHIFT 4

#define	RADEON_ALPHA_ARG_B_MASK (0xf << 4)

#define	RADEON_ALPHA_ARG_B_ZERO (0 << 4)

#define	RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)

#define	RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)

#define	RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)

#define	RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)

#define	RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)

#define	RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)

#define	RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)

#define	RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)

#define	RADEON_ALPHA_ARG_C_SHIFT 8

#define	RADEON_ALPHA_ARG_C_MASK (0xf << 8)

#define	RADEON_ALPHA_ARG_C_ZERO (0 << 8)

#define	RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)

#define	RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)

#define	RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)

#define	RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)

#define	RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)

#define	RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)

#define	RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)

#define	RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)

#define	RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)

#define	RADEON_ALPHA_ARG_MASK 0xf

#define	RADEON_PP_TFACTOR_0 0x1c68

#define	RADEON_PP_TFACTOR_1 0x1c80

#define	RADEON_PP_TFACTOR_2 0x1c98

#define	RADEON_RB3D_BLENDCNTL 0x1c20

#define	RADEON_COMB_FCN_MASK (3 << 12)

#define	RADEON_COMB_FCN_ADD_CLAMP (0 << 12)

#define	RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)

#define	RADEON_COMB_FCN_SUB_CLAMP (2 << 12)

#define	RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)

#define	RADEON_SRC_BLEND_GL_ZERO (32 << 16)

#define	RADEON_SRC_BLEND_GL_ONE (33 << 16)

#define	RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)

#define	RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)

#define	RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)

#define	RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)

#define	RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)

#define	RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)

#define	RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)

#define	RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)

#define	RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)

#define	RADEON_SRC_BLEND_MASK (63 << 16)

#define	RADEON_DST_BLEND_GL_ZERO (32 << 24)

#define	RADEON_DST_BLEND_GL_ONE (33 << 24)

#define	RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)

#define	RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)

#define	RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)

#define	RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)

#define	RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)

#define	RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)

#define	RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)

#define	RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)

#define	RADEON_DST_BLEND_MASK (63 << 24)

#define	RADEON_RB3D_CNTL 0x1c3c

#define	RADEON_ALPHA_BLEND_ENABLE (1 << 0)

#define	RADEON_PLANE_MASK_ENABLE (1 << 1)

#define	RADEON_DITHER_ENABLE (1 << 2)

#define	RADEON_ROUND_ENABLE (1 << 3)

#define	RADEON_SCALE_DITHER_ENABLE (1 << 4)

#define	RADEON_DITHER_INIT (1 << 5)

#define	RADEON_ROP_ENABLE (1 << 6)

#define	RADEON_STENCIL_ENABLE (1 << 7)

#define	RADEON_Z_ENABLE (1 << 8)

#define	RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9)

#define	RADEON_RB3D_COLOR_FORMAT_SHIFT 10

#define	RADEON_COLOR_FORMAT_ARGB1555 3

#define	RADEON_COLOR_FORMAT_RGB565 4

#define	RADEON_COLOR_FORMAT_ARGB8888 6

#define	RADEON_COLOR_FORMAT_RGB332 7

#define	RADEON_COLOR_FORMAT_Y8 8

#define	RADEON_COLOR_FORMAT_RGB8 9

#define	RADEON_COLOR_FORMAT_YUV422_VYUY 11

#define	RADEON_COLOR_FORMAT_YUV422_YVYU 12

#define	RADEON_COLOR_FORMAT_aYUV444 14

#define	RADEON_COLOR_FORMAT_ARGB4444 15

#define	RADEON_CLRCMP_FLIP_ENABLE (1 << 14)

#define	RADEON_RB3D_COLOROFFSET 0x1c40

#define	RADEON_COLOROFFSET_MASK 0xfffffff0

#define	RADEON_RB3D_COLORPITCH 0x1c48

#define	RADEON_COLORPITCH_MASK 0x000001ff8

#define	RADEON_COLOR_TILE_ENABLE (1 << 16)

#define	RADEON_COLOR_MICROTILE_ENABLE (1 << 17)

#define	RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)

#define	RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)

#define	RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)

#define	RADEON_RB3D_DEPTHOFFSET 0x1c24

#define	RADEON_RB3D_DEPTHPITCH 0x1c28

#define	RADEON_DEPTHPITCH_MASK 0x00001ff8

#define	RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)

#define	RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)

#define	RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)

#define	RADEON_RB3D_PLANEMASK 0x1d84

#define	RADEON_RB3D_ROPCNTL 0x1d80

#define	RADEON_ROP_MASK (15 << 8)

#define	RADEON_ROP_CLEAR (0 << 8)

#define	RADEON_ROP_NOR (1 << 8)

#define	RADEON_ROP_AND_INVERTED (2 << 8)

#define	RADEON_ROP_COPY_INVERTED (3 << 8)

#define	RADEON_ROP_AND_REVERSE (4 << 8)

#define	RADEON_ROP_INVERT (5 << 8)

#define	RADEON_ROP_XOR (6 << 8)

#define	RADEON_ROP_NAND (7 << 8)

#define	RADEON_ROP_AND (8 << 8)

#define	RADEON_ROP_EQUIV (9 << 8)

#define	RADEON_ROP_NOOP (10 << 8)

#define	RADEON_ROP_OR_INVERTED (11 << 8)

#define	RADEON_ROP_COPY (12 << 8)

#define	RADEON_ROP_OR_REVERSE (13 << 8)

#define	RADEON_ROP_OR (14 << 8)

#define	RADEON_ROP_SET (15 << 8)

#define	RADEON_RB3D_STENCILREFMASK 0x1d7c

#define	RADEON_STENCIL_REF_SHIFT 0

#define	RADEON_STENCIL_REF_MASK (0xff << 0)

#define	RADEON_STENCIL_MASK_SHIFT 16

#define	RADEON_STENCIL_VALUE_MASK (0xff << 16)

#define	RADEON_STENCIL_WRITEMASK_SHIFT 24

#define	RADEON_STENCIL_WRITE_MASK (0xff << 24)

#define	RADEON_RB3D_ZSTENCILCNTL 0x1c2c

#define	RADEON_DEPTH_FORMAT_MASK (0xf << 0)

#define	RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)

#define	RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)

#define	RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)

#define	RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)

#define	RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)

#define	RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)

#define	RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)

#define	RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)

#define	RADEON_Z_TEST_NEVER (0 << 4)

#define	RADEON_Z_TEST_LESS (1 << 4)

#define	RADEON_Z_TEST_LEQUAL (2 << 4)

#define	RADEON_Z_TEST_EQUAL (3 << 4)

#define	RADEON_Z_TEST_GEQUAL (4 << 4)

#define	RADEON_Z_TEST_GREATER (5 << 4)

#define	RADEON_Z_TEST_NEQUAL (6 << 4)

#define	RADEON_Z_TEST_ALWAYS (7 << 4)

#define	RADEON_Z_TEST_MASK (7 << 4)

#define	RADEON_STENCIL_TEST_NEVER (0 << 12)

#define	RADEON_STENCIL_TEST_LESS (1 << 12)

#define	RADEON_STENCIL_TEST_LEQUAL (2 << 12)

#define	RADEON_STENCIL_TEST_EQUAL (3 << 12)

#define	RADEON_STENCIL_TEST_GEQUAL (4 << 12)

#define	RADEON_STENCIL_TEST_GREATER (5 << 12)

#define	RADEON_STENCIL_TEST_NEQUAL (6 << 12)

#define	RADEON_STENCIL_TEST_ALWAYS (7 << 12)

#define	RADEON_STENCIL_TEST_MASK (0x7 << 12)

#define	RADEON_STENCIL_FAIL_KEEP (0 << 16)

#define	RADEON_STENCIL_FAIL_ZERO (1 << 16)

#define	RADEON_STENCIL_FAIL_REPLACE (2 << 16)

#define	RADEON_STENCIL_FAIL_INC (3 << 16)

#define	RADEON_STENCIL_FAIL_DEC (4 << 16)

#define	RADEON_STENCIL_FAIL_INVERT (5 << 16)

#define	RADEON_STENCIL_FAIL_MASK (0x7 << 16)

#define	RADEON_STENCIL_ZPASS_KEEP (0 << 20)

#define	RADEON_STENCIL_ZPASS_ZERO (1 << 20)

#define	RADEON_STENCIL_ZPASS_REPLACE (2 << 20)

#define	RADEON_STENCIL_ZPASS_INC (3 << 20)

#define	RADEON_STENCIL_ZPASS_DEC (4 << 20)

#define	RADEON_STENCIL_ZPASS_INVERT (5 << 20)

#define	RADEON_STENCIL_ZPASS_MASK (0x7 << 20)

#define	RADEON_STENCIL_ZFAIL_KEEP (0 << 24)

#define	RADEON_STENCIL_ZFAIL_ZERO (1 << 24)

#define	RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)

#define	RADEON_STENCIL_ZFAIL_INC (3 << 24)

#define	RADEON_STENCIL_ZFAIL_DEC (4 << 24)

#define	RADEON_STENCIL_ZFAIL_INVERT (5 << 24)

#define	RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)

#define	RADEON_Z_COMPRESSION_ENABLE (1 << 28)

#define	RADEON_FORCE_Z_DIRTY (1 << 29)

#define	RADEON_Z_WRITE_ENABLE (1 << 30)

#define	RADEON_RE_LINE_PATTERN 0x1cd0

#define	RADEON_LINE_PATTERN_MASK 0x0000ffff

#define	RADEON_LINE_REPEAT_COUNT_SHIFT 16

#define	RADEON_LINE_PATTERN_START_SHIFT 24

#define	RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)

#define	RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)

#define	RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)

#define	RADEON_RE_LINE_STATE 0x1cd4

#define	RADEON_LINE_CURRENT_PTR_SHIFT 0

#define	RADEON_LINE_CURRENT_COUNT_SHIFT 8

#define	RADEON_RE_MISC 0x26c4

#define	RADEON_STIPPLE_COORD_MASK 0x1f

#define	RADEON_STIPPLE_X_OFFSET_SHIFT 0

#define	RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)

#define	RADEON_STIPPLE_Y_OFFSET_SHIFT 8

#define	RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)

#define	RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)

#define	RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)

#define	RADEON_RE_SOLID_COLOR 0x1c1c

#define	RADEON_RE_TOP_LEFT 0x26c0

#define	RADEON_RE_LEFT_SHIFT 0

#define	RADEON_RE_TOP_SHIFT 16

#define	RADEON_RE_WIDTH_HEIGHT 0x1c44

#define	RADEON_RE_WIDTH_SHIFT 0

#define	RADEON_RE_HEIGHT_SHIFT 16

#define	RADEON_RB3D_ZPASS_DATA 0x3290

#define	RADEON_RB3D_ZPASS_ADDR 0x3294

#define	RADEON_SE_CNTL 0x1c4c

#define	RADEON_FFACE_CULL_CW (0 << 0)

#define	RADEON_FFACE_CULL_CCW (1 << 0)

#define	RADEON_FFACE_CULL_DIR_MASK (1 << 0)

#define	RADEON_BFACE_CULL (0 << 1)

#define	RADEON_BFACE_SOLID (3 << 1)

#define	RADEON_FFACE_CULL (0 << 3)

#define	RADEON_FFACE_SOLID (3 << 3)

#define	RADEON_FFACE_CULL_MASK (3 << 3)

#define	RADEON_BADVTX_CULL_DISABLE (1 << 5)

#define	RADEON_FLAT_SHADE_VTX_0 (0 << 6)

#define	RADEON_FLAT_SHADE_VTX_1 (1 << 6)

#define	RADEON_FLAT_SHADE_VTX_2 (2 << 6)

#define	RADEON_FLAT_SHADE_VTX_LAST (3 << 6)

#define	RADEON_DIFFUSE_SHADE_SOLID (0 << 8)

#define	RADEON_DIFFUSE_SHADE_FLAT (1 << 8)

#define	RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)

#define	RADEON_DIFFUSE_SHADE_MASK (3 << 8)

#define	RADEON_ALPHA_SHADE_SOLID (0 << 10)

#define	RADEON_ALPHA_SHADE_FLAT (1 << 10)

#define	RADEON_ALPHA_SHADE_GOURAUD (2 << 10)

#define	RADEON_ALPHA_SHADE_MASK (3 << 10)

#define	RADEON_SPECULAR_SHADE_SOLID (0 << 12)

#define	RADEON_SPECULAR_SHADE_FLAT (1 << 12)

#define	RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)

#define	RADEON_SPECULAR_SHADE_MASK (3 << 12)

#define	RADEON_FOG_SHADE_SOLID (0 << 14)

#define	RADEON_FOG_SHADE_FLAT (1 << 14)

#define	RADEON_FOG_SHADE_GOURAUD (2 << 14)

#define	RADEON_FOG_SHADE_MASK (3 << 14)

#define	RADEON_ZBIAS_ENABLE_POINT (1 << 16)

#define	RADEON_ZBIAS_ENABLE_LINE (1 << 17)

#define	RADEON_ZBIAS_ENABLE_TRI (1 << 18)

#define	RADEON_WIDELINE_ENABLE (1 << 20)

#define	RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)

#define	RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)

#define	RADEON_VTX_PIX_CENTER_D3D (0 << 27)

#define	RADEON_VTX_PIX_CENTER_OGL (1 << 27)

#define	RADEON_ROUND_MODE_TRUNC (0 << 28)

#define	RADEON_ROUND_MODE_ROUND (1 << 28)

#define	RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)

#define	RADEON_ROUND_MODE_ROUND_ODD (3 << 28)

#define	RADEON_ROUND_PREC_16TH_PIX (0 << 30)

#define	RADEON_ROUND_PREC_8TH_PIX (1 << 30)

#define	RADEON_ROUND_PREC_4TH_PIX (2 << 30)

#define	RADEON_ROUND_PREC_HALF_PIX (3 << 30)

#define	R200_RE_CNTL 0x1c50

#define	R200_STIPPLE_ENABLE 0x1

#define	R200_SCISSOR_ENABLE 0x2

#define	R200_PATTERN_ENABLE 0x4

#define	R200_PERSPECTIVE_ENABLE 0x8

#define	R200_POINT_SMOOTH 0x20

#define	R200_VTX_STQ0_D3D 0x00010000

#define	R200_VTX_STQ1_D3D 0x00040000

#define	R200_VTX_STQ2_D3D 0x00100000

#define	R200_VTX_STQ3_D3D 0x00400000

#define	R200_VTX_STQ4_D3D 0x01000000

#define	R200_VTX_STQ5_D3D 0x04000000

#define	RADEON_SE_CNTL_STATUS 0x2140

#define	RADEON_VC_NO_SWAP (0 << 0)

#define	RADEON_VC_16BIT_SWAP (1 << 0)

#define	RADEON_VC_32BIT_SWAP (2 << 0)

#define	RADEON_VC_HALF_DWORD_SWAP (3 << 0)

#define	RADEON_TCL_BYPASS (1 << 8)

#define	RADEON_SE_COORD_FMT 0x1c50

#define	RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)

#define	RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)

#define	RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)

#define	RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)

#define	RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)

#define	RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)

#define	RADEON_VTX_W0_NORMALIZE (1 << 12)

#define	RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)

#define	RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)

#define	RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)

#define	RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)

#define	RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)

#define	RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)

#define	RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)

#define	RADEON_SE_LINE_WIDTH 0x1db8

#define	RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c

#define	RADEON_LIGHTING_ENABLE (1 << 0)

#define	RADEON_LIGHT_IN_MODELSPACE (1 << 1)

#define	RADEON_LOCAL_VIEWER (1 << 2)

#define	RADEON_NORMALIZE_NORMALS (1 << 3)

#define	RADEON_RESCALE_NORMALS (1 << 4)

#define	RADEON_SPECULAR_LIGHTS (1 << 5)

#define	RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)

#define	RADEON_LIGHT_ALPHA (1 << 7)

#define	RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)

#define	RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)

#define	RADEON_LM_SOURCE_STATE_PREMULT 0

#define	RADEON_LM_SOURCE_STATE_MULT 1

#define	RADEON_LM_SOURCE_VERTEX_DIFFUSE 2

#define	RADEON_LM_SOURCE_VERTEX_SPECULAR 3

#define	RADEON_EMISSIVE_SOURCE_SHIFT 16

#define	RADEON_AMBIENT_SOURCE_SHIFT 18

#define	RADEON_DIFFUSE_SOURCE_SHIFT 20

#define	RADEON_SPECULAR_SOURCE_SHIFT 22

#define	RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220

#define	RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224

#define	RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228

#define	RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c

#define	RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230

#define	RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234

#define	RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238

#define	RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c

#define	RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210

#define	RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214

#define	RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218

#define	RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c

#define	RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240

#define	RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244

#define	RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248

#define	RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c

#define	RADEON_SE_TCL_MATRIX_SELECT_0 0x225c

#define	RADEON_MODELVIEW_0_SHIFT 0

#define	RADEON_MODELVIEW_1_SHIFT 4

#define	RADEON_MODELVIEW_2_SHIFT 8

#define	RADEON_MODELVIEW_3_SHIFT 12

#define	RADEON_IT_MODELVIEW_0_SHIFT 16

#define	RADEON_IT_MODELVIEW_1_SHIFT 20

#define	RADEON_IT_MODELVIEW_2_SHIFT 24

#define	RADEON_IT_MODELVIEW_3_SHIFT 28

#define	RADEON_SE_TCL_MATRIX_SELECT_1 0x2260

#define	RADEON_MODELPROJECT_0_SHIFT 0

#define	RADEON_MODELPROJECT_1_SHIFT 4

#define	RADEON_MODELPROJECT_2_SHIFT 8

#define	RADEON_MODELPROJECT_3_SHIFT 12

#define	RADEON_TEXMAT_0_SHIFT 16

#define	RADEON_TEXMAT_1_SHIFT 20

#define	RADEON_TEXMAT_2_SHIFT 24

#define	RADEON_TEXMAT_3_SHIFT 28

#define	RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254

#define	RADEON_TCL_VTX_W0 (1 << 0)

#define	RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)

#define	RADEON_TCL_VTX_FP_ALPHA (1 << 2)

#define	RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)

#define	RADEON_TCL_VTX_FP_SPEC (1 << 4)

#define	RADEON_TCL_VTX_FP_FOG (1 << 5)

#define	RADEON_TCL_VTX_PK_SPEC (1 << 6)

#define	RADEON_TCL_VTX_ST0 (1 << 7)

#define	RADEON_TCL_VTX_ST1 (1 << 8)

#define	RADEON_TCL_VTX_Q1 (1 << 9)

#define	RADEON_TCL_VTX_ST2 (1 << 10)

#define	RADEON_TCL_VTX_Q2 (1 << 11)

#define	RADEON_TCL_VTX_ST3 (1 << 12)

#define	RADEON_TCL_VTX_Q3 (1 << 13)

#define	RADEON_TCL_VTX_Q0 (1 << 14)

#define	RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15

#define	RADEON_TCL_VTX_NORM0 (1 << 18)

#define	RADEON_TCL_VTX_XY1 (1 << 27)

#define	RADEON_TCL_VTX_Z1 (1 << 28)

#define	RADEON_TCL_VTX_W1 (1 << 29)

#define	RADEON_TCL_VTX_NORM1 (1 << 30)

#define	RADEON_TCL_VTX_Z0 (1 << 31)

#define	RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258

#define	RADEON_TCL_COMPUTE_XYZW (1 << 0)

#define	RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)

#define	RADEON_TCL_COMPUTE_SPECULAR (1 << 2)

#define	RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)

#define	RADEON_TCL_FORCE_INORDER_PROC (1 << 4)

#define	RADEON_TCL_TEX_INPUT_TEX_0 0

#define	RADEON_TCL_TEX_INPUT_TEX_1 1

#define	RADEON_TCL_TEX_INPUT_TEX_2 2

#define	RADEON_TCL_TEX_INPUT_TEX_3 3

#define	RADEON_TCL_TEX_COMPUTED_TEX_0 8

#define	RADEON_TCL_TEX_COMPUTED_TEX_1 9

#define	RADEON_TCL_TEX_COMPUTED_TEX_2 10

#define	RADEON_TCL_TEX_COMPUTED_TEX_3 11

#define	RADEON_TCL_TEX_0_OUTPUT_SHIFT 16

#define	RADEON_TCL_TEX_1_OUTPUT_SHIFT 20

#define	RADEON_TCL_TEX_2_OUTPUT_SHIFT 24

#define	RADEON_TCL_TEX_3_OUTPUT_SHIFT 28

#define	RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270

#define	RADEON_LIGHT_0_ENABLE (1 << 0)

#define	RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)

#define	RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)

#define	RADEON_LIGHT_0_IS_LOCAL (1 << 3)

#define	RADEON_LIGHT_0_IS_SPOT (1 << 4)

#define	RADEON_LIGHT_0_DUAL_CONE (1 << 5)

#define	RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)

#define	RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)

#define	RADEON_LIGHT_0_SHIFT 0

#define	RADEON_LIGHT_1_ENABLE (1 << 16)

#define	RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)

#define	RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)

#define	RADEON_LIGHT_1_IS_LOCAL (1 << 19)

#define	RADEON_LIGHT_1_IS_SPOT (1 << 20)

#define	RADEON_LIGHT_1_DUAL_CONE (1 << 21)

#define	RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)

#define	RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)

#define	RADEON_LIGHT_1_SHIFT 16

#define	RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274

#define	RADEON_LIGHT_2_SHIFT 0

#define	RADEON_LIGHT_3_SHIFT 16

#define	RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278

#define	RADEON_LIGHT_4_SHIFT 0

#define	RADEON_LIGHT_5_SHIFT 16

#define	RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c

#define	RADEON_LIGHT_6_SHIFT 0

#define	RADEON_LIGHT_7_SHIFT 16

#define	RADEON_SE_TCL_SHININESS 0x2250

#define	RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268

#define	RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)

#define	RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)

#define	RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)

#define	RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)

#define	RADEON_TEXMAT_0_ENABLE (1 << 4)

#define	RADEON_TEXMAT_1_ENABLE (1 << 5)

#define	RADEON_TEXMAT_2_ENABLE (1 << 6)

#define	RADEON_TEXMAT_3_ENABLE (1 << 7)

#define	RADEON_TEXGEN_INPUT_MASK 0xf

#define	RADEON_TEXGEN_INPUT_TEXCOORD_0 0

#define	RADEON_TEXGEN_INPUT_TEXCOORD_1 1

#define	RADEON_TEXGEN_INPUT_TEXCOORD_2 2

#define	RADEON_TEXGEN_INPUT_TEXCOORD_3 3

#define	RADEON_TEXGEN_INPUT_OBJ 4

#define	RADEON_TEXGEN_INPUT_EYE 5

#define	RADEON_TEXGEN_INPUT_EYE_NORMAL 6

#define	RADEON_TEXGEN_INPUT_EYE_REFLECT 7

#define	RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8

#define	RADEON_TEXGEN_0_INPUT_SHIFT 16

#define	RADEON_TEXGEN_1_INPUT_SHIFT 20

#define	RADEON_TEXGEN_2_INPUT_SHIFT 24

#define	RADEON_TEXGEN_3_INPUT_SHIFT 28

#define	RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264

#define	RADEON_UCP_IN_CLIP_SPACE (1 << 0)

#define	RADEON_UCP_IN_MODEL_SPACE (1 << 1)

#define	RADEON_UCP_ENABLE_0 (1 << 2)

#define	RADEON_UCP_ENABLE_1 (1 << 3)

#define	RADEON_UCP_ENABLE_2 (1 << 4)

#define	RADEON_UCP_ENABLE_3 (1 << 5)

#define	RADEON_UCP_ENABLE_4 (1 << 6)

#define	RADEON_UCP_ENABLE_5 (1 << 7)

#define	RADEON_TCL_FOG_MASK (3 << 8)

#define	RADEON_TCL_FOG_DISABLE (0 << 8)

#define	RADEON_TCL_FOG_EXP (1 << 8)

#define	RADEON_TCL_FOG_EXP2 (2 << 8)

#define	RADEON_TCL_FOG_LINEAR (3 << 8)

#define	RADEON_RNG_BASED_FOG (1 << 10)

#define	RADEON_LIGHT_TWOSIDE (1 << 11)

#define	RADEON_BLEND_OP_COUNT_MASK (7 << 12)

#define	RADEON_BLEND_OP_COUNT_SHIFT 12

#define	RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)

#define	RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)

#define	RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)

#define	RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)

#define	RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)

#define	RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)

#define	RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)

#define	RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)

#define	RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)

#define	RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)

#define	RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)

#define	RADEON_CULL_FRONT_IS_CW (0 << 28)

#define	RADEON_CULL_FRONT_IS_CCW (1 << 28)

#define	RADEON_CULL_FRONT (1 << 29)

#define	RADEON_CULL_BACK (1 << 30)

#define	RADEON_FORCE_W_TO_ONE (1 << 31)

#define	RADEON_SE_VPORT_XSCALE 0x1d98

#define	RADEON_SE_VPORT_XOFFSET 0x1d9c

#define	RADEON_SE_VPORT_YSCALE 0x1da0

#define	RADEON_SE_VPORT_YOFFSET 0x1da4

#define	RADEON_SE_VPORT_ZSCALE 0x1da8

#define	RADEON_SE_VPORT_ZOFFSET 0x1dac

#define	RADEON_SE_ZBIAS_FACTOR 0x1db0

#define	RADEON_SE_ZBIAS_CONSTANT 0x1db4

#define	RADEON_SE_VTX_FMT 0x2080

#define	RADEON_SE_VTX_FMT_XY 0x00000000

#define	RADEON_SE_VTX_FMT_W0 0x00000001

#define	RADEON_SE_VTX_FMT_FPCOLOR 0x00000002

#define	RADEON_SE_VTX_FMT_FPALPHA 0x00000004

#define	RADEON_SE_VTX_FMT_PKCOLOR 0x00000008

#define	RADEON_SE_VTX_FMT_FPSPEC 0x00000010

#define	RADEON_SE_VTX_FMT_FPFOG 0x00000020

#define	RADEON_SE_VTX_FMT_PKSPEC 0x00000040

#define	RADEON_SE_VTX_FMT_ST0 0x00000080

#define	RADEON_SE_VTX_FMT_ST1 0x00000100

#define	RADEON_SE_VTX_FMT_Q1 0x00000200

#define	RADEON_SE_VTX_FMT_ST2 0x00000400

#define	RADEON_SE_VTX_FMT_Q2 0x00000800

#define	RADEON_SE_VTX_FMT_ST3 0x00001000

#define	RADEON_SE_VTX_FMT_Q3 0x00002000

#define	RADEON_SE_VTX_FMT_Q0 0x00004000

#define	RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000

#define	RADEON_SE_VTX_FMT_N0 0x00040000

#define	RADEON_SE_VTX_FMT_XY1 0x08000000

#define	RADEON_SE_VTX_FMT_Z1 0x10000000

#define	RADEON_SE_VTX_FMT_W1 0x20000000

#define	RADEON_SE_VTX_FMT_N1 0x40000000

#define	RADEON_SE_VTX_FMT_Z 0x80000000

#define	RADEON_SE_VF_CNTL 0x2084

#define	RADEON_VF_PRIM_TYPE_POINT_LIST 1

#define	RADEON_VF_PRIM_TYPE_LINE_LIST 2

#define	RADEON_VF_PRIM_TYPE_LINE_STRIP 3

#define	RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4

#define	RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5

#define	RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6

#define	RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7

#define	RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8

#define	RADEON_VF_PRIM_TYPE_POINT_LIST_3 9

#define	RADEON_VF_PRIM_TYPE_LINE_LIST_3 10

#define	RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11

#define	RADEON_VF_PRIM_TYPE_LINE_LOOP 12

#define	RADEON_VF_PRIM_TYPE_QUAD_LIST 13

#define	RADEON_VF_PRIM_TYPE_QUAD_STRIP 14

#define	RADEON_VF_PRIM_TYPE_POLYGON 15

#define	RADEON_VF_PRIM_WALK_STATE (0<<4)

#define	RADEON_VF_PRIM_WALK_INDEX (1<<4)

#define	RADEON_VF_PRIM_WALK_LIST (2<<4)

#define	RADEON_VF_PRIM_WALK_DATA (3<<4)

#define	RADEON_VF_COLOR_ORDER_RGBA (1<<6)

#define	RADEON_VF_RADEON_MODE (1<<8)

#define	RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)

#define	RADEON_VF_PROG_STREAM_ENA (1<<10)

#define	RADEON_VF_INDEX_SIZE_SHIFT 11

#define	RADEON_VF_NUM_VERTICES_SHIFT 16

#define	RADEON_SE_PORT_DATA0 0x2000

#define	R200_SE_VAP_CNTL 0x2080

#define	R200_VAP_TCL_ENABLE 0x00000001

#define	R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010

#define	R200_VAP_FORCE_W_TO_ONE 0x00010000

#define	R200_VAP_D3D_TEX_DEFAULT 0x00020000

#define	R200_VAP_VF_MAX_VTX_NUM__SHIFT 18

#define	R200_VAP_VF_MAX_VTX_NUM (9 << 18)

#define	R200_VAP_DX_CLIP_SPACE_DEF 0x00400000

#define	R200_VF_MAX_VTX_INDX 0x210c

#define	R200_VF_MIN_VTX_INDX 0x2110

#define	R200_SE_VTE_CNTL 0x20b0

#define	R200_VPORT_X_SCALE_ENA 0x00000001

#define	R200_VPORT_X_OFFSET_ENA 0x00000002

#define	R200_VPORT_Y_SCALE_ENA 0x00000004

#define	R200_VPORT_Y_OFFSET_ENA 0x00000008

#define	R200_VPORT_Z_SCALE_ENA 0x00000010

#define	R200_VPORT_Z_OFFSET_ENA 0x00000020

#define	R200_VTX_XY_FMT 0x00000100

#define	R200_VTX_Z_FMT 0x00000200

#define	R200_VTX_W0_FMT 0x00000400

#define	R200_VTX_W0_NORMALIZE 0x00000800

#define	R200_VTX_ST_DENORMALIZED 0x00001000

#define	R200_SE_VAP_CNTL_STATUS 0x2140

#define	R200_VC_NO_SWAP (0 << 0)

#define	R200_VC_16BIT_SWAP (1 << 0)

#define	R200_VC_32BIT_SWAP (2 << 0)

#define	R200_PP_TXFILTER_0 0x2c00

#define	R200_PP_TXFILTER_1 0x2c20

#define	R200_PP_TXFILTER_2 0x2c40

#define	R200_PP_TXFILTER_3 0x2c60

#define	R200_PP_TXFILTER_4 0x2c80

#define	R200_PP_TXFILTER_5 0x2ca0

#define	R200_MAG_FILTER_NEAREST (0 << 0)

#define	R200_MAG_FILTER_LINEAR (1 << 0)

#define	R200_MAG_FILTER_MASK (1 << 0)

#define	R200_MIN_FILTER_NEAREST (0 << 1)

#define	R200_MIN_FILTER_LINEAR (1 << 1)

#define	R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)

#define	R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)

#define	R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)

#define	R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)

#define	R200_MIN_FILTER_ANISO_NEAREST (8 << 1)

#define	R200_MIN_FILTER_ANISO_LINEAR (9 << 1)

#define	R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)

#define	R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)

#define	R200_MIN_FILTER_MASK (15 << 1)

#define	R200_MAX_ANISO_1_TO_1 (0 << 5)

#define	R200_MAX_ANISO_2_TO_1 (1 << 5)

#define	R200_MAX_ANISO_4_TO_1 (2 << 5)

#define	R200_MAX_ANISO_8_TO_1 (3 << 5)

#define	R200_MAX_ANISO_16_TO_1 (4 << 5)

#define	R200_MAX_ANISO_MASK (7 << 5)

#define	R200_MAX_MIP_LEVEL_MASK (0x0f << 16)

#define	R200_MAX_MIP_LEVEL_SHIFT 16

#define	R200_YUV_TO_RGB (1 << 20)

#define	R200_YUV_TEMPERATURE_COOL (0 << 21)

#define	R200_YUV_TEMPERATURE_HOT (1 << 21)

#define	R200_YUV_TEMPERATURE_MASK (1 << 21)

#define	R200_WRAPEN_S (1 << 22)

#define	R200_CLAMP_S_WRAP (0 << 23)

#define	R200_CLAMP_S_MIRROR (1 << 23)

#define	R200_CLAMP_S_CLAMP_LAST (2 << 23)

#define	R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)

#define	R200_CLAMP_S_CLAMP_BORDER (4 << 23)

#define	R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)

#define	R200_CLAMP_S_CLAMP_GL (6 << 23)

#define	R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)

#define	R200_CLAMP_S_MASK (7 << 23)

#define	R200_WRAPEN_T (1 << 26)

#define	R200_CLAMP_T_WRAP (0 << 27)

#define	R200_CLAMP_T_MIRROR (1 << 27)

#define	R200_CLAMP_T_CLAMP_LAST (2 << 27)

#define	R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)

#define	R200_CLAMP_T_CLAMP_BORDER (4 << 27)

#define	R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)

#define	R200_CLAMP_T_CLAMP_GL (6 << 27)

#define	R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)

#define	R200_CLAMP_T_MASK (7 << 27)

#define	R200_KILL_LT_ZERO (1 << 30)

#define	R200_BORDER_MODE_OGL (0 << 31)

#define	R200_BORDER_MODE_D3D (1 << 31)

#define	R200_PP_TXFORMAT_0 0x2c04

#define	R200_PP_TXFORMAT_1 0x2c24

#define	R200_PP_TXFORMAT_2 0x2c44

#define	R200_PP_TXFORMAT_3 0x2c64

#define	R200_PP_TXFORMAT_4 0x2c84

#define	R200_PP_TXFORMAT_5 0x2ca4

#define	R200_TXFORMAT_I8 (0 << 0)

#define	R200_TXFORMAT_AI88 (1 << 0)

#define	R200_TXFORMAT_RGB332 (2 << 0)

#define	R200_TXFORMAT_ARGB1555 (3 << 0)

#define	R200_TXFORMAT_RGB565 (4 << 0)

#define	R200_TXFORMAT_ARGB4444 (5 << 0)

#define	R200_TXFORMAT_ARGB8888 (6 << 0)

#define	R200_TXFORMAT_RGBA8888 (7 << 0)

#define	R200_TXFORMAT_Y8 (8 << 0)

#define	R200_TXFORMAT_AVYU4444 (9 << 0)

#define	R200_TXFORMAT_VYUY422 (10 << 0)

#define	R200_TXFORMAT_YVYU422 (11 << 0)

#define	R200_TXFORMAT_DXT1 (12 << 0)

#define	R200_TXFORMAT_DXT23 (14 << 0)

#define	R200_TXFORMAT_DXT45 (15 << 0)

#define	R200_TXFORMAT_DVDU88 (18 << 0)

#define	R200_TXFORMAT_LDVDU655 (19 << 0)

#define	R200_TXFORMAT_LDVDU8888 (20 << 0)

#define	R200_TXFORMAT_GR1616 (21 << 0)

#define	R200_TXFORMAT_ABGR8888 (22 << 0)

#define	R200_TXFORMAT_BGR111110 (23 << 0)

#define	R200_TXFORMAT_FORMAT_MASK (31 << 0)

#define	R200_TXFORMAT_FORMAT_SHIFT 0

#define	R200_TXFORMAT_ALPHA_IN_MAP (1 << 6)

#define	R200_TXFORMAT_NON_POWER2 (1 << 7)

#define	R200_TXFORMAT_WIDTH_MASK (15 << 8)

#define	R200_TXFORMAT_WIDTH_SHIFT 8

#define	R200_TXFORMAT_HEIGHT_MASK (15 << 12)

#define	R200_TXFORMAT_HEIGHT_SHIFT 12

#define	R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */

#define	R200_TXFORMAT_F5_WIDTH_SHIFT 16

#define	R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20)

#define	R200_TXFORMAT_F5_HEIGHT_SHIFT 20

#define	R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)

#define	R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)

#define	R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)

#define	R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24)

#define	R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24)

#define	R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24)

#define	R200_TXFORMAT_ST_ROUTE_MASK (7 << 24)

#define	R200_TXFORMAT_ST_ROUTE_SHIFT 24

#define	R200_TXFORMAT_LOOKUP_DISABLE (1 << 27)

#define	R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)

#define	R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)

#define	R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)

#define	R200_PP_TXFORMAT_X_0 0x2c08

#define	R200_PP_TXFORMAT_X_1 0x2c28

#define	R200_PP_TXFORMAT_X_2 0x2c48

#define	R200_PP_TXFORMAT_X_3 0x2c68

#define	R200_PP_TXFORMAT_X_4 0x2c88

#define	R200_PP_TXFORMAT_X_5 0x2ca8

#define	R200_PP_TXSIZE_0 0x2c0c /* NPOT only */

#define	R200_PP_TXSIZE_1 0x2c2c /* NPOT only */

#define	R200_PP_TXSIZE_2 0x2c4c /* NPOT only */

#define	R200_PP_TXSIZE_3 0x2c6c /* NPOT only */

#define	R200_PP_TXSIZE_4 0x2c8c /* NPOT only */

#define	R200_PP_TXSIZE_5 0x2cac /* NPOT only */

#define	R200_PP_TXPITCH_0 0x2c10 /* NPOT only */

#define	R200_PP_TXPITCH_1 0x2c30 /* NPOT only */

#define	R200_PP_TXPITCH_2 0x2c50 /* NPOT only */

#define	R200_PP_TXPITCH_3 0x2c70 /* NPOT only */

#define	R200_PP_TXPITCH_4 0x2c90 /* NPOT only */

#define	R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */

#define	R200_PP_CUBIC_FACES_0 0x2c18

#define	R200_PP_CUBIC_FACES_1 0x2c38

#define	R200_PP_CUBIC_FACES_2 0x2c58

#define	R200_PP_CUBIC_FACES_3 0x2c78

#define	R200_PP_CUBIC_FACES_4 0x2c98

#define	R200_PP_CUBIC_FACES_5 0x2cb8

#define	R200_PP_TXOFFSET_0 0x2d00

#define	R200_TXO_ENDIAN_NO_SWAP (0 << 0)

#define	R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)

#define	R200_TXO_ENDIAN_WORD_SWAP (2 << 0)

#define	R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0)

#define	R200_TXO_MACRO_LINEAR (0 << 2)

#define	R200_TXO_MACRO_TILE (1 << 2)

#define	R200_TXO_MICRO_LINEAR (0 << 3)

#define	R200_TXO_MICRO_TILE (1 << 3)

#define	R200_TXO_OFFSET_MASK 0xffffffe0

#define	R200_TXO_OFFSET_SHIFT 5

#define	R200_PP_CUBIC_OFFSET_F1_0 0x2d04

#define	R200_PP_CUBIC_OFFSET_F2_0 0x2d08

#define	R200_PP_CUBIC_OFFSET_F3_0 0x2d0c

#define	R200_PP_CUBIC_OFFSET_F4_0 0x2d10

#define	R200_PP_CUBIC_OFFSET_F5_0 0x2d14

#define	R200_PP_TXOFFSET_1 0x2d18

#define	R200_PP_CUBIC_OFFSET_F1_1 0x2d1c

#define	R200_PP_CUBIC_OFFSET_F2_1 0x2d20

#define	R200_PP_CUBIC_OFFSET_F3_1 0x2d24

#define	R200_PP_CUBIC_OFFSET_F4_1 0x2d28

#define	R200_PP_CUBIC_OFFSET_F5_1 0x2d2c

#define	R200_PP_TXOFFSET_2 0x2d30

#define	R200_PP_CUBIC_OFFSET_F1_2 0x2d34

#define	R200_PP_CUBIC_OFFSET_F2_2 0x2d38

#define	R200_PP_CUBIC_OFFSET_F3_2 0x2d3c

#define	R200_PP_CUBIC_OFFSET_F4_2 0x2d40

#define	R200_PP_CUBIC_OFFSET_F5_2 0x2d44

#define	R200_PP_TXOFFSET_3 0x2d48

#define	R200_PP_CUBIC_OFFSET_F1_3 0x2d4c

#define	R200_PP_CUBIC_OFFSET_F2_3 0x2d50

#define	R200_PP_CUBIC_OFFSET_F3_3 0x2d54

#define	R200_PP_CUBIC_OFFSET_F4_3 0x2d58

#define	R200_PP_CUBIC_OFFSET_F5_3 0x2d5c

#define	R200_PP_TXOFFSET_4 0x2d60

#define	R200_PP_CUBIC_OFFSET_F1_4 0x2d64

#define	R200_PP_CUBIC_OFFSET_F2_4 0x2d68

#define	R200_PP_CUBIC_OFFSET_F3_4 0x2d6c

#define	R200_PP_CUBIC_OFFSET_F4_4 0x2d70

#define	R200_PP_CUBIC_OFFSET_F5_4 0x2d74

#define	R200_PP_TXOFFSET_5 0x2d78

#define	R200_PP_CUBIC_OFFSET_F1_5 0x2d7c

#define	R200_PP_CUBIC_OFFSET_F2_5 0x2d80

#define	R200_PP_CUBIC_OFFSET_F3_5 0x2d84

#define	R200_PP_CUBIC_OFFSET_F4_5 0x2d88

#define	R200_PP_CUBIC_OFFSET_F5_5 0x2d8c

#define	R200_PP_TFACTOR_0 0x2ee0

#define	R200_PP_TFACTOR_1 0x2ee4

#define	R200_PP_TFACTOR_2 0x2ee8

#define	R200_PP_TFACTOR_3 0x2eec

#define	R200_PP_TFACTOR_4 0x2ef0

#define	R200_PP_TFACTOR_5 0x2ef4

#define	R200_PP_TXCBLEND_0 0x2f00

#define	R200_TXC_ARG_A_ZERO (0)

#define	R200_TXC_ARG_A_CURRENT_COLOR (2)

#define	R200_TXC_ARG_A_CURRENT_ALPHA (3)

#define	R200_TXC_ARG_A_DIFFUSE_COLOR (4)

#define	R200_TXC_ARG_A_DIFFUSE_ALPHA (5)

#define	R200_TXC_ARG_A_SPECULAR_COLOR (6)

#define	R200_TXC_ARG_A_SPECULAR_ALPHA (7)

#define	R200_TXC_ARG_A_TFACTOR_COLOR (8)

#define	R200_TXC_ARG_A_TFACTOR_ALPHA (9)

#define	R200_TXC_ARG_A_R0_COLOR (10)

#define	R200_TXC_ARG_A_R0_ALPHA (11)

#define	R200_TXC_ARG_A_R1_COLOR (12)

#define	R200_TXC_ARG_A_R1_ALPHA (13)

#define	R200_TXC_ARG_A_R2_COLOR (14)

#define	R200_TXC_ARG_A_R2_ALPHA (15)

#define	R200_TXC_ARG_A_R3_COLOR (16)

#define	R200_TXC_ARG_A_R3_ALPHA (17)

#define	R200_TXC_ARG_A_R4_COLOR (18)

#define	R200_TXC_ARG_A_R4_ALPHA (19)

#define	R200_TXC_ARG_A_R5_COLOR (20)

#define	R200_TXC_ARG_A_R5_ALPHA (21)

#define	R200_TXC_ARG_A_TFACTOR1_COLOR (26)

#define	R200_TXC_ARG_A_TFACTOR1_ALPHA (27)

#define	R200_TXC_ARG_A_MASK (31 << 0)

#define	R200_TXC_ARG_A_SHIFT 0

#define	R200_TXC_ARG_B_ZERO (0 << 5)

#define	R200_TXC_ARG_B_CURRENT_COLOR (2 << 5)

#define	R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5)

#define	R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5)

#define	R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5)

#define	R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5)

#define	R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5)

#define	R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5)

#define	R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5)

#define	R200_TXC_ARG_B_R0_COLOR (10 << 5)

#define	R200_TXC_ARG_B_R0_ALPHA (11 << 5)

#define	R200_TXC_ARG_B_R1_COLOR (12 << 5)

#define	R200_TXC_ARG_B_R1_ALPHA (13 << 5)

#define	R200_TXC_ARG_B_R2_COLOR (14 << 5)

#define	R200_TXC_ARG_B_R2_ALPHA (15 << 5)

#define	R200_TXC_ARG_B_R3_COLOR (16 << 5)

#define	R200_TXC_ARG_B_R3_ALPHA (17 << 5)

#define	R200_TXC_ARG_B_R4_COLOR (18 << 5)

#define	R200_TXC_ARG_B_R4_ALPHA (19 << 5)

#define	R200_TXC_ARG_B_R5_COLOR (20 << 5)

#define	R200_TXC_ARG_B_R5_ALPHA (21 << 5)

#define	R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5)

#define	R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5)

#define	R200_TXC_ARG_B_MASK (31 << 5)

#define	R200_TXC_ARG_B_SHIFT 5

#define	R200_TXC_ARG_C_ZERO (0 << 10)

#define	R200_TXC_ARG_C_CURRENT_COLOR (2 << 10)

#define	R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10)

#define	R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10)

#define	R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10)

#define	R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10)

#define	R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10)

#define	R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10)

#define	R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10)

#define	R200_TXC_ARG_C_R0_COLOR (10 << 10)

#define	R200_TXC_ARG_C_R0_ALPHA (11 << 10)

#define	R200_TXC_ARG_C_R1_COLOR (12 << 10)

#define	R200_TXC_ARG_C_R1_ALPHA (13 << 10)

#define	R200_TXC_ARG_C_R2_COLOR (14 << 10)

#define	R200_TXC_ARG_C_R2_ALPHA (15 << 10)

#define	R200_TXC_ARG_C_R3_COLOR (16 << 10)

#define	R200_TXC_ARG_C_R3_ALPHA (17 << 10)

#define	R200_TXC_ARG_C_R4_COLOR (18 << 10)

#define	R200_TXC_ARG_C_R4_ALPHA (19 << 10)

#define	R200_TXC_ARG_C_R5_COLOR (20 << 10)

#define	R200_TXC_ARG_C_R5_ALPHA (21 << 10)

#define	R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10)

#define	R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10)

#define	R200_TXC_ARG_C_MASK (31 << 10)

#define	R200_TXC_ARG_C_SHIFT 10

#define	R200_TXC_COMP_ARG_A (1 << 16)

#define	R200_TXC_COMP_ARG_A_SHIFT (16)

#define	R200_TXC_BIAS_ARG_A (1 << 17)

#define	R200_TXC_SCALE_ARG_A (1 << 18)

#define	R200_TXC_NEG_ARG_A (1 << 19)

#define	R200_TXC_COMP_ARG_B (1 << 20)

#define	R200_TXC_COMP_ARG_B_SHIFT (20)

#define	R200_TXC_BIAS_ARG_B (1 << 21)

#define	R200_TXC_SCALE_ARG_B (1 << 22)

#define	R200_TXC_NEG_ARG_B (1 << 23)

#define	R200_TXC_COMP_ARG_C (1 << 24)

#define	R200_TXC_COMP_ARG_C_SHIFT (24)

#define	R200_TXC_BIAS_ARG_C (1 << 25)

#define	R200_TXC_SCALE_ARG_C (1 << 26)

#define	R200_TXC_NEG_ARG_C (1 << 27)

#define	R200_TXC_OP_MADD (0 << 28)

#define	R200_TXC_OP_CND0 (2 << 28)

#define	R200_TXC_OP_LERP (3 << 28)

#define	R200_TXC_OP_DOT3 (4 << 28)

#define	R200_TXC_OP_DOT4 (5 << 28)

#define	R200_TXC_OP_CONDITIONAL (6 << 28)

#define	R200_TXC_OP_DOT2_ADD (7 << 28)

#define	R200_TXC_OP_MASK (7 << 28)

#define	R200_PP_TXCBLEND2_0 0x2f04

#define	R200_TXC_TFACTOR_SEL_SHIFT 0

#define	R200_TXC_TFACTOR_SEL_MASK 0x7

#define	R200_TXC_TFACTOR1_SEL_SHIFT 4

#define	R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4)

#define	R200_TXC_SCALE_SHIFT 8

#define	R200_TXC_SCALE_MASK (7 << 8)

#define	R200_TXC_SCALE_1X (0 << 8)

#define	R200_TXC_SCALE_2X (1 << 8)

#define	R200_TXC_SCALE_4X (2 << 8)

#define	R200_TXC_SCALE_8X (3 << 8)

#define	R200_TXC_SCALE_INV2 (5 << 8)

#define	R200_TXC_SCALE_INV4 (6 << 8)

#define	R200_TXC_SCALE_INV8 (7 << 8)

#define	R200_TXC_CLAMP_SHIFT 12

#define	R200_TXC_CLAMP_MASK (3 << 12)

#define	R200_TXC_CLAMP_WRAP (0 << 12)

#define	R200_TXC_CLAMP_0_1 (1 << 12)

#define	R200_TXC_CLAMP_8_8 (2 << 12)

#define	R200_TXC_OUTPUT_REG_MASK (7 << 16)

#define	R200_TXC_OUTPUT_REG_NONE (0 << 16)

#define	R200_TXC_OUTPUT_REG_R0 (1 << 16)

#define	R200_TXC_OUTPUT_REG_R1 (2 << 16)

#define	R200_TXC_OUTPUT_REG_R2 (3 << 16)

#define	R200_TXC_OUTPUT_REG_R3 (4 << 16)

#define	R200_TXC_OUTPUT_REG_R4 (5 << 16)

#define	R200_TXC_OUTPUT_REG_R5 (6 << 16)

#define	R200_TXC_OUTPUT_MASK_MASK (7 << 20)

#define	R200_TXC_OUTPUT_MASK_RGB (0 << 20)

#define	R200_TXC_OUTPUT_MASK_RG (1 << 20)

#define	R200_TXC_OUTPUT_MASK_RB (2 << 20)

#define	R200_TXC_OUTPUT_MASK_R (3 << 20)

#define	R200_TXC_OUTPUT_MASK_GB (4 << 20)

#define	R200_TXC_OUTPUT_MASK_G (5 << 20)

#define	R200_TXC_OUTPUT_MASK_B (6 << 20)

#define	R200_TXC_OUTPUT_MASK_NONE (7 << 20)

#define	R200_TXC_REPL_NORMAL 0

#define	R200_TXC_REPL_RED 1

#define	R200_TXC_REPL_GREEN 2

#define	R200_TXC_REPL_BLUE 3

#define	R200_TXC_REPL_ARG_A_SHIFT 26

#define	R200_TXC_REPL_ARG_A_MASK (3 << 26)

#define	R200_TXC_REPL_ARG_B_SHIFT 28

#define	R200_TXC_REPL_ARG_B_MASK (3 << 28)

#define	R200_TXC_REPL_ARG_C_SHIFT 30

#define	R200_TXC_REPL_ARG_C_MASK (3 << 30)

#define	R200_PP_TXABLEND_0 0x2f08

#define	R200_TXA_ARG_A_ZERO (0)

#define	R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */

#define	R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */

#define	R200_TXA_ARG_A_DIFFUSE_ALPHA (4)

#define	R200_TXA_ARG_A_DIFFUSE_BLUE (5)

#define	R200_TXA_ARG_A_SPECULAR_ALPHA (6)

#define	R200_TXA_ARG_A_SPECULAR_BLUE (7)

#define	R200_TXA_ARG_A_TFACTOR_ALPHA (8)

#define	R200_TXA_ARG_A_TFACTOR_BLUE (9)

#define	R200_TXA_ARG_A_R0_ALPHA (10)

#define	R200_TXA_ARG_A_R0_BLUE (11)

#define	R200_TXA_ARG_A_R1_ALPHA (12)

#define	R200_TXA_ARG_A_R1_BLUE (13)

#define	R200_TXA_ARG_A_R2_ALPHA (14)

#define	R200_TXA_ARG_A_R2_BLUE (15)

#define	R200_TXA_ARG_A_R3_ALPHA (16)

#define	R200_TXA_ARG_A_R3_BLUE (17)

#define	R200_TXA_ARG_A_R4_ALPHA (18)

#define	R200_TXA_ARG_A_R4_BLUE (19)

#define	R200_TXA_ARG_A_R5_ALPHA (20)

#define	R200_TXA_ARG_A_R5_BLUE (21)

#define	R200_TXA_ARG_A_TFACTOR1_ALPHA (26)

#define	R200_TXA_ARG_A_TFACTOR1_BLUE (27)

#define	R200_TXA_ARG_A_MASK (31 << 0)

#define	R200_TXA_ARG_A_SHIFT 0

#define	R200_TXA_ARG_B_ZERO (0 << 5)

#define	R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */

#define	R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */

#define	R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5)

#define	R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5)

#define	R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5)

#define	R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5)

#define	R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5)

#define	R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5)

#define	R200_TXA_ARG_B_R0_ALPHA (10 << 5)

#define	R200_TXA_ARG_B_R0_BLUE (11 << 5)

#define	R200_TXA_ARG_B_R1_ALPHA (12 << 5)

#define	R200_TXA_ARG_B_R1_BLUE (13 << 5)

#define	R200_TXA_ARG_B_R2_ALPHA (14 << 5)

#define	R200_TXA_ARG_B_R2_BLUE (15 << 5)

#define	R200_TXA_ARG_B_R3_ALPHA (16 << 5)

#define	R200_TXA_ARG_B_R3_BLUE (17 << 5)

#define	R200_TXA_ARG_B_R4_ALPHA (18 << 5)

#define	R200_TXA_ARG_B_R4_BLUE (19 << 5)

#define	R200_TXA_ARG_B_R5_ALPHA (20 << 5)

#define	R200_TXA_ARG_B_R5_BLUE (21 << 5)

#define	R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5)

#define	R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5)

#define	R200_TXA_ARG_B_MASK (31 << 5)

#define	R200_TXA_ARG_B_SHIFT 5

#define	R200_TXA_ARG_C_ZERO (0 << 10)

#define	R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */

#define	R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */

#define	R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10)

#define	R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10)

#define	R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10)

#define	R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10)

#define	R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10)

#define	R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10)

#define	R200_TXA_ARG_C_R0_ALPHA (10 << 10)

#define	R200_TXA_ARG_C_R0_BLUE (11 << 10)

#define	R200_TXA_ARG_C_R1_ALPHA (12 << 10)

#define	R200_TXA_ARG_C_R1_BLUE (13 << 10)

#define	R200_TXA_ARG_C_R2_ALPHA (14 << 10)

#define	R200_TXA_ARG_C_R2_BLUE (15 << 10)

#define	R200_TXA_ARG_C_R3_ALPHA (16 << 10)

#define	R200_TXA_ARG_C_R3_BLUE (17 << 10)

#define	R200_TXA_ARG_C_R4_ALPHA (18 << 10)

#define	R200_TXA_ARG_C_R4_BLUE (19 << 10)

#define	R200_TXA_ARG_C_R5_ALPHA (20 << 10)

#define	R200_TXA_ARG_C_R5_BLUE (21 << 10)

#define	R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10)

#define	R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10)

#define	R200_TXA_ARG_C_MASK (31 << 10)

#define	R200_TXA_ARG_C_SHIFT 10

#define	R200_TXA_COMP_ARG_A (1 << 16)

#define	R200_TXA_COMP_ARG_A_SHIFT (16)

#define	R200_TXA_BIAS_ARG_A (1 << 17)

#define	R200_TXA_SCALE_ARG_A (1 << 18)

#define	R200_TXA_NEG_ARG_A (1 << 19)

#define	R200_TXA_COMP_ARG_B (1 << 20)

#define	R200_TXA_COMP_ARG_B_SHIFT (20)

#define	R200_TXA_BIAS_ARG_B (1 << 21)

#define	R200_TXA_SCALE_ARG_B (1 << 22)

#define	R200_TXA_NEG_ARG_B (1 << 23)

#define	R200_TXA_COMP_ARG_C (1 << 24)

#define	R200_TXA_COMP_ARG_C_SHIFT (24)

#define	R200_TXA_BIAS_ARG_C (1 << 25)

#define	R200_TXA_SCALE_ARG_C (1 << 26)

#define	R200_TXA_NEG_ARG_C (1 << 27)

#define	R200_TXA_OP_MADD (0 << 28)

#define	R200_TXA_OP_CND0 (2 << 28)

#define	R200_TXA_OP_LERP (3 << 28)

#define	R200_TXA_OP_CONDITIONAL (6 << 28)

#define	R200_TXA_OP_MASK (7 << 28)

#define	R200_PP_TXABLEND2_0 0x2f0c

#define	R200_TXA_TFACTOR_SEL_SHIFT 0

#define	R200_TXA_TFACTOR_SEL_MASK 0x7

#define	R200_TXA_TFACTOR1_SEL_SHIFT 4

#define	R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4)

#define	R200_TXA_SCALE_SHIFT 8

#define	R200_TXA_SCALE_MASK (7 << 8)

#define	R200_TXA_SCALE_1X (0 << 8)

#define	R200_TXA_SCALE_2X (1 << 8)

#define	R200_TXA_SCALE_4X (2 << 8)

#define	R200_TXA_SCALE_8X (3 << 8)

#define	R200_TXA_SCALE_INV2 (5 << 8)

#define	R200_TXA_SCALE_INV4 (6 << 8)

#define	R200_TXA_SCALE_INV8 (7 << 8)

#define	R200_TXA_CLAMP_SHIFT 12

#define	R200_TXA_CLAMP_MASK (3 << 12)

#define	R200_TXA_CLAMP_WRAP (0 << 12)

#define	R200_TXA_CLAMP_0_1 (1 << 12)

#define	R200_TXA_CLAMP_8_8 (2 << 12)

#define	R200_TXA_OUTPUT_REG_MASK (7 << 16)

#define	R200_TXA_OUTPUT_REG_NONE (0 << 16)

#define	R200_TXA_OUTPUT_REG_R0 (1 << 16)

#define	R200_TXA_OUTPUT_REG_R1 (2 << 16)

#define	R200_TXA_OUTPUT_REG_R2 (3 << 16)

#define	R200_TXA_OUTPUT_REG_R3 (4 << 16)

#define	R200_TXA_OUTPUT_REG_R4 (5 << 16)

#define	R200_TXA_OUTPUT_REG_R5 (6 << 16)

#define	R200_TXA_DOT_ALPHA (1 << 20)

#define	R200_TXA_REPL_NORMAL 0

#define	R200_TXA_REPL_RED 1

#define	R200_TXA_REPL_GREEN 2

#define	R200_TXA_REPL_ARG_A_SHIFT 26

#define	R200_TXA_REPL_ARG_A_MASK (3 << 26)

#define	R200_TXA_REPL_ARG_B_SHIFT 28

#define	R200_TXA_REPL_ARG_B_MASK (3 << 28)

#define	R200_TXA_REPL_ARG_C_SHIFT 30

#define	R200_TXA_REPL_ARG_C_MASK (3 << 30)

#define	R200_SE_VTX_FMT_0 0x2088

#define	R200_VTX_XY 0 /* always have xy */

#define	R200_VTX_Z0 (1<<0)

#define	R200_VTX_W0 (1<<1)

#define	R200_VTX_WEIGHT_COUNT_SHIFT (2)

#define	R200_VTX_PV_MATRIX_SEL (1<<5)

#define	R200_VTX_N0 (1<<6)

#define	R200_VTX_POINT_SIZE (1<<7)

#define	R200_VTX_DISCRETE_FOG (1<<8)

#define	R200_VTX_SHININESS_0 (1<<9)

#define	R200_VTX_SHININESS_1 (1<<10)

#define	R200_VTX_COLOR_NOT_PRESENT 0

#define	R200_VTX_PK_RGBA 1

#define	R200_VTX_FP_RGB 2

#define	R200_VTX_FP_RGBA 3

#define	R200_VTX_COLOR_MASK 3

#define	R200_VTX_COLOR_0_SHIFT 11

#define	R200_VTX_COLOR_1_SHIFT 13

#define	R200_VTX_COLOR_2_SHIFT 15

#define	R200_VTX_COLOR_3_SHIFT 17

#define	R200_VTX_COLOR_4_SHIFT 19

#define	R200_VTX_COLOR_5_SHIFT 21

#define	R200_VTX_COLOR_6_SHIFT 23

#define	R200_VTX_COLOR_7_SHIFT 25

#define	R200_VTX_XY1 (1<<28)

#define	R200_VTX_Z1 (1<<29)

#define	R200_VTX_W1 (1<<30)

#define	R200_VTX_N1 (1<<31)

#define	R200_SE_VTX_FMT_1 0x208c

#define	R200_VTX_TEX0_COMP_CNT_SHIFT 0

#define	R200_VTX_TEX1_COMP_CNT_SHIFT 3

#define	R200_VTX_TEX2_COMP_CNT_SHIFT 6

#define	R200_VTX_TEX3_COMP_CNT_SHIFT 9

#define	R200_VTX_TEX4_COMP_CNT_SHIFT 12

#define	R200_VTX_TEX5_COMP_CNT_SHIFT 15

#define	R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090

#define	R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094

#define	R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250

#define	R200_OUTPUT_XYZW (1<<0)

#define	R200_OUTPUT_COLOR_0 (1<<8)

#define	R200_OUTPUT_COLOR_1 (1<<9)

#define	R200_OUTPUT_TEX_0 (1<<16)

#define	R200_OUTPUT_TEX_1 (1<<17)

#define	R200_OUTPUT_TEX_2 (1<<18)

#define	R200_OUTPUT_TEX_3 (1<<19)

#define	R200_OUTPUT_TEX_4 (1<<20)

#define	R200_OUTPUT_TEX_5 (1<<21)

#define	R200_OUTPUT_TEX_MASK (0x3f<<16)

#define	R200_OUTPUT_DISCRETE_FOG (1<<24)

#define	R200_OUTPUT_PT_SIZE (1<<25)

#define	R200_FORCE_INORDER_PROC (1<<31)

#define	R200_PP_CNTL_X 0x2cc4

#define	R200_PP_TXMULTI_CTL_0 0x2c1c

#define	R200_PP_TXMULTI_CTL_1 0x2c3c

#define	R200_PP_TXMULTI_CTL_2 0x2c5c

#define	R200_PP_TXMULTI_CTL_3 0x2c7c

#define	R200_PP_TXMULTI_CTL_4 0x2c9c

#define	R200_PP_TXMULTI_CTL_5 0x2cbc

#define	R200_SE_VTX_STATE_CNTL 0x2180

#define	R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)

#define	RADEON_CP_ME_RAM_ADDR 0x07d4

#define	RADEON_CP_ME_RAM_RADDR 0x07d8

#define	RADEON_CP_ME_RAM_DATAH 0x07dc

#define	RADEON_CP_ME_RAM_DATAL 0x07e0

#define	RADEON_CP_RB_BASE 0x0700

#define	RADEON_CP_RB_CNTL 0x0704

#define	RADEON_RB_BUFSZ_SHIFT 0

#define	RADEON_RB_BUFSZ_MASK (0x3f << 0)

#define	RADEON_RB_BLKSZ_SHIFT 8

#define	RADEON_RB_BLKSZ_MASK (0x3f << 8)

#define	RADEON_BUF_SWAP_32BIT (2 << 16)

#define	RADEON_MAX_FETCH_SHIFT 18

#define	RADEON_MAX_FETCH_MASK (0x3 << 18)

#define	RADEON_RB_NO_UPDATE (1 << 27)

#define	RADEON_RB_RPTR_WR_ENA (1 << 31)

#define	RADEON_CP_RB_RPTR_ADDR 0x070c

#define	RADEON_CP_RB_RPTR 0x0710

#define	RADEON_CP_RB_WPTR 0x0714

#define	RADEON_CP_RB_RPTR_WR 0x071c

#define	RADEON_SCRATCH_UMSK 0x0770

#define	RADEON_SCRATCH_ADDR 0x0774

#define	R600_CP_RB_BASE 0xc100

#define	R600_CP_RB_CNTL 0xc104

#define	R600_RB_BUFSZ(x) ((x) << 0)

#define	R600_RB_BLKSZ(x) ((x) << 8)

#define	R600_RB_NO_UPDATE (1 << 27)

#define	R600_RB_RPTR_WR_ENA (1 << 31)

#define	R600_CP_RB_RPTR_WR 0xc108

#define	R600_CP_RB_RPTR_ADDR 0xc10c

#define	R600_CP_RB_RPTR_ADDR_HI 0xc110

#define	R600_CP_RB_WPTR 0xc114

#define	R600_CP_RB_WPTR_ADDR 0xc118

#define	R600_CP_RB_WPTR_ADDR_HI 0xc11c

#define	R600_CP_RB_RPTR 0x8700

#define	R600_CP_RB_WPTR_DELAY 0x8704

#define	RADEON_CP_IB_BASE 0x0738

#define	RADEON_CP_IB_BUFSZ 0x073c

#define	RADEON_CP_CSQ_CNTL 0x0740

#define	RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)

#define	RADEON_CSQ_PRIDIS_INDDIS (0 << 28)

#define	RADEON_CSQ_PRIPIO_INDDIS (1 << 28)

#define	RADEON_CSQ_PRIBM_INDDIS (2 << 28)

#define	RADEON_CSQ_PRIPIO_INDBM (3 << 28)

#define	RADEON_CSQ_PRIBM_INDBM (4 << 28)

#define	RADEON_CSQ_PRIPIO_INDPIO (15 << 28)

#define	R300_CP_RESYNC_ADDR 0x778

#define	R300_CP_RESYNC_DATA 0x77c

#define	RADEON_CP_CSQ_STAT 0x07f8

#define	RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)

#define	RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)

#define	RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)

#define	RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)

#define	RADEON_CP_CSQ2_STAT 0x07fc

#define	RADEON_CP_CSQ_ADDR 0x07f0

#define	RADEON_CP_CSQ_DATA 0x07f4

#define	RADEON_CP_CSQ_APER_PRIMARY 0x1000

#define	RADEON_CP_CSQ_APER_INDIRECT 0x1300

#define	RADEON_CP_RB_WPTR_DELAY 0x0718

#define	RADEON_PRE_WRITE_TIMER_SHIFT 0

#define	RADEON_PRE_WRITE_LIMIT_SHIFT 23

#define	RADEON_CP_CSQ_MODE 0x0744

#define	RADEON_INDIRECT2_START_SHIFT 0

#define	RADEON_INDIRECT2_START_MASK (0x7f << 0)

#define	RADEON_INDIRECT1_START_SHIFT 8

#define	RADEON_INDIRECT1_START_MASK (0x7f << 8)

#define	RADEON_AIC_CNTL 0x01d0

#define	RADEON_PCIGART_TRANSLATE_EN (1 << 0)

#define	RADEON_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1)

#define	RS400_MSI_REARM (1 << 3) /* rs400/rs480 */

#define	RADEON_AIC_LO_ADDR 0x01dc

#define	RADEON_AIC_PT_BASE 0x01d8

#define	RADEON_AIC_HI_ADDR 0x01e0

#define	RADEON_CP_PACKET0 0x00000000

#define	RADEON_CP_PACKET1 0x40000000

#define	RADEON_CP_PACKET2 0x80000000

#define	RADEON_CP_PACKET3 0xC0000000

#define	RADEON_CP_PACKET_MASK 0xC0000000

#define	RADEON_CP_PACKET_COUNT_MASK 0x3fff0000

#define	RADEON_CP_PACKET_MAX_DWORDS (1 << 12)

#define	RADEON_CP_PACKET0_REG_MASK 0x000007ff

#define	R300_CP_PACKET0_REG_MASK 0x00001fff

#define	R600_CP_PACKET0_REG_MASK 0x0000ffff

#define	RADEON_CP_PACKET1_REG0_MASK 0x000007ff

#define	RADEON_CP_PACKET1_REG1_MASK 0x003ff800

#define	RADEON_CP_PACKET0_ONE_REG_WR 0x00008000

#define	RADEON_CP_PACKET3_NOP 0xC0001000

#define	RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900

#define	RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00

#define	RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00

#define	RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300

#define	RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400

#define	RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600

#define	RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800

#define	RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900

#define	RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00

#define	RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00

#define	R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500

#define	RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00

#define	RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100

#define	RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200

#define	RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300

#define	RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400

#define	RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500

#define	RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800

#define	RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00

#define	RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00

#define	RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00

#define	RADEON_CP_VC_FRMT_XY 0x00000000

#define	RADEON_CP_VC_FRMT_W0 0x00000001

#define	RADEON_CP_VC_FRMT_FPCOLOR 0x00000002

#define	RADEON_CP_VC_FRMT_FPALPHA 0x00000004

#define	RADEON_CP_VC_FRMT_PKCOLOR 0x00000008

#define	RADEON_CP_VC_FRMT_FPSPEC 0x00000010

#define	RADEON_CP_VC_FRMT_FPFOG 0x00000020

#define	RADEON_CP_VC_FRMT_PKSPEC 0x00000040

#define	RADEON_CP_VC_FRMT_ST0 0x00000080

#define	RADEON_CP_VC_FRMT_ST1 0x00000100

#define	RADEON_CP_VC_FRMT_Q1 0x00000200

#define	RADEON_CP_VC_FRMT_ST2 0x00000400

#define	RADEON_CP_VC_FRMT_Q2 0x00000800

#define	RADEON_CP_VC_FRMT_ST3 0x00001000

#define	RADEON_CP_VC_FRMT_Q3 0x00002000

#define	RADEON_CP_VC_FRMT_Q0 0x00004000

#define	RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000

#define	RADEON_CP_VC_FRMT_N0 0x00040000

#define	RADEON_CP_VC_FRMT_XY1 0x08000000

#define	RADEON_CP_VC_FRMT_Z1 0x10000000

#define	RADEON_CP_VC_FRMT_W1 0x20000000

#define	RADEON_CP_VC_FRMT_N1 0x40000000

#define	RADEON_CP_VC_FRMT_Z 0x80000000

#define	RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000

#define	RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001

#define	RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002

#define	RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003

#define	RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004

#define	RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005

#define	RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006

#define	RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007

#define	RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008

#define	RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009

#define	RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a

#define	RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010

#define	RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020

#define	RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030

#define	RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000

#define	RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040

#define	RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080

#define	RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000

#define	RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100

#define	RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000

#define	RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200

#define	RADEON_CP_VC_CNTL_NUM_SHIFT 16

#define	RADEON_VS_MATRIX_0_ADDR 0

#define	RADEON_VS_MATRIX_1_ADDR 4

#define	RADEON_VS_MATRIX_2_ADDR 8

#define	RADEON_VS_MATRIX_3_ADDR 12

#define	RADEON_VS_MATRIX_4_ADDR 16

#define	RADEON_VS_MATRIX_5_ADDR 20

#define	RADEON_VS_MATRIX_6_ADDR 24

#define	RADEON_VS_MATRIX_7_ADDR 28

#define	RADEON_VS_MATRIX_8_ADDR 32

#define	RADEON_VS_MATRIX_9_ADDR 36

#define	RADEON_VS_MATRIX_10_ADDR 40

#define	RADEON_VS_MATRIX_11_ADDR 44

#define	RADEON_VS_MATRIX_12_ADDR 48

#define	RADEON_VS_MATRIX_13_ADDR 52

#define	RADEON_VS_MATRIX_14_ADDR 56

#define	RADEON_VS_MATRIX_15_ADDR 60

#define	RADEON_VS_LIGHT_AMBIENT_ADDR 64

#define	RADEON_VS_LIGHT_DIFFUSE_ADDR 72

#define	RADEON_VS_LIGHT_SPECULAR_ADDR 80

#define	RADEON_VS_LIGHT_DIRPOS_ADDR 88

#define	RADEON_VS_LIGHT_HWVSPOT_ADDR 96

#define	RADEON_VS_LIGHT_ATTENUATION_ADDR 104

#define	RADEON_VS_MATRIX_EYE2CLIP_ADDR 112

#define	RADEON_VS_UCP_ADDR 116

#define	RADEON_VS_GLOBAL_AMBIENT_ADDR 122

#define	RADEON_VS_FOG_PARAM_ADDR 123

#define	RADEON_VS_EYE_VECTOR_ADDR 124

#define	RADEON_SS_LIGHT_DCD_ADDR 0

#define	RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8

#define	RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16

#define	RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24

#define	RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32

#define	RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48

#define	RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49

#define	RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50

#define	RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51

#define	RADEON_SS_SHININESS 60

#define	RADEON_TV_MASTER_CNTL 0x0800

#define	RADEON_TV_ASYNC_RST (1 << 0)

#define	RADEON_CRT_ASYNC_RST (1 << 1)

#define	RADEON_RESTART_PHASE_FIX (1 << 3)

#define	RADEON_TV_FIFO_ASYNC_RST (1 << 4)

#define	RADEON_VIN_ASYNC_RST (1 << 5)

#define	RADEON_AUD_ASYNC_RST (1 << 6)

#define	RADEON_DVS_ASYNC_RST (1 << 7)

#define	RADEON_CRT_FIFO_CE_EN (1 << 9)

#define	RADEON_TV_FIFO_CE_EN (1 << 10)

#define	RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)

#define	RADEON_TVCLK_ALWAYS_ONb (1 << 30)

#define	RADEON_TV_ON (1 << 31)

#define	RADEON_TV_PRE_DAC_MUX_CNTL 0x0888

#define	RADEON_Y_RED_EN (1 << 0)

#define	RADEON_C_GRN_EN (1 << 1)

#define	RADEON_CMP_BLU_EN (1 << 2)

#define	RADEON_DAC_DITHER_EN (1 << 3)

#define	RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)

#define	RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)

#define	RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)

#define	RADEON_TV_FORCE_DAC_DATA_SHIFT 16

#define	RADEON_TV_RGB_CNTL 0x0804

#define	RADEON_SWITCH_TO_BLUE (1 << 4)

#define	RADEON_RGB_DITHER_EN (1 << 5)

#define	RADEON_RGB_SRC_SEL_MASK (3 << 8)

#define	RADEON_RGB_SRC_SEL_CRTC1 (0 << 8)

#define	RADEON_RGB_SRC_SEL_RMX (1 << 8)

#define	RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)

#define	RADEON_RGB_CONVERT_BY_PASS (1 << 10)

#define	RADEON_UVRAM_READ_MARGIN_SHIFT 16

#define	RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20

#define	RADEON_RGB_ATTEN_SEL(x) ((x) << 24)

#define	RADEON_TVOUT_SCALE_EN (1 << 26)

#define	RADEON_RGB_ATTEN_VAL(x) ((x) << 28)

#define	RADEON_TV_SYNC_CNTL 0x0808

#define	RADEON_SYNC_OE (1 << 0)

#define	RADEON_SYNC_OUT (1 << 1)

#define	RADEON_SYNC_IN (1 << 2)

#define	RADEON_SYNC_PUB (1 << 3)

#define	RADEON_SYNC_PD (1 << 4)

#define	RADEON_TV_SYNC_IO_DRIVE (1 << 5)

#define	RADEON_TV_HTOTAL 0x080c

#define	RADEON_TV_HDISP 0x0810

#define	RADEON_TV_HSTART 0x0818

#define	RADEON_TV_HCOUNT 0x081C

#define	RADEON_TV_VTOTAL 0x0820

#define	RADEON_TV_VDISP 0x0824

#define	RADEON_TV_VCOUNT 0x0828

#define	RADEON_TV_FTOTAL 0x082c

#define	RADEON_TV_FCOUNT 0x0830

#define	RADEON_TV_FRESTART 0x0834

#define	RADEON_TV_HRESTART 0x0838

#define	RADEON_TV_VRESTART 0x083c

#define	RADEON_TV_HOST_READ_DATA 0x0840

#define	RADEON_TV_HOST_WRITE_DATA 0x0844

#define	RADEON_TV_HOST_RD_WT_CNTL 0x0848

#define	RADEON_HOST_FIFO_RD (1 << 12)

#define	RADEON_HOST_FIFO_RD_ACK (1 << 13)

#define	RADEON_HOST_FIFO_WT (1 << 14)

#define	RADEON_HOST_FIFO_WT_ACK (1 << 15)

#define	RADEON_TV_VSCALER_CNTL1 0x084c

#define	RADEON_UV_INC_MASK 0xffff

#define	RADEON_UV_INC_SHIFT 0

#define	RADEON_Y_W_EN (1 << 24)

#define	RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */

#define	RADEON_Y_DEL_W_SIG_SHIFT 26

#define	RADEON_TV_TIMING_CNTL 0x0850

#define	RADEON_H_INC_MASK 0xfff

#define	RADEON_H_INC_SHIFT 0

#define	RADEON_REQ_Y_FIRST (1 << 19)

#define	RADEON_FORCE_BURST_ALWAYS (1 << 21)

#define	RADEON_UV_POST_SCALE_BYPASS (1 << 23)

#define	RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24

#define	RADEON_TV_VSCALER_CNTL2 0x0854

#define	RADEON_DITHER_MODE (1 << 0)

#define	RADEON_Y_OUTPUT_DITHER_EN (1 << 1)

#define	RADEON_UV_OUTPUT_DITHER_EN (1 << 2)

#define	RADEON_UV_TO_BUF_DITHER_EN (1 << 3)

#define	RADEON_TV_Y_FALL_CNTL 0x0858

#define	RADEON_Y_FALL_PING_PONG (1 << 16)

#define	RADEON_Y_COEF_EN (1 << 17)

#define	RADEON_TV_Y_RISE_CNTL 0x085c

#define	RADEON_Y_RISE_PING_PONG (1 << 16)

#define	RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860

#define	RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864

#define	RADEON_YUPSAMP_EN (1 << 0)

#define	RADEON_UVUPSAMP_EN (1 << 2)

#define	RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868

#define	RADEON_Y_GAIN_LIMIT_SHIFT 0

#define	RADEON_UV_GAIN_LIMIT_SHIFT 16

#define	RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c

#define	RADEON_Y_GAIN_SHIFT 0

#define	RADEON_UV_GAIN_SHIFT 16

#define	RADEON_TV_MODULATOR_CNTL1 0x0870

#define	RADEON_YFLT_EN (1 << 2)

#define	RADEON_UVFLT_EN (1 << 3)

#define	RADEON_ALT_PHASE_EN (1 << 6)

#define	RADEON_SYNC_TIP_LEVEL (1 << 7)

#define	RADEON_BLANK_LEVEL_SHIFT 8

#define	RADEON_SET_UP_LEVEL_SHIFT 16

#define	RADEON_SLEW_RATE_LIMIT (1 << 23)

#define	RADEON_CY_FILT_BLEND_SHIFT 28

#define	RADEON_TV_MODULATOR_CNTL2 0x0874

#define	RADEON_TV_U_BURST_LEVEL_MASK 0x1ff

#define	RADEON_TV_V_BURST_LEVEL_MASK 0x1ff

#define	RADEON_TV_V_BURST_LEVEL_SHIFT 16

#define	RADEON_TV_CRC_CNTL 0x0890

#define	RADEON_TV_UV_ADR 0x08ac

#define	RADEON_MAX_UV_ADR_MASK 0x000000ff

#define	RADEON_MAX_UV_ADR_SHIFT 0

#define	RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00

#define	RADEON_TABLE1_BOT_ADR_SHIFT 8

#define	RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000

#define	RADEON_TABLE3_TOP_ADR_SHIFT 16

#define	RADEON_HCODE_TABLE_SEL_MASK 0x06000000

#define	RADEON_HCODE_TABLE_SEL_SHIFT 25

#define	RADEON_VCODE_TABLE_SEL_MASK 0x18000000

#define	RADEON_VCODE_TABLE_SEL_SHIFT 27

#define	RADEON_TV_MAX_FIFO_ADDR 0x1a7

#define	RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff

#define	RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */

#define	RADEON_TV_PLL_CNTL 0x0021 /* PLL */

#define	RADEON_TV_M0LO_MASK 0xff

#define	RADEON_TV_M0HI_MASK 0x7

#define	RADEON_TV_M0HI_SHIFT 18

#define	RADEON_TV_N0LO_MASK 0x1ff

#define	RADEON_TV_N0LO_SHIFT 8

#define	RADEON_TV_N0HI_MASK 0x3

#define	RADEON_TV_N0HI_SHIFT 21

#define	RADEON_TV_P_MASK 0xf

#define	RADEON_TV_P_SHIFT 24

#define	RADEON_TV_SLIP_EN (1 << 23)

#define	RADEON_TV_DTO_EN (1 << 28)

#define	RADEON_TV_PLL_CNTL1 0x0022 /* PLL */

#define	RADEON_TVPLL_RESET (1 << 1)

#define	RADEON_TVPLL_SLEEP (1 << 3)

#define	RADEON_TVPLL_REFCLK_SEL (1 << 4)

#define	RADEON_TVPCP_SHIFT 8

#define	RADEON_TVPCP_MASK (7 << 8)

#define	RADEON_TVPVG_SHIFT 11

#define	RADEON_TVPVG_MASK (7 << 11)

#define	RADEON_TVPDC_SHIFT 14

#define	RADEON_TVPDC_MASK (3 << 14)

#define	RADEON_TVPLL_TEST_DIS (1 << 31)

#define	RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)

#define	RS400_DISP2_REQ_CNTL1 0xe30

#define	RS400_DISP2_START_REQ_LEVEL_SHIFT 0

#define	RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff

#define	RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12

#define	RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff

#define	RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22

#define	RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff

#define	RS400_DISP2_REQ_CNTL2 0xe34

#define	RS400_DISP2_CRITICAL_POINT_START_SHIFT 12

#define	RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff

#define	RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22

#define	RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff

#define	RS400_DMIF_MEM_CNTL1 0xe38

#define	RS400_DISP2_START_ADR_SHIFT 0

#define	RS400_DISP2_START_ADR_MASK 0x3ff

#define	RS400_DISP1_CRITICAL_POINT_START_SHIFT 12

#define	RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff

#define	RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22

#define	RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff

#define	RS400_DISP1_REQ_CNTL1 0xe3c

#define	RS400_DISP1_START_REQ_LEVEL_SHIFT 0

#define	RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff

#define	RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12

#define	RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff

#define	RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22

#define	RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff

#define	RADEON_PCIE_INDEX 0x0030

#define	RADEON_PCIE_DATA 0x0034

#define	RADEON_PCIE_TX_GART_CNTL 0x10

#define	RADEON_PCIE_TX_GART_EN (1 << 0)

#define	RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)

#define	RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)

#define	RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)

#define	RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)

#define	RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)

#define	RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)

#define	RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)

#define	RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11

#define	RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12

#define	RADEON_PCIE_TX_GART_BASE 0x13

#define	RADEON_PCIE_TX_GART_START_LO 0x14

#define	RADEON_PCIE_TX_GART_START_HI 0x15

#define	RADEON_PCIE_TX_GART_END_LO 0x16

#define	RADEON_PCIE_TX_GART_END_HI 0x17

#define	RADEON_PCIE_TX_GART_ERROR 0x18

#define	RADEON_SCRATCH_REG0 0x15e0

#define	RADEON_SCRATCH_REG1 0x15e4

#define	RADEON_SCRATCH_REG2 0x15e8

#define	RADEON_SCRATCH_REG3 0x15ec

#define	RADEON_SCRATCH_REG4 0x15f0

#define	RADEON_SCRATCH_REG5 0x15f4

#define	RV530_GB_PIPE_SELECT2 0x4124

Macro Definition Documentation

#define ATI_DATATYPE_ARGB1555 3

Definition at line 77 of file radeon_reg.h.

#define ATI_DATATYPE_ARGB4444 15

Definition at line 88 of file radeon_reg.h.

#define ATI_DATATYPE_ARGB8888 6

Definition at line 80 of file radeon_reg.h.

#define ATI_DATATYPE_AYUV_444 14

Definition at line 87 of file radeon_reg.h.

#define ATI_DATATYPE_CI16 10

Definition at line 84 of file radeon_reg.h.

#define ATI_DATATYPE_CI4 1

Definition at line 75 of file radeon_reg.h.

#define ATI_DATATYPE_CI8 2

Definition at line 76 of file radeon_reg.h.

#define ATI_DATATYPE_RGB332 7

Definition at line 81 of file radeon_reg.h.

#define ATI_DATATYPE_RGB565 4

Definition at line 78 of file radeon_reg.h.

#define ATI_DATATYPE_RGB8 9

Definition at line 83 of file radeon_reg.h.

#define ATI_DATATYPE_RGB888 5

Definition at line 79 of file radeon_reg.h.

#define ATI_DATATYPE_VQ 0

Definition at line 74 of file radeon_reg.h.

#define ATI_DATATYPE_VYUY_422 11

Definition at line 85 of file radeon_reg.h.

#define ATI_DATATYPE_Y8 8

Definition at line 82 of file radeon_reg.h.

#define ATI_DATATYPE_YVYU_422 12

Definition at line 86 of file radeon_reg.h.

#define AVIVO_DISPLAY_INT_STATUS (1 << 0)

Definition at line 1020 of file radeon_reg.h.

#define R200_BORDER_MODE_D3D (1 << 31)

Definition at line 2811 of file radeon_reg.h.

#define R200_BORDER_MODE_OGL (0 << 31)

Definition at line 2810 of file radeon_reg.h.

#define R200_CLAMP_S_CLAMP_BORDER (4 << 23)

Definition at line 2794 of file radeon_reg.h.

#define R200_CLAMP_S_CLAMP_GL (6 << 23)

Definition at line 2796 of file radeon_reg.h.

#define R200_CLAMP_S_CLAMP_LAST (2 << 23)

Definition at line 2792 of file radeon_reg.h.

#define R200_CLAMP_S_MASK (7 << 23)

Definition at line 2798 of file radeon_reg.h.

#define R200_CLAMP_S_MIRROR (1 << 23)

Definition at line 2791 of file radeon_reg.h.

#define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)

Definition at line 2795 of file radeon_reg.h.

#define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)

Definition at line 2797 of file radeon_reg.h.

#define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)

Definition at line 2793 of file radeon_reg.h.

#define R200_CLAMP_S_WRAP (0 << 23)

Definition at line 2790 of file radeon_reg.h.

#define R200_CLAMP_T_CLAMP_BORDER (4 << 27)

Definition at line 2804 of file radeon_reg.h.

#define R200_CLAMP_T_CLAMP_GL (6 << 27)

Definition at line 2806 of file radeon_reg.h.

#define R200_CLAMP_T_CLAMP_LAST (2 << 27)

Definition at line 2802 of file radeon_reg.h.

#define R200_CLAMP_T_MASK (7 << 27)

Definition at line 2808 of file radeon_reg.h.

#define R200_CLAMP_T_MIRROR (1 << 27)

Definition at line 2801 of file radeon_reg.h.

#define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)

Definition at line 2805 of file radeon_reg.h.

#define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)

Definition at line 2807 of file radeon_reg.h.

#define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)

Definition at line 2803 of file radeon_reg.h.

#define R200_CLAMP_T_WRAP (0 << 27)

Definition at line 2800 of file radeon_reg.h.

#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500

Definition at line 3407 of file radeon_reg.h.

#define R200_DVI_I2C_PIN_SEL ( x ) ((x) << 3)

Definition at line 1108 of file radeon_reg.h.

#define R200_FORCE_INORDER_PROC (1<<31)

Definition at line 3278 of file radeon_reg.h.

#define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)

Definition at line 951 of file radeon_reg.h.

#define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)

Definition at line 936 of file radeon_reg.h.

#define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)

Definition at line 937 of file radeon_reg.h.

#define R200_FP2_SOURCE_SEL_MASK (3 << 10)

Definition at line 935 of file radeon_reg.h.

#define R200_FP2_SOURCE_SEL_RMX (2 << 10)

Definition at line 938 of file radeon_reg.h.

#define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)

Definition at line 939 of file radeon_reg.h.

#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)

Definition at line 912 of file radeon_reg.h.

#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)

Definition at line 913 of file radeon_reg.h.

#define R200_FP_SOURCE_SEL_MASK (3 << 10)

Definition at line 911 of file radeon_reg.h.

#define R200_FP_SOURCE_SEL_RMX (2 << 10)

Definition at line 914 of file radeon_reg.h.

#define R200_FP_SOURCE_SEL_TRANS (3 << 10)

Definition at line 915 of file radeon_reg.h.

#define R200_KILL_LT_ZERO (1 << 30)

Definition at line 2809 of file radeon_reg.h.

#define R200_MAG_FILTER_LINEAR (1 << 0)

Definition at line 2764 of file radeon_reg.h.

#define R200_MAG_FILTER_MASK (1 << 0)

Definition at line 2765 of file radeon_reg.h.

#define R200_MAG_FILTER_NEAREST (0 << 0)

Definition at line 2763 of file radeon_reg.h.

#define R200_MAX_ANISO_16_TO_1 (4 << 5)

Definition at line 2781 of file radeon_reg.h.

#define R200_MAX_ANISO_1_TO_1 (0 << 5)

Definition at line 2777 of file radeon_reg.h.

#define R200_MAX_ANISO_2_TO_1 (1 << 5)

Definition at line 2778 of file radeon_reg.h.

#define R200_MAX_ANISO_4_TO_1 (2 << 5)

Definition at line 2779 of file radeon_reg.h.

#define R200_MAX_ANISO_8_TO_1 (3 << 5)

Definition at line 2780 of file radeon_reg.h.

#define R200_MAX_ANISO_MASK (7 << 5)

Definition at line 2782 of file radeon_reg.h.

#define R200_MAX_MIP_LEVEL_MASK (0x0f << 16)

Definition at line 2783 of file radeon_reg.h.

#define R200_MAX_MIP_LEVEL_SHIFT 16

Definition at line 2784 of file radeon_reg.h.

#define R200_MIN_FILTER_ANISO_LINEAR (9 << 1)

Definition at line 2773 of file radeon_reg.h.

#define R200_MIN_FILTER_ANISO_NEAREST (8 << 1)

Definition at line 2772 of file radeon_reg.h.

#define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)

Definition at line 2775 of file radeon_reg.h.

#define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)

Definition at line 2774 of file radeon_reg.h.

#define R200_MIN_FILTER_LINEAR (1 << 1)

Definition at line 2767 of file radeon_reg.h.

#define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)

Definition at line 2771 of file radeon_reg.h.

#define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)

Definition at line 2770 of file radeon_reg.h.

#define R200_MIN_FILTER_MASK (15 << 1)

Definition at line 2776 of file radeon_reg.h.

#define R200_MIN_FILTER_NEAREST (0 << 1)

Definition at line 2766 of file radeon_reg.h.

#define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)

Definition at line 2769 of file radeon_reg.h.

#define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)

Definition at line 2768 of file radeon_reg.h.

#define R200_OUTPUT_COLOR_0 (1<<8)

Definition at line 3267 of file radeon_reg.h.

#define R200_OUTPUT_COLOR_1 (1<<9)

Definition at line 3268 of file radeon_reg.h.

#define R200_OUTPUT_DISCRETE_FOG (1<<24)

Definition at line 3276 of file radeon_reg.h.

#define R200_OUTPUT_PT_SIZE (1<<25)

Definition at line 3277 of file radeon_reg.h.

#define R200_OUTPUT_TEX_0 (1<<16)

Definition at line 3269 of file radeon_reg.h.

#define R200_OUTPUT_TEX_1 (1<<17)

Definition at line 3270 of file radeon_reg.h.

#define R200_OUTPUT_TEX_2 (1<<18)

Definition at line 3271 of file radeon_reg.h.

#define R200_OUTPUT_TEX_3 (1<<19)

Definition at line 3272 of file radeon_reg.h.

#define R200_OUTPUT_TEX_4 (1<<20)

Definition at line 3273 of file radeon_reg.h.

#define R200_OUTPUT_TEX_5 (1<<21)

Definition at line 3274 of file radeon_reg.h.

#define R200_OUTPUT_TEX_MASK (0x3f<<16)

Definition at line 3275 of file radeon_reg.h.

#define R200_OUTPUT_XYZW (1<<0)

Definition at line 3266 of file radeon_reg.h.

#define R200_PATTERN_ENABLE 0x4

Definition at line 2449 of file radeon_reg.h.

#define R200_PERSPECTIVE_ENABLE 0x8

Definition at line 2450 of file radeon_reg.h.

#define R200_POINT_SMOOTH 0x20

Definition at line 2451 of file radeon_reg.h.

#define R200_PP_CNTL_X 0x2cc4

Definition at line 3279 of file radeon_reg.h.

#define R200_PP_CUBIC_FACES_0 0x2c18

Definition at line 2884 of file radeon_reg.h.

#define R200_PP_CUBIC_FACES_1 0x2c38

Definition at line 2885 of file radeon_reg.h.

#define R200_PP_CUBIC_FACES_2 0x2c58

Definition at line 2886 of file radeon_reg.h.

#define R200_PP_CUBIC_FACES_3 0x2c78

Definition at line 2887 of file radeon_reg.h.

#define R200_PP_CUBIC_FACES_4 0x2c98

Definition at line 2888 of file radeon_reg.h.

#define R200_PP_CUBIC_FACES_5 0x2cb8

Definition at line 2889 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04

Definition at line 2902 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c

Definition at line 2909 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34

Definition at line 2916 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c

Definition at line 2923 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64

Definition at line 2929 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c

Definition at line 2935 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08

Definition at line 2903 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20

Definition at line 2910 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38

Definition at line 2917 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50

Definition at line 2924 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68

Definition at line 2930 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80

Definition at line 2936 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c

Definition at line 2904 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24

Definition at line 2911 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c

Definition at line 2918 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54

Definition at line 2925 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c

Definition at line 2931 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84

Definition at line 2937 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10

Definition at line 2905 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28

Definition at line 2912 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40

Definition at line 2919 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58

Definition at line 2926 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70

Definition at line 2932 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88

Definition at line 2938 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14

Definition at line 2906 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c

Definition at line 2913 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44

Definition at line 2920 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c

Definition at line 2927 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74

Definition at line 2933 of file radeon_reg.h.

#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c

Definition at line 2939 of file radeon_reg.h.

#define R200_PP_TFACTOR_0 0x2ee0

Definition at line 2941 of file radeon_reg.h.

#define R200_PP_TFACTOR_1 0x2ee4

Definition at line 2942 of file radeon_reg.h.

#define R200_PP_TFACTOR_2 0x2ee8

Definition at line 2943 of file radeon_reg.h.

#define R200_PP_TFACTOR_3 0x2eec

Definition at line 2944 of file radeon_reg.h.

#define R200_PP_TFACTOR_4 0x2ef0

Definition at line 2945 of file radeon_reg.h.

#define R200_PP_TFACTOR_5 0x2ef4

Definition at line 2946 of file radeon_reg.h.

#define R200_PP_TXABLEND2_0 0x2f0c

Definition at line 3189 of file radeon_reg.h.

#define R200_PP_TXABLEND_0 0x2f08

Definition at line 3093 of file radeon_reg.h.

#define R200_PP_TXCBLEND2_0 0x2f04

Definition at line 3047 of file radeon_reg.h.

#define R200_PP_TXCBLEND_0 0x2f00

Definition at line 2948 of file radeon_reg.h.

#define R200_PP_TXFILTER_0 0x2c00

Definition at line 2757 of file radeon_reg.h.

#define R200_PP_TXFILTER_1 0x2c20

Definition at line 2758 of file radeon_reg.h.

#define R200_PP_TXFILTER_2 0x2c40

Definition at line 2759 of file radeon_reg.h.

#define R200_PP_TXFILTER_3 0x2c60

Definition at line 2760 of file radeon_reg.h.

#define R200_PP_TXFILTER_4 0x2c80

Definition at line 2761 of file radeon_reg.h.

#define R200_PP_TXFILTER_5 0x2ca0

Definition at line 2762 of file radeon_reg.h.

#define R200_PP_TXFORMAT_0 0x2c04

Definition at line 2812 of file radeon_reg.h.

#define R200_PP_TXFORMAT_1 0x2c24

Definition at line 2813 of file radeon_reg.h.

#define R200_PP_TXFORMAT_2 0x2c44

Definition at line 2814 of file radeon_reg.h.

#define R200_PP_TXFORMAT_3 0x2c64

Definition at line 2815 of file radeon_reg.h.

#define R200_PP_TXFORMAT_4 0x2c84

Definition at line 2816 of file radeon_reg.h.

#define R200_PP_TXFORMAT_5 0x2ca4

Definition at line 2817 of file radeon_reg.h.

#define R200_PP_TXFORMAT_X_0 0x2c08

Definition at line 2863 of file radeon_reg.h.

#define R200_PP_TXFORMAT_X_1 0x2c28

Definition at line 2864 of file radeon_reg.h.

#define R200_PP_TXFORMAT_X_2 0x2c48

Definition at line 2865 of file radeon_reg.h.

#define R200_PP_TXFORMAT_X_3 0x2c68

Definition at line 2866 of file radeon_reg.h.

#define R200_PP_TXFORMAT_X_4 0x2c88

Definition at line 2867 of file radeon_reg.h.

#define R200_PP_TXFORMAT_X_5 0x2ca8

Definition at line 2868 of file radeon_reg.h.

#define R200_PP_TXMULTI_CTL_0 0x2c1c

Definition at line 3280 of file radeon_reg.h.

#define R200_PP_TXMULTI_CTL_1 0x2c3c

Definition at line 3281 of file radeon_reg.h.

#define R200_PP_TXMULTI_CTL_2 0x2c5c

Definition at line 3282 of file radeon_reg.h.

#define R200_PP_TXMULTI_CTL_3 0x2c7c

Definition at line 3283 of file radeon_reg.h.

#define R200_PP_TXMULTI_CTL_4 0x2c9c

Definition at line 3284 of file radeon_reg.h.

#define R200_PP_TXMULTI_CTL_5 0x2cbc

Definition at line 3285 of file radeon_reg.h.

#define R200_PP_TXOFFSET_0 0x2d00

Definition at line 2891 of file radeon_reg.h.

#define R200_PP_TXOFFSET_1 0x2d18

Definition at line 2908 of file radeon_reg.h.

#define R200_PP_TXOFFSET_2 0x2d30

Definition at line 2915 of file radeon_reg.h.

#define R200_PP_TXOFFSET_3 0x2d48

Definition at line 2922 of file radeon_reg.h.

#define R200_PP_TXOFFSET_4 0x2d60

Definition at line 2928 of file radeon_reg.h.

#define R200_PP_TXOFFSET_5 0x2d78

Definition at line 2934 of file radeon_reg.h.

#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */

Definition at line 2877 of file radeon_reg.h.

#define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */

Definition at line 2878 of file radeon_reg.h.

#define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */

Definition at line 2879 of file radeon_reg.h.

#define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */

Definition at line 2880 of file radeon_reg.h.

#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */

Definition at line 2881 of file radeon_reg.h.

#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */

Definition at line 2882 of file radeon_reg.h.

#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */

Definition at line 2870 of file radeon_reg.h.

#define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */

Definition at line 2871 of file radeon_reg.h.

#define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */

Definition at line 2872 of file radeon_reg.h.

#define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */

Definition at line 2873 of file radeon_reg.h.

#define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */

Definition at line 2874 of file radeon_reg.h.

#define R200_PP_TXSIZE_5 0x2cac /* NPOT only */

Definition at line 2875 of file radeon_reg.h.

#define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)

Definition at line 1620 of file radeon_reg.h.

#define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)

Definition at line 1621 of file radeon_reg.h.

#define R200_RE_CNTL 0x1c50

Definition at line 2446 of file radeon_reg.h.

#define R200_SCISSOR_ENABLE 0x2

Definition at line 2448 of file radeon_reg.h.

#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250

Definition at line 3265 of file radeon_reg.h.

#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090

Definition at line 3263 of file radeon_reg.h.

#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094

Definition at line 3264 of file radeon_reg.h.

#define R200_SE_VAP_CNTL 0x2080

Definition at line 2731 of file radeon_reg.h.

#define R200_SE_VAP_CNTL_STATUS 0x2140

Definition at line 2753 of file radeon_reg.h.

#define R200_SE_VTE_CNTL 0x20b0

Definition at line 2741 of file radeon_reg.h.

#define R200_SE_VTX_FMT_0 0x2088

Definition at line 3227 of file radeon_reg.h.

#define R200_SE_VTX_FMT_1 0x208c

Definition at line 3255 of file radeon_reg.h.

#define R200_SE_VTX_STATE_CNTL 0x2180

Definition at line 3286 of file radeon_reg.h.

#define R200_SEL_DDC1 0 /* depends on asic */

Definition at line 1109 of file radeon_reg.h.

#define R200_SEL_DDC2 1 /* depends on asic */

Definition at line 1110 of file radeon_reg.h.

#define R200_SEL_DDC3 2 /* depends on asic */

Definition at line 1111 of file radeon_reg.h.

#define R200_STIPPLE_ENABLE 0x1

Definition at line 2447 of file radeon_reg.h.

#define R200_SURF_TILE_COLOR_BOTH (3 << 16)

Definition at line 1733 of file radeon_reg.h.

#define R200_SURF_TILE_COLOR_MACRO (1 << 16)

Definition at line 1731 of file radeon_reg.h.

#define R200_SURF_TILE_COLOR_MICRO (2 << 16)

Definition at line 1732 of file radeon_reg.h.

#define R200_SURF_TILE_DEPTH_16BPP (5 << 16)

Definition at line 1735 of file radeon_reg.h.

#define R200_SURF_TILE_DEPTH_32BPP (4 << 16)

Definition at line 1734 of file radeon_reg.h.

#define R200_SURF_TILE_NONE (0 << 16)

Definition at line 1730 of file radeon_reg.h.

#define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */

Definition at line 3095 of file radeon_reg.h.

#define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */

Definition at line 3096 of file radeon_reg.h.

#define R200_TXA_ARG_A_DIFFUSE_ALPHA (4)

Definition at line 3097 of file radeon_reg.h.

#define R200_TXA_ARG_A_DIFFUSE_BLUE (5)

Definition at line 3098 of file radeon_reg.h.

#define R200_TXA_ARG_A_MASK (31 << 0)

Definition at line 3117 of file radeon_reg.h.

#define R200_TXA_ARG_A_R0_ALPHA (10)

Definition at line 3103 of file radeon_reg.h.

#define R200_TXA_ARG_A_R0_BLUE (11)

Definition at line 3104 of file radeon_reg.h.

#define R200_TXA_ARG_A_R1_ALPHA (12)

Definition at line 3105 of file radeon_reg.h.

#define R200_TXA_ARG_A_R1_BLUE (13)

Definition at line 3106 of file radeon_reg.h.

#define R200_TXA_ARG_A_R2_ALPHA (14)

Definition at line 3107 of file radeon_reg.h.

#define R200_TXA_ARG_A_R2_BLUE (15)

Definition at line 3108 of file radeon_reg.h.

#define R200_TXA_ARG_A_R3_ALPHA (16)

Definition at line 3109 of file radeon_reg.h.

#define R200_TXA_ARG_A_R3_BLUE (17)

Definition at line 3110 of file radeon_reg.h.

#define R200_TXA_ARG_A_R4_ALPHA (18)

Definition at line 3111 of file radeon_reg.h.

#define R200_TXA_ARG_A_R4_BLUE (19)

Definition at line 3112 of file radeon_reg.h.

#define R200_TXA_ARG_A_R5_ALPHA (20)

Definition at line 3113 of file radeon_reg.h.

#define R200_TXA_ARG_A_R5_BLUE (21)

Definition at line 3114 of file radeon_reg.h.

#define R200_TXA_ARG_A_SHIFT 0

Definition at line 3118 of file radeon_reg.h.

#define R200_TXA_ARG_A_SPECULAR_ALPHA (6)

Definition at line 3099 of file radeon_reg.h.

#define R200_TXA_ARG_A_SPECULAR_BLUE (7)

Definition at line 3100 of file radeon_reg.h.

#define R200_TXA_ARG_A_TFACTOR1_ALPHA (26)

Definition at line 3115 of file radeon_reg.h.

#define R200_TXA_ARG_A_TFACTOR1_BLUE (27)

Definition at line 3116 of file radeon_reg.h.

#define R200_TXA_ARG_A_TFACTOR_ALPHA (8)

Definition at line 3101 of file radeon_reg.h.

#define R200_TXA_ARG_A_TFACTOR_BLUE (9)

Definition at line 3102 of file radeon_reg.h.

#define R200_TXA_ARG_A_ZERO (0)

Definition at line 3094 of file radeon_reg.h.

#define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */

Definition at line 3120 of file radeon_reg.h.

#define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */

Definition at line 3121 of file radeon_reg.h.

#define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5)

Definition at line 3122 of file radeon_reg.h.

#define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5)

Definition at line 3123 of file radeon_reg.h.

#define R200_TXA_ARG_B_MASK (31 << 5)

Definition at line 3142 of file radeon_reg.h.

#define R200_TXA_ARG_B_R0_ALPHA (10 << 5)

Definition at line 3128 of file radeon_reg.h.

#define R200_TXA_ARG_B_R0_BLUE (11 << 5)

Definition at line 3129 of file radeon_reg.h.

#define R200_TXA_ARG_B_R1_ALPHA (12 << 5)

Definition at line 3130 of file radeon_reg.h.

#define R200_TXA_ARG_B_R1_BLUE (13 << 5)

Definition at line 3131 of file radeon_reg.h.

#define R200_TXA_ARG_B_R2_ALPHA (14 << 5)

Definition at line 3132 of file radeon_reg.h.

#define R200_TXA_ARG_B_R2_BLUE (15 << 5)

Definition at line 3133 of file radeon_reg.h.

#define R200_TXA_ARG_B_R3_ALPHA (16 << 5)

Definition at line 3134 of file radeon_reg.h.

#define R200_TXA_ARG_B_R3_BLUE (17 << 5)

Definition at line 3135 of file radeon_reg.h.

#define R200_TXA_ARG_B_R4_ALPHA (18 << 5)

Definition at line 3136 of file radeon_reg.h.

#define R200_TXA_ARG_B_R4_BLUE (19 << 5)

Definition at line 3137 of file radeon_reg.h.

#define R200_TXA_ARG_B_R5_ALPHA (20 << 5)

Definition at line 3138 of file radeon_reg.h.

#define R200_TXA_ARG_B_R5_BLUE (21 << 5)

Definition at line 3139 of file radeon_reg.h.

#define R200_TXA_ARG_B_SHIFT 5

Definition at line 3143 of file radeon_reg.h.

#define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5)

Definition at line 3124 of file radeon_reg.h.

#define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5)

Definition at line 3125 of file radeon_reg.h.

#define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5)

Definition at line 3140 of file radeon_reg.h.

#define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5)

Definition at line 3141 of file radeon_reg.h.

#define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5)

Definition at line 3126 of file radeon_reg.h.

#define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5)

Definition at line 3127 of file radeon_reg.h.

#define R200_TXA_ARG_B_ZERO (0 << 5)

Definition at line 3119 of file radeon_reg.h.

#define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */

Definition at line 3145 of file radeon_reg.h.

#define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */

Definition at line 3146 of file radeon_reg.h.

#define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10)

Definition at line 3147 of file radeon_reg.h.

#define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10)

Definition at line 3148 of file radeon_reg.h.

#define R200_TXA_ARG_C_MASK (31 << 10)

Definition at line 3167 of file radeon_reg.h.

#define R200_TXA_ARG_C_R0_ALPHA (10 << 10)

Definition at line 3153 of file radeon_reg.h.

#define R200_TXA_ARG_C_R0_BLUE (11 << 10)

Definition at line 3154 of file radeon_reg.h.

#define R200_TXA_ARG_C_R1_ALPHA (12 << 10)

Definition at line 3155 of file radeon_reg.h.

#define R200_TXA_ARG_C_R1_BLUE (13 << 10)

Definition at line 3156 of file radeon_reg.h.

#define R200_TXA_ARG_C_R2_ALPHA (14 << 10)

Definition at line 3157 of file radeon_reg.h.

#define R200_TXA_ARG_C_R2_BLUE (15 << 10)

Definition at line 3158 of file radeon_reg.h.

#define R200_TXA_ARG_C_R3_ALPHA (16 << 10)

Definition at line 3159 of file radeon_reg.h.

#define R200_TXA_ARG_C_R3_BLUE (17 << 10)

Definition at line 3160 of file radeon_reg.h.

#define R200_TXA_ARG_C_R4_ALPHA (18 << 10)

Definition at line 3161 of file radeon_reg.h.

#define R200_TXA_ARG_C_R4_BLUE (19 << 10)

Definition at line 3162 of file radeon_reg.h.

#define R200_TXA_ARG_C_R5_ALPHA (20 << 10)

Definition at line 3163 of file radeon_reg.h.

#define R200_TXA_ARG_C_R5_BLUE (21 << 10)

Definition at line 3164 of file radeon_reg.h.

#define R200_TXA_ARG_C_SHIFT 10

Definition at line 3168 of file radeon_reg.h.

#define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10)

Definition at line 3149 of file radeon_reg.h.

#define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10)

Definition at line 3150 of file radeon_reg.h.

#define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10)

Definition at line 3165 of file radeon_reg.h.

#define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10)

Definition at line 3166 of file radeon_reg.h.

#define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10)

Definition at line 3151 of file radeon_reg.h.

#define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10)

Definition at line 3152 of file radeon_reg.h.

#define R200_TXA_ARG_C_ZERO (0 << 10)

Definition at line 3144 of file radeon_reg.h.

#define R200_TXA_BIAS_ARG_A (1 << 17)

Definition at line 3171 of file radeon_reg.h.

#define R200_TXA_BIAS_ARG_B (1 << 21)

Definition at line 3176 of file radeon_reg.h.

#define R200_TXA_BIAS_ARG_C (1 << 25)

Definition at line 3181 of file radeon_reg.h.

#define R200_TXA_CLAMP_0_1 (1 << 12)

Definition at line 3206 of file radeon_reg.h.

#define R200_TXA_CLAMP_8_8 (2 << 12)

Definition at line 3207 of file radeon_reg.h.

#define R200_TXA_CLAMP_MASK (3 << 12)

Definition at line 3204 of file radeon_reg.h.

#define R200_TXA_CLAMP_SHIFT 12

Definition at line 3203 of file radeon_reg.h.

#define R200_TXA_CLAMP_WRAP (0 << 12)

Definition at line 3205 of file radeon_reg.h.

#define R200_TXA_COMP_ARG_A (1 << 16)

Definition at line 3169 of file radeon_reg.h.

#define R200_TXA_COMP_ARG_A_SHIFT (16)

Definition at line 3170 of file radeon_reg.h.

#define R200_TXA_COMP_ARG_B (1 << 20)

Definition at line 3174 of file radeon_reg.h.

#define R200_TXA_COMP_ARG_B_SHIFT (20)

Definition at line 3175 of file radeon_reg.h.

#define R200_TXA_COMP_ARG_C (1 << 24)

Definition at line 3179 of file radeon_reg.h.

#define R200_TXA_COMP_ARG_C_SHIFT (24)

Definition at line 3180 of file radeon_reg.h.

#define R200_TXA_DOT_ALPHA (1 << 20)

Definition at line 3216 of file radeon_reg.h.

#define R200_TXA_NEG_ARG_A (1 << 19)

Definition at line 3173 of file radeon_reg.h.

#define R200_TXA_NEG_ARG_B (1 << 23)

Definition at line 3178 of file radeon_reg.h.

#define R200_TXA_NEG_ARG_C (1 << 27)

Definition at line 3183 of file radeon_reg.h.

#define R200_TXA_OP_CND0 (2 << 28)

Definition at line 3185 of file radeon_reg.h.

#define R200_TXA_OP_CONDITIONAL (6 << 28)

Definition at line 3187 of file radeon_reg.h.

#define R200_TXA_OP_LERP (3 << 28)

Definition at line 3186 of file radeon_reg.h.

#define R200_TXA_OP_MADD (0 << 28)

Definition at line 3184 of file radeon_reg.h.

#define R200_TXA_OP_MASK (7 << 28)

Definition at line 3188 of file radeon_reg.h.

#define R200_TXA_OUTPUT_REG_MASK (7 << 16)

Definition at line 3208 of file radeon_reg.h.

#define R200_TXA_OUTPUT_REG_NONE (0 << 16)

Definition at line 3209 of file radeon_reg.h.

#define R200_TXA_OUTPUT_REG_R0 (1 << 16)

Definition at line 3210 of file radeon_reg.h.

#define R200_TXA_OUTPUT_REG_R1 (2 << 16)

Definition at line 3211 of file radeon_reg.h.

#define R200_TXA_OUTPUT_REG_R2 (3 << 16)

Definition at line 3212 of file radeon_reg.h.

#define R200_TXA_OUTPUT_REG_R3 (4 << 16)

Definition at line 3213 of file radeon_reg.h.

#define R200_TXA_OUTPUT_REG_R4 (5 << 16)

Definition at line 3214 of file radeon_reg.h.

#define R200_TXA_OUTPUT_REG_R5 (6 << 16)

Definition at line 3215 of file radeon_reg.h.

#define R200_TXA_REPL_ARG_A_MASK (3 << 26)

Definition at line 3221 of file radeon_reg.h.

#define R200_TXA_REPL_ARG_A_SHIFT 26

Definition at line 3220 of file radeon_reg.h.

#define R200_TXA_REPL_ARG_B_MASK (3 << 28)

Definition at line 3223 of file radeon_reg.h.

#define R200_TXA_REPL_ARG_B_SHIFT 28

Definition at line 3222 of file radeon_reg.h.

#define R200_TXA_REPL_ARG_C_MASK (3 << 30)

Definition at line 3225 of file radeon_reg.h.

#define R200_TXA_REPL_ARG_C_SHIFT 30

Definition at line 3224 of file radeon_reg.h.

#define R200_TXA_REPL_GREEN 2

Definition at line 3219 of file radeon_reg.h.

#define R200_TXA_REPL_NORMAL 0

Definition at line 3217 of file radeon_reg.h.

#define R200_TXA_REPL_RED 1

Definition at line 3218 of file radeon_reg.h.

#define R200_TXA_SCALE_1X (0 << 8)

Definition at line 3196 of file radeon_reg.h.

#define R200_TXA_SCALE_2X (1 << 8)

Definition at line 3197 of file radeon_reg.h.

#define R200_TXA_SCALE_4X (2 << 8)

Definition at line 3198 of file radeon_reg.h.

#define R200_TXA_SCALE_8X (3 << 8)

Definition at line 3199 of file radeon_reg.h.

#define R200_TXA_SCALE_ARG_A (1 << 18)

Definition at line 3172 of file radeon_reg.h.

#define R200_TXA_SCALE_ARG_B (1 << 22)

Definition at line 3177 of file radeon_reg.h.

#define R200_TXA_SCALE_ARG_C (1 << 26)

Definition at line 3182 of file radeon_reg.h.

#define R200_TXA_SCALE_INV2 (5 << 8)

Definition at line 3200 of file radeon_reg.h.

#define R200_TXA_SCALE_INV4 (6 << 8)

Definition at line 3201 of file radeon_reg.h.

#define R200_TXA_SCALE_INV8 (7 << 8)

Definition at line 3202 of file radeon_reg.h.

#define R200_TXA_SCALE_MASK (7 << 8)

Definition at line 3195 of file radeon_reg.h.

#define R200_TXA_SCALE_SHIFT 8

Definition at line 3194 of file radeon_reg.h.

#define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4)

Definition at line 3193 of file radeon_reg.h.

#define R200_TXA_TFACTOR1_SEL_SHIFT 4

Definition at line 3192 of file radeon_reg.h.

#define R200_TXA_TFACTOR_SEL_MASK 0x7

Definition at line 3191 of file radeon_reg.h.

#define R200_TXA_TFACTOR_SEL_SHIFT 0

Definition at line 3190 of file radeon_reg.h.

#define R200_TXC_ARG_A_CURRENT_ALPHA (3)

Definition at line 2951 of file radeon_reg.h.

#define R200_TXC_ARG_A_CURRENT_COLOR (2)

Definition at line 2950 of file radeon_reg.h.

#define R200_TXC_ARG_A_DIFFUSE_ALPHA (5)

Definition at line 2953 of file radeon_reg.h.

#define R200_TXC_ARG_A_DIFFUSE_COLOR (4)

Definition at line 2952 of file radeon_reg.h.

#define R200_TXC_ARG_A_MASK (31 << 0)

Definition at line 2972 of file radeon_reg.h.

#define R200_TXC_ARG_A_R0_ALPHA (11)

Definition at line 2959 of file radeon_reg.h.

#define R200_TXC_ARG_A_R0_COLOR (10)

Definition at line 2958 of file radeon_reg.h.

#define R200_TXC_ARG_A_R1_ALPHA (13)

Definition at line 2961 of file radeon_reg.h.

#define R200_TXC_ARG_A_R1_COLOR (12)

Definition at line 2960 of file radeon_reg.h.

#define R200_TXC_ARG_A_R2_ALPHA (15)

Definition at line 2963 of file radeon_reg.h.

#define R200_TXC_ARG_A_R2_COLOR (14)

Definition at line 2962 of file radeon_reg.h.

#define R200_TXC_ARG_A_R3_ALPHA (17)

Definition at line 2965 of file radeon_reg.h.

#define R200_TXC_ARG_A_R3_COLOR (16)

Definition at line 2964 of file radeon_reg.h.

#define R200_TXC_ARG_A_R4_ALPHA (19)

Definition at line 2967 of file radeon_reg.h.

#define R200_TXC_ARG_A_R4_COLOR (18)

Definition at line 2966 of file radeon_reg.h.

#define R200_TXC_ARG_A_R5_ALPHA (21)

Definition at line 2969 of file radeon_reg.h.

#define R200_TXC_ARG_A_R5_COLOR (20)

Definition at line 2968 of file radeon_reg.h.

#define R200_TXC_ARG_A_SHIFT 0

Definition at line 2973 of file radeon_reg.h.

#define R200_TXC_ARG_A_SPECULAR_ALPHA (7)

Definition at line 2955 of file radeon_reg.h.

#define R200_TXC_ARG_A_SPECULAR_COLOR (6)

Definition at line 2954 of file radeon_reg.h.

#define R200_TXC_ARG_A_TFACTOR1_ALPHA (27)

Definition at line 2971 of file radeon_reg.h.

#define R200_TXC_ARG_A_TFACTOR1_COLOR (26)

Definition at line 2970 of file radeon_reg.h.

#define R200_TXC_ARG_A_TFACTOR_ALPHA (9)

Definition at line 2957 of file radeon_reg.h.

#define R200_TXC_ARG_A_TFACTOR_COLOR (8)

Definition at line 2956 of file radeon_reg.h.

#define R200_TXC_ARG_A_ZERO (0)

Definition at line 2949 of file radeon_reg.h.

#define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5)

Definition at line 2976 of file radeon_reg.h.

#define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5)

Definition at line 2975 of file radeon_reg.h.

#define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5)

Definition at line 2978 of file radeon_reg.h.

#define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5)

Definition at line 2977 of file radeon_reg.h.

#define R200_TXC_ARG_B_MASK (31 << 5)

Definition at line 2997 of file radeon_reg.h.

#define R200_TXC_ARG_B_R0_ALPHA (11 << 5)

Definition at line 2984 of file radeon_reg.h.

#define R200_TXC_ARG_B_R0_COLOR (10 << 5)

Definition at line 2983 of file radeon_reg.h.

#define R200_TXC_ARG_B_R1_ALPHA (13 << 5)

Definition at line 2986 of file radeon_reg.h.

#define R200_TXC_ARG_B_R1_COLOR (12 << 5)

Definition at line 2985 of file radeon_reg.h.

#define R200_TXC_ARG_B_R2_ALPHA (15 << 5)

Definition at line 2988 of file radeon_reg.h.

#define R200_TXC_ARG_B_R2_COLOR (14 << 5)

Definition at line 2987 of file radeon_reg.h.

#define R200_TXC_ARG_B_R3_ALPHA (17 << 5)

Definition at line 2990 of file radeon_reg.h.

#define R200_TXC_ARG_B_R3_COLOR (16 << 5)

Definition at line 2989 of file radeon_reg.h.

#define R200_TXC_ARG_B_R4_ALPHA (19 << 5)

Definition at line 2992 of file radeon_reg.h.

#define R200_TXC_ARG_B_R4_COLOR (18 << 5)

Definition at line 2991 of file radeon_reg.h.

#define R200_TXC_ARG_B_R5_ALPHA (21 << 5)

Definition at line 2994 of file radeon_reg.h.

#define R200_TXC_ARG_B_R5_COLOR (20 << 5)

Definition at line 2993 of file radeon_reg.h.

#define R200_TXC_ARG_B_SHIFT 5

Definition at line 2998 of file radeon_reg.h.

#define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5)

Definition at line 2980 of file radeon_reg.h.

#define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5)

Definition at line 2979 of file radeon_reg.h.

#define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5)

Definition at line 2996 of file radeon_reg.h.

#define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5)

Definition at line 2995 of file radeon_reg.h.

#define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5)

Definition at line 2982 of file radeon_reg.h.

#define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5)

Definition at line 2981 of file radeon_reg.h.

#define R200_TXC_ARG_B_ZERO (0 << 5)

Definition at line 2974 of file radeon_reg.h.

#define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10)

Definition at line 3001 of file radeon_reg.h.

#define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10)

Definition at line 3000 of file radeon_reg.h.

#define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10)

Definition at line 3003 of file radeon_reg.h.

#define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10)

Definition at line 3002 of file radeon_reg.h.

#define R200_TXC_ARG_C_MASK (31 << 10)

Definition at line 3022 of file radeon_reg.h.

#define R200_TXC_ARG_C_R0_ALPHA (11 << 10)

Definition at line 3009 of file radeon_reg.h.

#define R200_TXC_ARG_C_R0_COLOR (10 << 10)

Definition at line 3008 of file radeon_reg.h.

#define R200_TXC_ARG_C_R1_ALPHA (13 << 10)

Definition at line 3011 of file radeon_reg.h.

#define R200_TXC_ARG_C_R1_COLOR (12 << 10)

Definition at line 3010 of file radeon_reg.h.

#define R200_TXC_ARG_C_R2_ALPHA (15 << 10)

Definition at line 3013 of file radeon_reg.h.

#define R200_TXC_ARG_C_R2_COLOR (14 << 10)

Definition at line 3012 of file radeon_reg.h.

#define R200_TXC_ARG_C_R3_ALPHA (17 << 10)

Definition at line 3015 of file radeon_reg.h.

#define R200_TXC_ARG_C_R3_COLOR (16 << 10)

Definition at line 3014 of file radeon_reg.h.

#define R200_TXC_ARG_C_R4_ALPHA (19 << 10)

Definition at line 3017 of file radeon_reg.h.

#define R200_TXC_ARG_C_R4_COLOR (18 << 10)

Definition at line 3016 of file radeon_reg.h.

#define R200_TXC_ARG_C_R5_ALPHA (21 << 10)

Definition at line 3019 of file radeon_reg.h.

#define R200_TXC_ARG_C_R5_COLOR (20 << 10)

Definition at line 3018 of file radeon_reg.h.

#define R200_TXC_ARG_C_SHIFT 10

Definition at line 3023 of file radeon_reg.h.

#define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10)

Definition at line 3005 of file radeon_reg.h.

#define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10)

Definition at line 3004 of file radeon_reg.h.

#define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10)

Definition at line 3021 of file radeon_reg.h.

#define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10)

Definition at line 3020 of file radeon_reg.h.

#define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10)

Definition at line 3007 of file radeon_reg.h.

#define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10)

Definition at line 3006 of file radeon_reg.h.

#define R200_TXC_ARG_C_ZERO (0 << 10)

Definition at line 2999 of file radeon_reg.h.

#define R200_TXC_BIAS_ARG_A (1 << 17)

Definition at line 3026 of file radeon_reg.h.

#define R200_TXC_BIAS_ARG_B (1 << 21)

Definition at line 3031 of file radeon_reg.h.

#define R200_TXC_BIAS_ARG_C (1 << 25)

Definition at line 3036 of file radeon_reg.h.

#define R200_TXC_CLAMP_0_1 (1 << 12)

Definition at line 3064 of file radeon_reg.h.

#define R200_TXC_CLAMP_8_8 (2 << 12)

Definition at line 3065 of file radeon_reg.h.

#define R200_TXC_CLAMP_MASK (3 << 12)

Definition at line 3062 of file radeon_reg.h.

#define R200_TXC_CLAMP_SHIFT 12

Definition at line 3061 of file radeon_reg.h.

#define R200_TXC_CLAMP_WRAP (0 << 12)

Definition at line 3063 of file radeon_reg.h.

#define R200_TXC_COMP_ARG_A (1 << 16)

Definition at line 3024 of file radeon_reg.h.

#define R200_TXC_COMP_ARG_A_SHIFT (16)

Definition at line 3025 of file radeon_reg.h.

#define R200_TXC_COMP_ARG_B (1 << 20)

Definition at line 3029 of file radeon_reg.h.

#define R200_TXC_COMP_ARG_B_SHIFT (20)

Definition at line 3030 of file radeon_reg.h.

#define R200_TXC_COMP_ARG_C (1 << 24)

Definition at line 3034 of file radeon_reg.h.

#define R200_TXC_COMP_ARG_C_SHIFT (24)

Definition at line 3035 of file radeon_reg.h.

#define R200_TXC_NEG_ARG_A (1 << 19)

Definition at line 3028 of file radeon_reg.h.

#define R200_TXC_NEG_ARG_B (1 << 23)

Definition at line 3033 of file radeon_reg.h.

#define R200_TXC_NEG_ARG_C (1 << 27)

Definition at line 3038 of file radeon_reg.h.

#define R200_TXC_OP_CND0 (2 << 28)

Definition at line 3040 of file radeon_reg.h.

#define R200_TXC_OP_CONDITIONAL (6 << 28)

Definition at line 3044 of file radeon_reg.h.

#define R200_TXC_OP_DOT2_ADD (7 << 28)

Definition at line 3045 of file radeon_reg.h.

#define R200_TXC_OP_DOT3 (4 << 28)

Definition at line 3042 of file radeon_reg.h.

#define R200_TXC_OP_DOT4 (5 << 28)

Definition at line 3043 of file radeon_reg.h.

#define R200_TXC_OP_LERP (3 << 28)

Definition at line 3041 of file radeon_reg.h.

#define R200_TXC_OP_MADD (0 << 28)

Definition at line 3039 of file radeon_reg.h.

#define R200_TXC_OP_MASK (7 << 28)

Definition at line 3046 of file radeon_reg.h.

#define R200_TXC_OUTPUT_MASK_B (6 << 20)

Definition at line 3081 of file radeon_reg.h.

#define R200_TXC_OUTPUT_MASK_G (5 << 20)

Definition at line 3080 of file radeon_reg.h.

#define R200_TXC_OUTPUT_MASK_GB (4 << 20)

Definition at line 3079 of file radeon_reg.h.

#define R200_TXC_OUTPUT_MASK_MASK (7 << 20)

Definition at line 3074 of file radeon_reg.h.

#define R200_TXC_OUTPUT_MASK_NONE (7 << 20)

Definition at line 3082 of file radeon_reg.h.

#define R200_TXC_OUTPUT_MASK_R (3 << 20)

Definition at line 3078 of file radeon_reg.h.

#define R200_TXC_OUTPUT_MASK_RB (2 << 20)

Definition at line 3077 of file radeon_reg.h.

#define R200_TXC_OUTPUT_MASK_RG (1 << 20)

Definition at line 3076 of file radeon_reg.h.

#define R200_TXC_OUTPUT_MASK_RGB (0 << 20)

Definition at line 3075 of file radeon_reg.h.

#define R200_TXC_OUTPUT_REG_MASK (7 << 16)

Definition at line 3066 of file radeon_reg.h.

#define R200_TXC_OUTPUT_REG_NONE (0 << 16)

Definition at line 3067 of file radeon_reg.h.

#define R200_TXC_OUTPUT_REG_R0 (1 << 16)

Definition at line 3068 of file radeon_reg.h.

#define R200_TXC_OUTPUT_REG_R1 (2 << 16)

Definition at line 3069 of file radeon_reg.h.

#define R200_TXC_OUTPUT_REG_R2 (3 << 16)

Definition at line 3070 of file radeon_reg.h.

#define R200_TXC_OUTPUT_REG_R3 (4 << 16)

Definition at line 3071 of file radeon_reg.h.

#define R200_TXC_OUTPUT_REG_R4 (5 << 16)

Definition at line 3072 of file radeon_reg.h.

#define R200_TXC_OUTPUT_REG_R5 (6 << 16)

Definition at line 3073 of file radeon_reg.h.

#define R200_TXC_REPL_ARG_A_MASK (3 << 26)

Definition at line 3088 of file radeon_reg.h.

#define R200_TXC_REPL_ARG_A_SHIFT 26

Definition at line 3087 of file radeon_reg.h.

#define R200_TXC_REPL_ARG_B_MASK (3 << 28)

Definition at line 3090 of file radeon_reg.h.

#define R200_TXC_REPL_ARG_B_SHIFT 28

Definition at line 3089 of file radeon_reg.h.

#define R200_TXC_REPL_ARG_C_MASK (3 << 30)

Definition at line 3092 of file radeon_reg.h.

#define R200_TXC_REPL_ARG_C_SHIFT 30

Definition at line 3091 of file radeon_reg.h.

#define R200_TXC_REPL_BLUE 3

Definition at line 3086 of file radeon_reg.h.

#define R200_TXC_REPL_GREEN 2

Definition at line 3085 of file radeon_reg.h.

#define R200_TXC_REPL_NORMAL 0

Definition at line 3083 of file radeon_reg.h.

#define R200_TXC_REPL_RED 1

Definition at line 3084 of file radeon_reg.h.

#define R200_TXC_SCALE_1X (0 << 8)

Definition at line 3054 of file radeon_reg.h.

#define R200_TXC_SCALE_2X (1 << 8)

Definition at line 3055 of file radeon_reg.h.

#define R200_TXC_SCALE_4X (2 << 8)

Definition at line 3056 of file radeon_reg.h.

#define R200_TXC_SCALE_8X (3 << 8)

Definition at line 3057 of file radeon_reg.h.

#define R200_TXC_SCALE_ARG_A (1 << 18)

Definition at line 3027 of file radeon_reg.h.

#define R200_TXC_SCALE_ARG_B (1 << 22)

Definition at line 3032 of file radeon_reg.h.

#define R200_TXC_SCALE_ARG_C (1 << 26)

Definition at line 3037 of file radeon_reg.h.

#define R200_TXC_SCALE_INV2 (5 << 8)

Definition at line 3058 of file radeon_reg.h.

#define R200_TXC_SCALE_INV4 (6 << 8)

Definition at line 3059 of file radeon_reg.h.

#define R200_TXC_SCALE_INV8 (7 << 8)

Definition at line 3060 of file radeon_reg.h.

#define R200_TXC_SCALE_MASK (7 << 8)

Definition at line 3053 of file radeon_reg.h.

#define R200_TXC_SCALE_SHIFT 8

Definition at line 3052 of file radeon_reg.h.

#define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4)

Definition at line 3051 of file radeon_reg.h.

#define R200_TXC_TFACTOR1_SEL_SHIFT 4

Definition at line 3050 of file radeon_reg.h.

#define R200_TXC_TFACTOR_SEL_MASK 0x7

Definition at line 3049 of file radeon_reg.h.

#define R200_TXC_TFACTOR_SEL_SHIFT 0

Definition at line 3048 of file radeon_reg.h.

#define R200_TXFORMAT_ABGR8888 (22 << 0)

Definition at line 2837 of file radeon_reg.h.

#define R200_TXFORMAT_AI88 (1 << 0)

Definition at line 2819 of file radeon_reg.h.

#define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6)

Definition at line 2841 of file radeon_reg.h.

#define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)

Definition at line 2860 of file radeon_reg.h.

#define R200_TXFORMAT_ARGB1555 (3 << 0)

Definition at line 2821 of file radeon_reg.h.

#define R200_TXFORMAT_ARGB4444 (5 << 0)

Definition at line 2823 of file radeon_reg.h.

#define R200_TXFORMAT_ARGB8888 (6 << 0)

Definition at line 2824 of file radeon_reg.h.

#define R200_TXFORMAT_AVYU4444 (9 << 0)

Definition at line 2827 of file radeon_reg.h.

#define R200_TXFORMAT_BGR111110 (23 << 0)

Definition at line 2838 of file radeon_reg.h.

#define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)

Definition at line 2861 of file radeon_reg.h.

#define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)

Definition at line 2862 of file radeon_reg.h.

#define R200_TXFORMAT_DVDU88 (18 << 0)

Definition at line 2833 of file radeon_reg.h.

#define R200_TXFORMAT_DXT1 (12 << 0)

Definition at line 2830 of file radeon_reg.h.

#define R200_TXFORMAT_DXT23 (14 << 0)

Definition at line 2831 of file radeon_reg.h.

#define R200_TXFORMAT_DXT45 (15 << 0)

Definition at line 2832 of file radeon_reg.h.

#define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20)

Definition at line 2849 of file radeon_reg.h.

#define R200_TXFORMAT_F5_HEIGHT_SHIFT 20

Definition at line 2850 of file radeon_reg.h.

#define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */

Definition at line 2847 of file radeon_reg.h.

#define R200_TXFORMAT_F5_WIDTH_SHIFT 16

Definition at line 2848 of file radeon_reg.h.

#define R200_TXFORMAT_FORMAT_MASK (31 << 0)

Definition at line 2839 of file radeon_reg.h.

#define R200_TXFORMAT_FORMAT_SHIFT 0

Definition at line 2840 of file radeon_reg.h.

#define R200_TXFORMAT_GR1616 (21 << 0)

Definition at line 2836 of file radeon_reg.h.

#define R200_TXFORMAT_HEIGHT_MASK (15 << 12)

Definition at line 2845 of file radeon_reg.h.

#define R200_TXFORMAT_HEIGHT_SHIFT 12

Definition at line 2846 of file radeon_reg.h.

#define R200_TXFORMAT_I8 (0 << 0)

Definition at line 2818 of file radeon_reg.h.

#define R200_TXFORMAT_LDVDU655 (19 << 0)

Definition at line 2834 of file radeon_reg.h.

#define R200_TXFORMAT_LDVDU8888 (20 << 0)

Definition at line 2835 of file radeon_reg.h.

#define R200_TXFORMAT_LOOKUP_DISABLE (1 << 27)

Definition at line 2859 of file radeon_reg.h.

#define R200_TXFORMAT_NON_POWER2 (1 << 7)

Definition at line 2842 of file radeon_reg.h.

#define R200_TXFORMAT_RGB332 (2 << 0)

Definition at line 2820 of file radeon_reg.h.

#define R200_TXFORMAT_RGB565 (4 << 0)

Definition at line 2822 of file radeon_reg.h.

#define R200_TXFORMAT_RGBA8888 (7 << 0)

Definition at line 2825 of file radeon_reg.h.

#define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24)

Definition at line 2857 of file radeon_reg.h.

#define R200_TXFORMAT_ST_ROUTE_SHIFT 24

Definition at line 2858 of file radeon_reg.h.

#define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)

Definition at line 2851 of file radeon_reg.h.

#define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)

Definition at line 2852 of file radeon_reg.h.

#define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)

Definition at line 2853 of file radeon_reg.h.

#define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24)

Definition at line 2854 of file radeon_reg.h.

#define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24)

Definition at line 2855 of file radeon_reg.h.

#define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24)

Definition at line 2856 of file radeon_reg.h.

#define R200_TXFORMAT_VYUY422 (10 << 0)

Definition at line 2828 of file radeon_reg.h.

#define R200_TXFORMAT_WIDTH_MASK (15 << 8)

Definition at line 2843 of file radeon_reg.h.

#define R200_TXFORMAT_WIDTH_SHIFT 8

Definition at line 2844 of file radeon_reg.h.

#define R200_TXFORMAT_Y8 (8 << 0)

Definition at line 2826 of file radeon_reg.h.

#define R200_TXFORMAT_YVYU422 (11 << 0)

Definition at line 2829 of file radeon_reg.h.

#define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)

Definition at line 2893 of file radeon_reg.h.

#define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0)

Definition at line 2895 of file radeon_reg.h.

#define R200_TXO_ENDIAN_NO_SWAP (0 << 0)

Definition at line 2892 of file radeon_reg.h.

#define R200_TXO_ENDIAN_WORD_SWAP (2 << 0)

Definition at line 2894 of file radeon_reg.h.

#define R200_TXO_MACRO_LINEAR (0 << 2)

Definition at line 2896 of file radeon_reg.h.

#define R200_TXO_MACRO_TILE (1 << 2)

Definition at line 2897 of file radeon_reg.h.

#define R200_TXO_MICRO_LINEAR (0 << 3)

Definition at line 2898 of file radeon_reg.h.

#define R200_TXO_MICRO_TILE (1 << 3)

Definition at line 2899 of file radeon_reg.h.

#define R200_TXO_OFFSET_MASK 0xffffffe0

Definition at line 2900 of file radeon_reg.h.

#define R200_TXO_OFFSET_SHIFT 5

Definition at line 2901 of file radeon_reg.h.

#define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)

Definition at line 3287 of file radeon_reg.h.

#define R200_VAP_D3D_TEX_DEFAULT 0x00020000

Definition at line 2735 of file radeon_reg.h.

#define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000

Definition at line 2738 of file radeon_reg.h.

#define R200_VAP_FORCE_W_TO_ONE 0x00010000

Definition at line 2734 of file radeon_reg.h.

#define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010

Definition at line 2733 of file radeon_reg.h.

#define R200_VAP_TCL_ENABLE 0x00000001

Definition at line 2732 of file radeon_reg.h.

#define R200_VAP_VF_MAX_VTX_NUM (9 << 18)

Definition at line 2737 of file radeon_reg.h.

#define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18

Definition at line 2736 of file radeon_reg.h.

#define R200_VC_16BIT_SWAP (1 << 0)

Definition at line 2755 of file radeon_reg.h.

#define R200_VC_32BIT_SWAP (2 << 0)

Definition at line 2756 of file radeon_reg.h.

#define R200_VC_NO_SWAP (0 << 0)

Definition at line 2754 of file radeon_reg.h.

#define R200_VF_MAX_VTX_INDX 0x210c

Definition at line 2739 of file radeon_reg.h.

#define R200_VF_MIN_VTX_INDX 0x2110

Definition at line 2740 of file radeon_reg.h.

#define R200_VPORT_X_OFFSET_ENA 0x00000002

Definition at line 2743 of file radeon_reg.h.

#define R200_VPORT_X_SCALE_ENA 0x00000001

Definition at line 2742 of file radeon_reg.h.

#define R200_VPORT_Y_OFFSET_ENA 0x00000008

Definition at line 2745 of file radeon_reg.h.

#define R200_VPORT_Y_SCALE_ENA 0x00000004

Definition at line 2744 of file radeon_reg.h.

#define R200_VPORT_Z_OFFSET_ENA 0x00000020

Definition at line 2747 of file radeon_reg.h.

#define R200_VPORT_Z_SCALE_ENA 0x00000010

Definition at line 2746 of file radeon_reg.h.

#define R200_VTX_COLOR_0_SHIFT 11

Definition at line 3243 of file radeon_reg.h.

#define R200_VTX_COLOR_1_SHIFT 13

Definition at line 3244 of file radeon_reg.h.

#define R200_VTX_COLOR_2_SHIFT 15

Definition at line 3245 of file radeon_reg.h.

#define R200_VTX_COLOR_3_SHIFT 17

Definition at line 3246 of file radeon_reg.h.

#define R200_VTX_COLOR_4_SHIFT 19

Definition at line 3247 of file radeon_reg.h.

#define R200_VTX_COLOR_5_SHIFT 21

Definition at line 3248 of file radeon_reg.h.

#define R200_VTX_COLOR_6_SHIFT 23

Definition at line 3249 of file radeon_reg.h.

#define R200_VTX_COLOR_7_SHIFT 25

Definition at line 3250 of file radeon_reg.h.

#define R200_VTX_COLOR_MASK 3

Definition at line 3242 of file radeon_reg.h.

#define R200_VTX_COLOR_NOT_PRESENT 0

Definition at line 3238 of file radeon_reg.h.

#define R200_VTX_DISCRETE_FOG (1<<8)

Definition at line 3235 of file radeon_reg.h.

#define R200_VTX_FP_RGB 2

Definition at line 3240 of file radeon_reg.h.

#define R200_VTX_FP_RGBA 3

Definition at line 3241 of file radeon_reg.h.

#define R200_VTX_N0 (1<<6)

Definition at line 3233 of file radeon_reg.h.

#define R200_VTX_N1 (1<<31)

Definition at line 3254 of file radeon_reg.h.

#define R200_VTX_PK_RGBA 1

Definition at line 3239 of file radeon_reg.h.

#define R200_VTX_POINT_SIZE (1<<7)

Definition at line 3234 of file radeon_reg.h.

#define R200_VTX_PV_MATRIX_SEL (1<<5)

Definition at line 3232 of file radeon_reg.h.

#define R200_VTX_SHININESS_0 (1<<9)

Definition at line 3236 of file radeon_reg.h.

#define R200_VTX_SHININESS_1 (1<<10)

Definition at line 3237 of file radeon_reg.h.

#define R200_VTX_ST_DENORMALIZED 0x00001000

Definition at line 2752 of file radeon_reg.h.

#define R200_VTX_STQ0_D3D 0x00010000

Definition at line 2452 of file radeon_reg.h.

#define R200_VTX_STQ1_D3D 0x00040000

Definition at line 2453 of file radeon_reg.h.

#define R200_VTX_STQ2_D3D 0x00100000

Definition at line 2454 of file radeon_reg.h.

#define R200_VTX_STQ3_D3D 0x00400000

Definition at line 2455 of file radeon_reg.h.

#define R200_VTX_STQ4_D3D 0x01000000

Definition at line 2456 of file radeon_reg.h.

#define R200_VTX_STQ5_D3D 0x04000000

Definition at line 2457 of file radeon_reg.h.

#define R200_VTX_TEX0_COMP_CNT_SHIFT 0

Definition at line 3256 of file radeon_reg.h.

#define R200_VTX_TEX1_COMP_CNT_SHIFT 3

Definition at line 3257 of file radeon_reg.h.

#define R200_VTX_TEX2_COMP_CNT_SHIFT 6

Definition at line 3258 of file radeon_reg.h.

#define R200_VTX_TEX3_COMP_CNT_SHIFT 9

Definition at line 3259 of file radeon_reg.h.

#define R200_VTX_TEX4_COMP_CNT_SHIFT 12

Definition at line 3260 of file radeon_reg.h.

#define R200_VTX_TEX5_COMP_CNT_SHIFT 15

Definition at line 3261 of file radeon_reg.h.

#define R200_VTX_W0 (1<<1)

Definition at line 3230 of file radeon_reg.h.

#define R200_VTX_W0_FMT 0x00000400

Definition at line 2750 of file radeon_reg.h.

#define R200_VTX_W0_NORMALIZE 0x00000800

Definition at line 2751 of file radeon_reg.h.

#define R200_VTX_W1 (1<<30)

Definition at line 3253 of file radeon_reg.h.

#define R200_VTX_WEIGHT_COUNT_SHIFT (2)

Definition at line 3231 of file radeon_reg.h.

#define R200_VTX_XY 0 /* always have xy */

Definition at line 3228 of file radeon_reg.h.

#define R200_VTX_XY1 (1<<28)

Definition at line 3251 of file radeon_reg.h.

#define R200_VTX_XY_FMT 0x00000100

Definition at line 2748 of file radeon_reg.h.

#define R200_VTX_Z0 (1<<0)

Definition at line 3229 of file radeon_reg.h.

#define R200_VTX_Z1 (1<<29)

Definition at line 3252 of file radeon_reg.h.

#define R200_VTX_Z_FMT 0x00000200

Definition at line 2749 of file radeon_reg.h.

#define R200_WRAPEN_S (1 << 22)

Definition at line 2789 of file radeon_reg.h.

#define R200_WRAPEN_T (1 << 26)

Definition at line 2799 of file radeon_reg.h.

#define R200_YUV_TEMPERATURE_COOL (0 << 21)

Definition at line 2786 of file radeon_reg.h.

#define R200_YUV_TEMPERATURE_HOT (1 << 21)

Definition at line 2787 of file radeon_reg.h.

#define R200_YUV_TEMPERATURE_MASK (1 << 21)

Definition at line 2788 of file radeon_reg.h.

#define R200_YUV_TO_RGB (1 << 20)

Definition at line 2785 of file radeon_reg.h.

#define R300_CP_PACKET0_REG_MASK 0x00001fff

Definition at line 3389 of file radeon_reg.h.

#define R300_CP_RESYNC_ADDR 0x778

Definition at line 3341 of file radeon_reg.h.

#define R300_CP_RESYNC_DATA 0x77c

Definition at line 3342 of file radeon_reg.h.

#define R300_CRTC2_TILE_X0_Y0 0x0358

Definition at line 532 of file radeon_reg.h.

#define R300_CRTC_MACRO_TILE_EN (1 << 15)

Definition at line 523 of file radeon_reg.h.

#define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)

Definition at line 522 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)

Definition at line 516 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)

Definition at line 519 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)

Definition at line 518 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)

Definition at line 515 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)

Definition at line 510 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)

Definition at line 513 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)

Definition at line 512 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)

Definition at line 509 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)

Definition at line 511 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)

Definition at line 517 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_EN (1 << 13)

Definition at line 521 of file radeon_reg.h.

#define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)

Definition at line 520 of file radeon_reg.h.

#define R300_CRTC_TILE_X0_Y0 0x0350

Definition at line 531 of file radeon_reg.h.

#define R300_CRTC_X_Y_MODE_EN (1 << 9)

Definition at line 514 of file radeon_reg.h.

#define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)

Definition at line 508 of file radeon_reg.h.

#define R300_DISABLE_MC_MCLKA (1 << 21)

Definition at line 1182 of file radeon_reg.h.

#define R300_DISABLE_MC_MCLKB (1 << 21)

Definition at line 1183 of file radeon_reg.h.

#define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)

Definition at line 1553 of file radeon_reg.h.

#define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)

Definition at line 1791 of file radeon_reg.h.

#define R300_DVOCLK_ALWAYS_ONb (1 << 10)

Definition at line 1542 of file radeon_reg.h.

#define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)

Definition at line 952 of file radeon_reg.h.

#define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)

Definition at line 953 of file radeon_reg.h.

#define R300_HPD_SEL ( x ) ((x) << 13)

Definition at line 918 of file radeon_reg.h.

#define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)

Definition at line 1157 of file radeon_reg.h.

#define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)

Definition at line 1158 of file radeon_reg.h.

#define R300_LVDS_SRC_SEL_MASK (3 << 18)

Definition at line 1156 of file radeon_reg.h.

#define R300_LVDS_SRC_SEL_RMX (2 << 18)

Definition at line 1159 of file radeon_reg.h.

#define R300_MC_DISP0R_INIT_LAT_MASK 0xf

Definition at line 1171 of file radeon_reg.h.

#define R300_MC_DISP0R_INIT_LAT_SHIFT 8

Definition at line 1170 of file radeon_reg.h.

#define R300_MC_DISP1R_INIT_LAT_MASK 0xf

Definition at line 1173 of file radeon_reg.h.

#define R300_MC_DISP1R_INIT_LAT_SHIFT 12

Definition at line 1172 of file radeon_reg.h.

#define R300_MC_IDLE (1 << 4)

Definition at line 1223 of file radeon_reg.h.

#define R300_MC_IND_ADDR_MASK 0x3f

Definition at line 1237 of file radeon_reg.h.

#define R300_MC_IND_DATA 0x01fc

Definition at line 1239 of file radeon_reg.h.

#define R300_MC_IND_INDEX 0x01f8

Definition at line 1236 of file radeon_reg.h.

#define R300_MC_IND_WR_EN (1 << 8)

Definition at line 1238 of file radeon_reg.h.

#define R300_MC_INIT_MISC_LAT_TIMER 0x180

Definition at line 1169 of file radeon_reg.h.

#define R300_MC_READ_CNTL_AB 0x017c

Definition at line 1240 of file radeon_reg.h.

#define R300_MC_READ_CNTL_CD_mcind 0x24

Definition at line 1242 of file radeon_reg.h.

#define R300_MEM_NUM_CHANNELS_MASK 0x03

Definition at line 1205 of file radeon_reg.h.

#define R300_MEM_PWRUP_COMPL_C (1 << 2)

Definition at line 1217 of file radeon_reg.h.

#define R300_MEM_PWRUP_COMPL_D (1 << 3)

Definition at line 1218 of file radeon_reg.h.

#define R300_MEM_PWRUP_COMPLETE 0x0f

Definition at line 1220 of file radeon_reg.h.

#define R300_MEM_RBS_POSITION_A_MASK 0x03

Definition at line 1241 of file radeon_reg.h.

#define R300_MEM_RBS_POSITION_C_MASK 0x03

Definition at line 1243 of file radeon_reg.h.

#define R300_MEM_USE_CD_CH_ONLY (1 << 2)

Definition at line 1206 of file radeon_reg.h.

#define R300_P2G2CLK_ALWAYS_ONb (1 << 18)

Definition at line 1551 of file radeon_reg.h.

#define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)

Definition at line 1552 of file radeon_reg.h.

#define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)

Definition at line 1546 of file radeon_reg.h.

#define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)

Definition at line 1549 of file radeon_reg.h.

#define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)

Definition at line 1550 of file radeon_reg.h.

#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)

Definition at line 1526 of file radeon_reg.h.

#define R300_PPLL_REF_DIV_ACC_SHIFT 18

Definition at line 1527 of file radeon_reg.h.

#define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)

Definition at line 1693 of file radeon_reg.h.

#define R300_SCLK_CNTL2 0x1e /* PLL */

Definition at line 1690 of file radeon_reg.h.

#define R300_SCLK_FORCE_CBA (1<<14)

Definition at line 1695 of file radeon_reg.h.

#define R300_SCLK_FORCE_GA (1<<15)

Definition at line 1696 of file radeon_reg.h.

#define R300_SCLK_FORCE_PX (1<<26)

Definition at line 1686 of file radeon_reg.h.

#define R300_SCLK_FORCE_SR (1<<25)

Definition at line 1685 of file radeon_reg.h.

#define R300_SCLK_FORCE_SU (1<<30)

Definition at line 1689 of file radeon_reg.h.

#define R300_SCLK_FORCE_TCL (1<<13)

Definition at line 1694 of file radeon_reg.h.

#define R300_SCLK_FORCE_TX (1<<27)

Definition at line 1687 of file radeon_reg.h.

#define R300_SCLK_FORCE_US (1<<28)

Definition at line 1688 of file radeon_reg.h.

#define R300_SCLK_FORCE_VAP (1<<21)

Definition at line 1684 of file radeon_reg.h.

#define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)

Definition at line 1692 of file radeon_reg.h.

#define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)

Definition at line 1691 of file radeon_reg.h.

#define R300_SURF_TILE_COLOR_MACRO (1 << 16)

Definition at line 1737 of file radeon_reg.h.

#define R300_SURF_TILE_DEPTH_32BPP (2 << 16)

Definition at line 1738 of file radeon_reg.h.

#define R300_SURF_TILE_NONE (0 << 16)

Definition at line 1736 of file radeon_reg.h.

#define R420_TV_DAC_BDACPD (1 << 27)

Definition at line 673 of file radeon_reg.h.

#define R420_TV_DAC_DACADJ_MASK (0x1f << 20)

Definition at line 670 of file radeon_reg.h.

#define R420_TV_DAC_GDACPD (1 << 26)

Definition at line 672 of file radeon_reg.h.

#define R420_TV_DAC_RDACPD (1 << 25)

Definition at line 671 of file radeon_reg.h.

#define R420_TV_DAC_TVENABLE (1 << 28)

Definition at line 674 of file radeon_reg.h.

#define R600_CP_PACKET0_REG_MASK 0x0000ffff

Definition at line 3390 of file radeon_reg.h.

#define R600_CP_RB_BASE 0xc100

Definition at line 3314 of file radeon_reg.h.

#define R600_CP_RB_CNTL 0xc104

Definition at line 3315 of file radeon_reg.h.

#define R600_CP_RB_RPTR 0x8700

Definition at line 3326 of file radeon_reg.h.

#define R600_CP_RB_RPTR_ADDR 0xc10c

Definition at line 3321 of file radeon_reg.h.

#define R600_CP_RB_RPTR_ADDR_HI 0xc110

Definition at line 3322 of file radeon_reg.h.

#define R600_CP_RB_RPTR_WR 0xc108

Definition at line 3320 of file radeon_reg.h.

#define R600_CP_RB_WPTR 0xc114

Definition at line 3323 of file radeon_reg.h.

#define R600_CP_RB_WPTR_ADDR 0xc118

Definition at line 3324 of file radeon_reg.h.

#define R600_CP_RB_WPTR_ADDR_HI 0xc11c

Definition at line 3325 of file radeon_reg.h.

#define R600_CP_RB_WPTR_DELAY 0x8704

Definition at line 3327 of file radeon_reg.h.

#define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)

Definition at line 327 of file radeon_reg.h.

#define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10)

Definition at line 329 of file radeon_reg.h.

#define R600_PCIE_LC_RENEGOTIATION_SUPPORT (1 << 9)

Definition at line 328 of file radeon_reg.h.

#define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11)

Definition at line 330 of file radeon_reg.h.

#define R600_PCIE_LC_UPCONFIGURE_DIS (1 << 13)

Definition at line 332 of file radeon_reg.h.

#define R600_PCIE_LC_UPCONFIGURE_SUPPORT (1 << 12)

Definition at line 331 of file radeon_reg.h.

#define R600_RB_BLKSZ ( x ) ((x) << 8)

Definition at line 3317 of file radeon_reg.h.

#define R600_RB_BUFSZ ( x ) ((x) << 0)

Definition at line 3316 of file radeon_reg.h.

#define R600_RB_NO_UPDATE (1 << 27)

Definition at line 3318 of file radeon_reg.h.

#define R600_RB_RPTR_WR_ENA (1 << 31)

Definition at line 3319 of file radeon_reg.h.

#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c

Definition at line 334 of file radeon_reg.h.

#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c

Definition at line 335 of file radeon_reg.h.

#define RADEON_ABORT_HW_DVI_I2C (1 << 15)

Definition at line 1116 of file radeon_reg.h.

#define RADEON_ACC_MODE_CHANGE (1 << 2)

Definition at line 207 of file radeon_reg.h.

#define RADEON_ACC_REQ_CRT1 (1 << 17)

Definition at line 200 of file radeon_reg.h.

#define RADEON_ACC_REQ_CRT2 (1 << 21)

Definition at line 203 of file radeon_reg.h.

#define RADEON_ACC_REQ_DFP1 (1 << 19)

Definition at line 202 of file radeon_reg.h.

#define RADEON_ACC_REQ_DFP2 (1 << 23)

Definition at line 205 of file radeon_reg.h.

#define RADEON_ACC_REQ_LCD1 (1 << 16)

Definition at line 199 of file radeon_reg.h.

#define RADEON_ACC_REQ_TV1 (1 << 18)

Definition at line 201 of file radeon_reg.h.

#define RADEON_ACC_REQ_TV2 (1 << 22)

Definition at line 204 of file radeon_reg.h.

#define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)

Definition at line 351 of file radeon_reg.h.

#define RADEON_ACTIVE_HILO_LAT_SHIFT 13

Definition at line 352 of file radeon_reg.h.

#define RADEON_ADAPTER_ID 0x0f2c /* PCI */

Definition at line 91 of file radeon_reg.h.

#define RADEON_AGP_1X_MODE 0x01

Definition at line 114 of file radeon_reg.h.

#define RADEON_AGP_2X_MODE 0x02

Definition at line 115 of file radeon_reg.h.

#define RADEON_AGP_4X_MODE 0x04

Definition at line 116 of file radeon_reg.h.

#define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)

Definition at line 95 of file radeon_reg.h.

#define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)

Definition at line 98 of file radeon_reg.h.

#define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)

Definition at line 94 of file radeon_reg.h.

#define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)

Definition at line 97 of file radeon_reg.h.

#define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)

Definition at line 100 of file radeon_reg.h.

#define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)

Definition at line 96 of file radeon_reg.h.

#define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)

Definition at line 99 of file radeon_reg.h.

#define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)

Definition at line 101 of file radeon_reg.h.

#define RADEON_AGP_BASE 0x0170

Definition at line 92 of file radeon_reg.h.

#define RADEON_AGP_BASE 0x0170

Definition at line 92 of file radeon_reg.h.

#define RADEON_AGP_BASE_2 0x015c /* r200+ only */

Definition at line 71 of file radeon_reg.h.

#define RADEON_AGP_CNTL 0x0174

Definition at line 93 of file radeon_reg.h.

#define RADEON_AGP_COMMAND 0x0f60 /* PCI */

Definition at line 109 of file radeon_reg.h.

#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/

Definition at line 110 of file radeon_reg.h.

#define RADEON_AGP_ENABLE (1<<8)

Definition at line 111 of file radeon_reg.h.

#define RADEON_AGP_FW_MODE 0x10

Definition at line 117 of file radeon_reg.h.

#define RADEON_AGP_MODE_MASK 0x17

Definition at line 118 of file radeon_reg.h.

#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */

Definition at line 112 of file radeon_reg.h.

#define RADEON_AGP_STATUS 0x0f5c /* PCI */

Definition at line 113 of file radeon_reg.h.

#define RADEON_AGPv3_4X_MODE 0x01

Definition at line 120 of file radeon_reg.h.

#define RADEON_AGPv3_8X_MODE 0x02

Definition at line 121 of file radeon_reg.h.

#define RADEON_AGPv3_MODE 0x08

Definition at line 119 of file radeon_reg.h.

#define RADEON_AIC_CNTL 0x01d0

Definition at line 3364 of file radeon_reg.h.

#define RADEON_AIC_HI_ADDR 0x01e0

Definition at line 3370 of file radeon_reg.h.

#define RADEON_AIC_LO_ADDR 0x01dc

Definition at line 3368 of file radeon_reg.h.

#define RADEON_AIC_PT_BASE 0x01d8

Definition at line 3369 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)

Definition at line 2187 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)

Definition at line 2188 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_A_MASK (0xf << 0)

Definition at line 2185 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_A_SHIFT 0

Definition at line 2184 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)

Definition at line 2189 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)

Definition at line 2191 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)

Definition at line 2192 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)

Definition at line 2193 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)

Definition at line 2194 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)

Definition at line 2190 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_A_ZERO (0 << 0)

Definition at line 2186 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)

Definition at line 2198 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)

Definition at line 2199 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_B_MASK (0xf << 4)

Definition at line 2196 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_B_SHIFT 4

Definition at line 2195 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)

Definition at line 2200 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)

Definition at line 2202 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)

Definition at line 2203 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)

Definition at line 2204 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)

Definition at line 2205 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)

Definition at line 2201 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_B_ZERO (0 << 4)

Definition at line 2197 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)

Definition at line 2209 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)

Definition at line 2210 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_C_MASK (0xf << 8)

Definition at line 2207 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_C_SHIFT 8

Definition at line 2206 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)

Definition at line 2211 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)

Definition at line 2213 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)

Definition at line 2214 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)

Definition at line 2215 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)

Definition at line 2216 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)

Definition at line 2212 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_C_ZERO (0 << 8)

Definition at line 2208 of file radeon_reg.h.

#define RADEON_ALPHA_ARG_MASK 0xf

Definition at line 2218 of file radeon_reg.h.

#define RADEON_ALPHA_BLEND_ENABLE (1 << 0)

Definition at line 2254 of file radeon_reg.h.

#define RADEON_ALPHA_SHADE_FLAT (1 << 10)

Definition at line 2419 of file radeon_reg.h.

#define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)

Definition at line 2420 of file radeon_reg.h.

#define RADEON_ALPHA_SHADE_MASK (3 << 10)

Definition at line 2421 of file radeon_reg.h.

#define RADEON_ALPHA_SHADE_SOLID (0 << 10)

Definition at line 2418 of file radeon_reg.h.

#define RADEON_ALPHA_TEST_ENABLE (1 << 23)

Definition at line 1884 of file radeon_reg.h.

#define RADEON_ALPHA_TEST_EQUAL (3 << 8)

Definition at line 1909 of file radeon_reg.h.

#define RADEON_ALPHA_TEST_FAIL (0 << 8)

Definition at line 1906 of file radeon_reg.h.

#define RADEON_ALPHA_TEST_GEQUAL (4 << 8)

Definition at line 1910 of file radeon_reg.h.

#define RADEON_ALPHA_TEST_GREATER (5 << 8)

Definition at line 1911 of file radeon_reg.h.

#define RADEON_ALPHA_TEST_LEQUAL (2 << 8)

Definition at line 1908 of file radeon_reg.h.

#define RADEON_ALPHA_TEST_LESS (1 << 8)

Definition at line 1907 of file radeon_reg.h.

#define RADEON_ALPHA_TEST_NEQUAL (6 << 8)

Definition at line 1912 of file radeon_reg.h.

#define RADEON_ALPHA_TEST_OP_MASK (7 << 8)

Definition at line 1914 of file radeon_reg.h.

#define RADEON_ALPHA_TEST_PASS (7 << 8)

Definition at line 1913 of file radeon_reg.h.

#define RADEON_ALT_PHASE_EN (1 << 6)

Definition at line 3603 of file radeon_reg.h.

#define RADEON_AMBIENT_SOURCE_SHIFT 18

Definition at line 2496 of file radeon_reg.h.

#define RADEON_ANTI_ALIAS_LINE (1 << 24)

Definition at line 1886 of file radeon_reg.h.

#define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)

Definition at line 1888 of file radeon_reg.h.

#define RADEON_ANTI_ALIAS_NONE (0 << 24)

Definition at line 1885 of file radeon_reg.h.

#define RADEON_ANTI_ALIAS_POLY (2 << 24)

Definition at line 1887 of file radeon_reg.h.

#define RADEON_ATTRDR 0x03c1 /* VGA */

Definition at line 122 of file radeon_reg.h.

#define RADEON_ATTRDW 0x03c0 /* VGA */

Definition at line 123 of file radeon_reg.h.

#define RADEON_ATTRX 0x03c0 /* VGA */

Definition at line 124 of file radeon_reg.h.

#define RADEON_AUD_ASYNC_RST (1 << 6)

Definition at line 3512 of file radeon_reg.h.

#define RADEON_AUTO_PWRUP_EN (1 << 26)

Definition at line 647 of file radeon_reg.h.

#define RADEON_AUX1_SC_BOTTOM 0x1670

Definition at line 135 of file radeon_reg.h.

#define RADEON_AUX1_SC_EN (1 << 0)

Definition at line 126 of file radeon_reg.h.

#define RADEON_AUX1_SC_LEFT 0x1664

Definition at line 136 of file radeon_reg.h.

#define RADEON_AUX1_SC_MODE_NAND (1 << 1)

Definition at line 128 of file radeon_reg.h.

#define RADEON_AUX1_SC_MODE_OR (0 << 1)

Definition at line 127 of file radeon_reg.h.

#define RADEON_AUX1_SC_RIGHT 0x1668

Definition at line 137 of file radeon_reg.h.

#define RADEON_AUX1_SC_TOP 0x166c

Definition at line 138 of file radeon_reg.h.

#define RADEON_AUX2_SC_BOTTOM 0x1680

Definition at line 139 of file radeon_reg.h.

#define RADEON_AUX2_SC_EN (1 << 2)

Definition at line 129 of file radeon_reg.h.

#define RADEON_AUX2_SC_LEFT 0x1674

Definition at line 140 of file radeon_reg.h.

#define RADEON_AUX2_SC_MODE_NAND (1 << 3)

Definition at line 131 of file radeon_reg.h.

#define RADEON_AUX2_SC_MODE_OR (0 << 3)

Definition at line 130 of file radeon_reg.h.

#define RADEON_AUX2_SC_RIGHT 0x1678

Definition at line 141 of file radeon_reg.h.

#define RADEON_AUX2_SC_TOP 0x167c

Definition at line 142 of file radeon_reg.h.

#define RADEON_AUX3_SC_BOTTOM 0x1690

Definition at line 143 of file radeon_reg.h.

#define RADEON_AUX3_SC_EN (1 << 4)

Definition at line 132 of file radeon_reg.h.

#define RADEON_AUX3_SC_LEFT 0x1684

Definition at line 144 of file radeon_reg.h.

#define RADEON_AUX3_SC_MODE_NAND (1 << 5)

Definition at line 134 of file radeon_reg.h.

#define RADEON_AUX3_SC_MODE_OR (0 << 5)

Definition at line 133 of file radeon_reg.h.

#define RADEON_AUX3_SC_RIGHT 0x1688

Definition at line 145 of file radeon_reg.h.

#define RADEON_AUX3_SC_TOP 0x168c

Definition at line 146 of file radeon_reg.h.

#define RADEON_AUX_SC_CNTL 0x1660

Definition at line 125 of file radeon_reg.h.

#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8

Definition at line 147 of file radeon_reg.h.

#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc

Definition at line 148 of file radeon_reg.h.

#define RADEON_B3MEM_RESET_MASK 0x6fffffff

Definition at line 1212 of file radeon_reg.h.

#define RADEON_BADVTX_CULL_DISABLE (1 << 5)

Definition at line 2409 of file radeon_reg.h.

#define RADEON_BASE_CODE 0x0f0b

Definition at line 150 of file radeon_reg.h.

#define RADEON_BFACE_CULL (0 << 1)

Definition at line 2404 of file radeon_reg.h.

#define RADEON_BFACE_SOLID (3 << 1)

Definition at line 2405 of file radeon_reg.h.

#define RADEON_BIOS_0_SCRATCH 0x0010

Definition at line 151 of file radeon_reg.h.

#define RADEON_BIOS_1_SCRATCH 0x0014

Definition at line 161 of file radeon_reg.h.

#define RADEON_BIOS_2_SCRATCH 0x0018

Definition at line 162 of file radeon_reg.h.

#define RADEON_BIOS_3_SCRATCH 0x001c

Definition at line 163 of file radeon_reg.h.

#define RADEON_BIOS_4_SCRATCH 0x0020

Definition at line 164 of file radeon_reg.h.

#define RADEON_BIOS_5_SCRATCH 0x0024

Definition at line 177 of file radeon_reg.h.

#define RADEON_BIOS_6_SCRATCH 0x0028

Definition at line 206 of file radeon_reg.h.

#define RADEON_BIOS_7_SCRATCH 0x002c

Definition at line 221 of file radeon_reg.h.

#define RADEON_BIOS_ROM 0x0f30 /* PCI */

Definition at line 224 of file radeon_reg.h.

#define RADEON_BIST 0x0f0f /* PCI */

Definition at line 225 of file radeon_reg.h.

#define RADEON_BLANK_LEVEL_SHIFT 8

Definition at line 3605 of file radeon_reg.h.

#define RADEON_BLEND_CTL_ADD (0 << 18)

Definition at line 2164 of file radeon_reg.h.

#define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)

Definition at line 2166 of file radeon_reg.h.

#define RADEON_BLEND_CTL_BLEND (3 << 18)

Definition at line 2167 of file radeon_reg.h.

#define RADEON_BLEND_CTL_DOT3 (4 << 18)

Definition at line 2168 of file radeon_reg.h.

#define RADEON_BLEND_CTL_MASK (7 << 18)

Definition at line 2163 of file radeon_reg.h.

#define RADEON_BLEND_CTL_SUBTRACT (1 << 18)

Definition at line 2165 of file radeon_reg.h.

#define RADEON_BLEND_OP_COUNT_MASK (7 << 12)

Definition at line 2649 of file radeon_reg.h.

#define RADEON_BLEND_OP_COUNT_SHIFT 12

Definition at line 2650 of file radeon_reg.h.

#define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)

Definition at line 3526 of file radeon_reg.h.

#define RADEON_BORDER_MODE_D3D (1 << 31)

Definition at line 1982 of file radeon_reg.h.

#define RADEON_BORDER_MODE_OGL (0 << 31)

Definition at line 1981 of file radeon_reg.h.

#define RADEON_BRES_CNTL_SHIFT 8

Definition at line 845 of file radeon_reg.h.

#define RADEON_BRUSH_DATA0 0x1480

Definition at line 226 of file radeon_reg.h.

#define RADEON_BRUSH_DATA1 0x1484

Definition at line 227 of file radeon_reg.h.

#define RADEON_BRUSH_DATA10 0x14a8

Definition at line 228 of file radeon_reg.h.

#define RADEON_BRUSH_DATA11 0x14ac

Definition at line 229 of file radeon_reg.h.

#define RADEON_BRUSH_DATA12 0x14b0

Definition at line 230 of file radeon_reg.h.

#define RADEON_BRUSH_DATA13 0x14b4

Definition at line 231 of file radeon_reg.h.

#define RADEON_BRUSH_DATA14 0x14b8

Definition at line 232 of file radeon_reg.h.

#define RADEON_BRUSH_DATA15 0x14bc

Definition at line 233 of file radeon_reg.h.

#define RADEON_BRUSH_DATA16 0x14c0

Definition at line 234 of file radeon_reg.h.

#define RADEON_BRUSH_DATA17 0x14c4

Definition at line 235 of file radeon_reg.h.

#define RADEON_BRUSH_DATA18 0x14c8

Definition at line 236 of file radeon_reg.h.

#define RADEON_BRUSH_DATA19 0x14cc

Definition at line 237 of file radeon_reg.h.

#define RADEON_BRUSH_DATA2 0x1488

Definition at line 238 of file radeon_reg.h.

#define RADEON_BRUSH_DATA20 0x14d0

Definition at line 239 of file radeon_reg.h.

#define RADEON_BRUSH_DATA21 0x14d4

Definition at line 240 of file radeon_reg.h.

#define RADEON_BRUSH_DATA22 0x14d8

Definition at line 241 of file radeon_reg.h.

#define RADEON_BRUSH_DATA23 0x14dc

Definition at line 242 of file radeon_reg.h.

#define RADEON_BRUSH_DATA24 0x14e0

Definition at line 243 of file radeon_reg.h.

#define RADEON_BRUSH_DATA25 0x14e4

Definition at line 244 of file radeon_reg.h.

#define RADEON_BRUSH_DATA26 0x14e8

Definition at line 245 of file radeon_reg.h.

#define RADEON_BRUSH_DATA27 0x14ec

Definition at line 246 of file radeon_reg.h.

#define RADEON_BRUSH_DATA28 0x14f0

Definition at line 247 of file radeon_reg.h.

#define RADEON_BRUSH_DATA29 0x14f4

Definition at line 248 of file radeon_reg.h.

#define RADEON_BRUSH_DATA3 0x148c

Definition at line 249 of file radeon_reg.h.

#define RADEON_BRUSH_DATA30 0x14f8

Definition at line 250 of file radeon_reg.h.

#define RADEON_BRUSH_DATA31 0x14fc

Definition at line 251 of file radeon_reg.h.

#define RADEON_BRUSH_DATA32 0x1500

Definition at line 252 of file radeon_reg.h.

#define RADEON_BRUSH_DATA33 0x1504

Definition at line 253 of file radeon_reg.h.

#define RADEON_BRUSH_DATA34 0x1508

Definition at line 254 of file radeon_reg.h.

#define RADEON_BRUSH_DATA35 0x150c

Definition at line 255 of file radeon_reg.h.

#define RADEON_BRUSH_DATA36 0x1510

Definition at line 256 of file radeon_reg.h.

#define RADEON_BRUSH_DATA37 0x1514

Definition at line 257 of file radeon_reg.h.

#define RADEON_BRUSH_DATA38 0x1518

Definition at line 258 of file radeon_reg.h.

#define RADEON_BRUSH_DATA39 0x151c

Definition at line 259 of file radeon_reg.h.

#define RADEON_BRUSH_DATA4 0x1490

Definition at line 260 of file radeon_reg.h.

#define RADEON_BRUSH_DATA40 0x1520

Definition at line 261 of file radeon_reg.h.

#define RADEON_BRUSH_DATA41 0x1524

Definition at line 262 of file radeon_reg.h.

#define RADEON_BRUSH_DATA42 0x1528

Definition at line 263 of file radeon_reg.h.

#define RADEON_BRUSH_DATA43 0x152c

Definition at line 264 of file radeon_reg.h.

#define RADEON_BRUSH_DATA44 0x1530

Definition at line 265 of file radeon_reg.h.

#define RADEON_BRUSH_DATA45 0x1534

Definition at line 266 of file radeon_reg.h.

#define RADEON_BRUSH_DATA46 0x1538

Definition at line 267 of file radeon_reg.h.

#define RADEON_BRUSH_DATA47 0x153c

Definition at line 268 of file radeon_reg.h.

#define RADEON_BRUSH_DATA48 0x1540

Definition at line 269 of file radeon_reg.h.

#define RADEON_BRUSH_DATA49 0x1544

Definition at line 270 of file radeon_reg.h.

#define RADEON_BRUSH_DATA5 0x1494

Definition at line 271 of file radeon_reg.h.

#define RADEON_BRUSH_DATA50 0x1548

Definition at line 272 of file radeon_reg.h.

#define RADEON_BRUSH_DATA51 0x154c

Definition at line 273 of file radeon_reg.h.

#define RADEON_BRUSH_DATA52 0x1550

Definition at line 274 of file radeon_reg.h.

#define RADEON_BRUSH_DATA53 0x1554

Definition at line 275 of file radeon_reg.h.

#define RADEON_BRUSH_DATA54 0x1558

Definition at line 276 of file radeon_reg.h.

#define RADEON_BRUSH_DATA55 0x155c

Definition at line 277 of file radeon_reg.h.

#define RADEON_BRUSH_DATA56 0x1560

Definition at line 278 of file radeon_reg.h.

#define RADEON_BRUSH_DATA57 0x1564

Definition at line 279 of file radeon_reg.h.

#define RADEON_BRUSH_DATA58 0x1568

Definition at line 280 of file radeon_reg.h.

#define RADEON_BRUSH_DATA59 0x156c

Definition at line 281 of file radeon_reg.h.

#define RADEON_BRUSH_DATA6 0x1498

Definition at line 282 of file radeon_reg.h.

#define RADEON_BRUSH_DATA60 0x1570

Definition at line 283 of file radeon_reg.h.

#define RADEON_BRUSH_DATA61 0x1574

Definition at line 284 of file radeon_reg.h.

#define RADEON_BRUSH_DATA62 0x1578

Definition at line 285 of file radeon_reg.h.

#define RADEON_BRUSH_DATA63 0x157c

Definition at line 286 of file radeon_reg.h.

#define RADEON_BRUSH_DATA7 0x149c

Definition at line 287 of file radeon_reg.h.

#define RADEON_BRUSH_DATA8 0x14a0

Definition at line 288 of file radeon_reg.h.

#define RADEON_BRUSH_DATA9 0x14a4

Definition at line 289 of file radeon_reg.h.

#define RADEON_BRUSH_SCALE 0x1470

Definition at line 290 of file radeon_reg.h.

#define RADEON_BRUSH_Y_X 0x1474

Definition at line 291 of file radeon_reg.h.

#define RADEON_BUF_SWAP_32BIT (2 << 16)

Definition at line 3301 of file radeon_reg.h.

#define RADEON_BUMP_MAP_ENABLE (1 << 26)

Definition at line 1889 of file radeon_reg.h.

#define RADEON_BUMPED_MAP_T0 (0 << 27)

Definition at line 1890 of file radeon_reg.h.

#define RADEON_BUMPED_MAP_T1 (1 << 27)

Definition at line 1891 of file radeon_reg.h.

#define RADEON_BUMPED_MAP_T2 (2 << 27)

Definition at line 1892 of file radeon_reg.h.

#define RADEON_BUS_BIOS_DIS_ROM (1 << 12)

Definition at line 294 of file radeon_reg.h.

#define RADEON_BUS_CNTL 0x0030

Definition at line 292 of file radeon_reg.h.

#define RADEON_BUS_CNTL1 0x0034

Definition at line 302 of file radeon_reg.h.

#define RADEON_BUS_MASTER_DIS (1 << 6)

Definition at line 293 of file radeon_reg.h.

#define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)

Definition at line 299 of file radeon_reg.h.

#define RADEON_BUS_RD_ABORT_EN (1 << 25)

Definition at line 298 of file radeon_reg.h.

#define RADEON_BUS_RD_DISCARD_EN (1 << 24)

Definition at line 297 of file radeon_reg.h.

#define RADEON_BUS_READ_BURST (1 << 30)

Definition at line 301 of file radeon_reg.h.

#define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)

Definition at line 303 of file radeon_reg.h.

#define RADEON_BUS_WRT_BURST (1 << 29)

Definition at line 300 of file radeon_reg.h.

#define RADEON_C_GRN_EN (1 << 1)

Definition at line 3521 of file radeon_reg.h.

#define RADEON_CACHE_CNTL 0x1724

Definition at line 337 of file radeon_reg.h.

#define RADEON_CACHE_LINE 0x0f0c /* PCI */

Definition at line 338 of file radeon_reg.h.

#define RADEON_CAP0_ANC2_OFFSET 0x0988

Definition at line 1472 of file radeon_reg.h.

#define RADEON_CAP0_ANC3_OFFSET 0x098C

Definition at line 1473 of file radeon_reg.h.

#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960

Definition at line 1463 of file radeon_reg.h.

#define RADEON_CAP0_ANC_H_WINDOW 0x0964

Definition at line 1464 of file radeon_reg.h.

#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C

Definition at line 1462 of file radeon_reg.h.

#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928

Definition at line 1415 of file radeon_reg.h.

#define RADEON_CAP0_BUF0_OFFSET 0x0920

Definition at line 1413 of file radeon_reg.h.

#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C

Definition at line 1416 of file radeon_reg.h.

#define RADEON_CAP0_BUF1_OFFSET 0x0924

Definition at line 1414 of file radeon_reg.h.

#define RADEON_CAP0_BUF_PITCH 0x0930

Definition at line 1418 of file radeon_reg.h.

#define RADEON_CAP0_BUF_STATUS 0x0970

Definition at line 1467 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG 0x0958

Definition at line 1428 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000

Definition at line 1441 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080

Definition at line 1436 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100

Definition at line 1437 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010

Definition at line 1433 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020

Definition at line 1434 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001

Definition at line 1429 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000

Definition at line 1447 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000

Definition at line 1445 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000

Definition at line 1452 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000

Definition at line 1453 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000

Definition at line 1456 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000

Definition at line 1455 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000

Definition at line 1454 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000

Definition at line 1457 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000

Definition at line 1448 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000

Definition at line 1449 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200

Definition at line 1438 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000

Definition at line 1446 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400

Definition at line 1439 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040

Definition at line 1435 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000

Definition at line 1443 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004

Definition at line 1431 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008

Definition at line 1432 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002

Definition at line 1430 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000

Definition at line 1460 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000

Definition at line 1461 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_VBI_EN 0x00002000

Definition at line 1442 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000

Definition at line 1450 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000

Definition at line 1451 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000

Definition at line 1459 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000

Definition at line 1458 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800

Definition at line 1440 of file radeon_reg.h.

#define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000

Definition at line 1444 of file radeon_reg.h.

#define RADEON_CAP0_DEBUG 0x0954

Definition at line 1427 of file radeon_reg.h.

#define RADEON_CAP0_H_WINDOW 0x0938

Definition at line 1420 of file radeon_reg.h.

#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C

Definition at line 1466 of file radeon_reg.h.

#define RADEON_CAP0_PORT_MODE_CNTL 0x094C

Definition at line 1425 of file radeon_reg.h.

#define RADEON_CAP0_TRIG_CNTL 0x0950

Definition at line 1426 of file radeon_reg.h.

#define RADEON_CAP0_V_WINDOW 0x0934

Definition at line 1419 of file radeon_reg.h.

#define RADEON_CAP0_VBI0_OFFSET 0x093C

Definition at line 1421 of file radeon_reg.h.

#define RADEON_CAP0_VBI1_OFFSET 0x0940

Definition at line 1422 of file radeon_reg.h.

#define RADEON_CAP0_VBI2_OFFSET 0x0980

Definition at line 1470 of file radeon_reg.h.

#define RADEON_CAP0_VBI3_OFFSET 0x0984

Definition at line 1471 of file radeon_reg.h.

#define RADEON_CAP0_VBI_H_WINDOW 0x0948

Definition at line 1424 of file radeon_reg.h.

#define RADEON_CAP0_VBI_V_WINDOW 0x0944

Definition at line 1423 of file radeon_reg.h.

#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968

Definition at line 1465 of file radeon_reg.h.

#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0

Definition at line 1495 of file radeon_reg.h.

#define RADEON_CAP1_ANC_H_WINDOW 0x09D4

Definition at line 1496 of file radeon_reg.h.

#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC

Definition at line 1494 of file radeon_reg.h.

#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998

Definition at line 1480 of file radeon_reg.h.

#define RADEON_CAP1_BUF0_OFFSET 0x0990

Definition at line 1478 of file radeon_reg.h.

#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C

Definition at line 1481 of file radeon_reg.h.

#define RADEON_CAP1_BUF1_OFFSET 0x0994

Definition at line 1479 of file radeon_reg.h.

#define RADEON_CAP1_BUF_PITCH 0x09A0

Definition at line 1483 of file radeon_reg.h.

#define RADEON_CAP1_BUF_STATUS 0x09E0

Definition at line 1499 of file radeon_reg.h.

#define RADEON_CAP1_CONFIG 0x09C8

Definition at line 1493 of file radeon_reg.h.

#define RADEON_CAP1_DEBUG 0x09C4

Definition at line 1492 of file radeon_reg.h.

#define RADEON_CAP1_DWNSC_XRATIO 0x09E8

Definition at line 1500 of file radeon_reg.h.

#define RADEON_CAP1_H_WINDOW 0x09A8

Definition at line 1485 of file radeon_reg.h.

#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC

Definition at line 1498 of file radeon_reg.h.

#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC

Definition at line 1490 of file radeon_reg.h.

#define RADEON_CAP1_TRIG_CNTL 0x09C0

Definition at line 1491 of file radeon_reg.h.

#define RADEON_CAP1_V_WINDOW 0x09A4

Definition at line 1484 of file radeon_reg.h.

#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0

Definition at line 1487 of file radeon_reg.h.

#define RADEON_CAP1_VBI_H_WINDOW 0x09B8

Definition at line 1489 of file radeon_reg.h.

#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC

Definition at line 1486 of file radeon_reg.h.

#define RADEON_CAP1_VBI_V_WINDOW 0x09B4

Definition at line 1488 of file radeon_reg.h.

#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8

Definition at line 1497 of file radeon_reg.h.

#define RADEON_CAP1_XSHARPNESS 0x09EC

Definition at line 1501 of file radeon_reg.h.

#define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */

Definition at line 107 of file radeon_reg.h.

#define RADEON_CAP_ID_EXP 0x10 /* PCI Express */

Definition at line 108 of file radeon_reg.h.

#define RADEON_CAP_ID_NULL 0x00 /* End of capability list */

Definition at line 106 of file radeon_reg.h.

#define RADEON_CAP_LIST 0x100000

Definition at line 103 of file radeon_reg.h.

#define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */

Definition at line 105 of file radeon_reg.h.

#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */

Definition at line 339 of file radeon_reg.h.

#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */

Definition at line 340 of file radeon_reg.h.

#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/

Definition at line 104 of file radeon_reg.h.

#define RADEON_CFG_ATI_REV_A11 (0 << 16)

Definition at line 383 of file radeon_reg.h.

#define RADEON_CFG_ATI_REV_A12 (1 << 16)

Definition at line 384 of file radeon_reg.h.

#define RADEON_CFG_ATI_REV_A13 (2 << 16)

Definition at line 385 of file radeon_reg.h.

#define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)

Definition at line 386 of file radeon_reg.h.

#define RADEON_CFG_VGA_IO_DIS (1 << 9)

Definition at line 382 of file radeon_reg.h.

#define RADEON_CFG_VGA_RAM_EN (1 << 8)

Definition at line 381 of file radeon_reg.h.

#define RADEON_CG_NO1_DEBUG_0 (1 << 24)

Definition at line 356 of file radeon_reg.h.

#define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)

Definition at line 357 of file radeon_reg.h.

#define RADEON_CHROMA_FUNC_EQUAL (3 << 16)

Definition at line 1918 of file radeon_reg.h.

#define RADEON_CHROMA_FUNC_FAIL (0 << 16)

Definition at line 1915 of file radeon_reg.h.

#define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)

Definition at line 1917 of file radeon_reg.h.

#define RADEON_CHROMA_FUNC_PASS (1 << 16)

Definition at line 1916 of file radeon_reg.h.

#define RADEON_CHROMA_KEY_NEAREST (0 << 18)

Definition at line 1919 of file radeon_reg.h.

#define RADEON_CHROMA_KEY_ZERO (1 << 18)

Definition at line 1920 of file radeon_reg.h.

#define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)

Definition at line 1966 of file radeon_reg.h.

#define RADEON_CLAMP_S_CLAMP_GL (6 << 23)

Definition at line 1968 of file radeon_reg.h.

#define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)

Definition at line 1964 of file radeon_reg.h.

#define RADEON_CLAMP_S_MASK (7 << 23)

Definition at line 1970 of file radeon_reg.h.

#define RADEON_CLAMP_S_MIRROR (1 << 23)

Definition at line 1963 of file radeon_reg.h.

#define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)

Definition at line 1967 of file radeon_reg.h.

#define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)

Definition at line 1969 of file radeon_reg.h.

#define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)

Definition at line 1965 of file radeon_reg.h.

#define RADEON_CLAMP_S_WRAP (0 << 23)

Definition at line 1962 of file radeon_reg.h.

#define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)

Definition at line 1976 of file radeon_reg.h.

#define RADEON_CLAMP_T_CLAMP_GL (6 << 27)

Definition at line 1978 of file radeon_reg.h.

#define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)

Definition at line 1974 of file radeon_reg.h.

#define RADEON_CLAMP_T_MASK (7 << 27)

Definition at line 1980 of file radeon_reg.h.

#define RADEON_CLAMP_T_MIRROR (1 << 27)

Definition at line 1973 of file radeon_reg.h.

#define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)

Definition at line 1977 of file radeon_reg.h.

#define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)

Definition at line 1979 of file radeon_reg.h.

#define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)

Definition at line 1975 of file radeon_reg.h.

#define RADEON_CLAMP_T_WRAP (0 << 27)

Definition at line 1972 of file radeon_reg.h.

#define RADEON_CLAMP_TX (1 << 23)

Definition at line 2174 of file radeon_reg.h.

#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */

Definition at line 341 of file radeon_reg.h.

#define RADEON_CLK_PWRMGT_CNTL 0x0014

Definition at line 349 of file radeon_reg.h.

#define RADEON_CLOCK_CNTL_DATA 0x000c

Definition at line 344 of file radeon_reg.h.

#define RADEON_CLOCK_CNTL_INDEX 0x0008

Definition at line 345 of file radeon_reg.h.

#define RADEON_CLR_CMP_CLR_3D 0x1a24

Definition at line 364 of file radeon_reg.h.

#define RADEON_CLR_CMP_CLR_DST 0x15c8

Definition at line 365 of file radeon_reg.h.

#define RADEON_CLR_CMP_CLR_SRC 0x15c4

Definition at line 366 of file radeon_reg.h.

#define RADEON_CLR_CMP_CNTL 0x15c0

Definition at line 367 of file radeon_reg.h.

#define RADEON_CLR_CMP_MASK 0x15cc

Definition at line 371 of file radeon_reg.h.

#define RADEON_CLR_CMP_MASK_3D 0x1A28

Definition at line 373 of file radeon_reg.h.

#define RADEON_CLR_CMP_MSK 0xffffffff

Definition at line 372 of file radeon_reg.h.

#define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)

Definition at line 370 of file radeon_reg.h.

#define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)

Definition at line 2277 of file radeon_reg.h.

#define RADEON_CMDFIFO_ENTRIES_MASK 0x7f

Definition at line 1849 of file radeon_reg.h.

#define RADEON_CMDFIFO_ENTRIES_SHIFT 10

Definition at line 1848 of file radeon_reg.h.

#define RADEON_CMP_BLU_EN (1 << 2)

Definition at line 3522 of file radeon_reg.h.

#define RADEON_CMP_MIX_AND 0x00000100L

Definition at line 1318 of file radeon_reg.h.

#define RADEON_CMP_MIX_MASK 0x00000100L

Definition at line 1316 of file radeon_reg.h.

#define RADEON_CMP_MIX_OR 0x00000000L

Definition at line 1317 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)

Definition at line 2104 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)

Definition at line 2103 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)

Definition at line 2106 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)

Definition at line 2105 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_MASK (0x1f << 0)

Definition at line 2101 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_SHIFT 0

Definition at line 2100 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)

Definition at line 2108 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)

Definition at line 2107 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)

Definition at line 2112 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)

Definition at line 2111 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)

Definition at line 2114 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)

Definition at line 2113 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)

Definition at line 2116 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)

Definition at line 2115 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)

Definition at line 2118 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)

Definition at line 2117 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)

Definition at line 2110 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)

Definition at line 2109 of file radeon_reg.h.

#define RADEON_COLOR_ARG_A_ZERO (0 << 0)

Definition at line 2102 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)

Definition at line 2123 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)

Definition at line 2122 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)

Definition at line 2125 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)

Definition at line 2124 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_MASK (0x1f << 5)

Definition at line 2120 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_SHIFT 5

Definition at line 2119 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)

Definition at line 2127 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)

Definition at line 2126 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)

Definition at line 2131 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)

Definition at line 2130 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)

Definition at line 2133 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)

Definition at line 2132 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)

Definition at line 2135 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)

Definition at line 2134 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)

Definition at line 2137 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)

Definition at line 2136 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)

Definition at line 2129 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)

Definition at line 2128 of file radeon_reg.h.

#define RADEON_COLOR_ARG_B_ZERO (0 << 5)

Definition at line 2121 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)

Definition at line 2142 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)

Definition at line 2141 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)

Definition at line 2144 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)

Definition at line 2143 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_MASK (0x1f << 10)

Definition at line 2139 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_SHIFT 10

Definition at line 2138 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)

Definition at line 2146 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)

Definition at line 2145 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)

Definition at line 2150 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)

Definition at line 2149 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)

Definition at line 2152 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)

Definition at line 2151 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)

Definition at line 2154 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)

Definition at line 2153 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)

Definition at line 2156 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)

Definition at line 2155 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)

Definition at line 2148 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)

Definition at line 2147 of file radeon_reg.h.

#define RADEON_COLOR_ARG_C_ZERO (0 << 10)

Definition at line 2140 of file radeon_reg.h.

#define RADEON_COLOR_ARG_MASK 0x1f

Definition at line 2179 of file radeon_reg.h.

#define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)

Definition at line 2286 of file radeon_reg.h.

#define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)

Definition at line 2284 of file radeon_reg.h.

#define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)

Definition at line 2285 of file radeon_reg.h.

#define RADEON_COLOR_FORMAT_ARGB1555 3

Definition at line 2266 of file radeon_reg.h.

#define RADEON_COLOR_FORMAT_ARGB4444 15

Definition at line 2275 of file radeon_reg.h.

#define RADEON_COLOR_FORMAT_ARGB8888 6

Definition at line 2268 of file radeon_reg.h.

#define RADEON_COLOR_FORMAT_aYUV444 14

Definition at line 2274 of file radeon_reg.h.

#define RADEON_COLOR_FORMAT_RGB332 7

Definition at line 2269 of file radeon_reg.h.

#define RADEON_COLOR_FORMAT_RGB565 4

Definition at line 2267 of file radeon_reg.h.

#define RADEON_COLOR_FORMAT_RGB8 9

Definition at line 2271 of file radeon_reg.h.

#define RADEON_COLOR_FORMAT_Y8 8

Definition at line 2270 of file radeon_reg.h.

#define RADEON_COLOR_FORMAT_YUV422_VYUY 11

Definition at line 2272 of file radeon_reg.h.

#define RADEON_COLOR_FORMAT_YUV422_YVYU 12

Definition at line 2273 of file radeon_reg.h.

#define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)

Definition at line 2283 of file radeon_reg.h.

#define RADEON_COLOR_TILE_ENABLE (1 << 16)

Definition at line 2282 of file radeon_reg.h.

#define RADEON_COLOROFFSET_MASK 0xfffffff0

Definition at line 2279 of file radeon_reg.h.

#define RADEON_COLORPITCH_MASK 0x000001ff8

Definition at line 2281 of file radeon_reg.h.

#define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)

Definition at line 2226 of file radeon_reg.h.

#define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)

Definition at line 2227 of file radeon_reg.h.

#define RADEON_COMB_FCN_MASK (3 << 12)

Definition at line 2225 of file radeon_reg.h.

#define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)

Definition at line 2228 of file radeon_reg.h.

#define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)

Definition at line 2229 of file radeon_reg.h.

#define RADEON_COMMAND 0x0f04 /* PCI */

Definition at line 374 of file radeon_reg.h.

#define RADEON_COMP_ARG_A (1 << 15)

Definition at line 2157 of file radeon_reg.h.

#define RADEON_COMP_ARG_A_SHIFT 15

Definition at line 2158 of file radeon_reg.h.

#define RADEON_COMP_ARG_B (1 << 16)

Definition at line 2159 of file radeon_reg.h.

#define RADEON_COMP_ARG_B_SHIFT 16

Definition at line 2160 of file radeon_reg.h.

#define RADEON_COMP_ARG_C (1 << 17)

Definition at line 2161 of file radeon_reg.h.

#define RADEON_COMP_ARG_C_SHIFT 17

Definition at line 2162 of file radeon_reg.h.

#define RADEON_COMP_ARG_SHIFT 15

Definition at line 2180 of file radeon_reg.h.

#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c

Definition at line 375 of file radeon_reg.h.

#define RADEON_CONFIG_APER_0_BASE 0x0100

Definition at line 376 of file radeon_reg.h.

#define RADEON_CONFIG_APER_1_BASE 0x0104

Definition at line 377 of file radeon_reg.h.

#define RADEON_CONFIG_APER_SIZE 0x0108

Definition at line 378 of file radeon_reg.h.

#define RADEON_CONFIG_BONDS 0x00e8

Definition at line 379 of file radeon_reg.h.

#define RADEON_CONFIG_CNTL 0x00e0

Definition at line 380 of file radeon_reg.h.

#define RADEON_CONFIG_MEMSIZE 0x00f8

Definition at line 387 of file radeon_reg.h.

#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114

Definition at line 388 of file radeon_reg.h.

#define RADEON_CONFIG_REG_1_BASE 0x010c

Definition at line 389 of file radeon_reg.h.

#define RADEON_CONFIG_REG_APER_SIZE 0x0110

Definition at line 390 of file radeon_reg.h.

#define RADEON_CONFIG_XSTRAP 0x00e4

Definition at line 391 of file radeon_reg.h.

#define RADEON_CONSTANT_COLOR_C 0x1d34

Definition at line 392 of file radeon_reg.h.

#define RADEON_CONSTANT_COLOR_MASK 0x00ffffff

Definition at line 393 of file radeon_reg.h.

#define RADEON_CONSTANT_COLOR_ONE 0x00ffffff

Definition at line 394 of file radeon_reg.h.

#define RADEON_CONSTANT_COLOR_ZERO 0x00000000

Definition at line 395 of file radeon_reg.h.

#define RADEON_CP_CSQ2_STAT 0x07fc

Definition at line 3349 of file radeon_reg.h.

#define RADEON_CP_CSQ_ADDR 0x07f0

Definition at line 3350 of file radeon_reg.h.

#define RADEON_CP_CSQ_APER_INDIRECT 0x1300

Definition at line 3353 of file radeon_reg.h.

#define RADEON_CP_CSQ_APER_PRIMARY 0x1000

Definition at line 3352 of file radeon_reg.h.

#define RADEON_CP_CSQ_CNTL 0x0740

Definition at line 3332 of file radeon_reg.h.

#define RADEON_CP_CSQ_DATA 0x07f4

Definition at line 3351 of file radeon_reg.h.

#define RADEON_CP_CSQ_MODE 0x0744

Definition at line 3358 of file radeon_reg.h.

#define RADEON_CP_CSQ_STAT 0x07f8

Definition at line 3344 of file radeon_reg.h.

#define RADEON_CP_IB_BASE 0x0738

Definition at line 3329 of file radeon_reg.h.

#define RADEON_CP_IB_BUFSZ 0x073c

Definition at line 3330 of file radeon_reg.h.

#define RADEON_CP_MAX_DYN_STOP_LAT 0x0008

Definition at line 1665 of file radeon_reg.h.

#define RADEON_CP_ME_RAM_ADDR 0x07d4

Definition at line 3290 of file radeon_reg.h.

#define RADEON_CP_ME_RAM_DATAH 0x07dc

Definition at line 3292 of file radeon_reg.h.

#define RADEON_CP_ME_RAM_DATAL 0x07e0

Definition at line 3293 of file radeon_reg.h.

#define RADEON_CP_ME_RAM_RADDR 0x07d8

Definition at line 3291 of file radeon_reg.h.

#define RADEON_CP_PACKET0 0x00000000

Definition at line 3381 of file radeon_reg.h.

#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000

Definition at line 3394 of file radeon_reg.h.

#define RADEON_CP_PACKET0_REG_MASK 0x000007ff

Definition at line 3388 of file radeon_reg.h.

#define RADEON_CP_PACKET1 0x40000000

Definition at line 3382 of file radeon_reg.h.

#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff

Definition at line 3391 of file radeon_reg.h.

#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800

Definition at line 3392 of file radeon_reg.h.

#define RADEON_CP_PACKET2 0x80000000

Definition at line 3383 of file radeon_reg.h.

#define RADEON_CP_PACKET3 0xC0000000

Definition at line 3384 of file radeon_reg.h.

#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900

Definition at line 3404 of file radeon_reg.h.

#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00

Definition at line 3405 of file radeon_reg.h.

#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800

Definition at line 3403 of file radeon_reg.h.

#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00

Definition at line 3408 of file radeon_reg.h.

#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300

Definition at line 3400 of file radeon_reg.h.

#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200

Definition at line 3410 of file radeon_reg.h.

#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00

Definition at line 3416 of file radeon_reg.h.

#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400

Definition at line 3412 of file radeon_reg.h.

#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100

Definition at line 3409 of file radeon_reg.h.

#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00

Definition at line 3415 of file radeon_reg.h.

#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500

Definition at line 3413 of file radeon_reg.h.

#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800

Definition at line 3414 of file radeon_reg.h.

#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300

Definition at line 3411 of file radeon_reg.h.

#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00

Definition at line 3417 of file radeon_reg.h.

#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400

Definition at line 3401 of file radeon_reg.h.

#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00

Definition at line 3406 of file radeon_reg.h.

#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900

Definition at line 3397 of file radeon_reg.h.

#define RADEON_CP_PACKET3_NOP 0xC0001000

Definition at line 3396 of file radeon_reg.h.

#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00

Definition at line 3398 of file radeon_reg.h.

#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00

Definition at line 3399 of file radeon_reg.h.

#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600

Definition at line 3402 of file radeon_reg.h.

#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000

Definition at line 3386 of file radeon_reg.h.

#define RADEON_CP_PACKET_MASK 0xC0000000

Definition at line 3385 of file radeon_reg.h.

#define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)

Definition at line 3387 of file radeon_reg.h.

#define RADEON_CP_RB_BASE 0x0700

Definition at line 3295 of file radeon_reg.h.

#define RADEON_CP_RB_CNTL 0x0704

Definition at line 3296 of file radeon_reg.h.

#define RADEON_CP_RB_RPTR 0x0710

Definition at line 3307 of file radeon_reg.h.

#define RADEON_CP_RB_RPTR_ADDR 0x070c

Definition at line 3306 of file radeon_reg.h.

#define RADEON_CP_RB_RPTR_WR 0x071c

Definition at line 3309 of file radeon_reg.h.

#define RADEON_CP_RB_WPTR 0x0714

Definition at line 3308 of file radeon_reg.h.

#define RADEON_CP_RB_WPTR_DELAY 0x0718

Definition at line 3355 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000

Definition at line 3458 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040

Definition at line 3459 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080

Definition at line 3460 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_NUM_SHIFT 16

Definition at line 3465 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a

Definition at line 3454 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009

Definition at line 3453 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002

Definition at line 3446 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003

Definition at line 3447 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000

Definition at line 3444 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001

Definition at line 3445 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008

Definition at line 3452 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005

Definition at line 3449 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004

Definition at line 3448 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006

Definition at line 3450 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007

Definition at line 3451 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010

Definition at line 3455 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020

Definition at line 3456 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030

Definition at line 3457 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000

Definition at line 3463 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200

Definition at line 3464 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000

Definition at line 3461 of file radeon_reg.h.

#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100

Definition at line 3462 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000

Definition at line 3436 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004

Definition at line 3423 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002

Definition at line 3422 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_FPFOG 0x00000020

Definition at line 3426 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010

Definition at line 3425 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_N0 0x00040000

Definition at line 3437 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_N1 0x40000000

Definition at line 3441 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008

Definition at line 3424 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040

Definition at line 3427 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_Q0 0x00004000

Definition at line 3435 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_Q1 0x00000200

Definition at line 3430 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_Q2 0x00000800

Definition at line 3432 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_Q3 0x00002000

Definition at line 3434 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_ST0 0x00000080

Definition at line 3428 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_ST1 0x00000100

Definition at line 3429 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_ST2 0x00000400

Definition at line 3431 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_ST3 0x00001000

Definition at line 3433 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_W0 0x00000001

Definition at line 3421 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_W1 0x20000000

Definition at line 3440 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_XY 0x00000000

Definition at line 3420 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_XY1 0x08000000

Definition at line 3438 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_Z 0x80000000

Definition at line 3442 of file radeon_reg.h.

#define RADEON_CP_VC_FRMT_Z1 0x10000000

Definition at line 3439 of file radeon_reg.h.

#define RADEON_CRC_CMDFIFO_ADDR 0x0740

Definition at line 396 of file radeon_reg.h.

#define RADEON_CRC_CMDFIFO_DOUT 0x0744

Definition at line 397 of file radeon_reg.h.

#define RADEON_CRT1_ATTACHED_COLOR (2 << 0)

Definition at line 167 of file radeon_reg.h.

#define RADEON_CRT1_ATTACHED_MASK (3 << 0)

Definition at line 165 of file radeon_reg.h.

#define RADEON_CRT1_ATTACHED_MONO (1 << 0)

Definition at line 166 of file radeon_reg.h.

#define RADEON_CRT1_CRTC_MASK (1 << 9)

Definition at line 187 of file radeon_reg.h.

#define RADEON_CRT1_CRTC_SHIFT 9

Definition at line 188 of file radeon_reg.h.

#define RADEON_CRT1_ON (1 << 1)

Definition at line 179 of file radeon_reg.h.

#define RADEON_CRT2_ATTACHED_COLOR (2 << 8)

Definition at line 175 of file radeon_reg.h.

#define RADEON_CRT2_ATTACHED_MASK (3 << 8)

Definition at line 173 of file radeon_reg.h.

#define RADEON_CRT2_ATTACHED_MONO (1 << 8)

Definition at line 174 of file radeon_reg.h.

#define RADEON_CRT2_CRTC_MASK (1 << 12)

Definition at line 193 of file radeon_reg.h.

#define RADEON_CRT2_CRTC_SHIFT 12

Definition at line 194 of file radeon_reg.h.

#define RADEON_CRT2_DISP1_SEL (1 << 5)

Definition at line 676 of file radeon_reg.h.

#define RADEON_CRT2_ON (1 << 5)

Definition at line 182 of file radeon_reg.h.

#define RADEON_CRT_ASYNC_RST (1 << 1)

Definition at line 3508 of file radeon_reg.h.

#define RADEON_CRT_DPMS_ON (1 << 21)

Definition at line 210 of file radeon_reg.h.

#define RADEON_CRT_FIFO_CE_EN (1 << 9)

Definition at line 3514 of file radeon_reg.h.

#define RADEON_CRTC2_CRNT_FRAME 0x0314

Definition at line 574 of file radeon_reg.h.

#define RADEON_CRTC2_CRT2_ON (1 << 7)

Definition at line 454 of file radeon_reg.h.

#define RADEON_CRTC2_CSYNC_EN (1 << 27)

Definition at line 463 of file radeon_reg.h.

#define RADEON_CRTC2_CUR_EN (1 << 16)

Definition at line 458 of file radeon_reg.h.

#define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)

Definition at line 459 of file radeon_reg.h.

#define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)

Definition at line 449 of file radeon_reg.h.

#define RADEON_CRTC2_DISP_DIS (1 << 23)

Definition at line 460 of file radeon_reg.h.

#define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)

Definition at line 462 of file radeon_reg.h.

#define RADEON_CRTC2_EN (1 << 25)

Definition at line 461 of file radeon_reg.h.

#define RADEON_CRTC2_GEN_CNTL 0x03f8

Definition at line 448 of file radeon_reg.h.

#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318

Definition at line 575 of file radeon_reg.h.

#define RADEON_CRTC2_H_DISP (0x01ff << 16)

Definition at line 494 of file radeon_reg.h.

#define RADEON_CRTC2_H_DISP_SHIFT 16

Definition at line 495 of file radeon_reg.h.

#define RADEON_CRTC2_H_SYNC_POL (1 << 23)

Definition at line 485 of file radeon_reg.h.

#define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)

Definition at line 481 of file radeon_reg.h.

#define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3

Definition at line 482 of file radeon_reg.h.

#define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)

Definition at line 480 of file radeon_reg.h.

#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304

Definition at line 479 of file radeon_reg.h.

#define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)

Definition at line 483 of file radeon_reg.h.

#define RADEON_CRTC2_H_SYNC_WID_SHIFT 16

Definition at line 484 of file radeon_reg.h.

#define RADEON_CRTC2_H_TOTAL (0x03ff << 0)

Definition at line 492 of file radeon_reg.h.

#define RADEON_CRTC2_H_TOTAL_DISP 0x0300

Definition at line 491 of file radeon_reg.h.

#define RADEON_CRTC2_H_TOTAL_SHIFT 0

Definition at line 493 of file radeon_reg.h.

#define RADEON_CRTC2_HSYNC_DIS (1 << 28)

Definition at line 464 of file radeon_reg.h.

#define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)

Definition at line 452 of file radeon_reg.h.

#define RADEON_CRTC2_ICON_EN (1 << 15)

Definition at line 457 of file radeon_reg.h.

#define RADEON_CRTC2_INTERLACE_EN (1 << 1)

Definition at line 450 of file radeon_reg.h.

#define RADEON_CRTC2_OFFSET 0x0324

Definition at line 502 of file radeon_reg.h.

#define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)

Definition at line 503 of file radeon_reg.h.

#define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)

Definition at line 504 of file radeon_reg.h.

#define RADEON_CRTC2_OFFSET_CNTL 0x0328

Definition at line 534 of file radeon_reg.h.

#define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)

Definition at line 535 of file radeon_reg.h.

#define RADEON_CRTC2_PITCH 0x032c

Definition at line 541 of file radeon_reg.h.

#define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)

Definition at line 456 of file radeon_reg.h.

#define RADEON_CRTC2_PIX_WIDTH_SHIFT 8

Definition at line 455 of file radeon_reg.h.

#define RADEON_CRTC2_STATUS 0x03fc

Definition at line 546 of file radeon_reg.h.

#define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)

Definition at line 451 of file radeon_reg.h.

#define RADEON_CRTC2_TILE_EN (1 << 15)

Definition at line 536 of file radeon_reg.h.

#define RADEON_CRTC2_V_DISP (0x07ff << 16)

Definition at line 570 of file radeon_reg.h.

#define RADEON_CRTC2_V_DISP_SHIFT 16

Definition at line 571 of file radeon_reg.h.

#define RADEON_CRTC2_V_SYNC_POL (1 << 23)

Definition at line 561 of file radeon_reg.h.

#define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)

Definition at line 557 of file radeon_reg.h.

#define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0

Definition at line 558 of file radeon_reg.h.

#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c

Definition at line 556 of file radeon_reg.h.

#define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)

Definition at line 559 of file radeon_reg.h.

#define RADEON_CRTC2_V_SYNC_WID_SHIFT 16

Definition at line 560 of file radeon_reg.h.

#define RADEON_CRTC2_V_TOTAL (0x07ff << 0)

Definition at line 568 of file radeon_reg.h.

#define RADEON_CRTC2_V_TOTAL_DISP 0x0308

Definition at line 567 of file radeon_reg.h.

#define RADEON_CRTC2_V_TOTAL_SHIFT 0

Definition at line 569 of file radeon_reg.h.

#define RADEON_CRTC2_VBLANK_CUR (1 << 0)

Definition at line 547 of file radeon_reg.h.

#define RADEON_CRTC2_VBLANK_MASK (1 << 9)

Definition at line 1015 of file radeon_reg.h.

#define RADEON_CRTC2_VBLANK_SAVE (1 << 1)

Definition at line 548 of file radeon_reg.h.

#define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)

Definition at line 549 of file radeon_reg.h.

#define RADEON_CRTC2_VBLANK_STAT (1 << 9)

Definition at line 1025 of file radeon_reg.h.

#define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)

Definition at line 1026 of file radeon_reg.h.

#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310

Definition at line 576 of file radeon_reg.h.

#define RADEON_CRTC2_VSYNC_DIS (1 << 29)

Definition at line 465 of file radeon_reg.h.

#define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)

Definition at line 453 of file radeon_reg.h.

#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */

Definition at line 577 of file radeon_reg.h.

#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */

Definition at line 578 of file radeon_reg.h.

#define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)

Definition at line 467 of file radeon_reg.h.

#define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)

Definition at line 468 of file radeon_reg.h.

#define RADEON_CRTC_CRNT_FRAME 0x0214

Definition at line 420 of file radeon_reg.h.

#define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)

Definition at line 573 of file radeon_reg.h.

#define RADEON_CRTC_CRT_ON (1 << 15)

Definition at line 429 of file radeon_reg.h.

#define RADEON_CRTC_CSYNC_EN (1 << 4)

Definition at line 437 of file radeon_reg.h.

#define RADEON_CRTC_CUR_EN (1 << 16)

Definition at line 439 of file radeon_reg.h.

#define RADEON_CRTC_CUR_MODE_24BPP 2

Definition at line 444 of file radeon_reg.h.

#define RADEON_CRTC_CUR_MODE_MASK (7 << 20)

Definition at line 441 of file radeon_reg.h.

#define RADEON_CRTC_CUR_MODE_MONO 0

Definition at line 443 of file radeon_reg.h.

#define RADEON_CRTC_CUR_MODE_SHIFT 20

Definition at line 442 of file radeon_reg.h.

#define RADEON_CRTC_DBL_SCAN_EN (1 << 0)

Definition at line 435 of file radeon_reg.h.

#define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)

Definition at line 447 of file radeon_reg.h.

#define RADEON_CRTC_DISPLAY_DIS (1 << 10)

Definition at line 427 of file radeon_reg.h.

#define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)

Definition at line 433 of file radeon_reg.h.

#define RADEON_CRTC_EN (1 << 25)

Definition at line 446 of file radeon_reg.h.

#define RADEON_CRTC_EXT_CNTL 0x0054

Definition at line 421 of file radeon_reg.h.

#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055

Definition at line 430 of file radeon_reg.h.

#define RADEON_CRTC_EXT_DISP_EN (1 << 24)

Definition at line 445 of file radeon_reg.h.

#define RADEON_CRTC_GEN_CNTL 0x0050

Definition at line 434 of file radeon_reg.h.

#define RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN (1 << 28)

Definition at line 528 of file radeon_reg.h.

#define RADEON_CRTC_GUI_TRIG_OFFSET_RIGHT_EN (1 << 29)

Definition at line 529 of file radeon_reg.h.

#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218

Definition at line 471 of file radeon_reg.h.

#define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)

Definition at line 469 of file radeon_reg.h.

#define RADEON_CRTC_H_DISP (0x01ff << 16)

Definition at line 489 of file radeon_reg.h.

#define RADEON_CRTC_H_DISP_SHIFT 16

Definition at line 490 of file radeon_reg.h.

#define RADEON_CRTC_H_SYNC_POL (1 << 23)

Definition at line 478 of file radeon_reg.h.

#define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)

Definition at line 474 of file radeon_reg.h.

#define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3

Definition at line 475 of file radeon_reg.h.

#define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)

Definition at line 473 of file radeon_reg.h.

#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204

Definition at line 472 of file radeon_reg.h.

#define RADEON_CRTC_H_SYNC_WID (0x3f << 16)

Definition at line 476 of file radeon_reg.h.

#define RADEON_CRTC_H_SYNC_WID_SHIFT 16

Definition at line 477 of file radeon_reg.h.

#define RADEON_CRTC_H_TOTAL (0x03ff << 0)

Definition at line 487 of file radeon_reg.h.

#define RADEON_CRTC_H_TOTAL_DISP 0x0200

Definition at line 486 of file radeon_reg.h.

#define RADEON_CRTC_H_TOTAL_SHIFT 0

Definition at line 488 of file radeon_reg.h.

#define RADEON_CRTC_HSYNC_DIS (1 << 8)

Definition at line 425 of file radeon_reg.h.

#define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)

Definition at line 431 of file radeon_reg.h.

#define RADEON_CRTC_ICON_EN (1 << 15)

Definition at line 438 of file radeon_reg.h.

#define RADEON_CRTC_INTERLACE_EN (1 << 1)

Definition at line 436 of file radeon_reg.h.

#define RADEON_CRTC_MORE_CNTL 0x27c

Definition at line 466 of file radeon_reg.h.

#define RADEON_CRTC_OFFSET 0x0224

Definition at line 498 of file radeon_reg.h.

#define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)

Definition at line 499 of file radeon_reg.h.

#define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)

Definition at line 500 of file radeon_reg.h.

#define RADEON_CRTC_OFFSET_CNTL 0x0228

Definition at line 505 of file radeon_reg.h.

#define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)

Definition at line 526 of file radeon_reg.h.

#define RADEON_CRTC_OFFSET_RIGHT 0x0220

Definition at line 497 of file radeon_reg.h.

#define RADEON_CRTC_PITCH 0x022c

Definition at line 537 of file radeon_reg.h.

#define RADEON_CRTC_PITCH__RIGHT_SHIFT 16

Definition at line 539 of file radeon_reg.h.

#define RADEON_CRTC_PITCH__SHIFT 0

Definition at line 538 of file radeon_reg.h.

#define RADEON_CRTC_STATUS 0x005c

Definition at line 542 of file radeon_reg.h.

#define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)

Definition at line 527 of file radeon_reg.h.

#define RADEON_CRTC_SYNC_TRISTAT (1 << 11)

Definition at line 428 of file radeon_reg.h.

#define RADEON_CRTC_TILE_EN (1 << 15)

Definition at line 525 of file radeon_reg.h.

#define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)

Definition at line 524 of file radeon_reg.h.

#define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4

Definition at line 507 of file radeon_reg.h.

#define RADEON_CRTC_TILE_LINE_SHIFT 0

Definition at line 506 of file radeon_reg.h.

#define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)

Definition at line 470 of file radeon_reg.h.

#define RADEON_CRTC_V_DISP (0x07ff << 16)

Definition at line 565 of file radeon_reg.h.

#define RADEON_CRTC_V_DISP_SHIFT 16

Definition at line 566 of file radeon_reg.h.

#define RADEON_CRTC_V_SYNC_POL (1 << 23)

Definition at line 555 of file radeon_reg.h.

#define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)

Definition at line 551 of file radeon_reg.h.

#define RADEON_CRTC_V_SYNC_STRT_SHIFT 0

Definition at line 552 of file radeon_reg.h.

#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c

Definition at line 550 of file radeon_reg.h.

#define RADEON_CRTC_V_SYNC_WID (0x1f << 16)

Definition at line 553 of file radeon_reg.h.

#define RADEON_CRTC_V_SYNC_WID_SHIFT 16

Definition at line 554 of file radeon_reg.h.

#define RADEON_CRTC_V_TOTAL (0x07ff << 0)

Definition at line 563 of file radeon_reg.h.

#define RADEON_CRTC_V_TOTAL_DISP 0x0208

Definition at line 562 of file radeon_reg.h.

#define RADEON_CRTC_V_TOTAL_SHIFT 0

Definition at line 564 of file radeon_reg.h.

#define RADEON_CRTC_VBLANK_CUR (1 << 0)

Definition at line 543 of file radeon_reg.h.

#define RADEON_CRTC_VBLANK_MASK (1 << 0)

Definition at line 1013 of file radeon_reg.h.

#define RADEON_CRTC_VBLANK_SAVE (1 << 1)

Definition at line 544 of file radeon_reg.h.

#define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)

Definition at line 545 of file radeon_reg.h.

#define RADEON_CRTC_VBLANK_STAT (1 << 0)

Definition at line 1021 of file radeon_reg.h.

#define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)

Definition at line 1022 of file radeon_reg.h.

#define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)

Definition at line 422 of file radeon_reg.h.

#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210

Definition at line 572 of file radeon_reg.h.

#define RADEON_CRTC_VSTAT_MODE_MASK (3 << 17)

Definition at line 440 of file radeon_reg.h.

#define RADEON_CRTC_VSYNC_DIS (1 << 9)

Definition at line 426 of file radeon_reg.h.

#define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)

Definition at line 432 of file radeon_reg.h.

#define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)

Definition at line 3333 of file radeon_reg.h.

#define RADEON_CSQ_PRIBM_INDBM (4 << 28)

Definition at line 3338 of file radeon_reg.h.

#define RADEON_CSQ_PRIBM_INDDIS (2 << 28)

Definition at line 3336 of file radeon_reg.h.

#define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)

Definition at line 3334 of file radeon_reg.h.

#define RADEON_CSQ_PRIPIO_INDBM (3 << 28)

Definition at line 3337 of file radeon_reg.h.

#define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)

Definition at line 3335 of file radeon_reg.h.

#define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)

Definition at line 3339 of file radeon_reg.h.

#define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)

Definition at line 3347 of file radeon_reg.h.

#define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)

Definition at line 3345 of file radeon_reg.h.

#define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)

Definition at line 3348 of file radeon_reg.h.

#define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)

Definition at line 3346 of file radeon_reg.h.

#define RADEON_CULL_BACK (1 << 30)

Definition at line 2665 of file radeon_reg.h.

#define RADEON_CULL_FRONT (1 << 29)

Definition at line 2664 of file radeon_reg.h.

#define RADEON_CULL_FRONT_IS_CCW (1 << 28)

Definition at line 2663 of file radeon_reg.h.

#define RADEON_CULL_FRONT_IS_CW (0 << 28)

Definition at line 2662 of file radeon_reg.h.

#define RADEON_CUR2_CLR0 0x036c

Definition at line 585 of file radeon_reg.h.

#define RADEON_CUR2_CLR1 0x0370

Definition at line 586 of file radeon_reg.h.

#define RADEON_CUR2_HORZ_VERT_OFF 0x0368

Definition at line 587 of file radeon_reg.h.

#define RADEON_CUR2_HORZ_VERT_POSN 0x0364

Definition at line 588 of file radeon_reg.h.

#define RADEON_CUR2_LOCK (1 << 31)

Definition at line 590 of file radeon_reg.h.

#define RADEON_CUR2_OFFSET 0x0360

Definition at line 589 of file radeon_reg.h.

#define RADEON_CUR_CLR0 0x026c

Definition at line 579 of file radeon_reg.h.

#define RADEON_CUR_CLR1 0x0270

Definition at line 580 of file radeon_reg.h.

#define RADEON_CUR_HORZ_VERT_OFF 0x0268

Definition at line 581 of file radeon_reg.h.

#define RADEON_CUR_HORZ_VERT_POSN 0x0264

Definition at line 582 of file radeon_reg.h.

#define RADEON_CUR_LOCK (1 << 31)

Definition at line 584 of file radeon_reg.h.

#define RADEON_CUR_OFFSET 0x0260

Definition at line 583 of file radeon_reg.h.

#define RADEON_CV1_CRTC_MASK (1 << 13)

Definition at line 195 of file radeon_reg.h.

#define RADEON_CV1_CRTC_SHIFT 13

Definition at line 196 of file radeon_reg.h.

#define RADEON_CV1_ON (1 << 6)

Definition at line 183 of file radeon_reg.h.

#define RADEON_CY_FILT_BLEND_SHIFT 28

Definition at line 3608 of file radeon_reg.h.

#define RADEON_DAC2_CMP_EN (1 << 7)

Definition at line 609 of file radeon_reg.h.

#define RADEON_DAC2_CMP_OUT_B (1 << 10)

Definition at line 612 of file radeon_reg.h.

#define RADEON_DAC2_CMP_OUT_G (1 << 9)

Definition at line 611 of file radeon_reg.h.

#define RADEON_DAC2_CMP_OUT_R (1 << 8)

Definition at line 610 of file radeon_reg.h.

#define RADEON_DAC2_CMP_OUTPUT (1 << 11)

Definition at line 613 of file radeon_reg.h.

#define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)

Definition at line 607 of file radeon_reg.h.

#define RADEON_DAC2_DAC_CLK_SEL (1 << 0)

Definition at line 606 of file radeon_reg.h.

#define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)

Definition at line 615 of file radeon_reg.h.

#define RADEON_DAC2_FORCE_DATA_EN (1 << 1)

Definition at line 616 of file radeon_reg.h.

#define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)

Definition at line 608 of file radeon_reg.h.

#define RADEON_DAC2_TV_CLK_SEL (0 << 1)

Definition at line 605 of file radeon_reg.h.

#define RADEON_DAC_8BIT_EN (1 << 8)

Definition at line 599 of file radeon_reg.h.

#define RADEON_DAC_BLANKING (1 << 2)

Definition at line 596 of file radeon_reg.h.

#define RADEON_DAC_CMP_EN (1 << 3)

Definition at line 597 of file radeon_reg.h.

#define RADEON_DAC_CMP_OUTPUT (1 << 7)

Definition at line 598 of file radeon_reg.h.

#define RADEON_DAC_CNTL 0x0058

Definition at line 592 of file radeon_reg.h.

#define RADEON_DAC_CNTL2 0x007c

Definition at line 604 of file radeon_reg.h.

#define RADEON_DAC_CRC_SIG 0x02cc

Definition at line 698 of file radeon_reg.h.

#define RADEON_DAC_DATA 0x03c9 /* VGA */

Definition at line 699 of file radeon_reg.h.

#define RADEON_DAC_DITHER_EN (1 << 3)

Definition at line 3523 of file radeon_reg.h.

#define RADEON_DAC_EXT_CNTL 0x0280

Definition at line 614 of file radeon_reg.h.

#define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)

Definition at line 617 of file radeon_reg.h.

#define RADEON_DAC_FORCE_DATA_EN (1 << 5)

Definition at line 618 of file radeon_reg.h.

#define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00

Definition at line 624 of file radeon_reg.h.

#define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)

Definition at line 622 of file radeon_reg.h.

#define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)

Definition at line 621 of file radeon_reg.h.

#define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)

Definition at line 619 of file radeon_reg.h.

#define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)

Definition at line 620 of file radeon_reg.h.

#define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)

Definition at line 623 of file radeon_reg.h.

#define RADEON_DAC_FORCE_DATA_SHIFT 8

Definition at line 625 of file radeon_reg.h.

#define RADEON_DAC_MACRO_CNTL 0x0d04

Definition at line 626 of file radeon_reg.h.

#define RADEON_DAC_MASK 0x03c6 /* VGA */

Definition at line 700 of file radeon_reg.h.

#define RADEON_DAC_MASK_ALL (0xff << 24)

Definition at line 603 of file radeon_reg.h.

#define RADEON_DAC_PDWN (1 << 15)

Definition at line 602 of file radeon_reg.h.

#define RADEON_DAC_PDWN_B (1 << 18)

Definition at line 629 of file radeon_reg.h.

#define RADEON_DAC_PDWN_G (1 << 17)

Definition at line 628 of file radeon_reg.h.

#define RADEON_DAC_PDWN_R (1 << 16)

Definition at line 627 of file radeon_reg.h.

#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */

Definition at line 701 of file radeon_reg.h.

#define RADEON_DAC_RANGE_CNTL (3 << 0)

Definition at line 593 of file radeon_reg.h.

#define RADEON_DAC_RANGE_CNTL_MASK 0x03

Definition at line 595 of file radeon_reg.h.

#define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)

Definition at line 594 of file radeon_reg.h.

#define RADEON_DAC_TVO_EN (1 << 10)

Definition at line 600 of file radeon_reg.h.

#define RADEON_DAC_VGA_ADR_EN (1 << 13)

Definition at line 601 of file radeon_reg.h.

#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */

Definition at line 702 of file radeon_reg.h.

#define RADEON_DDA_CONFIG 0x02e0

Definition at line 703 of file radeon_reg.h.

#define RADEON_DDA_ON_OFF 0x02e4

Definition at line 704 of file radeon_reg.h.

#define RADEON_DEFAULT_OFFSET 0x16e0

Definition at line 705 of file radeon_reg.h.

#define RADEON_DEFAULT_PITCH 0x16e4

Definition at line 706 of file radeon_reg.h.

#define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)

Definition at line 709 of file radeon_reg.h.

#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8

Definition at line 707 of file radeon_reg.h.

#define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)

Definition at line 708 of file radeon_reg.h.

#define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)

Definition at line 2292 of file radeon_reg.h.

#define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)

Definition at line 2290 of file radeon_reg.h.

#define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)

Definition at line 2291 of file radeon_reg.h.

#define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)

Definition at line 2326 of file radeon_reg.h.

#define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)

Definition at line 2321 of file radeon_reg.h.

#define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)

Definition at line 2327 of file radeon_reg.h.

#define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)

Definition at line 2323 of file radeon_reg.h.

#define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)

Definition at line 2322 of file radeon_reg.h.

#define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)

Definition at line 2328 of file radeon_reg.h.

#define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)

Definition at line 2325 of file radeon_reg.h.

#define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)

Definition at line 2324 of file radeon_reg.h.

#define RADEON_DEPTH_FORMAT_MASK (0xf << 0)

Definition at line 2320 of file radeon_reg.h.

#define RADEON_DEPTHPITCH_MASK 0x00001ff8

Definition at line 2289 of file radeon_reg.h.

#define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9)

Definition at line 2263 of file radeon_reg.h.

#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824

Definition at line 711 of file radeon_reg.h.

#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820

Definition at line 710 of file radeon_reg.h.

#define RADEON_DEVICE_ID 0x0f02 /* PCI */

Definition at line 712 of file radeon_reg.h.

#define RADEON_DFP1_ATTACHED (1 << 3)

Definition at line 169 of file radeon_reg.h.

#define RADEON_DFP1_CRTC_MASK (1 << 11)

Definition at line 191 of file radeon_reg.h.

#define RADEON_DFP1_CRTC_SHIFT 11

Definition at line 192 of file radeon_reg.h.

#define RADEON_DFP1_ON (1 << 3)

Definition at line 181 of file radeon_reg.h.

#define RADEON_DFP2_ATTACHED (1 << 11)

Definition at line 176 of file radeon_reg.h.

#define RADEON_DFP2_CRTC_MASK (1 << 14)

Definition at line 197 of file radeon_reg.h.

#define RADEON_DFP2_CRTC_SHIFT 14

Definition at line 198 of file radeon_reg.h.

#define RADEON_DFP2_ON (1 << 7)

Definition at line 184 of file radeon_reg.h.

#define RADEON_DFP_DPMS_ON (1 << 23)

Definition at line 212 of file radeon_reg.h.

#define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)

Definition at line 2415 of file radeon_reg.h.

#define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)

Definition at line 2416 of file radeon_reg.h.

#define RADEON_DIFFUSE_SHADE_MASK (3 << 8)

Definition at line 2417 of file radeon_reg.h.

#define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)

Definition at line 2414 of file radeon_reg.h.

#define RADEON_DIFFUSE_SOURCE_SHIFT 20

Definition at line 2497 of file radeon_reg.h.

#define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)

Definition at line 2487 of file radeon_reg.h.

#define RADEON_DIG_TMDS_ENABLE_RST (1 << 24)

Definition at line 645 of file radeon_reg.h.

#define RADEON_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1)

Definition at line 3366 of file radeon_reg.h.

#define RADEON_DISP2_MERGE_CNTL 0x0d68

Definition at line 724 of file radeon_reg.h.

#define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)

Definition at line 725 of file radeon_reg.h.

#define RADEON_DISP_ALPHA_MODE_GLOBAL 2

Definition at line 719 of file radeon_reg.h.

#define RADEON_DISP_ALPHA_MODE_KEY 0

Definition at line 717 of file radeon_reg.h.

#define RADEON_DISP_ALPHA_MODE_MASK 0x03

Definition at line 716 of file radeon_reg.h.

#define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1

Definition at line 718 of file radeon_reg.h.

#define RADEON_DISP_D1D2_GRPH_RST (1 << 21)

Definition at line 642 of file radeon_reg.h.

#define RADEON_DISP_D1D2_OV0_RST (1 << 23)

Definition at line 644 of file radeon_reg.h.

#define RADEON_DISP_D1D2_SUBPIC_RST (1 << 22)

Definition at line 643 of file radeon_reg.h.

#define RADEON_DISP_D3_GRPH_RST (1 << 18)

Definition at line 639 of file radeon_reg.h.

#define RADEON_DISP_D3_OV0_RST (1 << 20)

Definition at line 641 of file radeon_reg.h.

#define RADEON_DISP_D3_REG_RST (1 << 17)

Definition at line 638 of file radeon_reg.h.

#define RADEON_DISP_D3_RST (1 << 16)

Definition at line 637 of file radeon_reg.h.

#define RADEON_DISP_D3_SUBPIC_RST (1 << 19)

Definition at line 640 of file radeon_reg.h.

#define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04

Definition at line 683 of file radeon_reg.h.

#define RADEON_DISP_DAC2_SOURCE_MASK 0x0c

Definition at line 679 of file radeon_reg.h.

#define RADEON_DISP_DAC_SOURCE_CRTC2 0x01

Definition at line 680 of file radeon_reg.h.

#define RADEON_DISP_DAC_SOURCE_LTU 0x03

Definition at line 682 of file radeon_reg.h.

#define RADEON_DISP_DAC_SOURCE_MASK 0x03

Definition at line 678 of file radeon_reg.h.

#define RADEON_DISP_DAC_SOURCE_RMX 0x02

Definition at line 681 of file radeon_reg.h.

#define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)

Definition at line 353 of file radeon_reg.h.

#define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)

Definition at line 721 of file radeon_reg.h.

#define RADEON_DISP_HW_DEBUG 0x0d14

Definition at line 675 of file radeon_reg.h.

#define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)

Definition at line 723 of file radeon_reg.h.

#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80

Definition at line 726 of file radeon_reg.h.

#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84

Definition at line 727 of file radeon_reg.h.

#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88

Definition at line 728 of file radeon_reg.h.

#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c

Definition at line 729 of file radeon_reg.h.

#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90

Definition at line 730 of file radeon_reg.h.

#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98

Definition at line 731 of file radeon_reg.h.

#define RADEON_DISP_MERGE_CNTL 0x0d60

Definition at line 715 of file radeon_reg.h.

#define RADEON_DISP_MISC_CNTL 0x0d00

Definition at line 713 of file radeon_reg.h.

#define RADEON_DISP_OUTPUT_CNTL 0x0d64

Definition at line 677 of file radeon_reg.h.

#define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)

Definition at line 722 of file radeon_reg.h.

#define RADEON_DISP_PWR_MAN 0x0d08

Definition at line 630 of file radeon_reg.h.

#define RADEON_DISP_PWR_MAN_D3_CRTC2_EN (1 << 4)

Definition at line 632 of file radeon_reg.h.

#define RADEON_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)

Definition at line 631 of file radeon_reg.h.

#define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8)

Definition at line 636 of file radeon_reg.h.

#define RADEON_DISP_PWR_MAN_DPMS_ON (0 << 8)

Definition at line 633 of file radeon_reg.h.

#define RADEON_DISP_PWR_MAN_DPMS_STANDBY (1 << 8)

Definition at line 634 of file radeon_reg.h.

#define RADEON_DISP_PWR_MAN_DPMS_SUSPEND (2 << 8)

Definition at line 635 of file radeon_reg.h.

#define RADEON_DISP_RGB_OFFSET_EN (1 << 8)

Definition at line 720 of file radeon_reg.h.

#define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)

Definition at line 690 of file radeon_reg.h.

#define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)

Definition at line 691 of file radeon_reg.h.

#define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)

Definition at line 689 of file radeon_reg.h.

#define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)

Definition at line 692 of file radeon_reg.h.

#define RADEON_DISP_TV_OUT_CNTL 0x0d6c

Definition at line 695 of file radeon_reg.h.

#define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)

Definition at line 697 of file radeon_reg.h.

#define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)

Definition at line 696 of file radeon_reg.h.

#define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */

Definition at line 693 of file radeon_reg.h.

#define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */

Definition at line 694 of file radeon_reg.h.

#define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0

Definition at line 685 of file radeon_reg.h.

#define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)

Definition at line 686 of file radeon_reg.h.

#define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)

Definition at line 688 of file radeon_reg.h.

#define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)

Definition at line 684 of file radeon_reg.h.

#define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)

Definition at line 687 of file radeon_reg.h.

#define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)

Definition at line 1541 of file radeon_reg.h.

#define RADEON_DISPLAY2_BASE_ADDR 0x33c

Definition at line 1166 of file radeon_reg.h.

#define RADEON_DISPLAY_BASE_ADDR 0x23c

Definition at line 1165 of file radeon_reg.h.

#define RADEON_DISPLAY_ROT_00 (0 << 28)

Definition at line 157 of file radeon_reg.h.

#define RADEON_DISPLAY_ROT_180 (2 << 28)

Definition at line 159 of file radeon_reg.h.

#define RADEON_DISPLAY_ROT_270 (3 << 28)

Definition at line 160 of file radeon_reg.h.

#define RADEON_DISPLAY_ROT_90 (1 << 28)

Definition at line 158 of file radeon_reg.h.

#define RADEON_DISPLAY_ROT_MASK (3 << 28)

Definition at line 156 of file radeon_reg.h.

#define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)

Definition at line 220 of file radeon_reg.h.

#define RADEON_DITHER_ENABLE (1 << 2)

Definition at line 2256 of file radeon_reg.h.

#define RADEON_DITHER_INIT (1 << 5)

Definition at line 2259 of file radeon_reg.h.

#define RADEON_DITHER_MODE (1 << 0)

Definition at line 3581 of file radeon_reg.h.

#define RADEON_DLL_READY (1 << 19)

Definition at line 355 of file radeon_reg.h.

#define RADEON_DONT_USE_XTALIN (1 << 4)

Definition at line 342 of file radeon_reg.h.

#define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)

Definition at line 2217 of file radeon_reg.h.

#define RADEON_DP_BRUSH_BKGD_CLR 0x1478

Definition at line 732 of file radeon_reg.h.

#define RADEON_DP_BRUSH_FRGD_CLR 0x147c

Definition at line 733 of file radeon_reg.h.

#define RADEON_DP_CNTL 0x16c0

Definition at line 734 of file radeon_reg.h.

#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0

Definition at line 741 of file radeon_reg.h.

#define RADEON_DP_DATATYPE 0x16c4

Definition at line 745 of file radeon_reg.h.

#define RADEON_DP_DST_TILE_BOTH (3 << 3)

Definition at line 740 of file radeon_reg.h.

#define RADEON_DP_DST_TILE_LINEAR (0 << 3)

Definition at line 737 of file radeon_reg.h.

#define RADEON_DP_DST_TILE_MACRO (1 << 3)

Definition at line 738 of file radeon_reg.h.

#define RADEON_DP_DST_TILE_MICRO (2 << 3)

Definition at line 739 of file radeon_reg.h.

#define RADEON_DP_GUI_MASTER_CNTL 0x146c

Definition at line 747 of file radeon_reg.h.

#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84

Definition at line 827 of file radeon_reg.h.

#define RADEON_DP_MIX 0x16c8

Definition at line 828 of file radeon_reg.h.

#define RADEON_DP_SRC_BKGD_CLR 0x15dc

Definition at line 829 of file radeon_reg.h.

#define RADEON_DP_SRC_FRGD_CLR 0x15d8

Definition at line 830 of file radeon_reg.h.

#define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)

Definition at line 792 of file radeon_reg.h.

#define RADEON_DP_SRC_SOURCE_MASK (7 << 24)

Definition at line 790 of file radeon_reg.h.

#define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)

Definition at line 791 of file radeon_reg.h.

#define RADEON_DP_WRITE_MASK 0x16cc

Definition at line 831 of file radeon_reg.h.

#define RADEON_DPMS_MASK (3 << 24)

Definition at line 213 of file radeon_reg.h.

#define RADEON_DPMS_OFF (3 << 24)

Definition at line 217 of file radeon_reg.h.

#define RADEON_DPMS_ON (0 << 24)

Definition at line 214 of file radeon_reg.h.

#define RADEON_DPMS_STANDBY (1 << 24)

Definition at line 215 of file radeon_reg.h.

#define RADEON_DPMS_SUSPEND (2 << 24)

Definition at line 216 of file radeon_reg.h.

#define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)

Definition at line 155 of file radeon_reg.h.

#define RADEON_DRIVER_CRITICAL (1 << 27)

Definition at line 219 of file radeon_reg.h.

#define RADEON_DRV_LOADED (1 << 12)

Definition at line 223 of file radeon_reg.h.

#define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)

Definition at line 2250 of file radeon_reg.h.

#define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)

Definition at line 2246 of file radeon_reg.h.

#define RADEON_DST_BLEND_GL_ONE (33 << 24)

Definition at line 2243 of file radeon_reg.h.

#define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)

Definition at line 2251 of file radeon_reg.h.

#define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)

Definition at line 2247 of file radeon_reg.h.

#define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)

Definition at line 2249 of file radeon_reg.h.

#define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)

Definition at line 2245 of file radeon_reg.h.

#define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)

Definition at line 2248 of file radeon_reg.h.

#define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)

Definition at line 2244 of file radeon_reg.h.

#define RADEON_DST_BLEND_GL_ZERO (32 << 24)

Definition at line 2242 of file radeon_reg.h.

#define RADEON_DST_BLEND_MASK (63 << 24)

Definition at line 2252 of file radeon_reg.h.

#define RADEON_DST_BRES_DEC 0x1630

Definition at line 832 of file radeon_reg.h.

#define RADEON_DST_BRES_ERR 0x1628

Definition at line 833 of file radeon_reg.h.

#define RADEON_DST_BRES_INC 0x162c

Definition at line 834 of file radeon_reg.h.

#define RADEON_DST_BRES_LNTH 0x1634

Definition at line 835 of file radeon_reg.h.

#define RADEON_DST_BRES_LNTH_SUB 0x1638

Definition at line 836 of file radeon_reg.h.

#define RADEON_DST_HEIGHT 0x1410

Definition at line 837 of file radeon_reg.h.

#define RADEON_DST_HEIGHT_WIDTH 0x143c

Definition at line 838 of file radeon_reg.h.

#define RADEON_DST_HEIGHT_WIDTH_8 0x158c

Definition at line 839 of file radeon_reg.h.

#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4

Definition at line 840 of file radeon_reg.h.

#define RADEON_DST_HEIGHT_Y 0x15a0

Definition at line 841 of file radeon_reg.h.

#define RADEON_DST_LINE_END 0x1604

Definition at line 843 of file radeon_reg.h.

#define RADEON_DST_LINE_PATCOUNT 0x1608

Definition at line 844 of file radeon_reg.h.

#define RADEON_DST_LINE_START 0x1600

Definition at line 842 of file radeon_reg.h.

#define RADEON_DST_OFFSET 0x1404

Definition at line 846 of file radeon_reg.h.

#define RADEON_DST_PITCH 0x1408

Definition at line 847 of file radeon_reg.h.

#define RADEON_DST_PITCH_OFFSET 0x142c

Definition at line 848 of file radeon_reg.h.

#define RADEON_DST_PITCH_OFFSET_C 0x1c80

Definition at line 849 of file radeon_reg.h.

#define RADEON_DST_TILE_BOTH (3 << 30)

Definition at line 854 of file radeon_reg.h.

#define RADEON_DST_TILE_LINEAR (0 << 30)

Definition at line 851 of file radeon_reg.h.

#define RADEON_DST_TILE_MACRO (1 << 30)

Definition at line 852 of file radeon_reg.h.

#define RADEON_DST_TILE_MICRO (2 << 30)

Definition at line 853 of file radeon_reg.h.

#define RADEON_DST_WIDTH 0x140c

Definition at line 855 of file radeon_reg.h.

#define RADEON_DST_WIDTH_HEIGHT 0x1598

Definition at line 856 of file radeon_reg.h.

#define RADEON_DST_WIDTH_X 0x1588

Definition at line 857 of file radeon_reg.h.

#define RADEON_DST_WIDTH_X_INCY 0x159c

Definition at line 858 of file radeon_reg.h.

#define RADEON_DST_X 0x141c

Definition at line 859 of file radeon_reg.h.

#define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)

Definition at line 744 of file radeon_reg.h.

#define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)

Definition at line 735 of file radeon_reg.h.

#define RADEON_DST_X_SUB 0x15a4

Definition at line 860 of file radeon_reg.h.

#define RADEON_DST_X_Y 0x1594

Definition at line 861 of file radeon_reg.h.

#define RADEON_DST_Y 0x1420

Definition at line 862 of file radeon_reg.h.

#define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)

Definition at line 743 of file radeon_reg.h.

#define RADEON_DST_Y_MAJOR (1 << 2)

Definition at line 742 of file radeon_reg.h.

#define RADEON_DST_Y_SUB 0x15a8

Definition at line 863 of file radeon_reg.h.

#define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)

Definition at line 736 of file radeon_reg.h.

#define RADEON_DST_Y_X 0x1438

Definition at line 864 of file radeon_reg.h.

#define RADEON_DSTCACHE_CTLSTAT 0x1714

Definition at line 1606 of file radeon_reg.h.

#define RADEON_DVI_I2C_CNTL_0 0x02e0

Definition at line 1107 of file radeon_reg.h.

#define RADEON_DVI_I2C_CNTL_1 0x02e4

Definition at line 1118 of file radeon_reg.h.

#define RADEON_DVI_I2C_DATA 0x02e8

Definition at line 1119 of file radeon_reg.h.

#define RADEON_DVS_ASYNC_RST (1 << 7)

Definition at line 3513 of file radeon_reg.h.

#define RADEON_DYN_STOP_LAT_MASK 0x00007ff8

Definition at line 1664 of file radeon_reg.h.

#define RADEON_DYN_STOP_MODE_MASK (7 << 21)

Definition at line 358 of file radeon_reg.h.

#define RADEON_EMISSIVE_SOURCE_SHIFT 16

Definition at line 2495 of file radeon_reg.h.

#define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)

Definition at line 1852 of file radeon_reg.h.

#define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)

Definition at line 1853 of file radeon_reg.h.

#define RADEON_ENGIN_DYNCLK_MODE (1 << 12)

Definition at line 350 of file radeon_reg.h.

#define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000

Definition at line 1264 of file radeon_reg.h.

#define RADEON_EXCL_HORZ_END_MASK 0x0000ff00

Definition at line 1263 of file radeon_reg.h.

#define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000

Definition at line 1265 of file radeon_reg.h.

#define RADEON_EXCL_HORZ_START_MASK 0x000000ff

Definition at line 1262 of file radeon_reg.h.

#define RADEON_EXCL_VERT_END_MASK 0x03ff0000

Definition at line 1268 of file radeon_reg.h.

#define RADEON_EXCL_VERT_START_MASK 0x000003ff

Definition at line 1267 of file radeon_reg.h.

#define RADEON_EXT_DESKTOP_MODE (1 << 3)

Definition at line 208 of file radeon_reg.h.

#define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)

Definition at line 2036 of file radeon_reg.h.

#define RADEON_FACE_HEIGHT_1_SHIFT 4

Definition at line 2034 of file radeon_reg.h.

#define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)

Definition at line 2040 of file radeon_reg.h.

#define RADEON_FACE_HEIGHT_2_SHIFT 12

Definition at line 2038 of file radeon_reg.h.

#define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)

Definition at line 2044 of file radeon_reg.h.

#define RADEON_FACE_HEIGHT_3_SHIFT 20

Definition at line 2042 of file radeon_reg.h.

#define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)

Definition at line 2048 of file radeon_reg.h.

#define RADEON_FACE_HEIGHT_4_SHIFT 28

Definition at line 2046 of file radeon_reg.h.

#define RADEON_FACE_WIDTH_1_MASK (0xf << 0)

Definition at line 2035 of file radeon_reg.h.

#define RADEON_FACE_WIDTH_1_SHIFT 0

Definition at line 2033 of file radeon_reg.h.

#define RADEON_FACE_WIDTH_2_MASK (0xf << 8)

Definition at line 2039 of file radeon_reg.h.

#define RADEON_FACE_WIDTH_2_SHIFT 8

Definition at line 2037 of file radeon_reg.h.

#define RADEON_FACE_WIDTH_3_MASK (0xf << 16)

Definition at line 2043 of file radeon_reg.h.

#define RADEON_FACE_WIDTH_3_SHIFT 16

Definition at line 2041 of file radeon_reg.h.

#define RADEON_FACE_WIDTH_4_MASK (0xf << 24)

Definition at line 2047 of file radeon_reg.h.

#define RADEON_FACE_WIDTH_4_SHIFT 24

Definition at line 2045 of file radeon_reg.h.

#define RADEON_FCP0_SRC_GND 4

Definition at line 871 of file radeon_reg.h.

#define RADEON_FCP0_SRC_HREF 3

Definition at line 870 of file radeon_reg.h.

#define RADEON_FCP0_SRC_HREFb 5

Definition at line 872 of file radeon_reg.h.

#define RADEON_FCP0_SRC_PCICLK 0

Definition at line 867 of file radeon_reg.h.

#define RADEON_FCP0_SRC_PCLK 1

Definition at line 868 of file radeon_reg.h.

#define RADEON_FCP0_SRC_PCLKb 2

Definition at line 869 of file radeon_reg.h.

#define RADEON_FCP_CNTL 0x0910

Definition at line 866 of file radeon_reg.h.

#define RADEON_FFACE_CULL (0 << 3)

Definition at line 2406 of file radeon_reg.h.

#define RADEON_FFACE_CULL_CCW (1 << 0)

Definition at line 2402 of file radeon_reg.h.

#define RADEON_FFACE_CULL_CW (0 << 0)

Definition at line 2401 of file radeon_reg.h.

#define RADEON_FFACE_CULL_DIR_MASK (1 << 0)

Definition at line 2403 of file radeon_reg.h.

#define RADEON_FFACE_CULL_MASK (3 << 3)

Definition at line 2408 of file radeon_reg.h.

#define RADEON_FFACE_SOLID (3 << 3)

Definition at line 2407 of file radeon_reg.h.

#define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20

Definition at line 3537 of file radeon_reg.h.

#define RADEON_FILTER_COEF_MASK 0xf

Definition at line 1276 of file radeon_reg.h.

#define RADEON_FILTER_HARDCODED_COEF 0xf

Definition at line 1275 of file radeon_reg.h.

#define RADEON_FILTER_HC_COEF_HORZ_UV 0x2

Definition at line 1272 of file radeon_reg.h.

#define RADEON_FILTER_HC_COEF_HORZ_Y 0x1

Definition at line 1271 of file radeon_reg.h.

#define RADEON_FILTER_HC_COEF_VERT_UV 0x8

Definition at line 1274 of file radeon_reg.h.

#define RADEON_FILTER_HC_COEF_VERT_Y 0x4

Definition at line 1273 of file radeon_reg.h.

#define RADEON_FILTER_PROGRAMMABLE_COEF 0x0

Definition at line 1270 of file radeon_reg.h.

#define RADEON_FLAT_SHADE_VTX_0 (0 << 6)

Definition at line 2410 of file radeon_reg.h.

#define RADEON_FLAT_SHADE_VTX_1 (1 << 6)

Definition at line 2411 of file radeon_reg.h.

#define RADEON_FLAT_SHADE_VTX_2 (2 << 6)

Definition at line 2412 of file radeon_reg.h.

#define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)

Definition at line 2413 of file radeon_reg.h.

#define RADEON_FLUSH_1 0x1704

Definition at line 873 of file radeon_reg.h.

#define RADEON_FLUSH_2 0x1708

Definition at line 874 of file radeon_reg.h.

#define RADEON_FLUSH_3 0x170c

Definition at line 875 of file radeon_reg.h.

#define RADEON_FLUSH_4 0x1710

Definition at line 876 of file radeon_reg.h.

#define RADEON_FLUSH_5 0x1714

Definition at line 877 of file radeon_reg.h.

#define RADEON_FLUSH_6 0x1718

Definition at line 878 of file radeon_reg.h.

#define RADEON_FLUSH_7 0x171c

Definition at line 879 of file radeon_reg.h.

#define RADEON_FOG_3D_TABLE_DENSITY 0x181c

Definition at line 882 of file radeon_reg.h.

#define RADEON_FOG_3D_TABLE_END 0x1814

Definition at line 881 of file radeon_reg.h.

#define RADEON_FOG_3D_TABLE_START 0x1810

Definition at line 880 of file radeon_reg.h.

#define RADEON_FOG_COLOR_MASK 0x00ffffff

Definition at line 1897 of file radeon_reg.h.

#define RADEON_FOG_ENABLE (1 << 22)

Definition at line 1883 of file radeon_reg.h.

#define RADEON_FOG_SHADE_FLAT (1 << 14)

Definition at line 2427 of file radeon_reg.h.

#define RADEON_FOG_SHADE_GOURAUD (2 << 14)

Definition at line 2428 of file radeon_reg.h.

#define RADEON_FOG_SHADE_MASK (3 << 14)

Definition at line 2429 of file radeon_reg.h.

#define RADEON_FOG_SHADE_SOLID (0 << 14)

Definition at line 2426 of file radeon_reg.h.

#define RADEON_FOG_TABLE (1 << 24)

Definition at line 1899 of file radeon_reg.h.

#define RADEON_FOG_TABLE_DATA 0x1a18

Definition at line 884 of file radeon_reg.h.

#define RADEON_FOG_TABLE_INDEX 0x1a14

Definition at line 883 of file radeon_reg.h.

#define RADEON_FOG_USE_DEPTH (0 << 25)

Definition at line 1900 of file radeon_reg.h.

#define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)

Definition at line 1901 of file radeon_reg.h.

#define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)

Definition at line 1902 of file radeon_reg.h.

#define RADEON_FOG_VERTEX (0 << 24)

Definition at line 1898 of file radeon_reg.h.

#define RADEON_FORCE_BURST_ALWAYS (1 << 21)

Definition at line 3577 of file radeon_reg.h.

#define RADEON_FORCE_W_TO_ONE (1 << 31)

Definition at line 2666 of file radeon_reg.h.

#define RADEON_FORCE_Z_DIRTY (1 << 29)

Definition at line 2369 of file radeon_reg.h.

#define RADEON_FORCEON_AIC (1 << 21)

Definition at line 1181 of file radeon_reg.h.

#define RADEON_FORCEON_MC (1 << 20)

Definition at line 1180 of file radeon_reg.h.

#define RADEON_FORCEON_MCLKA (1 << 16)

Definition at line 1176 of file radeon_reg.h.

#define RADEON_FORCEON_MCLKB (1 << 17)

Definition at line 1177 of file radeon_reg.h.

#define RADEON_FORCEON_YCLKA (1 << 18)

Definition at line 1178 of file radeon_reg.h.

#define RADEON_FORCEON_YCLKB (1 << 19)

Definition at line 1179 of file radeon_reg.h.

#define RADEON_FP2_BLANK_EN (1 << 1)

Definition at line 930 of file radeon_reg.h.

#define RADEON_FP2_CRC_EN (1 << 23)

Definition at line 947 of file radeon_reg.h.

#define RADEON_FP2_CRC_READ_EN (1 << 24)

Definition at line 948 of file radeon_reg.h.

#define RADEON_FP2_DETECT_INT_POL (1 << 9)

Definition at line 934 of file radeon_reg.h.

#define RADEON_FP2_DETECT_MASK (1 << 10)

Definition at line 1016 of file radeon_reg.h.

#define RADEON_FP2_DETECT_SENSE (1 << 8)

Definition at line 933 of file radeon_reg.h.

#define RADEON_FP2_DETECT_STAT (1 << 10)

Definition at line 1027 of file radeon_reg.h.

#define RADEON_FP2_DETECT_STAT_ACK (1 << 10)

Definition at line 1028 of file radeon_reg.h.

#define RADEON_FP2_DVO_EN (1 << 25)

Definition at line 949 of file radeon_reg.h.

#define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)

Definition at line 950 of file radeon_reg.h.

#define RADEON_FP2_FP_POL (1 << 16)

Definition at line 942 of file radeon_reg.h.

#define RADEON_FP2_GEN_CNTL 0x0288

Definition at line 929 of file radeon_reg.h.

#define RADEON_FP2_LCD_CNTL_MASK (7 << 19)

Definition at line 945 of file radeon_reg.h.

#define RADEON_FP2_LP_POL (1 << 17)

Definition at line 943 of file radeon_reg.h.

#define RADEON_FP2_ON (1 << 2)

Definition at line 931 of file radeon_reg.h.

#define RADEON_FP2_PAD_FLOP_EN (1 << 22)

Definition at line 946 of file radeon_reg.h.

#define RADEON_FP2_PANEL_FORMAT (1 << 3)

Definition at line 932 of file radeon_reg.h.

#define RADEON_FP2_SCK_POL (1 << 18)

Definition at line 944 of file radeon_reg.h.

#define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)

Definition at line 941 of file radeon_reg.h.

#define RADEON_FP2_SRC_SEL_MASK (3 << 13)

Definition at line 940 of file radeon_reg.h.

#define RADEON_FP_BLANK_EN (1 << 1)

Definition at line 905 of file radeon_reg.h.

#define RADEON_FP_CHIP_SCALE_EN (1 << 18)

Definition at line 154 of file radeon_reg.h.

#define RADEON_FP_CRT_SYNC_ALT (1 << 26)

Definition at line 928 of file radeon_reg.h.

#define RADEON_FP_CRT_SYNC_SEL (1 << 23)

Definition at line 926 of file radeon_reg.h.

#define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)

Definition at line 921 of file radeon_reg.h.

#define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)

Definition at line 919 of file radeon_reg.h.

#define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)

Definition at line 920 of file radeon_reg.h.

#define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000

Definition at line 888 of file radeon_reg.h.

#define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010

Definition at line 896 of file radeon_reg.h.

#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250

Definition at line 885 of file radeon_reg.h.

#define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff

Definition at line 887 of file radeon_reg.h.

#define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000

Definition at line 895 of file radeon_reg.h.

#define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)

Definition at line 925 of file radeon_reg.h.

#define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)

Definition at line 922 of file radeon_reg.h.

#define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000

Definition at line 890 of file radeon_reg.h.

#define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010

Definition at line 898 of file radeon_reg.h.

#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254

Definition at line 886 of file radeon_reg.h.

#define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff

Definition at line 889 of file radeon_reg.h.

#define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000

Definition at line 897 of file radeon_reg.h.

#define RADEON_FP_DETECT_INT_POL (1 << 9)

Definition at line 910 of file radeon_reg.h.

#define RADEON_FP_DETECT_MASK (1 << 4)

Definition at line 1014 of file radeon_reg.h.

#define RADEON_FP_DETECT_SENSE (1 << 8)

Definition at line 909 of file radeon_reg.h.

#define RADEON_FP_DETECT_STAT (1 << 4)

Definition at line 1023 of file radeon_reg.h.

#define RADEON_FP_DETECT_STAT_ACK (1 << 4)

Definition at line 1024 of file radeon_reg.h.

#define RADEON_FP_DFP_SYNC_SEL (1 << 21)

Definition at line 924 of file radeon_reg.h.

#define RADEON_FP_EN_TMDS (1 << 7)

Definition at line 908 of file radeon_reg.h.

#define RADEON_FP_FPON (1 << 0)

Definition at line 904 of file radeon_reg.h.

#define RADEON_FP_GEN_CNTL 0x0284

Definition at line 903 of file radeon_reg.h.

#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4

Definition at line 955 of file radeon_reg.h.

#define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8

Definition at line 891 of file radeon_reg.h.

#define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003

Definition at line 899 of file radeon_reg.h.

#define RADEON_FP_H_SYNC_STRT_WID 0x02c4

Definition at line 954 of file radeon_reg.h.

#define RADEON_FP_H_SYNC_WID_MASK 0x003f0000

Definition at line 892 of file radeon_reg.h.

#define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010

Definition at line 900 of file radeon_reg.h.

#define RADEON_FP_HORZ2_STRETCH 0x038c

Definition at line 957 of file radeon_reg.h.

#define RADEON_FP_HORZ_STRETCH 0x028c

Definition at line 956 of file radeon_reg.h.

#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278

Definition at line 968 of file radeon_reg.h.

#define RADEON_FP_PANEL_FORMAT (1 << 3)

Definition at line 907 of file radeon_reg.h.

#define RADEON_FP_PANEL_SCALABLE (1 << 16)

Definition at line 152 of file radeon_reg.h.

#define RADEON_FP_PANEL_SCALE_EN (1 << 17)

Definition at line 153 of file radeon_reg.h.

#define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)

Definition at line 923 of file radeon_reg.h.

#define RADEON_FP_SEL_CRTC1 (0 << 13)

Definition at line 916 of file radeon_reg.h.

#define RADEON_FP_SEL_CRTC2 (1 << 13)

Definition at line 917 of file radeon_reg.h.

#define RADEON_FP_TMDS_EN (1 << 2)

Definition at line 906 of file radeon_reg.h.

#define RADEON_FP_USE_SHADOW_EN (1 << 24)

Definition at line 927 of file radeon_reg.h.

#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8

Definition at line 971 of file radeon_reg.h.

#define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff

Definition at line 893 of file radeon_reg.h.

#define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000

Definition at line 901 of file radeon_reg.h.

#define RADEON_FP_V_SYNC_STRT_WID 0x02c8

Definition at line 969 of file radeon_reg.h.

#define RADEON_FP_V_SYNC_WID_MASK 0x001f0000

Definition at line 894 of file radeon_reg.h.

#define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010

Definition at line 902 of file radeon_reg.h.

#define RADEON_FP_VERT2_STRETCH 0x0390

Definition at line 972 of file radeon_reg.h.

#define RADEON_FP_VERT_STRETCH 0x0290

Definition at line 970 of file radeon_reg.h.

#define RADEON_GEN_INT_CNTL 0x0040

Definition at line 1012 of file radeon_reg.h.

#define RADEON_GEN_INT_STATUS 0x0044

Definition at line 1019 of file radeon_reg.h.

#define RADEON_GENENB 0x03c3 /* VGA */

Definition at line 1034 of file radeon_reg.h.

#define RADEON_GENFC_RD 0x03ca /* VGA */

Definition at line 1035 of file radeon_reg.h.

#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */

Definition at line 1036 of file radeon_reg.h.

#define RADEON_GENMO_RD 0x03cc /* VGA */

Definition at line 1037 of file radeon_reg.h.

#define RADEON_GENMO_WT 0x03c2 /* VGA */

Definition at line 1038 of file radeon_reg.h.

#define RADEON_GENS0 0x03c2 /* VGA */

Definition at line 1039 of file radeon_reg.h.

#define RADEON_GENS1 0x03da /* VGA, 0x03ba */

Definition at line 1040 of file radeon_reg.h.

#define RADEON_GMC_3D_FCN_EN (1 << 27)

Definition at line 793 of file radeon_reg.h.

#define RADEON_GMC_AUX_CLIP_DIS (1 << 29)

Definition at line 795 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)

Definition at line 762 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)

Definition at line 755 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)

Definition at line 756 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)

Definition at line 757 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)

Definition at line 758 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)

Definition at line 759 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)

Definition at line 760 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)

Definition at line 761 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)

Definition at line 753 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)

Definition at line 754 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)

Definition at line 752 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_NONE (15 << 4)

Definition at line 764 of file radeon_reg.h.

#define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)

Definition at line 763 of file radeon_reg.h.

#define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)

Definition at line 785 of file radeon_reg.h.

#define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)

Definition at line 784 of file radeon_reg.h.

#define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)

Definition at line 783 of file radeon_reg.h.

#define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)

Definition at line 794 of file radeon_reg.h.

#define RADEON_GMC_CONVERSION_TEMP (1 << 15)

Definition at line 786 of file radeon_reg.h.

#define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)

Definition at line 787 of file radeon_reg.h.

#define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)

Definition at line 788 of file radeon_reg.h.

#define RADEON_GMC_DST_15BPP (3 << 8)

Definition at line 766 of file radeon_reg.h.

#define RADEON_GMC_DST_16BPP (4 << 8)

Definition at line 767 of file radeon_reg.h.

#define RADEON_GMC_DST_24BPP (5 << 8)

Definition at line 768 of file radeon_reg.h.

#define RADEON_GMC_DST_32BPP (6 << 8)

Definition at line 769 of file radeon_reg.h.

#define RADEON_GMC_DST_8BPP_CI (2 << 8)

Definition at line 765 of file radeon_reg.h.

#define RADEON_GMC_DST_8BPP_RGB (7 << 8)

Definition at line 770 of file radeon_reg.h.

#define RADEON_GMC_DST_ARGB4444 (15 << 8)

Definition at line 776 of file radeon_reg.h.

#define RADEON_GMC_DST_AYUV444 (14 << 8)

Definition at line 775 of file radeon_reg.h.

#define RADEON_GMC_DST_CLIPPING (1 << 3)

Definition at line 751 of file radeon_reg.h.

#define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)

Definition at line 777 of file radeon_reg.h.

#define RADEON_GMC_DST_DATATYPE_SHIFT 8

Definition at line 778 of file radeon_reg.h.

#define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)

Definition at line 749 of file radeon_reg.h.

#define RADEON_GMC_DST_RGB8 (9 << 8)

Definition at line 772 of file radeon_reg.h.

#define RADEON_GMC_DST_VYUY (11 << 8)

Definition at line 773 of file radeon_reg.h.

#define RADEON_GMC_DST_Y8 (8 << 8)

Definition at line 771 of file radeon_reg.h.

#define RADEON_GMC_DST_YVYU (12 << 8)

Definition at line 774 of file radeon_reg.h.

#define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)

Definition at line 797 of file radeon_reg.h.

#define RADEON_GMC_ROP3_MASK (0xff << 16)

Definition at line 789 of file radeon_reg.h.

#define RADEON_GMC_SRC_CLIPPING (1 << 2)

Definition at line 750 of file radeon_reg.h.

#define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)

Definition at line 782 of file radeon_reg.h.

#define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)

Definition at line 779 of file radeon_reg.h.

#define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)

Definition at line 780 of file radeon_reg.h.

#define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)

Definition at line 781 of file radeon_reg.h.

#define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)

Definition at line 748 of file radeon_reg.h.

#define RADEON_GMC_WR_MSK_DIS (1 << 30)

Definition at line 796 of file radeon_reg.h.

#define RADEON_GPIO_A_0 (1 << 0)

Definition at line 1046 of file radeon_reg.h.

#define RADEON_GPIO_A_1 (1 << 1)

Definition at line 1047 of file radeon_reg.h.

#define RADEON_GPIO_CRT2_DDC 0x006c

Definition at line 1043 of file radeon_reg.h.

#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */

Definition at line 1044 of file radeon_reg.h.

#define RADEON_GPIO_EN_0 (1 << 16)

Definition at line 1052 of file radeon_reg.h.

#define RADEON_GPIO_EN_1 (1 << 17)

Definition at line 1053 of file radeon_reg.h.

#define RADEON_GPIO_MASK_0 (1 << 24) /*??*/

Definition at line 1054 of file radeon_reg.h.

#define RADEON_GPIO_MASK_1 (1 << 25) /*??*/

Definition at line 1055 of file radeon_reg.h.

#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */

Definition at line 1041 of file radeon_reg.h.

#define RADEON_GPIO_MONIDB 0x006c

Definition at line 1042 of file radeon_reg.h.

#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */

Definition at line 1045 of file radeon_reg.h.

#define RADEON_GPIO_Y_0 (1 << 8)

Definition at line 1048 of file radeon_reg.h.

#define RADEON_GPIO_Y_1 (1 << 9)

Definition at line 1049 of file radeon_reg.h.

#define RADEON_GPIO_Y_SHIFT_0 8

Definition at line 1050 of file radeon_reg.h.

#define RADEON_GPIO_Y_SHIFT_1 9

Definition at line 1051 of file radeon_reg.h.

#define RADEON_GPIOPAD_A 0x019c

Definition at line 1191 of file radeon_reg.h.

#define RADEON_GPIOPAD_EN 0x01a0

Definition at line 1192 of file radeon_reg.h.

#define RADEON_GPIOPAD_MASK 0x0198

Definition at line 1190 of file radeon_reg.h.

#define RADEON_GPIOPAD_Y 0x01a4

Definition at line 1193 of file radeon_reg.h.

#define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L

Definition at line 1314 of file radeon_reg.h.

#define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L

Definition at line 1312 of file radeon_reg.h.

#define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L

Definition at line 1311 of file radeon_reg.h.

#define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L

Definition at line 1315 of file radeon_reg.h.

#define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L

Definition at line 1313 of file radeon_reg.h.

#define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)

Definition at line 3525 of file radeon_reg.h.

#define RADEON_GRPH2_BUFFER_CNTL 0x03f0

Definition at line 409 of file radeon_reg.h.

#define RADEON_GRPH2_BUFFER_SIZE (1<<29)

Definition at line 417 of file radeon_reg.h.

#define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)

Definition at line 418 of file radeon_reg.h.

#define RADEON_GRPH2_CRITICAL_CNTL (1<<28)

Definition at line 416 of file radeon_reg.h.

#define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)

Definition at line 414 of file radeon_reg.h.

#define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16

Definition at line 415 of file radeon_reg.h.

#define RADEON_GRPH2_START_REQ_MASK (0x7f)

Definition at line 410 of file radeon_reg.h.

#define RADEON_GRPH2_START_REQ_SHIFT 0

Definition at line 411 of file radeon_reg.h.

#define RADEON_GRPH2_STOP_CNTL (1<<31)

Definition at line 419 of file radeon_reg.h.

#define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)

Definition at line 412 of file radeon_reg.h.

#define RADEON_GRPH2_STOP_REQ_SHIFT 8

Definition at line 413 of file radeon_reg.h.

#define RADEON_GRPH8_DATA 0x03cf /* VGA */

Definition at line 1056 of file radeon_reg.h.

#define RADEON_GRPH8_IDX 0x03ce /* VGA */

Definition at line 1057 of file radeon_reg.h.

#define RADEON_GRPH_BUFFER_CNTL 0x02f0

Definition at line 398 of file radeon_reg.h.

#define RADEON_GRPH_BUFFER_SIZE (1<<29)

Definition at line 406 of file radeon_reg.h.

#define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)

Definition at line 407 of file radeon_reg.h.

#define RADEON_GRPH_CRITICAL_CNTL (1<<28)

Definition at line 405 of file radeon_reg.h.

#define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)

Definition at line 403 of file radeon_reg.h.

#define RADEON_GRPH_CRITICAL_POINT_SHIFT 16

Definition at line 404 of file radeon_reg.h.

#define RADEON_GRPH_START_REQ_MASK (0x7f)

Definition at line 399 of file radeon_reg.h.

#define RADEON_GRPH_START_REQ_SHIFT 0

Definition at line 400 of file radeon_reg.h.

#define RADEON_GRPH_STOP_CNTL (1<<31)

Definition at line 408 of file radeon_reg.h.

#define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)

Definition at line 401 of file radeon_reg.h.

#define RADEON_GRPH_STOP_REQ_SHIFT 8

Definition at line 402 of file radeon_reg.h.

#define RADEON_GUI_IDLE_MASK (1 << 19)

Definition at line 1017 of file radeon_reg.h.

#define RADEON_GUI_IDLE_STAT (1 << 19)

Definition at line 1029 of file radeon_reg.h.

#define RADEON_GUI_IDLE_STAT_ACK (1 << 19)

Definition at line 1030 of file radeon_reg.h.

#define RADEON_GUI_SCRATCH_REG0 0x15e0

Definition at line 1058 of file radeon_reg.h.

#define RADEON_GUI_SCRATCH_REG1 0x15e4

Definition at line 1059 of file radeon_reg.h.

#define RADEON_GUI_SCRATCH_REG2 0x15e8

Definition at line 1060 of file radeon_reg.h.

#define RADEON_GUI_SCRATCH_REG3 0x15ec

Definition at line 1061 of file radeon_reg.h.

#define RADEON_GUI_SCRATCH_REG4 0x15f0

Definition at line 1062 of file radeon_reg.h.

#define RADEON_GUI_SCRATCH_REG5 0x15f4

Definition at line 1063 of file radeon_reg.h.

#define RADEON_H_INC_MASK 0xfff

Definition at line 3574 of file radeon_reg.h.

#define RADEON_H_INC_SHIFT 0

Definition at line 3575 of file radeon_reg.h.

#define RADEON_HCODE_TABLE_SEL_MASK 0x06000000

Definition at line 3621 of file radeon_reg.h.

#define RADEON_HCODE_TABLE_SEL_SHIFT 25

Definition at line 3622 of file radeon_reg.h.

#define RADEON_HDP_APER_CNTL (1 << 23)

Definition at line 1079 of file radeon_reg.h.

#define RADEON_HDP_READ_BUFFER_INVALIDATE (1 << 27)

Definition at line 1077 of file radeon_reg.h.

#define RADEON_HDP_SOFT_RESET (1 << 26)

Definition at line 1078 of file radeon_reg.h.

#define RADEON_HEADER 0x0f0e /* PCI */

Definition at line 1065 of file radeon_reg.h.

#define RADEON_HORZ_AUTO_RATIO (1 << 27)

Definition at line 965 of file radeon_reg.h.

#define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)

Definition at line 967 of file radeon_reg.h.

#define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)

Definition at line 966 of file radeon_reg.h.

#define RADEON_HORZ_PANEL_SHIFT 16

Definition at line 961 of file radeon_reg.h.

#define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)

Definition at line 960 of file radeon_reg.h.

#define RADEON_HORZ_STRETCH_BLEND (1 << 26)

Definition at line 963 of file radeon_reg.h.

#define RADEON_HORZ_STRETCH_ENABLE (1 << 25)

Definition at line 964 of file radeon_reg.h.

#define RADEON_HORZ_STRETCH_PIXREP (0 << 25)

Definition at line 962 of file radeon_reg.h.

#define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff

Definition at line 958 of file radeon_reg.h.

#define RADEON_HORZ_STRETCH_RATIO_MAX 4096

Definition at line 959 of file radeon_reg.h.

#define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)

Definition at line 746 of file radeon_reg.h.

#define RADEON_HOST_DATA0 0x17c0

Definition at line 1066 of file radeon_reg.h.

#define RADEON_HOST_DATA1 0x17c4

Definition at line 1067 of file radeon_reg.h.

#define RADEON_HOST_DATA2 0x17c8

Definition at line 1068 of file radeon_reg.h.

#define RADEON_HOST_DATA3 0x17cc

Definition at line 1069 of file radeon_reg.h.

#define RADEON_HOST_DATA4 0x17d0

Definition at line 1070 of file radeon_reg.h.

#define RADEON_HOST_DATA5 0x17d4

Definition at line 1071 of file radeon_reg.h.

#define RADEON_HOST_DATA6 0x17d8

Definition at line 1072 of file radeon_reg.h.

#define RADEON_HOST_DATA7 0x17dc

Definition at line 1073 of file radeon_reg.h.

#define RADEON_HOST_DATA_LAST 0x17e0

Definition at line 1074 of file radeon_reg.h.

#define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)

Definition at line 1585 of file radeon_reg.h.

#define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)

Definition at line 1586 of file radeon_reg.h.

#define RADEON_HOST_DATA_SWAP_HDW (3 << 0)

Definition at line 1587 of file radeon_reg.h.

#define RADEON_HOST_DATA_SWAP_NONE (0 << 0)

Definition at line 1584 of file radeon_reg.h.

#define RADEON_HOST_FIFO_RD (1 << 12)

Definition at line 3563 of file radeon_reg.h.

#define RADEON_HOST_FIFO_RD_ACK (1 << 13)

Definition at line 3564 of file radeon_reg.h.

#define RADEON_HOST_FIFO_WT (1 << 14)

Definition at line 3565 of file radeon_reg.h.

#define RADEON_HOST_FIFO_WT_ACK (1 << 15)

Definition at line 3566 of file radeon_reg.h.

#define RADEON_HOST_PATH_CNTL 0x0130

Definition at line 1075 of file radeon_reg.h.

#define RADEON_HP_LIN_RD_CACHE_DIS (1 << 24)

Definition at line 1076 of file radeon_reg.h.

#define RADEON_HSYNC_DELAY_MASK (0xf << 28)

Definition at line 1153 of file radeon_reg.h.

#define RADEON_HSYNC_DELAY_SHIFT 28

Definition at line 1152 of file radeon_reg.h.

#define RADEON_HTOT_CNTL_VGA_EN (1 << 28)

Definition at line 1081 of file radeon_reg.h.

#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */

Definition at line 1082 of file radeon_reg.h.

#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */

Definition at line 1080 of file radeon_reg.h.

#define RADEON_HW_NEEDS_DVI_I2C (1 << 14)

Definition at line 1115 of file radeon_reg.h.

#define RADEON_HW_USING_DVI_I2C (1 << 15)

Definition at line 1117 of file radeon_reg.h.

#define RADEON_I2C_ABORT (1 << 11)

Definition at line 1095 of file radeon_reg.h.

#define RADEON_I2C_ADDR_COUNT_SHIFT 4

Definition at line 1100 of file radeon_reg.h.

#define RADEON_I2C_CNTL_0 0x0090

Definition at line 1085 of file radeon_reg.h.

#define RADEON_I2C_CNTL_1 0x0094

Definition at line 1098 of file radeon_reg.h.

#define RADEON_I2C_DATA 0x0098

Definition at line 1105 of file radeon_reg.h.

#define RADEON_I2C_DATA_COUNT_SHIFT 0

Definition at line 1099 of file radeon_reg.h.

#define RADEON_I2C_DONE (1 << 0)

Definition at line 1086 of file radeon_reg.h.

#define RADEON_I2C_DRIVE_EN (1 << 6)

Definition at line 1090 of file radeon_reg.h.

#define RADEON_I2C_DRIVE_SEL (1 << 7)

Definition at line 1091 of file radeon_reg.h.

#define RADEON_I2C_EN (1 << 17)

Definition at line 1103 of file radeon_reg.h.

#define RADEON_I2C_GO (1 << 12)

Definition at line 1096 of file radeon_reg.h.

#define RADEON_I2C_HALT (1 << 2)

Definition at line 1088 of file radeon_reg.h.

#define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 8

Definition at line 1101 of file radeon_reg.h.

#define RADEON_I2C_NACK (1 << 1)

Definition at line 1087 of file radeon_reg.h.

#define RADEON_I2C_PRESCALE_SHIFT 16

Definition at line 1097 of file radeon_reg.h.

#define RADEON_I2C_RECEIVE (1 << 10)

Definition at line 1094 of file radeon_reg.h.

#define RADEON_I2C_SEL (1 << 16)

Definition at line 1102 of file radeon_reg.h.

#define RADEON_I2C_SOFT_RST (1 << 5)

Definition at line 1089 of file radeon_reg.h.

#define RADEON_I2C_START (1 << 8)

Definition at line 1092 of file radeon_reg.h.

#define RADEON_I2C_STOP (1 << 9)

Definition at line 1093 of file radeon_reg.h.

#define RADEON_I2C_TIME_LIMIT_SHIFT 24

Definition at line 1104 of file radeon_reg.h.

#define RADEON_IDCT_AUTH 0x1F8C

Definition at line 1509 of file radeon_reg.h.

#define RADEON_IDCT_AUTH_CONTROL 0x1F88

Definition at line 1508 of file radeon_reg.h.

#define RADEON_IDCT_CONTROL 0x1FBC

Definition at line 1507 of file radeon_reg.h.

#define RADEON_IDCT_LEVELS 0x1F84

Definition at line 1506 of file radeon_reg.h.

#define RADEON_IDCT_RUNS 0x1F80

Definition at line 1505 of file radeon_reg.h.

#define RADEON_INDIRECT1_START_MASK (0x7f << 8)

Definition at line 3362 of file radeon_reg.h.

#define RADEON_INDIRECT1_START_SHIFT 8

Definition at line 3361 of file radeon_reg.h.

#define RADEON_INDIRECT2_START_MASK (0x7f << 0)

Definition at line 3360 of file radeon_reg.h.

#define RADEON_INDIRECT2_START_SHIFT 0

Definition at line 3359 of file radeon_reg.h.

#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */

Definition at line 1121 of file radeon_reg.h.

#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */

Definition at line 1122 of file radeon_reg.h.

#define RADEON_IO_BASE 0x0f14 /* PCI */

Definition at line 1123 of file radeon_reg.h.

#define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)

Definition at line 1188 of file radeon_reg.h.

#define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)

Definition at line 1186 of file radeon_reg.h.

#define RADEON_IT_MODELVIEW_0_SHIFT 16

Definition at line 2520 of file radeon_reg.h.

#define RADEON_IT_MODELVIEW_1_SHIFT 20

Definition at line 2521 of file radeon_reg.h.

#define RADEON_IT_MODELVIEW_2_SHIFT 24

Definition at line 2522 of file radeon_reg.h.

#define RADEON_IT_MODELVIEW_3_SHIFT 28

Definition at line 2523 of file radeon_reg.h.

#define RADEON_LATENCY 0x0f0d /* PCI */

Definition at line 1125 of file radeon_reg.h.

#define RADEON_LCD1_ATTACHED (1 << 2)

Definition at line 168 of file radeon_reg.h.

#define RADEON_LCD1_CRTC_MASK (1 << 8)

Definition at line 185 of file radeon_reg.h.

#define RADEON_LCD1_CRTC_SHIFT 8

Definition at line 186 of file radeon_reg.h.

#define RADEON_LCD1_ON (1 << 0)

Definition at line 178 of file radeon_reg.h.

#define RADEON_LCD_DPMS_ON (1 << 20)

Definition at line 209 of file radeon_reg.h.

#define RADEON_LEAD_BRES_DEC 0x1608

Definition at line 1126 of file radeon_reg.h.

#define RADEON_LEAD_BRES_LNTH 0x161c

Definition at line 1127 of file radeon_reg.h.

#define RADEON_LEAD_BRES_LNTH_SUB 0x1624

Definition at line 1128 of file radeon_reg.h.

#define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)

Definition at line 2586 of file radeon_reg.h.

#define RADEON_LIGHT_0_DUAL_CONE (1 << 5)

Definition at line 2584 of file radeon_reg.h.

#define RADEON_LIGHT_0_ENABLE (1 << 0)

Definition at line 2579 of file radeon_reg.h.

#define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)

Definition at line 2580 of file radeon_reg.h.

#define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)

Definition at line 2585 of file radeon_reg.h.

#define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)

Definition at line 2581 of file radeon_reg.h.

#define RADEON_LIGHT_0_IS_LOCAL (1 << 3)

Definition at line 2582 of file radeon_reg.h.

#define RADEON_LIGHT_0_IS_SPOT (1 << 4)

Definition at line 2583 of file radeon_reg.h.

#define RADEON_LIGHT_0_SHIFT 0

Definition at line 2587 of file radeon_reg.h.

#define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)

Definition at line 2595 of file radeon_reg.h.

#define RADEON_LIGHT_1_DUAL_CONE (1 << 21)

Definition at line 2593 of file radeon_reg.h.

#define RADEON_LIGHT_1_ENABLE (1 << 16)

Definition at line 2588 of file radeon_reg.h.

#define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)

Definition at line 2589 of file radeon_reg.h.

#define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)

Definition at line 2594 of file radeon_reg.h.

#define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)

Definition at line 2590 of file radeon_reg.h.

#define RADEON_LIGHT_1_IS_LOCAL (1 << 19)

Definition at line 2591 of file radeon_reg.h.

#define RADEON_LIGHT_1_IS_SPOT (1 << 20)

Definition at line 2592 of file radeon_reg.h.

#define RADEON_LIGHT_1_SHIFT 16

Definition at line 2596 of file radeon_reg.h.

#define RADEON_LIGHT_2_SHIFT 0

Definition at line 2598 of file radeon_reg.h.

#define RADEON_LIGHT_3_SHIFT 16

Definition at line 2599 of file radeon_reg.h.

#define RADEON_LIGHT_4_SHIFT 0

Definition at line 2601 of file radeon_reg.h.

#define RADEON_LIGHT_5_SHIFT 16

Definition at line 2602 of file radeon_reg.h.

#define RADEON_LIGHT_6_SHIFT 0

Definition at line 2604 of file radeon_reg.h.

#define RADEON_LIGHT_7_SHIFT 16

Definition at line 2605 of file radeon_reg.h.

#define RADEON_LIGHT_ALPHA (1 << 7)

Definition at line 2488 of file radeon_reg.h.

#define RADEON_LIGHT_IN_MODELSPACE (1 << 1)

Definition at line 2482 of file radeon_reg.h.

#define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)

Definition at line 2490 of file radeon_reg.h.

#define RADEON_LIGHT_TWOSIDE (1 << 11)

Definition at line 2648 of file radeon_reg.h.

#define RADEON_LIGHTING_ENABLE (1 << 0)

Definition at line 2481 of file radeon_reg.h.

#define RADEON_LINE_CURRENT_COUNT_SHIFT 8

Definition at line 2380 of file radeon_reg.h.

#define RADEON_LINE_CURRENT_PTR_SHIFT 0

Definition at line 2379 of file radeon_reg.h.

#define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)

Definition at line 2377 of file radeon_reg.h.

#define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)

Definition at line 2376 of file radeon_reg.h.

#define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)

Definition at line 2375 of file radeon_reg.h.

#define RADEON_LINE_PATTERN_MASK 0x0000ffff

Definition at line 2372 of file radeon_reg.h.

#define RADEON_LINE_PATTERN_START_SHIFT 24

Definition at line 2374 of file radeon_reg.h.

#define RADEON_LINE_REPEAT_COUNT_SHIFT 16

Definition at line 2373 of file radeon_reg.h.

#define RADEON_LM_SOURCE_STATE_MULT 1

Definition at line 2492 of file radeon_reg.h.

#define RADEON_LM_SOURCE_STATE_PREMULT 0

Definition at line 2491 of file radeon_reg.h.

#define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2

Definition at line 2493 of file radeon_reg.h.

#define RADEON_LM_SOURCE_VERTEX_SPECULAR 3

Definition at line 2494 of file radeon_reg.h.

#define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)

Definition at line 2489 of file radeon_reg.h.

#define RADEON_LOCAL_VIEWER (1 << 2)

Definition at line 2483 of file radeon_reg.h.

#define RADEON_LOD_BIAS_MASK (0xff << 8)

Definition at line 1953 of file radeon_reg.h.

#define RADEON_LOD_BIAS_SHIFT 8

Definition at line 1954 of file radeon_reg.h.

#define RADEON_LVDS_2_GREY (1 << 4)

Definition at line 1135 of file radeon_reg.h.

#define RADEON_LVDS_4_GREY (2 << 4)

Definition at line 1136 of file radeon_reg.h.

#define RADEON_LVDS_BL_CLK_SEL (1 << 17)

Definition at line 1142 of file radeon_reg.h.

#define RADEON_LVDS_BL_MOD_EN (1 << 16)

Definition at line 1141 of file radeon_reg.h.

#define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)

Definition at line 1140 of file radeon_reg.h.

#define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8

Definition at line 1139 of file radeon_reg.h.

#define RADEON_LVDS_BLON (1 << 19)

Definition at line 1144 of file radeon_reg.h.

#define RADEON_LVDS_DIGON (1 << 18)

Definition at line 1143 of file radeon_reg.h.

#define RADEON_LVDS_DISPLAY_DIS (1 << 1)

Definition at line 1131 of file radeon_reg.h.

#define RADEON_LVDS_DTM_POL_LOW (1 << 22)

Definition at line 1147 of file radeon_reg.h.

#define RADEON_LVDS_EN (1 << 7)

Definition at line 1138 of file radeon_reg.h.

#define RADEON_LVDS_FP_POL_LOW (1 << 20)

Definition at line 1145 of file radeon_reg.h.

#define RADEON_LVDS_FPDI_EN (1 << 27)

Definition at line 1149 of file radeon_reg.h.

#define RADEON_LVDS_GEN_CNTL 0x02d0

Definition at line 1129 of file radeon_reg.h.

#define RADEON_LVDS_HSYNC_DELAY_SHIFT 28

Definition at line 1150 of file radeon_reg.h.

#define RADEON_LVDS_LP_POL_LOW (1 << 21)

Definition at line 1146 of file radeon_reg.h.

#define RADEON_LVDS_NO_FM (0 << 4)

Definition at line 1134 of file radeon_reg.h.

#define RADEON_LVDS_ON (1 << 0)

Definition at line 1130 of file radeon_reg.h.

#define RADEON_LVDS_PANEL_FORMAT (1 << 3)

Definition at line 1133 of file radeon_reg.h.

#define RADEON_LVDS_PANEL_TYPE (1 << 2)

Definition at line 1132 of file radeon_reg.h.

#define RADEON_LVDS_PLL_CNTL 0x02d4

Definition at line 1151 of file radeon_reg.h.

#define RADEON_LVDS_PLL_EN (1 << 16)

Definition at line 1154 of file radeon_reg.h.

#define RADEON_LVDS_PLL_RESET (1 << 17)

Definition at line 1155 of file radeon_reg.h.

#define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT 16

Definition at line 1161 of file radeon_reg.h.

#define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT 20

Definition at line 1162 of file radeon_reg.h.

#define RADEON_LVDS_RST_FM (1 << 6)

Definition at line 1137 of file radeon_reg.h.

#define RADEON_LVDS_SEL_CRTC2 (1 << 23)

Definition at line 1148 of file radeon_reg.h.

#define RADEON_LVDS_SS_GEN_CNTL 0x02ec

Definition at line 1160 of file radeon_reg.h.

#define RADEON_M_SPLL_REF_DIV_MASK 0xff

Definition at line 1648 of file radeon_reg.h.

#define RADEON_M_SPLL_REF_DIV_SHIFT 0

Definition at line 1647 of file radeon_reg.h.

#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */

Definition at line 1646 of file radeon_reg.h.

#define RADEON_MAG_FILTER_LINEAR (1 << 0)

Definition at line 1934 of file radeon_reg.h.

#define RADEON_MAG_FILTER_MASK (1 << 0)

Definition at line 1935 of file radeon_reg.h.

#define RADEON_MAG_FILTER_NEAREST (0 << 0)

Definition at line 1933 of file radeon_reg.h.

#define RADEON_MAX_ANISO_16_TO_1 (4 << 5)

Definition at line 1951 of file radeon_reg.h.

#define RADEON_MAX_ANISO_1_TO_1 (0 << 5)

Definition at line 1947 of file radeon_reg.h.

#define RADEON_MAX_ANISO_2_TO_1 (1 << 5)

Definition at line 1948 of file radeon_reg.h.

#define RADEON_MAX_ANISO_4_TO_1 (2 << 5)

Definition at line 1949 of file radeon_reg.h.

#define RADEON_MAX_ANISO_8_TO_1 (3 << 5)

Definition at line 1950 of file radeon_reg.h.

#define RADEON_MAX_ANISO_MASK (7 << 5)

Definition at line 1952 of file radeon_reg.h.

#define RADEON_MAX_FETCH_MASK (0x3 << 18)

Definition at line 3303 of file radeon_reg.h.

#define RADEON_MAX_FETCH_SHIFT 18

Definition at line 3302 of file radeon_reg.h.

#define RADEON_MAX_LATENCY 0x0f3f /* PCI */

Definition at line 1164 of file radeon_reg.h.

#define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)

Definition at line 1955 of file radeon_reg.h.

#define RADEON_MAX_MIP_LEVEL_SHIFT 16

Definition at line 1956 of file radeon_reg.h.

#define RADEON_MAX_UV_ADR_MASK 0x000000ff

Definition at line 3615 of file radeon_reg.h.

#define RADEON_MAX_UV_ADR_SHIFT 0

Definition at line 3616 of file radeon_reg.h.

#define RADEON_MC_AGP_LOCATION 0x014c

Definition at line 61 of file radeon_reg.h.

#define RADEON_MC_AGP_START_MASK 0x0000FFFF

Definition at line 62 of file radeon_reg.h.

#define RADEON_MC_AGP_START_SHIFT 0

Definition at line 63 of file radeon_reg.h.

#define RADEON_MC_AGP_TOP_MASK 0xFFFF0000

Definition at line 64 of file radeon_reg.h.

#define RADEON_MC_AGP_TOP_SHIFT 16

Definition at line 65 of file radeon_reg.h.

#define RADEON_MC_BUSY (1 << 16)

Definition at line 354 of file radeon_reg.h.

#define RADEON_MC_ENABLE (1 << 31)

Definition at line 1895 of file radeon_reg.h.

#define RADEON_MC_FB_LOCATION 0x0148

Definition at line 66 of file radeon_reg.h.

#define RADEON_MC_FB_START_MASK 0x0000FFFF

Definition at line 67 of file radeon_reg.h.

#define RADEON_MC_FB_START_SHIFT 0

Definition at line 68 of file radeon_reg.h.

#define RADEON_MC_FB_TOP_MASK 0xFFFF0000

Definition at line 69 of file radeon_reg.h.

#define RADEON_MC_FB_TOP_SHIFT 16

Definition at line 70 of file radeon_reg.h.

#define RADEON_MC_IDLE (1 << 2)

Definition at line 1222 of file radeon_reg.h.

#define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)

Definition at line 1187 of file radeon_reg.h.

#define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)

Definition at line 1185 of file radeon_reg.h.

#define RADEON_MC_STATUS 0x0150

Definition at line 1221 of file radeon_reg.h.

#define RADEON_MCLK_CNTL 0x0012 /* PLL */

Definition at line 1174 of file radeon_reg.h.

#define RADEON_MCLK_MISC 0x001f /* PLL */

Definition at line 1184 of file radeon_reg.h.

#define RADEON_MCLKA_SRC_SEL_MASK 0x7

Definition at line 1175 of file radeon_reg.h.

#define RADEON_MDGPIO_A 0x01ac

Definition at line 1195 of file radeon_reg.h.

#define RADEON_MDGPIO_EN 0x01b0

Definition at line 1196 of file radeon_reg.h.

#define RADEON_MDGPIO_MASK 0x01a8

Definition at line 1194 of file radeon_reg.h.

#define RADEON_MDGPIO_Y 0x01b4

Definition at line 1197 of file radeon_reg.h.

#define RADEON_MEM_ADDR_CONFIG 0x0148

Definition at line 1199 of file radeon_reg.h.

#define RADEON_MEM_BASE 0x0f10 /* PCI */

Definition at line 1200 of file radeon_reg.h.

#define RADEON_MEM_CFG_TYPE_DDR (1 << 30)

Definition at line 1213 of file radeon_reg.h.

#define RADEON_MEM_CNTL 0x0140

Definition at line 1201 of file radeon_reg.h.

#define RADEON_MEM_INIT_LAT_TIMER 0x0154

Definition at line 1208 of file radeon_reg.h.

#define RADEON_MEM_INTF_CNTL 0x014c

Definition at line 1209 of file radeon_reg.h.

#define RADEON_MEM_NUM_CHANNELS_MASK 0x01

Definition at line 1202 of file radeon_reg.h.

#define RADEON_MEM_PWRUP_COMPL_A (1 << 0)

Definition at line 1215 of file radeon_reg.h.

#define RADEON_MEM_PWRUP_COMPL_B (1 << 1)

Definition at line 1216 of file radeon_reg.h.

#define RADEON_MEM_PWRUP_COMPLETE 0x03

Definition at line 1219 of file radeon_reg.h.

#define RADEON_MEM_SDRAM_MODE_REG 0x0158

Definition at line 1210 of file radeon_reg.h.

#define RADEON_MEM_STR_CNTL 0x0150

Definition at line 1214 of file radeon_reg.h.

#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */

Definition at line 1207 of file radeon_reg.h.

#define RADEON_MEM_USE_B_CH_ONLY (1 << 1)

Definition at line 1203 of file radeon_reg.h.

#define RADEON_MEM_VGA_RP_SEL 0x003c

Definition at line 1224 of file radeon_reg.h.

#define RADEON_MEM_VGA_WP_SEL 0x0038

Definition at line 1225 of file radeon_reg.h.

#define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)

Definition at line 1943 of file radeon_reg.h.

#define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)

Definition at line 1942 of file radeon_reg.h.

#define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)

Definition at line 1945 of file radeon_reg.h.

#define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)

Definition at line 1944 of file radeon_reg.h.

#define RADEON_MIN_FILTER_LINEAR (1 << 1)

Definition at line 1937 of file radeon_reg.h.

#define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)

Definition at line 1941 of file radeon_reg.h.

#define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)

Definition at line 1940 of file radeon_reg.h.

#define RADEON_MIN_FILTER_MASK (15 << 1)

Definition at line 1946 of file radeon_reg.h.

#define RADEON_MIN_FILTER_NEAREST (0 << 1)

Definition at line 1936 of file radeon_reg.h.

#define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)

Definition at line 1939 of file radeon_reg.h.

#define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)

Definition at line 1938 of file radeon_reg.h.

#define RADEON_MIN_GRANT 0x0f3e /* PCI */

Definition at line 1226 of file radeon_reg.h.

#define RADEON_MM_APER (1 << 31)

Definition at line 1229 of file radeon_reg.h.

#define RADEON_MM_DATA 0x0004

Definition at line 1227 of file radeon_reg.h.

#define RADEON_MM_INDEX 0x0000

Definition at line 1228 of file radeon_reg.h.

#define RADEON_MODELPROJECT_0_SHIFT 0

Definition at line 2525 of file radeon_reg.h.

#define RADEON_MODELPROJECT_1_SHIFT 4

Definition at line 2526 of file radeon_reg.h.

#define RADEON_MODELPROJECT_2_SHIFT 8

Definition at line 2527 of file radeon_reg.h.

#define RADEON_MODELPROJECT_3_SHIFT 12

Definition at line 2528 of file radeon_reg.h.

#define RADEON_MODELVIEW_0_SHIFT 0

Definition at line 2516 of file radeon_reg.h.

#define RADEON_MODELVIEW_1_SHIFT 4

Definition at line 2517 of file radeon_reg.h.

#define RADEON_MODELVIEW_2_SHIFT 8

Definition at line 2518 of file radeon_reg.h.

#define RADEON_MODELVIEW_3_SHIFT 12

Definition at line 2519 of file radeon_reg.h.

#define RADEON_MPLL_CNTL 0x000e /* PLL */

Definition at line 1230 of file radeon_reg.h.

#define RADEON_MPLL_FB_DIV_MASK 0xff

Definition at line 1650 of file radeon_reg.h.

#define RADEON_MPLL_FB_DIV_SHIFT 8

Definition at line 1649 of file radeon_reg.h.

#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */

Definition at line 1232 of file radeon_reg.h.

#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */

Definition at line 1231 of file radeon_reg.h.

#define RADEON_MSI_REARM_EN 0x0160

Definition at line 307 of file radeon_reg.h.

#define RADEON_N_VIF_COUNT 0x0248

Definition at line 1245 of file radeon_reg.h.

#define RADEON_NB_TOM 0x15c

Definition at line 1168 of file radeon_reg.h.

#define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)

Definition at line 1721 of file radeon_reg.h.

#define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)

Definition at line 1722 of file radeon_reg.h.

#define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)

Definition at line 1723 of file radeon_reg.h.

#define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)

Definition at line 1724 of file radeon_reg.h.

#define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)

Definition at line 2652 of file radeon_reg.h.

#define RADEON_NORMALIZE_NORMALS (1 << 3)

Definition at line 2484 of file radeon_reg.h.

#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470

Definition at line 1247 of file radeon_reg.h.

#define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000

Definition at line 1257 of file radeon_reg.h.

#define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020

Definition at line 1251 of file radeon_reg.h.

#define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000

Definition at line 1254 of file radeon_reg.h.

#define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000

Definition at line 1255 of file radeon_reg.h.

#define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000

Definition at line 1256 of file radeon_reg.h.

#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007

Definition at line 1248 of file radeon_reg.h.

#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010

Definition at line 1250 of file radeon_reg.h.

#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040

Definition at line 1252 of file radeon_reg.h.

#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008

Definition at line 1249 of file radeon_reg.h.

#define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300

Definition at line 1253 of file radeon_reg.h.

#define RADEON_OV0_BASE_ADDR 0x43c

Definition at line 1167 of file radeon_reg.h.

#define RADEON_OV0_COLOUR_CNTL 0x04E0

Definition at line 1259 of file radeon_reg.h.

#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474

Definition at line 1260 of file radeon_reg.h.

#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408

Definition at line 1261 of file radeon_reg.h.

#define RADEON_OV0_EXCLUSIVE_VERT 0x040C

Definition at line 1266 of file radeon_reg.h.

#define RADEON_OV0_FILTER_CNTL 0x04A0

Definition at line 1269 of file radeon_reg.h.

#define RADEON_OV0_FLAG_CNTL 0x04DC

Definition at line 1283 of file radeon_reg.h.

#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0

Definition at line 1278 of file radeon_reg.h.

#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4

Definition at line 1279 of file radeon_reg.h.

#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8

Definition at line 1280 of file radeon_reg.h.

#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC

Definition at line 1281 of file radeon_reg.h.

#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0

Definition at line 1282 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_000_00F 0x0d40

Definition at line 1284 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_010_01F 0x0d44

Definition at line 1285 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_020_03F 0x0d48

Definition at line 1286 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_040_07F 0x0d4c

Definition at line 1287 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_080_0BF 0x0e00

Definition at line 1288 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04

Definition at line 1289 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_100_13F 0x0e08

Definition at line 1290 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_140_17F 0x0e0c

Definition at line 1291 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_180_1BF 0x0e10

Definition at line 1292 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14

Definition at line 1293 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_200_23F 0x0e18

Definition at line 1294 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_240_27F 0x0e1c

Definition at line 1295 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_280_2BF 0x0e20

Definition at line 1296 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24

Definition at line 1297 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_300_33F 0x0e28

Definition at line 1298 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_340_37F 0x0e2c

Definition at line 1299 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_380_3BF 0x0d50

Definition at line 1300 of file radeon_reg.h.

#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54

Definition at line 1301 of file radeon_reg.h.

#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0

Definition at line 1303 of file radeon_reg.h.

#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC

Definition at line 1302 of file radeon_reg.h.

#define RADEON_OV0_H_INC 0x0480

Definition at line 1304 of file radeon_reg.h.

#define RADEON_OV0_KEY_CNTL 0x04F4

Definition at line 1305 of file radeon_reg.h.

#define RADEON_OV0_LIN_TRANS_A 0x0d20

Definition at line 1319 of file radeon_reg.h.

#define RADEON_OV0_LIN_TRANS_B 0x0d24

Definition at line 1320 of file radeon_reg.h.

#define RADEON_OV0_LIN_TRANS_C 0x0d28

Definition at line 1321 of file radeon_reg.h.

#define RADEON_OV0_LIN_TRANS_D 0x0d2c

Definition at line 1322 of file radeon_reg.h.

#define RADEON_OV0_LIN_TRANS_E 0x0d30

Definition at line 1323 of file radeon_reg.h.

#define RADEON_OV0_LIN_TRANS_F 0x0d34

Definition at line 1324 of file radeon_reg.h.

#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430

Definition at line 1325 of file radeon_reg.h.

#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488

Definition at line 1328 of file radeon_reg.h.

#define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L

Definition at line 1330 of file radeon_reg.h.

#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428

Definition at line 1329 of file radeon_reg.h.

#define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L

Definition at line 1331 of file radeon_reg.h.

#define RADEON_OV0_P1_X_START_END 0x0494

Definition at line 1332 of file radeon_reg.h.

#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434

Definition at line 1334 of file radeon_reg.h.

#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C

Definition at line 1337 of file radeon_reg.h.

#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C

Definition at line 1338 of file radeon_reg.h.

#define RADEON_OV0_P2_X_START_END 0x0498

Definition at line 1333 of file radeon_reg.h.

#define RADEON_OV0_P3_X_START_END 0x049C

Definition at line 1339 of file radeon_reg.h.

#define RADEON_OV0_REG_LOAD_CNTL 0x0410

Definition at line 1340 of file radeon_reg.h.

#define RADEON_OV0_SCALE_CNTL 0x0420

Definition at line 1346 of file radeon_reg.h.

#define RADEON_OV0_STEP_BY 0x0484

Definition at line 1375 of file radeon_reg.h.

#define RADEON_OV0_TEST 0x04F8

Definition at line 1376 of file radeon_reg.h.

#define RADEON_OV0_V_INC 0x0424

Definition at line 1377 of file radeon_reg.h.

#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440

Definition at line 1380 of file radeon_reg.h.

#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444

Definition at line 1385 of file radeon_reg.h.

#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448

Definition at line 1390 of file radeon_reg.h.

#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C

Definition at line 1395 of file radeon_reg.h.

#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450

Definition at line 1396 of file radeon_reg.h.

#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454

Definition at line 1397 of file radeon_reg.h.

#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460

Definition at line 1378 of file radeon_reg.h.

#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464

Definition at line 1379 of file radeon_reg.h.

#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8

Definition at line 1398 of file radeon_reg.h.

#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4

Definition at line 1399 of file radeon_reg.h.

#define RADEON_OV0_Y_X_END 0x0404

Definition at line 1401 of file radeon_reg.h.

#define RADEON_OV0_Y_X_START 0x0400

Definition at line 1400 of file radeon_reg.h.

#define RADEON_OV1_Y_X_END 0x0604

Definition at line 1403 of file radeon_reg.h.

#define RADEON_OV1_Y_X_START 0x0600

Definition at line 1402 of file radeon_reg.h.

#define RADEON_OVR2_CLR 0x0330

Definition at line 1407 of file radeon_reg.h.

#define RADEON_OVR2_WID_LEFT_RIGHT 0x0334

Definition at line 1408 of file radeon_reg.h.

#define RADEON_OVR2_WID_TOP_BOTTOM 0x0338

Definition at line 1409 of file radeon_reg.h.

#define RADEON_OVR_CLR 0x0230

Definition at line 1404 of file radeon_reg.h.

#define RADEON_OVR_WID_LEFT_RIGHT 0x0234

Definition at line 1405 of file radeon_reg.h.

#define RADEON_OVR_WID_TOP_BOTTOM 0x0238

Definition at line 1406 of file radeon_reg.h.

#define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L

Definition at line 1327 of file radeon_reg.h.

#define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL

Definition at line 1326 of file radeon_reg.h.

#define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L

Definition at line 1336 of file radeon_reg.h.

#define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL

Definition at line 1335 of file radeon_reg.h.

#define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)

Definition at line 1516 of file radeon_reg.h.

#define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */

Definition at line 1524 of file radeon_reg.h.

#define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)

Definition at line 1518 of file radeon_reg.h.

#define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */

Definition at line 1525 of file radeon_reg.h.

#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */

Definition at line 1511 of file radeon_reg.h.

#define RADEON_P2PLL_DIV_0 0x002c

Definition at line 1519 of file radeon_reg.h.

#define RADEON_P2PLL_FB0_DIV_MASK 0x07ff

Definition at line 1520 of file radeon_reg.h.

#define RADEON_P2PLL_POST0_DIV_MASK 0x00070000

Definition at line 1521 of file radeon_reg.h.

#define RADEON_P2PLL_PVG_MASK (7 << 11)

Definition at line 1514 of file radeon_reg.h.

#define RADEON_P2PLL_PVG_SHIFT 11

Definition at line 1515 of file radeon_reg.h.

#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */

Definition at line 1522 of file radeon_reg.h.

#define RADEON_P2PLL_REF_DIV_MASK 0x03ff

Definition at line 1523 of file radeon_reg.h.

#define RADEON_P2PLL_RESET (1 << 0)

Definition at line 1512 of file radeon_reg.h.

#define RADEON_P2PLL_SLEEP (1 << 1)

Definition at line 1513 of file radeon_reg.h.

#define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)

Definition at line 1517 of file radeon_reg.h.

#define RADEON_PALETTE_30_DATA 0x00b8

Definition at line 1529 of file radeon_reg.h.

#define RADEON_PALETTE_DATA 0x00b4

Definition at line 1528 of file radeon_reg.h.

#define RADEON_PALETTE_INDEX 0x00b0

Definition at line 1530 of file radeon_reg.h.

#define RADEON_PATTERN_ENABLE (1 << 2)

Definition at line 1869 of file radeon_reg.h.

#define RADEON_PCI_GART_PAGE 0x017c

Definition at line 1531 of file radeon_reg.h.

#define RADEON_PCIE_DATA 0x0034

Definition at line 3681 of file radeon_reg.h.

#define RADEON_PCIE_INDEX 0x0030

Definition at line 3680 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */

Definition at line 312 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7

Definition at line 314 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70

Definition at line 323 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4

Definition at line 322 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0

Definition at line 313 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_X0 0

Definition at line 315 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_X1 1

Definition at line 316 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_X12 5

Definition at line 320 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_X16 6

Definition at line 321 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_X2 2

Definition at line 317 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_X4 3

Definition at line 318 of file radeon_reg.h.

#define RADEON_PCIE_LC_LINK_WIDTH_X8 4

Definition at line 319 of file radeon_reg.h.

#define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)

Definition at line 325 of file radeon_reg.h.

#define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)

Definition at line 324 of file radeon_reg.h.

#define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)

Definition at line 326 of file radeon_reg.h.

#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12

Definition at line 3692 of file radeon_reg.h.

#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11

Definition at line 3691 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_BASE 0x13

Definition at line 3693 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)

Definition at line 3689 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_CNTL 0x10

Definition at line 3682 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_EN (1 << 0)

Definition at line 3683 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_END_HI 0x17

Definition at line 3697 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_END_LO 0x16

Definition at line 3696 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_ERROR 0x18

Definition at line 3698 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)

Definition at line 3690 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)

Definition at line 3687 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)

Definition at line 3688 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_START_HI 0x15

Definition at line 3695 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_START_LO 0x14

Definition at line 3694 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)

Definition at line 3685 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)

Definition at line 3686 of file radeon_reg.h.

#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)

Definition at line 3684 of file radeon_reg.h.

#define RADEON_PCIGART_TRANSLATE_EN (1 << 0)

Definition at line 3365 of file radeon_reg.h.

#define RADEON_PITCH_SHIFT 21

Definition at line 850 of file radeon_reg.h.

#define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)

Definition at line 1538 of file radeon_reg.h.

#define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)

Definition at line 1539 of file radeon_reg.h.

#define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02

Definition at line 1536 of file radeon_reg.h.

#define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00

Definition at line 1534 of file radeon_reg.h.

#define RADEON_PIX2CLK_SRC_SEL_MASK 0x03

Definition at line 1533 of file radeon_reg.h.

#define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03

Definition at line 1537 of file radeon_reg.h.

#define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01

Definition at line 1535 of file radeon_reg.h.

#define RADEON_PIXCLK_ALWAYS_ONb (1<<6)

Definition at line 1789 of file radeon_reg.h.

#define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)

Definition at line 1543 of file radeon_reg.h.

#define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)

Definition at line 1790 of file radeon_reg.h.

#define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)

Definition at line 1545 of file radeon_reg.h.

#define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)

Definition at line 1544 of file radeon_reg.h.

#define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)

Definition at line 1547 of file radeon_reg.h.

#define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)

Definition at line 1548 of file radeon_reg.h.

#define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)

Definition at line 1540 of file radeon_reg.h.

#define RADEON_PIXCLKS_CNTL 0x002d

Definition at line 1532 of file radeon_reg.h.

#define RADEON_PLANAR_YUV_ENABLE (1 << 20)

Definition at line 1881 of file radeon_reg.h.

#define RADEON_PLANE_3D_MASK_C 0x1d44

Definition at line 1554 of file radeon_reg.h.

#define RADEON_PLANE_MASK_ENABLE (1 << 1)

Definition at line 2255 of file radeon_reg.h.

#define RADEON_PLL2_DIV_SEL_MASK (~(3 << 8))

Definition at line 348 of file radeon_reg.h.

#define RADEON_PLL_DIV_SEL (3 << 8)

Definition at line 347 of file radeon_reg.h.

#define RADEON_PLL_MASK_READ_B (1 << 9)

Definition at line 1556 of file radeon_reg.h.

#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */

Definition at line 361 of file radeon_reg.h.

#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */

Definition at line 1555 of file radeon_reg.h.

#define RADEON_PLL_WR_EN (1 << 7)

Definition at line 346 of file radeon_reg.h.

#define RADEON_PM_MODE_SEL (1 << 13)

Definition at line 362 of file radeon_reg.h.

#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */

Definition at line 1557 of file radeon_reg.h.

#define RADEON_PMI_DATA 0x0f63 /* PCI */

Definition at line 1558 of file radeon_reg.h.

#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */

Definition at line 1559 of file radeon_reg.h.

#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */

Definition at line 1560 of file radeon_reg.h.

#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */

Definition at line 1561 of file radeon_reg.h.

#define RADEON_PMI_REGISTER 0x0f5c /* PCI */

Definition at line 1562 of file radeon_reg.h.

#define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)

Definition at line 2651 of file radeon_reg.h.

#define RADEON_PP_BORDER_COLOR_0 0x1d40

Definition at line 1863 of file radeon_reg.h.

#define RADEON_PP_BORDER_COLOR_1 0x1d44

Definition at line 1864 of file radeon_reg.h.

#define RADEON_PP_BORDER_COLOR_2 0x1d48

Definition at line 1865 of file radeon_reg.h.

#define RADEON_PP_CNTL 0x1c38

Definition at line 1866 of file radeon_reg.h.

#define RADEON_PP_CUBIC_FACES_0 0x1d24

Definition at line 2030 of file radeon_reg.h.

#define RADEON_PP_CUBIC_FACES_1 0x1d28

Definition at line 2031 of file radeon_reg.h.

#define RADEON_PP_CUBIC_FACES_2 0x1d2c

Definition at line 2032 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */

Definition at line 2065 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4

Definition at line 2066 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8

Definition at line 2067 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc

Definition at line 2068 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0

Definition at line 2069 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00

Definition at line 2070 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04

Definition at line 2071 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08

Definition at line 2072 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c

Definition at line 2073 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10

Definition at line 2074 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14

Definition at line 2075 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18

Definition at line 2076 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c

Definition at line 2077 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20

Definition at line 2078 of file radeon_reg.h.

#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24

Definition at line 2079 of file radeon_reg.h.

#define RADEON_PP_FOG_COLOR 0x1c18

Definition at line 1896 of file radeon_reg.h.

#define RADEON_PP_LUM_MATRIX 0x1d00

Definition at line 1903 of file radeon_reg.h.

#define RADEON_PP_MISC 0x1c14

Definition at line 1904 of file radeon_reg.h.

#define RADEON_PP_ROT_MATRIX_0 0x1d58

Definition at line 1928 of file radeon_reg.h.

#define RADEON_PP_ROT_MATRIX_1 0x1d5c

Definition at line 1929 of file radeon_reg.h.

#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */

Definition at line 2092 of file radeon_reg.h.

#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */

Definition at line 2093 of file radeon_reg.h.

#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */

Definition at line 2094 of file radeon_reg.h.

#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */

Definition at line 2081 of file radeon_reg.h.

#define RADEON_PP_TEX_SIZE_1 0x1d0c

Definition at line 2082 of file radeon_reg.h.

#define RADEON_PP_TEX_SIZE_2 0x1d14

Definition at line 2083 of file radeon_reg.h.

#define RADEON_PP_TFACTOR_0 0x1c68

Definition at line 2220 of file radeon_reg.h.

#define RADEON_PP_TFACTOR_1 0x1c80

Definition at line 2221 of file radeon_reg.h.

#define RADEON_PP_TFACTOR_2 0x1c98

Definition at line 2222 of file radeon_reg.h.

#define RADEON_PP_TXABLEND_0 0x1c64

Definition at line 2181 of file radeon_reg.h.

#define RADEON_PP_TXABLEND_1 0x1c7c

Definition at line 2182 of file radeon_reg.h.

#define RADEON_PP_TXABLEND_2 0x1c94

Definition at line 2183 of file radeon_reg.h.

#define RADEON_PP_TXCBLEND_0 0x1c60

Definition at line 2097 of file radeon_reg.h.

#define RADEON_PP_TXCBLEND_1 0x1c78

Definition at line 2098 of file radeon_reg.h.

#define RADEON_PP_TXCBLEND_2 0x1c90

Definition at line 2099 of file radeon_reg.h.

#define RADEON_PP_TXFILTER_0 0x1c54

Definition at line 1930 of file radeon_reg.h.

#define RADEON_PP_TXFILTER_1 0x1c6c

Definition at line 1931 of file radeon_reg.h.

#define RADEON_PP_TXFILTER_2 0x1c84

Definition at line 1932 of file radeon_reg.h.

#define RADEON_PP_TXFORMAT_0 0x1c58

Definition at line 1983 of file radeon_reg.h.

#define RADEON_PP_TXFORMAT_1 0x1c70

Definition at line 1984 of file radeon_reg.h.

#define RADEON_PP_TXFORMAT_2 0x1c88

Definition at line 1985 of file radeon_reg.h.

#define RADEON_PP_TXOFFSET_0 0x1c5c

Definition at line 2050 of file radeon_reg.h.

#define RADEON_PP_TXOFFSET_1 0x1c74

Definition at line 2051 of file radeon_reg.h.

#define RADEON_PP_TXOFFSET_2 0x1c8c

Definition at line 2052 of file radeon_reg.h.

#define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)

Definition at line 1568 of file radeon_reg.h.

#define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */

Definition at line 1579 of file radeon_reg.h.

#define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)

Definition at line 1570 of file radeon_reg.h.

#define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */

Definition at line 1580 of file radeon_reg.h.

#define RADEON_PPLL_CNTL 0x0002 /* PLL */

Definition at line 1563 of file radeon_reg.h.

#define RADEON_PPLL_DIV_0 0x0004 /* PLL */

Definition at line 1571 of file radeon_reg.h.

#define RADEON_PPLL_DIV_1 0x0005 /* PLL */

Definition at line 1572 of file radeon_reg.h.

#define RADEON_PPLL_DIV_2 0x0006 /* PLL */

Definition at line 1573 of file radeon_reg.h.

#define RADEON_PPLL_DIV_3 0x0007 /* PLL */

Definition at line 1574 of file radeon_reg.h.

#define RADEON_PPLL_FB3_DIV_MASK 0x07ff

Definition at line 1575 of file radeon_reg.h.

#define RADEON_PPLL_POST3_DIV_MASK 0x00070000

Definition at line 1576 of file radeon_reg.h.

#define RADEON_PPLL_PVG_MASK (7 << 11)

Definition at line 1566 of file radeon_reg.h.

#define RADEON_PPLL_PVG_SHIFT 11

Definition at line 1567 of file radeon_reg.h.

#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */

Definition at line 1577 of file radeon_reg.h.

#define RADEON_PPLL_REF_DIV_MASK 0x03ff

Definition at line 1578 of file radeon_reg.h.

#define RADEON_PPLL_RESET (1 << 0)

Definition at line 1564 of file radeon_reg.h.

#define RADEON_PPLL_SLEEP (1 << 1)

Definition at line 1565 of file radeon_reg.h.

#define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)

Definition at line 1569 of file radeon_reg.h.

#define RADEON_PRE_WRITE_LIMIT_SHIFT 23

Definition at line 3357 of file radeon_reg.h.

#define RADEON_PRE_WRITE_TIMER_SHIFT 0

Definition at line 3356 of file radeon_reg.h.

#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */

Definition at line 1581 of file radeon_reg.h.

#define RADEON_RB2D_DC_BUSY (1 << 31)

Definition at line 1604 of file radeon_reg.h.

#define RADEON_RB2D_DC_FLUSH (3 << 0)

Definition at line 1601 of file radeon_reg.h.

#define RADEON_RB2D_DC_FLUSH_ALL 0xf

Definition at line 1603 of file radeon_reg.h.

#define RADEON_RB2D_DC_FREE (3 << 2)

Definition at line 1602 of file radeon_reg.h.

#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c

Definition at line 1600 of file radeon_reg.h.

#define RADEON_RB2D_DSTCACHE_MODE 0x3428

Definition at line 1605 of file radeon_reg.h.

#define RADEON_RB3D_BLENDCNTL 0x1c20

Definition at line 2224 of file radeon_reg.h.

#define RADEON_RB3D_CNTL 0x1c3c

Definition at line 2253 of file radeon_reg.h.

#define RADEON_RB3D_COLOR_FORMAT_SHIFT 10

Definition at line 2264 of file radeon_reg.h.

#define RADEON_RB3D_COLOROFFSET 0x1c40

Definition at line 2278 of file radeon_reg.h.

#define RADEON_RB3D_COLORPITCH 0x1c48

Definition at line 2280 of file radeon_reg.h.

#define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)

Definition at line 1618 of file radeon_reg.h.

#define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)

Definition at line 1613 of file radeon_reg.h.

#define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)

Definition at line 1616 of file radeon_reg.h.

#define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)

Definition at line 1619 of file radeon_reg.h.

#define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)

Definition at line 1614 of file radeon_reg.h.

#define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)

Definition at line 1617 of file radeon_reg.h.

#define RADEON_RB3D_DC_BUSY (1 << 31)

Definition at line 1630 of file radeon_reg.h.

#define RADEON_RB3D_DC_CACHE_DISABLE (3)

Definition at line 1615 of file radeon_reg.h.

#define RADEON_RB3D_DC_CACHE_ENABLE (0)

Definition at line 1612 of file radeon_reg.h.

#define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)

Definition at line 1623 of file radeon_reg.h.

#define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)

Definition at line 1624 of file radeon_reg.h.

#define RADEON_RB3D_DC_FLUSH (3 << 0)

Definition at line 1627 of file radeon_reg.h.

#define RADEON_RB3D_DC_FLUSH_ALL 0xf

Definition at line 1629 of file radeon_reg.h.

#define RADEON_RB3D_DC_FORCE_RMW (1 << 16)

Definition at line 1622 of file radeon_reg.h.

#define RADEON_RB3D_DC_FREE (3 << 2)

Definition at line 1628 of file radeon_reg.h.

#define RADEON_RB3D_DEPTHOFFSET 0x1c24

Definition at line 2287 of file radeon_reg.h.

#define RADEON_RB3D_DEPTHPITCH 0x1c28

Definition at line 2288 of file radeon_reg.h.

#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C

Definition at line 1626 of file radeon_reg.h.

#define RADEON_RB3D_DSTCACHE_MODE 0x3258

Definition at line 1611 of file radeon_reg.h.

#define RADEON_RB3D_PLANEMASK 0x1d84

Definition at line 2293 of file radeon_reg.h.

#define RADEON_RB3D_ROPCNTL 0x1d80

Definition at line 2294 of file radeon_reg.h.

#define RADEON_RB3D_STENCILREFMASK 0x1d7c

Definition at line 2312 of file radeon_reg.h.

#define RADEON_RB3D_ZC_FLUSH_ALL 0x5

Definition at line 1610 of file radeon_reg.h.

#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254

Definition at line 1609 of file radeon_reg.h.

#define RADEON_RB3D_ZCACHE_MODE 0x3250

Definition at line 1608 of file radeon_reg.h.

#define RADEON_RB3D_ZPASS_ADDR 0x3294

Definition at line 2398 of file radeon_reg.h.

#define RADEON_RB3D_ZPASS_DATA 0x3290

Definition at line 2397 of file radeon_reg.h.

#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c

Definition at line 2319 of file radeon_reg.h.

#define RADEON_RB_BLKSZ_MASK (0x3f << 8)

Definition at line 3300 of file radeon_reg.h.

#define RADEON_RB_BLKSZ_SHIFT 8

Definition at line 3299 of file radeon_reg.h.

#define RADEON_RB_BUFSZ_MASK (0x3f << 0)

Definition at line 3298 of file radeon_reg.h.

#define RADEON_RB_BUFSZ_SHIFT 0

Definition at line 3297 of file radeon_reg.h.

#define RADEON_RB_NO_UPDATE (1 << 27)

Definition at line 3304 of file radeon_reg.h.

#define RADEON_RB_RPTR_WR_ENA (1 << 31)

Definition at line 3305 of file radeon_reg.h.

#define RADEON_RBBM_ACTIVE (1 << 31)

Definition at line 1599 of file radeon_reg.h.

#define RADEON_RBBM_FIFOCNT_MASK 0x007f

Definition at line 1598 of file radeon_reg.h.

#define RADEON_RBBM_GUICNTL 0x172c

Definition at line 1583 of file radeon_reg.h.

#define RADEON_RBBM_SOFT_RESET 0x00f0

Definition at line 1588 of file radeon_reg.h.

#define RADEON_RBBM_STATUS 0x0e40

Definition at line 1597 of file radeon_reg.h.

#define RADEON_RE_HEIGHT_SHIFT 16

Definition at line 2395 of file radeon_reg.h.

#define RADEON_RE_LEFT_SHIFT 0

Definition at line 2391 of file radeon_reg.h.

#define RADEON_RE_LINE_PATTERN 0x1cd0

Definition at line 2371 of file radeon_reg.h.

#define RADEON_RE_LINE_STATE 0x1cd4

Definition at line 2378 of file radeon_reg.h.

#define RADEON_RE_MISC 0x26c4

Definition at line 2381 of file radeon_reg.h.

#define RADEON_RE_SOLID_COLOR 0x1c1c

Definition at line 2389 of file radeon_reg.h.

#define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)

Definition at line 3516 of file radeon_reg.h.

#define RADEON_RE_TOP_LEFT 0x26c0

Definition at line 2390 of file radeon_reg.h.

#define RADEON_RE_TOP_SHIFT 16

Definition at line 2392 of file radeon_reg.h.

#define RADEON_RE_WIDTH_HEIGHT 0x1c44

Definition at line 2393 of file radeon_reg.h.

#define RADEON_RE_WIDTH_SHIFT 0

Definition at line 2394 of file radeon_reg.h.

#define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)

Definition at line 3524 of file radeon_reg.h.

#define RADEON_REF_ALPHA_MASK 0x000000ff

Definition at line 1905 of file radeon_reg.h.

#define RADEON_REG_BASE 0x0f18 /* PCI */

Definition at line 1632 of file radeon_reg.h.

#define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L

Definition at line 1345 of file radeon_reg.h.

#define RADEON_REG_LD_CTL_LOCK 0x00000001L

Definition at line 1341 of file radeon_reg.h.

#define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L

Definition at line 1344 of file radeon_reg.h.

#define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L

Definition at line 1343 of file radeon_reg.h.

#define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L

Definition at line 1342 of file radeon_reg.h.

#define RADEON_REGPROG_INF 0x0f09 /* PCI */

Definition at line 1633 of file radeon_reg.h.

#define RADEON_REQ_Y_FIRST (1 << 19)

Definition at line 3576 of file radeon_reg.h.

#define RADEON_RESCALE_NORMALS (1 << 4)

Definition at line 2485 of file radeon_reg.h.

#define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */

Definition at line 3571 of file radeon_reg.h.

#define RADEON_RESTART_PHASE_FIX (1 << 3)

Definition at line 3509 of file radeon_reg.h.

#define RADEON_REVISION_ID 0x0f08 /* PCI */

Definition at line 1634 of file radeon_reg.h.

#define RADEON_RGB_ATTEN_SEL ( x ) ((x) << 24)

Definition at line 3538 of file radeon_reg.h.

#define RADEON_RGB_ATTEN_VAL ( x ) ((x) << 28)

Definition at line 3540 of file radeon_reg.h.

#define RADEON_RGB_CONVERT_BY_PASS (1 << 10)

Definition at line 3535 of file radeon_reg.h.

#define RADEON_RGB_DITHER_EN (1 << 5)

Definition at line 3530 of file radeon_reg.h.

#define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8)

Definition at line 3532 of file radeon_reg.h.

#define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)

Definition at line 3534 of file radeon_reg.h.

#define RADEON_RGB_SRC_SEL_MASK (3 << 8)

Definition at line 3531 of file radeon_reg.h.

#define RADEON_RGB_SRC_SEL_RMX (1 << 8)

Definition at line 3533 of file radeon_reg.h.

#define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)

Definition at line 1926 of file radeon_reg.h.

#define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)

Definition at line 1927 of file radeon_reg.h.

#define RADEON_RNG_BASED_FOG (1 << 10)

Definition at line 2647 of file radeon_reg.h.

#define RADEON_ROP3_D 0x00aa0000

Definition at line 818 of file radeon_reg.h.

#define RADEON_ROP3_D 0x00aa0000

Definition at line 818 of file radeon_reg.h.

#define RADEON_ROP3_Dn 0x00550000

Definition at line 808 of file radeon_reg.h.

#define RADEON_ROP3_DPa 0x00a00000

Definition at line 814 of file radeon_reg.h.

#define RADEON_ROP3_DPan 0x005f0000

Definition at line 826 of file radeon_reg.h.

#define RADEON_ROP3_DPna 0x000a0000

Definition at line 817 of file radeon_reg.h.

#define RADEON_ROP3_DPno 0x00af0000

Definition at line 825 of file radeon_reg.h.

#define RADEON_ROP3_DPo 0x00fa0000

Definition at line 820 of file radeon_reg.h.

#define RADEON_ROP3_DPon 0x00050000

Definition at line 821 of file radeon_reg.h.

#define RADEON_ROP3_DPx 0x005a0000

Definition at line 819 of file radeon_reg.h.

#define RADEON_ROP3_DSa 0x00880000

Definition at line 799 of file radeon_reg.h.

#define RADEON_ROP3_DSan 0x00770000

Definition at line 812 of file radeon_reg.h.

#define RADEON_ROP3_DSna 0x00220000

Definition at line 802 of file radeon_reg.h.

#define RADEON_ROP3_DSno 0x00bb0000

Definition at line 811 of file radeon_reg.h.

#define RADEON_ROP3_DSo 0x00ee0000

Definition at line 805 of file radeon_reg.h.

#define RADEON_ROP3_DSon 0x00110000

Definition at line 806 of file radeon_reg.h.

#define RADEON_ROP3_DSx 0x00660000

Definition at line 804 of file radeon_reg.h.

#define RADEON_ROP3_DSxn 0x00990000

Definition at line 807 of file radeon_reg.h.

#define RADEON_ROP3_ONE 0x00ff0000

Definition at line 813 of file radeon_reg.h.

#define RADEON_ROP3_P 0x00f00000

Definition at line 816 of file radeon_reg.h.

#define RADEON_ROP3_PDna 0x00500000

Definition at line 815 of file radeon_reg.h.

#define RADEON_ROP3_PDno 0x00f50000

Definition at line 823 of file radeon_reg.h.

#define RADEON_ROP3_PDxn 0x00a50000

Definition at line 822 of file radeon_reg.h.

#define RADEON_ROP3_Pn 0x000f0000

Definition at line 824 of file radeon_reg.h.

#define RADEON_ROP3_S 0x00cc0000

Definition at line 801 of file radeon_reg.h.

#define RADEON_ROP3_SDna 0x00440000

Definition at line 800 of file radeon_reg.h.

#define RADEON_ROP3_SDno 0x00dd0000

Definition at line 809 of file radeon_reg.h.

#define RADEON_ROP3_Sn 0x00330000

Definition at line 810 of file radeon_reg.h.

#define RADEON_ROP3_ZERO 0x00000000

Definition at line 798 of file radeon_reg.h.

#define RADEON_ROP_AND (8 << 8)

Definition at line 2304 of file radeon_reg.h.

#define RADEON_ROP_AND_INVERTED (2 << 8)

Definition at line 2298 of file radeon_reg.h.

#define RADEON_ROP_AND_REVERSE (4 << 8)

Definition at line 2300 of file radeon_reg.h.

#define RADEON_ROP_CLEAR (0 << 8)

Definition at line 2296 of file radeon_reg.h.

#define RADEON_ROP_COPY (12 << 8)

Definition at line 2308 of file radeon_reg.h.

#define RADEON_ROP_COPY_INVERTED (3 << 8)

Definition at line 2299 of file radeon_reg.h.

#define RADEON_ROP_ENABLE (1 << 6)

Definition at line 2260 of file radeon_reg.h.

#define RADEON_ROP_EQUIV (9 << 8)

Definition at line 2305 of file radeon_reg.h.

#define RADEON_ROP_INVERT (5 << 8)

Definition at line 2301 of file radeon_reg.h.

#define RADEON_ROP_MASK (15 << 8)

Definition at line 2295 of file radeon_reg.h.

#define RADEON_ROP_NAND (7 << 8)

Definition at line 2303 of file radeon_reg.h.

#define RADEON_ROP_NOOP (10 << 8)

Definition at line 2306 of file radeon_reg.h.

#define RADEON_ROP_NOR (1 << 8)

Definition at line 2297 of file radeon_reg.h.

#define RADEON_ROP_OR (14 << 8)

Definition at line 2310 of file radeon_reg.h.

#define RADEON_ROP_OR_INVERTED (11 << 8)

Definition at line 2307 of file radeon_reg.h.

#define RADEON_ROP_OR_REVERSE (13 << 8)

Definition at line 2309 of file radeon_reg.h.

#define RADEON_ROP_SET (15 << 8)

Definition at line 2311 of file radeon_reg.h.

#define RADEON_ROP_XOR (6 << 8)

Definition at line 2302 of file radeon_reg.h.

#define RADEON_ROUND_ENABLE (1 << 3)

Definition at line 2257 of file radeon_reg.h.

#define RADEON_ROUND_MODE_ROUND (1 << 28)

Definition at line 2439 of file radeon_reg.h.

#define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)

Definition at line 2440 of file radeon_reg.h.

#define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)

Definition at line 2441 of file radeon_reg.h.

#define RADEON_ROUND_MODE_TRUNC (0 << 28)

Definition at line 2438 of file radeon_reg.h.

#define RADEON_ROUND_PREC_16TH_PIX (0 << 30)

Definition at line 2442 of file radeon_reg.h.

#define RADEON_ROUND_PREC_4TH_PIX (2 << 30)

Definition at line 2444 of file radeon_reg.h.

#define RADEON_ROUND_PREC_8TH_PIX (1 << 30)

Definition at line 2443 of file radeon_reg.h.

#define RADEON_ROUND_PREC_HALF_PIX (3 << 30)

Definition at line 2445 of file radeon_reg.h.

#define RADEON_SC_BOTTOM 0x164c

Definition at line 1636 of file radeon_reg.h.

#define RADEON_SC_BOTTOM_RIGHT 0x16f0

Definition at line 1637 of file radeon_reg.h.

#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c

Definition at line 1638 of file radeon_reg.h.

#define RADEON_SC_LEFT 0x1640

Definition at line 1639 of file radeon_reg.h.

#define RADEON_SC_RIGHT 0x1644

Definition at line 1640 of file radeon_reg.h.

#define RADEON_SC_SIGN_MASK_HI 0x80000000

Definition at line 1645 of file radeon_reg.h.

#define RADEON_SC_SIGN_MASK_LO 0x8000

Definition at line 1644 of file radeon_reg.h.

#define RADEON_SC_TOP 0x1648

Definition at line 1641 of file radeon_reg.h.

#define RADEON_SC_TOP_LEFT 0x16ec

Definition at line 1642 of file radeon_reg.h.

#define RADEON_SC_TOP_LEFT_C 0x1c88

Definition at line 1643 of file radeon_reg.h.

#define RADEON_SCALE_1X (0 << 21)

Definition at line 2171 of file radeon_reg.h.

#define RADEON_SCALE_2X (1 << 21)

Definition at line 2172 of file radeon_reg.h.

#define RADEON_SCALE_4X (2 << 21)

Definition at line 2173 of file radeon_reg.h.

#define RADEON_SCALE_DITHER_ENABLE (1 << 4)

Definition at line 2258 of file radeon_reg.h.

#define RADEON_SCALE_MASK (3 << 21)

Definition at line 2170 of file radeon_reg.h.

#define RADEON_SCALE_SHIFT 21

Definition at line 2169 of file radeon_reg.h.

#define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L

Definition at line 1364 of file radeon_reg.h.

#define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L

Definition at line 1368 of file radeon_reg.h.

#define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L

Definition at line 1355 of file radeon_reg.h.

#define RADEON_SCALER_CRTC_SEL 0x00004000L

Definition at line 1366 of file radeon_reg.h.

#define RADEON_SCALER_DIS_LIMIT 0x08000000L

Definition at line 1370 of file radeon_reg.h.

#define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L

Definition at line 1369 of file radeon_reg.h.

#define RADEON_SCALER_ENABLE 0x40000000L

Definition at line 1373 of file radeon_reg.h.

#define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L

Definition at line 1351 of file radeon_reg.h.

#define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L

Definition at line 1354 of file radeon_reg.h.

#define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L

Definition at line 1353 of file radeon_reg.h.

#define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L

Definition at line 1352 of file radeon_reg.h.

#define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L

Definition at line 1350 of file radeon_reg.h.

#define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L

Definition at line 1347 of file radeon_reg.h.

#define RADEON_SCALER_INT_EMU 0x20000000L

Definition at line 1372 of file radeon_reg.h.

#define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L

Definition at line 1371 of file radeon_reg.h.

#define RADEON_SCALER_SIGNED_UV 0x00000010L

Definition at line 1349 of file radeon_reg.h.

#define RADEON_SCALER_SMART_SWITCH 0x00008000L

Definition at line 1367 of file radeon_reg.h.

#define RADEON_SCALER_SOFT_RESET 0x80000000L

Definition at line 1374 of file radeon_reg.h.

#define RADEON_SCALER_SOURCE_15BPP 0x00000300L

Definition at line 1357 of file radeon_reg.h.

#define RADEON_SCALER_SOURCE_16BPP 0x00000400L

Definition at line 1358 of file radeon_reg.h.

#define RADEON_SCALER_SOURCE_32BPP 0x00000600L

Definition at line 1359 of file radeon_reg.h.

#define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L

Definition at line 1362 of file radeon_reg.h.

#define RADEON_SCALER_SOURCE_YUV12 0x00000A00L

Definition at line 1361 of file radeon_reg.h.

#define RADEON_SCALER_SOURCE_YUV9 0x00000900L

Definition at line 1360 of file radeon_reg.h.

#define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L

Definition at line 1363 of file radeon_reg.h.

#define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L

Definition at line 1356 of file radeon_reg.h.

#define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L

Definition at line 1365 of file radeon_reg.h.

#define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L

Definition at line 1348 of file radeon_reg.h.

#define RADEON_SCISSOR_ENABLE (1 << 1)

Definition at line 1868 of file radeon_reg.h.

#define RADEON_SCK_PRESCALE_MASK (0xff << 24)

Definition at line 1235 of file radeon_reg.h.

#define RADEON_SCK_PRESCALE_SHIFT 24

Definition at line 1234 of file radeon_reg.h.

#define RADEON_SCLK_CNTL 0x000d /* PLL */

Definition at line 1662 of file radeon_reg.h.

#define RADEON_SCLK_DYN_START_CNTL (1 << 15)

Definition at line 343 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_CP (1<<16)

Definition at line 1668 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_DISP1 (1<<18)

Definition at line 1670 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_DISP2 (1<<15)

Definition at line 1667 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_E2 (1<<20)

Definition at line 1672 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_HDP (1<<17)

Definition at line 1669 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_IDCT (1<<22)

Definition at line 1674 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_OV0 (1<<31)

Definition at line 1683 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_PB (1<<25)

Definition at line 1677 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_RB (1<<28)

Definition at line 1680 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_RE (1<<24)

Definition at line 1676 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_SE (1<<21)

Definition at line 1673 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_SUBPIC (1<<30)

Definition at line 1682 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_TAM (1<<26)

Definition at line 1678 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_TDM (1<<27)

Definition at line 1679 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_TOP (1<<19)

Definition at line 1671 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_TV_SCLK (1<<29)

Definition at line 1681 of file radeon_reg.h.

#define RADEON_SCLK_FORCE_VIP (1<<23)

Definition at line 1675 of file radeon_reg.h.

#define RADEON_SCLK_FORCEON_MASK 0xffff8000

Definition at line 1666 of file radeon_reg.h.

#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */

Definition at line 1697 of file radeon_reg.h.

#define RADEON_SCLK_MORE_FORCEON 0x0700

Definition at line 1699 of file radeon_reg.h.

#define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007

Definition at line 1698 of file radeon_reg.h.

#define RADEON_SCLK_SRC_SEL_MASK 0x0007

Definition at line 1663 of file radeon_reg.h.

#define RADEON_SCRATCH_ADDR 0x0774

Definition at line 3312 of file radeon_reg.h.

#define RADEON_SCRATCH_REG0 0x15e0

Definition at line 3700 of file radeon_reg.h.

#define RADEON_SCRATCH_REG1 0x15e4

Definition at line 3701 of file radeon_reg.h.

#define RADEON_SCRATCH_REG2 0x15e8

Definition at line 3702 of file radeon_reg.h.

#define RADEON_SCRATCH_REG3 0x15ec

Definition at line 3703 of file radeon_reg.h.

#define RADEON_SCRATCH_REG4 0x15f0

Definition at line 3704 of file radeon_reg.h.

#define RADEON_SCRATCH_REG5 0x15f4

Definition at line 3705 of file radeon_reg.h.

#define RADEON_SCRATCH_UMSK 0x0770

Definition at line 3311 of file radeon_reg.h.

#define RADEON_SCREEN_BLANKING (1 << 26)

Definition at line 218 of file radeon_reg.h.

#define RADEON_SDRAM_MODE_MASK 0xffff0000

Definition at line 1211 of file radeon_reg.h.

#define RADEON_SDRAM_MODE_REG 0x0158

Definition at line 1700 of file radeon_reg.h.

#define RADEON_SE_CNTL 0x1c4c

Definition at line 2400 of file radeon_reg.h.

#define RADEON_SE_CNTL_STATUS 0x2140

Definition at line 2458 of file radeon_reg.h.

#define RADEON_SE_COORD_FMT 0x1c50

Definition at line 2464 of file radeon_reg.h.

#define RADEON_SE_LINE_WIDTH 0x1db8

Definition at line 2479 of file radeon_reg.h.

#define RADEON_SE_PORT_DATA0 0x2000

Definition at line 2729 of file radeon_reg.h.

#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c

Definition at line 2480 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c

Definition at line 2502 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228

Definition at line 2501 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224

Definition at line 2500 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220

Definition at line 2499 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c

Definition at line 2506 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238

Definition at line 2505 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234

Definition at line 2504 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230

Definition at line 2503 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c

Definition at line 2510 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218

Definition at line 2509 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214

Definition at line 2508 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210

Definition at line 2507 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c

Definition at line 2514 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248

Definition at line 2513 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244

Definition at line 2512 of file radeon_reg.h.

#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240

Definition at line 2511 of file radeon_reg.h.

#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c

Definition at line 2515 of file radeon_reg.h.

#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260

Definition at line 2524 of file radeon_reg.h.

#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254

Definition at line 2535 of file radeon_reg.h.

#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258

Definition at line 2559 of file radeon_reg.h.

#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270

Definition at line 2578 of file radeon_reg.h.

#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274

Definition at line 2597 of file radeon_reg.h.

#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278

Definition at line 2600 of file radeon_reg.h.

#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c

Definition at line 2603 of file radeon_reg.h.

#define RADEON_SE_TCL_SHININESS 0x2250

Definition at line 2607 of file radeon_reg.h.

#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268

Definition at line 2609 of file radeon_reg.h.

#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264

Definition at line 2633 of file radeon_reg.h.

#define RADEON_SE_VF_CNTL 0x2084

Definition at line 2702 of file radeon_reg.h.

#define RADEON_SE_VPORT_XOFFSET 0x1d9c

Definition at line 2669 of file radeon_reg.h.

#define RADEON_SE_VPORT_XSCALE 0x1d98

Definition at line 2668 of file radeon_reg.h.

#define RADEON_SE_VPORT_YOFFSET 0x1da4

Definition at line 2671 of file radeon_reg.h.

#define RADEON_SE_VPORT_YSCALE 0x1da0

Definition at line 2670 of file radeon_reg.h.

#define RADEON_SE_VPORT_ZOFFSET 0x1dac

Definition at line 2673 of file radeon_reg.h.

#define RADEON_SE_VPORT_ZSCALE 0x1da8

Definition at line 2672 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT 0x2080

Definition at line 2677 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000

Definition at line 2694 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_FPALPHA 0x00000004

Definition at line 2681 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002

Definition at line 2680 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_FPFOG 0x00000020

Definition at line 2684 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_FPSPEC 0x00000010

Definition at line 2683 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_N0 0x00040000

Definition at line 2695 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_N1 0x40000000

Definition at line 2699 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008

Definition at line 2682 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_PKSPEC 0x00000040

Definition at line 2685 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_Q0 0x00004000

Definition at line 2693 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_Q1 0x00000200

Definition at line 2688 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_Q2 0x00000800

Definition at line 2690 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_Q3 0x00002000

Definition at line 2692 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_ST0 0x00000080

Definition at line 2686 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_ST1 0x00000100

Definition at line 2687 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_ST2 0x00000400

Definition at line 2689 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_ST3 0x00001000

Definition at line 2691 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_W0 0x00000001

Definition at line 2679 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_W1 0x20000000

Definition at line 2698 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_XY 0x00000000

Definition at line 2678 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_XY1 0x08000000

Definition at line 2696 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_Z 0x80000000

Definition at line 2700 of file radeon_reg.h.

#define RADEON_SE_VTX_FMT_Z1 0x10000000

Definition at line 2697 of file radeon_reg.h.

#define RADEON_SE_ZBIAS_CONSTANT 0x1db4

Definition at line 2675 of file radeon_reg.h.

#define RADEON_SE_ZBIAS_FACTOR 0x1db0

Definition at line 2674 of file radeon_reg.h.

#define RADEON_SEPROM_CNTL1 0x01c0

Definition at line 1233 of file radeon_reg.h.

#define RADEON_SEQ8_DATA 0x03c5 /* VGA */

Definition at line 1701 of file radeon_reg.h.

#define RADEON_SEQ8_IDX 0x03c4 /* VGA */

Definition at line 1702 of file radeon_reg.h.

#define RADEON_SET_UP_LEVEL_SHIFT 16

Definition at line 3606 of file radeon_reg.h.

#define RADEON_SHADOW_ENABLE (1 << 3)

Definition at line 1870 of file radeon_reg.h.

#define RADEON_SHADOW_FUNC_EQUAL (0 << 21)

Definition at line 1922 of file radeon_reg.h.

#define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)

Definition at line 1923 of file radeon_reg.h.

#define RADEON_SHADOW_ID_AUTO_INC (1 << 20)

Definition at line 1921 of file radeon_reg.h.

#define RADEON_SHADOW_PASS_1 (0 << 22)

Definition at line 1924 of file radeon_reg.h.

#define RADEON_SHADOW_PASS_2 (1 << 22)

Definition at line 1925 of file radeon_reg.h.

#define RADEON_SIGNED_ALPHA_MASK (1 << 31)

Definition at line 2090 of file radeon_reg.h.

#define RADEON_SIGNED_ALPHA_SHIFT 31

Definition at line 2091 of file radeon_reg.h.

#define RADEON_SIGNED_RGB_MASK (1 << 30)

Definition at line 2088 of file radeon_reg.h.

#define RADEON_SIGNED_RGB_SHIFT 30

Definition at line 2089 of file radeon_reg.h.

#define RADEON_SLEW_RATE_LIMIT (1 << 23)

Definition at line 3607 of file radeon_reg.h.

#define RADEON_SNAPSHOT_F_COUNT 0x0244

Definition at line 1703 of file radeon_reg.h.

#define RADEON_SNAPSHOT_VH_COUNTS 0x0240

Definition at line 1704 of file radeon_reg.h.

#define RADEON_SNAPSHOT_VIF_COUNT 0x024c

Definition at line 1705 of file radeon_reg.h.

#define RADEON_SOFT_RESET_CP (1 << 0)

Definition at line 1589 of file radeon_reg.h.

#define RADEON_SOFT_RESET_E2 (1 << 5)

Definition at line 1594 of file radeon_reg.h.

#define RADEON_SOFT_RESET_GRPH_PP (1 << 0)

Definition at line 714 of file radeon_reg.h.

#define RADEON_SOFT_RESET_HDP (1 << 7)

Definition at line 1596 of file radeon_reg.h.

#define RADEON_SOFT_RESET_HI (1 << 1)

Definition at line 1590 of file radeon_reg.h.

#define RADEON_SOFT_RESET_PP (1 << 4)

Definition at line 1593 of file radeon_reg.h.

#define RADEON_SOFT_RESET_RB (1 << 6)

Definition at line 1595 of file radeon_reg.h.

#define RADEON_SOFT_RESET_RE (1 << 3)

Definition at line 1592 of file radeon_reg.h.

#define RADEON_SOFT_RESET_SE (1 << 2)

Definition at line 1591 of file radeon_reg.h.

#define RADEON_SPECULAR_ENABLE (1 << 21)

Definition at line 1882 of file radeon_reg.h.

#define RADEON_SPECULAR_LIGHTS (1 << 5)

Definition at line 2486 of file radeon_reg.h.

#define RADEON_SPECULAR_SHADE_FLAT (1 << 12)

Definition at line 2423 of file radeon_reg.h.

#define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)

Definition at line 2424 of file radeon_reg.h.

#define RADEON_SPECULAR_SHADE_MASK (3 << 12)

Definition at line 2425 of file radeon_reg.h.

#define RADEON_SPECULAR_SHADE_SOLID (0 << 12)

Definition at line 2422 of file radeon_reg.h.

#define RADEON_SPECULAR_SOURCE_SHIFT 22

Definition at line 2498 of file radeon_reg.h.

#define RADEON_SPLL_CNTL 0x000c /* PLL */

Definition at line 1653 of file radeon_reg.h.

#define RADEON_SPLL_FB_DIV_MASK 0xff

Definition at line 1652 of file radeon_reg.h.

#define RADEON_SPLL_FB_DIV_SHIFT 16

Definition at line 1651 of file radeon_reg.h.

#define RADEON_SPLL_PCP_MASK 0x7

Definition at line 1656 of file radeon_reg.h.

#define RADEON_SPLL_PCP_SHIFT 8

Definition at line 1657 of file radeon_reg.h.

#define RADEON_SPLL_PDC_MASK 0x3

Definition at line 1660 of file radeon_reg.h.

#define RADEON_SPLL_PDC_SHIFT 14

Definition at line 1661 of file radeon_reg.h.

#define RADEON_SPLL_PVG_MASK 0x7

Definition at line 1658 of file radeon_reg.h.

#define RADEON_SPLL_PVG_SHIFT 11

Definition at line 1659 of file radeon_reg.h.

#define RADEON_SPLL_RESET (1 << 1)

Definition at line 1655 of file radeon_reg.h.

#define RADEON_SPLL_SLEEP (1 << 0)

Definition at line 1654 of file radeon_reg.h.

#define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)

Definition at line 2238 of file radeon_reg.h.

#define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)

Definition at line 2234 of file radeon_reg.h.

#define RADEON_SRC_BLEND_GL_ONE (33 << 16)

Definition at line 2231 of file radeon_reg.h.

#define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)

Definition at line 2239 of file radeon_reg.h.

#define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)

Definition at line 2235 of file radeon_reg.h.

#define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)

Definition at line 2237 of file radeon_reg.h.

#define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)

Definition at line 2233 of file radeon_reg.h.

#define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)

Definition at line 2236 of file radeon_reg.h.

#define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)

Definition at line 2240 of file radeon_reg.h.

#define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)

Definition at line 2232 of file radeon_reg.h.

#define RADEON_SRC_BLEND_GL_ZERO (32 << 16)

Definition at line 2230 of file radeon_reg.h.

#define RADEON_SRC_BLEND_MASK (63 << 16)

Definition at line 2241 of file radeon_reg.h.

#define RADEON_SRC_CMP_EQ_COLOR (4 << 0)

Definition at line 368 of file radeon_reg.h.

#define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)

Definition at line 369 of file radeon_reg.h.

#define RADEON_SRC_OFFSET 0x15ac

Definition at line 1706 of file radeon_reg.h.

#define RADEON_SRC_PITCH 0x15b0

Definition at line 1707 of file radeon_reg.h.

#define RADEON_SRC_PITCH_OFFSET 0x1428

Definition at line 1708 of file radeon_reg.h.

#define RADEON_SRC_SC_BOTTOM 0x165c

Definition at line 1709 of file radeon_reg.h.

#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4

Definition at line 1710 of file radeon_reg.h.

#define RADEON_SRC_SC_RIGHT 0x1654

Definition at line 1711 of file radeon_reg.h.

#define RADEON_SRC_X 0x1414

Definition at line 1712 of file radeon_reg.h.

#define RADEON_SRC_X_Y 0x1590

Definition at line 1713 of file radeon_reg.h.

#define RADEON_SRC_Y 0x1418

Definition at line 1714 of file radeon_reg.h.

#define RADEON_SRC_Y_X 0x1434

Definition at line 1715 of file radeon_reg.h.

#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50

Definition at line 3502 of file radeon_reg.h.

#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51

Definition at line 3503 of file radeon_reg.h.

#define RADEON_SS_LIGHT_DCD_ADDR 0

Definition at line 3495 of file radeon_reg.h.

#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32

Definition at line 3499 of file radeon_reg.h.

#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24

Definition at line 3498 of file radeon_reg.h.

#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16

Definition at line 3497 of file radeon_reg.h.

#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8

Definition at line 3496 of file radeon_reg.h.

#define RADEON_SS_SHININESS 60

Definition at line 3504 of file radeon_reg.h.

#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48

Definition at line 3500 of file radeon_reg.h.

#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49

Definition at line 3501 of file radeon_reg.h.

#define RADEON_STATUS 0x0f06 /* PCI */

Definition at line 1716 of file radeon_reg.h.

#define RADEON_STATUS_PCI_CONFIG 0x06

Definition at line 102 of file radeon_reg.h.

#define RADEON_STENCIL_ENABLE (1 << 7)

Definition at line 2261 of file radeon_reg.h.

#define RADEON_STENCIL_FAIL_DEC (4 << 16)

Definition at line 2351 of file radeon_reg.h.

#define RADEON_STENCIL_FAIL_INC (3 << 16)

Definition at line 2350 of file radeon_reg.h.

#define RADEON_STENCIL_FAIL_INVERT (5 << 16)

Definition at line 2352 of file radeon_reg.h.

#define RADEON_STENCIL_FAIL_KEEP (0 << 16)

Definition at line 2347 of file radeon_reg.h.

#define RADEON_STENCIL_FAIL_MASK (0x7 << 16)

Definition at line 2353 of file radeon_reg.h.

#define RADEON_STENCIL_FAIL_REPLACE (2 << 16)

Definition at line 2349 of file radeon_reg.h.

#define RADEON_STENCIL_FAIL_ZERO (1 << 16)

Definition at line 2348 of file radeon_reg.h.

#define RADEON_STENCIL_MASK_SHIFT 16

Definition at line 2315 of file radeon_reg.h.

#define RADEON_STENCIL_REF_MASK (0xff << 0)

Definition at line 2314 of file radeon_reg.h.

#define RADEON_STENCIL_REF_SHIFT 0

Definition at line 2313 of file radeon_reg.h.

#define RADEON_STENCIL_TEST_ALWAYS (7 << 12)

Definition at line 2345 of file radeon_reg.h.

#define RADEON_STENCIL_TEST_EQUAL (3 << 12)

Definition at line 2341 of file radeon_reg.h.

#define RADEON_STENCIL_TEST_GEQUAL (4 << 12)

Definition at line 2342 of file radeon_reg.h.

#define RADEON_STENCIL_TEST_GREATER (5 << 12)

Definition at line 2343 of file radeon_reg.h.

#define RADEON_STENCIL_TEST_LEQUAL (2 << 12)

Definition at line 2340 of file radeon_reg.h.

#define RADEON_STENCIL_TEST_LESS (1 << 12)

Definition at line 2339 of file radeon_reg.h.

#define RADEON_STENCIL_TEST_MASK (0x7 << 12)

Definition at line 2346 of file radeon_reg.h.

#define RADEON_STENCIL_TEST_NEQUAL (6 << 12)

Definition at line 2344 of file radeon_reg.h.

#define RADEON_STENCIL_TEST_NEVER (0 << 12)

Definition at line 2338 of file radeon_reg.h.

#define RADEON_STENCIL_VALUE_MASK (0xff << 16)

Definition at line 2316 of file radeon_reg.h.

#define RADEON_STENCIL_WRITE_MASK (0xff << 24)

Definition at line 2318 of file radeon_reg.h.

#define RADEON_STENCIL_WRITEMASK_SHIFT 24

Definition at line 2317 of file radeon_reg.h.

#define RADEON_STENCIL_ZFAIL_DEC (4 << 24)

Definition at line 2365 of file radeon_reg.h.

#define RADEON_STENCIL_ZFAIL_INC (3 << 24)

Definition at line 2364 of file radeon_reg.h.

#define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)

Definition at line 2366 of file radeon_reg.h.

#define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)

Definition at line 2361 of file radeon_reg.h.

#define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)

Definition at line 2367 of file radeon_reg.h.

#define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)

Definition at line 2363 of file radeon_reg.h.

#define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)

Definition at line 2362 of file radeon_reg.h.

#define RADEON_STENCIL_ZPASS_DEC (4 << 20)

Definition at line 2358 of file radeon_reg.h.

#define RADEON_STENCIL_ZPASS_INC (3 << 20)

Definition at line 2357 of file radeon_reg.h.

#define RADEON_STENCIL_ZPASS_INVERT (5 << 20)

Definition at line 2359 of file radeon_reg.h.

#define RADEON_STENCIL_ZPASS_KEEP (0 << 20)

Definition at line 2354 of file radeon_reg.h.

#define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)

Definition at line 2360 of file radeon_reg.h.

#define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)

Definition at line 2356 of file radeon_reg.h.

#define RADEON_STENCIL_ZPASS_ZERO (1 << 20)

Definition at line 2355 of file radeon_reg.h.

#define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)

Definition at line 2388 of file radeon_reg.h.

#define RADEON_STIPPLE_COORD_MASK 0x1f

Definition at line 2382 of file radeon_reg.h.

#define RADEON_STIPPLE_ENABLE (1 << 0)

Definition at line 1867 of file radeon_reg.h.

#define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)

Definition at line 2387 of file radeon_reg.h.

#define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)

Definition at line 2384 of file radeon_reg.h.

#define RADEON_STIPPLE_X_OFFSET_SHIFT 0

Definition at line 2383 of file radeon_reg.h.

#define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)

Definition at line 2386 of file radeon_reg.h.

#define RADEON_STIPPLE_Y_OFFSET_SHIFT 8

Definition at line 2385 of file radeon_reg.h.

#define RADEON_SUB_CLASS 0x0f0a /* PCI */

Definition at line 1718 of file radeon_reg.h.

#define RADEON_SUBPIC_CNTL 0x0540 /* ? */

Definition at line 1717 of file radeon_reg.h.

#define RADEON_SURF_AP0_SWP_16BPP (1 << 20)

Definition at line 1739 of file radeon_reg.h.

#define RADEON_SURF_AP0_SWP_32BPP (1 << 21)

Definition at line 1740 of file radeon_reg.h.

#define RADEON_SURF_AP1_SWP_16BPP (1 << 22)

Definition at line 1741 of file radeon_reg.h.

#define RADEON_SURF_AP1_SWP_32BPP (1 << 23)

Definition at line 1742 of file radeon_reg.h.

#define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)

Definition at line 1727 of file radeon_reg.h.

#define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)

Definition at line 1726 of file radeon_reg.h.

#define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)

Definition at line 1729 of file radeon_reg.h.

#define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)

Definition at line 1728 of file radeon_reg.h.

#define RADEON_SURF_TRANSLATION_DIS (1 << 8)

Definition at line 1720 of file radeon_reg.h.

#define RADEON_SURFACE0_INFO 0x0b0c

Definition at line 1725 of file radeon_reg.h.

#define RADEON_SURFACE0_LOWER_BOUND 0x0b04

Definition at line 1743 of file radeon_reg.h.

#define RADEON_SURFACE0_UPPER_BOUND 0x0b08

Definition at line 1744 of file radeon_reg.h.

#define RADEON_SURFACE1_INFO 0x0b1c

Definition at line 1745 of file radeon_reg.h.

#define RADEON_SURFACE1_LOWER_BOUND 0x0b14

Definition at line 1746 of file radeon_reg.h.

#define RADEON_SURFACE1_UPPER_BOUND 0x0b18

Definition at line 1747 of file radeon_reg.h.

#define RADEON_SURFACE2_INFO 0x0b2c

Definition at line 1748 of file radeon_reg.h.

#define RADEON_SURFACE2_LOWER_BOUND 0x0b24

Definition at line 1749 of file radeon_reg.h.

#define RADEON_SURFACE2_UPPER_BOUND 0x0b28

Definition at line 1750 of file radeon_reg.h.

#define RADEON_SURFACE3_INFO 0x0b3c

Definition at line 1751 of file radeon_reg.h.

#define RADEON_SURFACE3_LOWER_BOUND 0x0b34

Definition at line 1752 of file radeon_reg.h.

#define RADEON_SURFACE3_UPPER_BOUND 0x0b38

Definition at line 1753 of file radeon_reg.h.

#define RADEON_SURFACE4_INFO 0x0b4c

Definition at line 1754 of file radeon_reg.h.

#define RADEON_SURFACE4_LOWER_BOUND 0x0b44

Definition at line 1755 of file radeon_reg.h.

#define RADEON_SURFACE4_UPPER_BOUND 0x0b48

Definition at line 1756 of file radeon_reg.h.

#define RADEON_SURFACE5_INFO 0x0b5c

Definition at line 1757 of file radeon_reg.h.

#define RADEON_SURFACE5_LOWER_BOUND 0x0b54

Definition at line 1758 of file radeon_reg.h.

#define RADEON_SURFACE5_UPPER_BOUND 0x0b58

Definition at line 1759 of file radeon_reg.h.

#define RADEON_SURFACE6_INFO 0x0b6c

Definition at line 1760 of file radeon_reg.h.

#define RADEON_SURFACE6_LOWER_BOUND 0x0b64

Definition at line 1761 of file radeon_reg.h.

#define RADEON_SURFACE6_UPPER_BOUND 0x0b68

Definition at line 1762 of file radeon_reg.h.

#define RADEON_SURFACE7_INFO 0x0b7c

Definition at line 1763 of file radeon_reg.h.

#define RADEON_SURFACE7_LOWER_BOUND 0x0b74

Definition at line 1764 of file radeon_reg.h.

#define RADEON_SURFACE7_UPPER_BOUND 0x0b78

Definition at line 1765 of file radeon_reg.h.

#define RADEON_SURFACE_CNTL 0x0b00

Definition at line 1719 of file radeon_reg.h.

#define RADEON_SW_CAN_USE_DVI_I2C (1 << 13)

Definition at line 1113 of file radeon_reg.h.

#define RADEON_SW_DONE_USING_DVI_I2C (1 << 14)

Definition at line 1114 of file radeon_reg.h.

#define RADEON_SW_INT_ENABLE (1 << 25)

Definition at line 1018 of file radeon_reg.h.

#define RADEON_SW_INT_FIRE (1 << 26)

Definition at line 1031 of file radeon_reg.h.

#define RADEON_SW_INT_TEST (1 << 25)

Definition at line 1032 of file radeon_reg.h.

#define RADEON_SW_INT_TEST_ACK (1 << 25)

Definition at line 1033 of file radeon_reg.h.

#define RADEON_SW_SEMAPHORE 0x013c

Definition at line 1766 of file radeon_reg.h.

#define RADEON_SW_WANTS_TO_USE_DVI_I2C (1 << 13)

Definition at line 1112 of file radeon_reg.h.

#define RADEON_SWITCH_TO_BLUE (1 << 4)

Definition at line 3529 of file radeon_reg.h.

#define RADEON_SYNC_IN (1 << 2)

Definition at line 3544 of file radeon_reg.h.

#define RADEON_SYNC_OE (1 << 0)

Definition at line 3542 of file radeon_reg.h.

#define RADEON_SYNC_OUT (1 << 1)

Definition at line 3543 of file radeon_reg.h.

#define RADEON_SYNC_PD (1 << 4)

Definition at line 3546 of file radeon_reg.h.

#define RADEON_SYNC_PUB (1 << 3)

Definition at line 3545 of file radeon_reg.h.

#define RADEON_SYNC_TIP_LEVEL (1 << 7)

Definition at line 3604 of file radeon_reg.h.

#define RADEON_SYS_HOTKEY (1 << 10)

Definition at line 222 of file radeon_reg.h.

#define RADEON_T0_EQ_TCUR (1 << 24)

Definition at line 2175 of file radeon_reg.h.

#define RADEON_T1_EQ_TCUR (1 << 25)

Definition at line 2176 of file radeon_reg.h.

#define RADEON_T2_EQ_TCUR (1 << 26)

Definition at line 2177 of file radeon_reg.h.

#define RADEON_T3_EQ_TCUR (1 << 27)

Definition at line 2178 of file radeon_reg.h.

#define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00

Definition at line 3617 of file radeon_reg.h.

#define RADEON_TABLE1_BOT_ADR_SHIFT 8

Definition at line 3618 of file radeon_reg.h.

#define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000

Definition at line 3619 of file radeon_reg.h.

#define RADEON_TABLE3_TOP_ADR_SHIFT 16

Definition at line 3620 of file radeon_reg.h.

#define RADEON_TCL_BYPASS (1 << 8)

Definition at line 2463 of file radeon_reg.h.

#define RADEON_TCL_BYPASS_DISABLE (1 << 20)

Definition at line 363 of file radeon_reg.h.

#define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)

Definition at line 2561 of file radeon_reg.h.

#define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)

Definition at line 2562 of file radeon_reg.h.

#define RADEON_TCL_COMPUTE_XYZW (1 << 0)

Definition at line 2560 of file radeon_reg.h.

#define RADEON_TCL_FOG_DISABLE (0 << 8)

Definition at line 2643 of file radeon_reg.h.

#define RADEON_TCL_FOG_EXP (1 << 8)

Definition at line 2644 of file radeon_reg.h.

#define RADEON_TCL_FOG_EXP2 (2 << 8)

Definition at line 2645 of file radeon_reg.h.

#define RADEON_TCL_FOG_LINEAR (3 << 8)

Definition at line 2646 of file radeon_reg.h.

#define RADEON_TCL_FOG_MASK (3 << 8)

Definition at line 2642 of file radeon_reg.h.

#define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)

Definition at line 2564 of file radeon_reg.h.

#define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)

Definition at line 2563 of file radeon_reg.h.

#define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16

Definition at line 2573 of file radeon_reg.h.

#define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20

Definition at line 2574 of file radeon_reg.h.

#define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24

Definition at line 2575 of file radeon_reg.h.

#define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28

Definition at line 2576 of file radeon_reg.h.

#define RADEON_TCL_TEX_COMPUTED_TEX_0 8

Definition at line 2569 of file radeon_reg.h.

#define RADEON_TCL_TEX_COMPUTED_TEX_1 9

Definition at line 2570 of file radeon_reg.h.

#define RADEON_TCL_TEX_COMPUTED_TEX_2 10

Definition at line 2571 of file radeon_reg.h.

#define RADEON_TCL_TEX_COMPUTED_TEX_3 11

Definition at line 2572 of file radeon_reg.h.

#define RADEON_TCL_TEX_INPUT_TEX_0 0

Definition at line 2565 of file radeon_reg.h.

#define RADEON_TCL_TEX_INPUT_TEX_1 1

Definition at line 2566 of file radeon_reg.h.

#define RADEON_TCL_TEX_INPUT_TEX_2 2

Definition at line 2567 of file radeon_reg.h.

#define RADEON_TCL_TEX_INPUT_TEX_3 3

Definition at line 2568 of file radeon_reg.h.

#define RADEON_TCL_VTX_FP_ALPHA (1 << 2)

Definition at line 2538 of file radeon_reg.h.

#define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)

Definition at line 2537 of file radeon_reg.h.

#define RADEON_TCL_VTX_FP_FOG (1 << 5)

Definition at line 2541 of file radeon_reg.h.

#define RADEON_TCL_VTX_FP_SPEC (1 << 4)

Definition at line 2540 of file radeon_reg.h.

#define RADEON_TCL_VTX_NORM0 (1 << 18)

Definition at line 2552 of file radeon_reg.h.

#define RADEON_TCL_VTX_NORM1 (1 << 30)

Definition at line 2556 of file radeon_reg.h.

#define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)

Definition at line 2539 of file radeon_reg.h.

#define RADEON_TCL_VTX_PK_SPEC (1 << 6)

Definition at line 2542 of file radeon_reg.h.

#define RADEON_TCL_VTX_Q0 (1 << 14)

Definition at line 2550 of file radeon_reg.h.

#define RADEON_TCL_VTX_Q1 (1 << 9)

Definition at line 2545 of file radeon_reg.h.

#define RADEON_TCL_VTX_Q2 (1 << 11)

Definition at line 2547 of file radeon_reg.h.

#define RADEON_TCL_VTX_Q3 (1 << 13)

Definition at line 2549 of file radeon_reg.h.

#define RADEON_TCL_VTX_ST0 (1 << 7)

Definition at line 2543 of file radeon_reg.h.

#define RADEON_TCL_VTX_ST1 (1 << 8)

Definition at line 2544 of file radeon_reg.h.

#define RADEON_TCL_VTX_ST2 (1 << 10)

Definition at line 2546 of file radeon_reg.h.

#define RADEON_TCL_VTX_ST3 (1 << 12)

Definition at line 2548 of file radeon_reg.h.

#define RADEON_TCL_VTX_W0 (1 << 0)

Definition at line 2536 of file radeon_reg.h.

#define RADEON_TCL_VTX_W1 (1 << 29)

Definition at line 2555 of file radeon_reg.h.

#define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15

Definition at line 2551 of file radeon_reg.h.

#define RADEON_TCL_VTX_XY1 (1 << 27)

Definition at line 2553 of file radeon_reg.h.

#define RADEON_TCL_VTX_Z0 (1 << 31)

Definition at line 2557 of file radeon_reg.h.

#define RADEON_TCL_VTX_Z1 (1 << 28)

Definition at line 2554 of file radeon_reg.h.

#define RADEON_TEST_DEBUG_CNTL 0x0120

Definition at line 1768 of file radeon_reg.h.

#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001

Definition at line 1769 of file radeon_reg.h.

#define RADEON_TEST_DEBUG_MUX 0x0124

Definition at line 1771 of file radeon_reg.h.

#define RADEON_TEST_DEBUG_OUT 0x012c

Definition at line 1772 of file radeon_reg.h.

#define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)

Definition at line 2478 of file radeon_reg.h.

#define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)

Definition at line 2477 of file radeon_reg.h.

#define RADEON_TEX_0_ENABLE (1 << 4)

Definition at line 1872 of file radeon_reg.h.

#define RADEON_TEX_1_ENABLE (1 << 5)

Definition at line 1873 of file radeon_reg.h.

#define RADEON_TEX_2_ENABLE (1 << 6)

Definition at line 1874 of file radeon_reg.h.

#define RADEON_TEX_3_ENABLE (1 << 7)

Definition at line 1875 of file radeon_reg.h.

#define RADEON_TEX_3D_ENABLE_0 (1 << 29)

Definition at line 1893 of file radeon_reg.h.

#define RADEON_TEX_3D_ENABLE_1 (1 << 30)

Definition at line 1894 of file radeon_reg.h.

#define RADEON_TEX_BLEND_0_ENABLE (1 << 12)

Definition at line 1877 of file radeon_reg.h.

#define RADEON_TEX_BLEND_1_ENABLE (1 << 13)

Definition at line 1878 of file radeon_reg.h.

#define RADEON_TEX_BLEND_2_ENABLE (1 << 14)

Definition at line 1879 of file radeon_reg.h.

#define RADEON_TEX_BLEND_3_ENABLE (1 << 15)

Definition at line 1880 of file radeon_reg.h.

#define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)

Definition at line 1876 of file radeon_reg.h.

#define RADEON_TEX_ENABLE_MASK (0xf << 4)

Definition at line 1871 of file radeon_reg.h.

#define RADEON_TEX_USIZE_MASK (0x7ff << 0)

Definition at line 2084 of file radeon_reg.h.

#define RADEON_TEX_USIZE_SHIFT 0

Definition at line 2085 of file radeon_reg.h.

#define RADEON_TEX_VSIZE_MASK (0x7ff << 16)

Definition at line 2086 of file radeon_reg.h.

#define RADEON_TEX_VSIZE_SHIFT 16

Definition at line 2087 of file radeon_reg.h.

#define RADEON_TEXGEN_0_INPUT_SHIFT 16

Definition at line 2628 of file radeon_reg.h.

#define RADEON_TEXGEN_1_INPUT_SHIFT 20

Definition at line 2629 of file radeon_reg.h.

#define RADEON_TEXGEN_2_INPUT_SHIFT 24

Definition at line 2630 of file radeon_reg.h.

#define RADEON_TEXGEN_3_INPUT_SHIFT 28

Definition at line 2631 of file radeon_reg.h.

#define RADEON_TEXGEN_INPUT_EYE 5

Definition at line 2624 of file radeon_reg.h.

#define RADEON_TEXGEN_INPUT_EYE_NORMAL 6

Definition at line 2625 of file radeon_reg.h.

#define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8

Definition at line 2627 of file radeon_reg.h.

#define RADEON_TEXGEN_INPUT_EYE_REFLECT 7

Definition at line 2626 of file radeon_reg.h.

#define RADEON_TEXGEN_INPUT_MASK 0xf

Definition at line 2618 of file radeon_reg.h.

#define RADEON_TEXGEN_INPUT_OBJ 4

Definition at line 2623 of file radeon_reg.h.

#define RADEON_TEXGEN_INPUT_TEXCOORD_0 0

Definition at line 2619 of file radeon_reg.h.

#define RADEON_TEXGEN_INPUT_TEXCOORD_1 1

Definition at line 2620 of file radeon_reg.h.

#define RADEON_TEXGEN_INPUT_TEXCOORD_2 2

Definition at line 2621 of file radeon_reg.h.

#define RADEON_TEXGEN_INPUT_TEXCOORD_3 3

Definition at line 2622 of file radeon_reg.h.

#define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)

Definition at line 2610 of file radeon_reg.h.

#define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)

Definition at line 2611 of file radeon_reg.h.

#define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)

Definition at line 2612 of file radeon_reg.h.

#define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)

Definition at line 2613 of file radeon_reg.h.

#define RADEON_TEXMAT_0_ENABLE (1 << 4)

Definition at line 2614 of file radeon_reg.h.

#define RADEON_TEXMAT_0_SHIFT 16

Definition at line 2529 of file radeon_reg.h.

#define RADEON_TEXMAT_1_ENABLE (1 << 5)

Definition at line 2615 of file radeon_reg.h.

#define RADEON_TEXMAT_1_SHIFT 20

Definition at line 2530 of file radeon_reg.h.

#define RADEON_TEXMAT_2_ENABLE (1 << 6)

Definition at line 2616 of file radeon_reg.h.

#define RADEON_TEXMAT_2_SHIFT 24

Definition at line 2531 of file radeon_reg.h.

#define RADEON_TEXMAT_3_ENABLE (1 << 7)

Definition at line 2617 of file radeon_reg.h.

#define RADEON_TEXMAT_3_SHIFT 28

Definition at line 2532 of file radeon_reg.h.

#define RADEON_TMDS_PLL_CNTL 0x02a8

Definition at line 1773 of file radeon_reg.h.

#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4

Definition at line 1774 of file radeon_reg.h.

#define RADEON_TMDS_TRANSMITTER_PLLEN 1

Definition at line 1775 of file radeon_reg.h.

#define RADEON_TMDS_TRANSMITTER_PLLRST 2

Definition at line 1776 of file radeon_reg.h.

#define RADEON_TRAIL_BRES_DEC 0x1614

Definition at line 1777 of file radeon_reg.h.

#define RADEON_TRAIL_BRES_ERR 0x160c

Definition at line 1778 of file radeon_reg.h.

#define RADEON_TRAIL_BRES_INC 0x1610

Definition at line 1779 of file radeon_reg.h.

#define RADEON_TRAIL_X 0x1618

Definition at line 1780 of file radeon_reg.h.

#define RADEON_TRAIL_X_SUB 0x1620

Definition at line 1781 of file radeon_reg.h.

#define RADEON_TV1_ATTACHED_COMP (1 << 4)

Definition at line 171 of file radeon_reg.h.

#define RADEON_TV1_ATTACHED_MASK (3 << 4)

Definition at line 170 of file radeon_reg.h.

#define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)

Definition at line 172 of file radeon_reg.h.

#define RADEON_TV1_CRTC_MASK (1 << 10)

Definition at line 189 of file radeon_reg.h.

#define RADEON_TV1_CRTC_SHIFT 10

Definition at line 190 of file radeon_reg.h.

#define RADEON_TV1_ON (1 << 2)

Definition at line 180 of file radeon_reg.h.

#define RADEON_TV_ASYNC_RST (1 << 0)

Definition at line 3507 of file radeon_reg.h.

#define RADEON_TV_CRC_CNTL 0x0890

Definition at line 3613 of file radeon_reg.h.

#define RADEON_TV_DAC_BDACDET (1 << 31)

Definition at line 669 of file radeon_reg.h.

#define RADEON_TV_DAC_BDACPD (1 << 26)

Definition at line 666 of file radeon_reg.h.

#define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)

Definition at line 660 of file radeon_reg.h.

#define RADEON_TV_DAC_BGADJ_SHIFT 16

Definition at line 661 of file radeon_reg.h.

#define RADEON_TV_DAC_BGSLEEP (1 << 6)

Definition at line 659 of file radeon_reg.h.

#define RADEON_TV_DAC_CMPOUT (1 << 5)

Definition at line 653 of file radeon_reg.h.

#define RADEON_TV_DAC_CNTL 0x088c

Definition at line 648 of file radeon_reg.h.

#define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)

Definition at line 662 of file radeon_reg.h.

#define RADEON_TV_DAC_DACADJ_SHIFT 20

Definition at line 663 of file radeon_reg.h.

#define RADEON_TV_DAC_GDACDET (1 << 30)

Definition at line 668 of file radeon_reg.h.

#define RADEON_TV_DAC_GDACPD (1 << 25)

Definition at line 665 of file radeon_reg.h.

#define RADEON_TV_DAC_NBLANK (1 << 0)

Definition at line 649 of file radeon_reg.h.

#define RADEON_TV_DAC_NHOLD (1 << 1)

Definition at line 650 of file radeon_reg.h.

#define RADEON_TV_DAC_PEDESTAL (1 << 2)

Definition at line 651 of file radeon_reg.h.

#define RADEON_TV_DAC_RDACDET (1 << 29)

Definition at line 667 of file radeon_reg.h.

#define RADEON_TV_DAC_RDACPD (1 << 24)

Definition at line 664 of file radeon_reg.h.

#define RADEON_TV_DAC_STD_MASK (3 << 8)

Definition at line 654 of file radeon_reg.h.

#define RADEON_TV_DAC_STD_NTSC (1 << 8)

Definition at line 656 of file radeon_reg.h.

#define RADEON_TV_DAC_STD_PAL (0 << 8)

Definition at line 655 of file radeon_reg.h.

#define RADEON_TV_DAC_STD_PS2 (2 << 8)

Definition at line 657 of file radeon_reg.h.

#define RADEON_TV_DAC_STD_RS343 (3 << 8)

Definition at line 658 of file radeon_reg.h.

#define RADEON_TV_DPMS_ON (1 << 22)

Definition at line 211 of file radeon_reg.h.

#define RADEON_TV_DTO_EN (1 << 28)

Definition at line 3639 of file radeon_reg.h.

#define RADEON_TV_ENABLE_RST (1 << 25)

Definition at line 646 of file radeon_reg.h.

#define RADEON_TV_FCOUNT 0x0830

Definition at line 3556 of file radeon_reg.h.

#define RADEON_TV_FIFO_ASYNC_RST (1 << 4)

Definition at line 3510 of file radeon_reg.h.

#define RADEON_TV_FIFO_CE_EN (1 << 10)

Definition at line 3515 of file radeon_reg.h.

#define RADEON_TV_FORCE_DAC_DATA_SHIFT 16

Definition at line 3527 of file radeon_reg.h.

#define RADEON_TV_FRESTART 0x0834

Definition at line 3557 of file radeon_reg.h.

#define RADEON_TV_FTOTAL 0x082c

Definition at line 3555 of file radeon_reg.h.

#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868

Definition at line 3594 of file radeon_reg.h.

#define RADEON_TV_HCOUNT 0x081C

Definition at line 3551 of file radeon_reg.h.

#define RADEON_TV_HDISP 0x0810

Definition at line 3549 of file radeon_reg.h.

#define RADEON_TV_HOST_RD_WT_CNTL 0x0848

Definition at line 3562 of file radeon_reg.h.

#define RADEON_TV_HOST_READ_DATA 0x0840

Definition at line 3560 of file radeon_reg.h.

#define RADEON_TV_HOST_WRITE_DATA 0x0844

Definition at line 3561 of file radeon_reg.h.

#define RADEON_TV_HRESTART 0x0838

Definition at line 3558 of file radeon_reg.h.

#define RADEON_TV_HSTART 0x0818

Definition at line 3550 of file radeon_reg.h.

#define RADEON_TV_HTOTAL 0x080c

Definition at line 3548 of file radeon_reg.h.

#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c

Definition at line 3597 of file radeon_reg.h.

#define RADEON_TV_M0HI_MASK 0x7

Definition at line 3630 of file radeon_reg.h.

#define RADEON_TV_M0HI_SHIFT 18

Definition at line 3631 of file radeon_reg.h.

#define RADEON_TV_M0LO_MASK 0xff

Definition at line 3629 of file radeon_reg.h.

#define RADEON_TV_MASTER_CNTL 0x0800

Definition at line 3506 of file radeon_reg.h.

#define RADEON_TV_MAX_FIFO_ADDR 0x1a7

Definition at line 3625 of file radeon_reg.h.

#define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff

Definition at line 3626 of file radeon_reg.h.

#define RADEON_TV_MODULATOR_CNTL1 0x0870

Definition at line 3600 of file radeon_reg.h.

#define RADEON_TV_MODULATOR_CNTL2 0x0874

Definition at line 3609 of file radeon_reg.h.

#define RADEON_TV_MONITOR_DETECT_EN (1 << 4)

Definition at line 652 of file radeon_reg.h.

#define RADEON_TV_N0HI_MASK 0x3

Definition at line 3634 of file radeon_reg.h.

#define RADEON_TV_N0HI_SHIFT 21

Definition at line 3635 of file radeon_reg.h.

#define RADEON_TV_N0LO_MASK 0x1ff

Definition at line 3632 of file radeon_reg.h.

#define RADEON_TV_N0LO_SHIFT 8

Definition at line 3633 of file radeon_reg.h.

#define RADEON_TV_ON (1 << 31)

Definition at line 3518 of file radeon_reg.h.

#define RADEON_TV_P_MASK 0xf

Definition at line 3636 of file radeon_reg.h.

#define RADEON_TV_P_SHIFT 24

Definition at line 3637 of file radeon_reg.h.

#define RADEON_TV_PLL_CNTL 0x0021 /* PLL */

Definition at line 3628 of file radeon_reg.h.

#define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */

Definition at line 3640 of file radeon_reg.h.

#define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */

Definition at line 3627 of file radeon_reg.h.

#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888

Definition at line 3519 of file radeon_reg.h.

#define RADEON_TV_RGB_CNTL 0x0804

Definition at line 3528 of file radeon_reg.h.

#define RADEON_TV_SLIP_EN (1 << 23)

Definition at line 3638 of file radeon_reg.h.

#define RADEON_TV_SYNC_CNTL 0x0808

Definition at line 3541 of file radeon_reg.h.

#define RADEON_TV_SYNC_IO_DRIVE (1 << 5)

Definition at line 3547 of file radeon_reg.h.

#define RADEON_TV_TIMING_CNTL 0x0850

Definition at line 3573 of file radeon_reg.h.

#define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff

Definition at line 3610 of file radeon_reg.h.

#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864

Definition at line 3591 of file radeon_reg.h.

#define RADEON_TV_UV_ADR 0x08ac

Definition at line 3614 of file radeon_reg.h.

#define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff

Definition at line 3611 of file radeon_reg.h.

#define RADEON_TV_V_BURST_LEVEL_SHIFT 16

Definition at line 3612 of file radeon_reg.h.

#define RADEON_TV_VCOUNT 0x0828

Definition at line 3554 of file radeon_reg.h.

#define RADEON_TV_VDISP 0x0824

Definition at line 3553 of file radeon_reg.h.

#define RADEON_TV_VRESTART 0x083c

Definition at line 3559 of file radeon_reg.h.

#define RADEON_TV_VSCALER_CNTL1 0x084c

Definition at line 3567 of file radeon_reg.h.

#define RADEON_TV_VSCALER_CNTL2 0x0854

Definition at line 3580 of file radeon_reg.h.

#define RADEON_TV_VTOTAL 0x0820

Definition at line 3552 of file radeon_reg.h.

#define RADEON_TV_Y_FALL_CNTL 0x0858

Definition at line 3585 of file radeon_reg.h.

#define RADEON_TV_Y_RISE_CNTL 0x085c

Definition at line 3588 of file radeon_reg.h.

#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860

Definition at line 3590 of file radeon_reg.h.

#define RADEON_TVCLK_ALWAYS_ONb (1 << 30)

Definition at line 3517 of file radeon_reg.h.

#define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)

Definition at line 3651 of file radeon_reg.h.

#define RADEON_TVCLK_TURNOFF (1 << 31)

Definition at line 360 of file radeon_reg.h.

#define RADEON_TVOUT_SCALE_EN (1 << 26)

Definition at line 3539 of file radeon_reg.h.

#define RADEON_TVPCP_MASK (7 << 8)

Definition at line 3645 of file radeon_reg.h.

#define RADEON_TVPCP_SHIFT 8

Definition at line 3644 of file radeon_reg.h.

#define RADEON_TVPDC_MASK (3 << 14)

Definition at line 3649 of file radeon_reg.h.

#define RADEON_TVPDC_SHIFT 14

Definition at line 3648 of file radeon_reg.h.

#define RADEON_TVPLL_PWRMGT_OFF (1 << 30)

Definition at line 359 of file radeon_reg.h.

#define RADEON_TVPLL_REFCLK_SEL (1 << 4)

Definition at line 3643 of file radeon_reg.h.

#define RADEON_TVPLL_RESET (1 << 1)

Definition at line 3641 of file radeon_reg.h.

#define RADEON_TVPLL_SLEEP (1 << 3)

Definition at line 3642 of file radeon_reg.h.

#define RADEON_TVPLL_TEST_DIS (1 << 31)

Definition at line 3650 of file radeon_reg.h.

#define RADEON_TVPVG_MASK (7 << 11)

Definition at line 3647 of file radeon_reg.h.

#define RADEON_TVPVG_SHIFT 11

Definition at line 3646 of file radeon_reg.h.

#define RADEON_TXFORMAT_AI88 (1 << 0)

Definition at line 1987 of file radeon_reg.h.

#define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)

Definition at line 2008 of file radeon_reg.h.

#define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)

Definition at line 2026 of file radeon_reg.h.

#define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)

Definition at line 2007 of file radeon_reg.h.

#define RADEON_TXFORMAT_ARGB1555 (3 << 0)

Definition at line 1989 of file radeon_reg.h.

#define RADEON_TXFORMAT_ARGB4444 (5 << 0)

Definition at line 1991 of file radeon_reg.h.

#define RADEON_TXFORMAT_ARGB8888 (6 << 0)

Definition at line 1992 of file radeon_reg.h.

#define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)

Definition at line 2027 of file radeon_reg.h.

#define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)

Definition at line 2028 of file radeon_reg.h.

#define RADEON_TXFORMAT_DUDV88 (18 << 0)

Definition at line 2002 of file radeon_reg.h.

#define RADEON_TXFORMAT_DXT1 (12 << 0)

Definition at line 1997 of file radeon_reg.h.

#define RADEON_TXFORMAT_DXT23 (14 << 0)

Definition at line 1998 of file radeon_reg.h.

#define RADEON_TXFORMAT_DXT45 (15 << 0)

Definition at line 1999 of file radeon_reg.h.

#define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)

Definition at line 2023 of file radeon_reg.h.

#define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)

Definition at line 2024 of file radeon_reg.h.

#define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)

Definition at line 2025 of file radeon_reg.h.

#define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)

Definition at line 2022 of file radeon_reg.h.

#define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)

Definition at line 2016 of file radeon_reg.h.

#define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20

Definition at line 2017 of file radeon_reg.h.

#define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)

Definition at line 2014 of file radeon_reg.h.

#define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16

Definition at line 2015 of file radeon_reg.h.

#define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)

Definition at line 2005 of file radeon_reg.h.

#define RADEON_TXFORMAT_FORMAT_SHIFT 0

Definition at line 2006 of file radeon_reg.h.

#define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)

Definition at line 2012 of file radeon_reg.h.

#define RADEON_TXFORMAT_HEIGHT_SHIFT 12

Definition at line 2013 of file radeon_reg.h.

#define RADEON_TXFORMAT_I8 (0 << 0)

Definition at line 1986 of file radeon_reg.h.

#define RADEON_TXFORMAT_LDUDUV8888 (20 << 0)

Definition at line 2004 of file radeon_reg.h.

#define RADEON_TXFORMAT_LDUDV655 (19 << 0)

Definition at line 2003 of file radeon_reg.h.

#define RADEON_TXFORMAT_NON_POWER2 (1 << 7)

Definition at line 2009 of file radeon_reg.h.

#define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)

Definition at line 2029 of file radeon_reg.h.

#define RADEON_TXFORMAT_RGB332 (2 << 0)

Definition at line 1988 of file radeon_reg.h.

#define RADEON_TXFORMAT_RGB565 (4 << 0)

Definition at line 1990 of file radeon_reg.h.

#define RADEON_TXFORMAT_RGBA8888 (7 << 0)

Definition at line 1993 of file radeon_reg.h.

#define RADEON_TXFORMAT_SHADOW16 (16 << 0)

Definition at line 2000 of file radeon_reg.h.

#define RADEON_TXFORMAT_SHADOW32 (17 << 0)

Definition at line 2001 of file radeon_reg.h.

#define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)

Definition at line 2019 of file radeon_reg.h.

#define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)

Definition at line 2018 of file radeon_reg.h.

#define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)

Definition at line 2020 of file radeon_reg.h.

#define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)

Definition at line 2021 of file radeon_reg.h.

#define RADEON_TXFORMAT_VYUY422 (10 << 0)

Definition at line 1995 of file radeon_reg.h.

#define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)

Definition at line 2010 of file radeon_reg.h.

#define RADEON_TXFORMAT_WIDTH_SHIFT 8

Definition at line 2011 of file radeon_reg.h.

#define RADEON_TXFORMAT_Y8 (8 << 0)

Definition at line 1994 of file radeon_reg.h.

#define RADEON_TXFORMAT_YVYU422 (11 << 0)

Definition at line 1996 of file radeon_reg.h.

#define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)

Definition at line 2054 of file radeon_reg.h.

#define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)

Definition at line 2056 of file radeon_reg.h.

#define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)

Definition at line 2053 of file radeon_reg.h.

#define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)

Definition at line 2055 of file radeon_reg.h.

#define RADEON_TXO_MACRO_LINEAR (0 << 2)

Definition at line 2057 of file radeon_reg.h.

#define RADEON_TXO_MACRO_TILE (1 << 2)

Definition at line 2058 of file radeon_reg.h.

#define RADEON_TXO_MICRO_LINEAR (0 << 3)

Definition at line 2059 of file radeon_reg.h.

#define RADEON_TXO_MICRO_TILE_OPT (2 << 3)

Definition at line 2061 of file radeon_reg.h.

#define RADEON_TXO_MICRO_TILE_X2 (1 << 3)

Definition at line 2060 of file radeon_reg.h.

#define RADEON_TXO_OFFSET_MASK 0xffffffe0

Definition at line 2062 of file radeon_reg.h.

#define RADEON_TXO_OFFSET_SHIFT 5

Definition at line 2063 of file radeon_reg.h.

#define RADEON_UCP_ENABLE_0 (1 << 2)

Definition at line 2636 of file radeon_reg.h.

#define RADEON_UCP_ENABLE_1 (1 << 3)

Definition at line 2637 of file radeon_reg.h.

#define RADEON_UCP_ENABLE_2 (1 << 4)

Definition at line 2638 of file radeon_reg.h.

#define RADEON_UCP_ENABLE_3 (1 << 5)

Definition at line 2639 of file radeon_reg.h.

#define RADEON_UCP_ENABLE_4 (1 << 6)

Definition at line 2640 of file radeon_reg.h.

#define RADEON_UCP_ENABLE_5 (1 << 7)

Definition at line 2641 of file radeon_reg.h.

#define RADEON_UCP_IN_CLIP_SPACE (1 << 0)

Definition at line 2634 of file radeon_reg.h.

#define RADEON_UCP_IN_MODEL_SPACE (1 << 1)

Definition at line 2635 of file radeon_reg.h.

#define RADEON_UV_GAIN_LIMIT_SHIFT 16

Definition at line 3596 of file radeon_reg.h.

#define RADEON_UV_GAIN_SHIFT 16

Definition at line 3599 of file radeon_reg.h.

#define RADEON_UV_INC_MASK 0xffff

Definition at line 3568 of file radeon_reg.h.

#define RADEON_UV_INC_SHIFT 0

Definition at line 3569 of file radeon_reg.h.

#define RADEON_UV_OUTPUT_DITHER_EN (1 << 2)

Definition at line 3583 of file radeon_reg.h.

#define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24

Definition at line 3579 of file radeon_reg.h.

#define RADEON_UV_POST_SCALE_BYPASS (1 << 23)

Definition at line 3578 of file radeon_reg.h.

#define RADEON_UV_TO_BUF_DITHER_EN (1 << 3)

Definition at line 3584 of file radeon_reg.h.

#define RADEON_UVFLT_EN (1 << 3)

Definition at line 3602 of file radeon_reg.h.

#define RADEON_UVRAM_READ_MARGIN_SHIFT 16

Definition at line 3536 of file radeon_reg.h.

#define RADEON_UVUPSAMP_EN (1 << 2)

Definition at line 3593 of file radeon_reg.h.

#define RADEON_VC_16BIT_SWAP (1 << 0)

Definition at line 2460 of file radeon_reg.h.

#define RADEON_VC_32BIT_SWAP (2 << 0)

Definition at line 2461 of file radeon_reg.h.

#define RADEON_VC_HALF_DWORD_SWAP (3 << 0)

Definition at line 2462 of file radeon_reg.h.

#define RADEON_VC_NO_SWAP (0 << 0)

Definition at line 2459 of file radeon_reg.h.

#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */

Definition at line 1783 of file radeon_reg.h.

#define RADEON_VCLK_SRC_SEL_BYTECLK 0x02

Definition at line 1787 of file radeon_reg.h.

#define RADEON_VCLK_SRC_SEL_CPUCLK 0x00

Definition at line 1785 of file radeon_reg.h.

#define RADEON_VCLK_SRC_SEL_MASK 0x03

Definition at line 1784 of file radeon_reg.h.

#define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03

Definition at line 1788 of file radeon_reg.h.

#define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01

Definition at line 1786 of file radeon_reg.h.

#define RADEON_VCODE_TABLE_SEL_MASK 0x18000000

Definition at line 3623 of file radeon_reg.h.

#define RADEON_VCODE_TABLE_SEL_SHIFT 27

Definition at line 3624 of file radeon_reg.h.

#define RADEON_VENDOR_ID 0x0f00 /* PCI */

Definition at line 1793 of file radeon_reg.h.

#define RADEON_VERT_AUTO_RATIO_EN (1 << 27)

Definition at line 981 of file radeon_reg.h.

#define RADEON_VERT_AUTO_RATIO_INC (1 << 31)

Definition at line 982 of file radeon_reg.h.

#define RADEON_VERT_PANEL_SHIFT 12

Definition at line 974 of file radeon_reg.h.

#define RADEON_VERT_PANEL_SIZE (0xfff << 12)

Definition at line 973 of file radeon_reg.h.

#define RADEON_VERT_STRETCH_BLEND (1 << 26)

Definition at line 980 of file radeon_reg.h.

#define RADEON_VERT_STRETCH_ENABLE (1 << 25)

Definition at line 978 of file radeon_reg.h.

#define RADEON_VERT_STRETCH_LINEREP (0 << 26)

Definition at line 979 of file radeon_reg.h.

#define RADEON_VERT_STRETCH_RATIO_MASK 0xfff

Definition at line 975 of file radeon_reg.h.

#define RADEON_VERT_STRETCH_RATIO_MAX 4096

Definition at line 977 of file radeon_reg.h.

#define RADEON_VERT_STRETCH_RATIO_SHIFT 0

Definition at line 976 of file radeon_reg.h.

#define RADEON_VERT_STRETCH_RESERVED 0x71000000

Definition at line 983 of file radeon_reg.h.

#define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)

Definition at line 2653 of file radeon_reg.h.

#define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)

Definition at line 2654 of file radeon_reg.h.

#define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)

Definition at line 2655 of file radeon_reg.h.

#define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)

Definition at line 2656 of file radeon_reg.h.

#define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)

Definition at line 2657 of file radeon_reg.h.

#define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)

Definition at line 2658 of file radeon_reg.h.

#define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)

Definition at line 2659 of file radeon_reg.h.

#define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)

Definition at line 2660 of file radeon_reg.h.

#define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)

Definition at line 2661 of file radeon_reg.h.

#define RADEON_VF_COLOR_ORDER_RGBA (1<<6)

Definition at line 2722 of file radeon_reg.h.

#define RADEON_VF_INDEX_SIZE_SHIFT 11

Definition at line 2726 of file radeon_reg.h.

#define RADEON_VF_NUM_VERTICES_SHIFT 16

Definition at line 2727 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_LINE_LIST 2

Definition at line 2704 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10

Definition at line 2712 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_LINE_LOOP 12

Definition at line 2714 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_LINE_STRIP 3

Definition at line 2705 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_POINT_LIST 1

Definition at line 2703 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9

Definition at line 2711 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_POLYGON 15

Definition at line 2717 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_QUAD_LIST 13

Definition at line 2715 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14

Definition at line 2716 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8

Definition at line 2710 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11

Definition at line 2713 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5

Definition at line 2707 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7

Definition at line 2709 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4

Definition at line 2706 of file radeon_reg.h.

#define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6

Definition at line 2708 of file radeon_reg.h.

#define RADEON_VF_PRIM_WALK_DATA (3<<4)

Definition at line 2721 of file radeon_reg.h.

#define RADEON_VF_PRIM_WALK_INDEX (1<<4)

Definition at line 2719 of file radeon_reg.h.

#define RADEON_VF_PRIM_WALK_LIST (2<<4)

Definition at line 2720 of file radeon_reg.h.

#define RADEON_VF_PRIM_WALK_STATE (0<<4)

Definition at line 2718 of file radeon_reg.h.

#define RADEON_VF_PROG_STREAM_ENA (1<<10)

Definition at line 2725 of file radeon_reg.h.

#define RADEON_VF_RADEON_MODE (1<<8)

Definition at line 2723 of file radeon_reg.h.

#define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)

Definition at line 2724 of file radeon_reg.h.

#define RADEON_VGA_ATI_LINEAR (1 << 3)

Definition at line 423 of file radeon_reg.h.

#define RADEON_VGA_DDA_CONFIG 0x02e8

Definition at line 1794 of file radeon_reg.h.

#define RADEON_VGA_DDA_ON_OFF 0x02ec

Definition at line 1795 of file radeon_reg.h.

#define RADEON_VID_BUFFER_CONTROL 0x0900

Definition at line 1796 of file radeon_reg.h.

#define RADEON_VID_BUFFER_CONTROL 0x0900

Definition at line 1796 of file radeon_reg.h.

#define RADEON_VIDEO_KEY_FN_EQ 0x00000002L

Definition at line 1309 of file radeon_reg.h.

#define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L

Definition at line 1307 of file radeon_reg.h.

#define RADEON_VIDEO_KEY_FN_MASK 0x00000003L

Definition at line 1306 of file radeon_reg.h.

#define RADEON_VIDEO_KEY_FN_NE 0x00000003L

Definition at line 1310 of file radeon_reg.h.

#define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L

Definition at line 1308 of file radeon_reg.h.

#define RADEON_VIDEOMUX_CNTL 0x0190

Definition at line 1797 of file radeon_reg.h.

#define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L

Definition at line 1384 of file radeon_reg.h.

#define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L

Definition at line 1383 of file radeon_reg.h.

#define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L

Definition at line 1381 of file radeon_reg.h.

#define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L

Definition at line 1382 of file radeon_reg.h.

#define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L

Definition at line 1389 of file radeon_reg.h.

#define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L

Definition at line 1388 of file radeon_reg.h.

#define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L

Definition at line 1386 of file radeon_reg.h.

#define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L

Definition at line 1387 of file radeon_reg.h.

#define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L

Definition at line 1394 of file radeon_reg.h.

#define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L

Definition at line 1393 of file radeon_reg.h.

#define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L

Definition at line 1391 of file radeon_reg.h.

#define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L

Definition at line 1392 of file radeon_reg.h.

#define RADEON_VIN_ASYNC_RST (1 << 5)

Definition at line 3511 of file radeon_reg.h.

#define RADEON_VIP_BUSY 0

Definition at line 1817 of file radeon_reg.h.

#define RADEON_VIP_IDLE 1

Definition at line 1818 of file radeon_reg.h.

#define RADEON_VIP_RESET 2

Definition at line 1819 of file radeon_reg.h.

#define RADEON_VIPH_BM_CHUNK 0x0c48

Definition at line 1822 of file radeon_reg.h.

#define RADEON_VIPH_CH0_ABCNT 0x0c30

Definition at line 1812 of file radeon_reg.h.

#define RADEON_VIPH_CH0_ADDR 0x0c10

Definition at line 1804 of file radeon_reg.h.

#define RADEON_VIPH_CH0_DATA 0x0c00

Definition at line 1800 of file radeon_reg.h.

#define RADEON_VIPH_CH0_SBCNT 0x0c20

Definition at line 1808 of file radeon_reg.h.

#define RADEON_VIPH_CH1_ABCNT 0x0c34

Definition at line 1813 of file radeon_reg.h.

#define RADEON_VIPH_CH1_ADDR 0x0c14

Definition at line 1805 of file radeon_reg.h.

#define RADEON_VIPH_CH1_DATA 0x0c04

Definition at line 1801 of file radeon_reg.h.

#define RADEON_VIPH_CH1_SBCNT 0x0c24

Definition at line 1809 of file radeon_reg.h.

#define RADEON_VIPH_CH2_ABCNT 0x0c38

Definition at line 1814 of file radeon_reg.h.

#define RADEON_VIPH_CH2_ADDR 0x0c18

Definition at line 1806 of file radeon_reg.h.

#define RADEON_VIPH_CH2_DATA 0x0c08

Definition at line 1802 of file radeon_reg.h.

#define RADEON_VIPH_CH2_SBCNT 0x0c28

Definition at line 1810 of file radeon_reg.h.

#define RADEON_VIPH_CH3_ABCNT 0x0c3c

Definition at line 1815 of file radeon_reg.h.

#define RADEON_VIPH_CH3_ADDR 0x0c1c

Definition at line 1807 of file radeon_reg.h.

#define RADEON_VIPH_CH3_DATA 0x0c0c

Definition at line 1803 of file radeon_reg.h.

#define RADEON_VIPH_CH3_SBCNT 0x0c2c

Definition at line 1811 of file radeon_reg.h.

#define RADEON_VIPH_CONTROL 0x0c40

Definition at line 1816 of file radeon_reg.h.

#define RADEON_VIPH_DV_INT 0x0c4c

Definition at line 1823 of file radeon_reg.h.

#define RADEON_VIPH_DV_LAT 0x0c44

Definition at line 1821 of file radeon_reg.h.

#define RADEON_VIPH_EN (1 << 21)

Definition at line 1820 of file radeon_reg.h.

#define RADEON_VIPH_REG_ADDR 0x0080

Definition at line 1830 of file radeon_reg.h.

#define RADEON_VIPH_REG_DATA 0x0084

Definition at line 1829 of file radeon_reg.h.

#define RADEON_VIPH_TIMEOUT_STAT 0x0c50

Definition at line 1824 of file radeon_reg.h.

#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010

Definition at line 1826 of file radeon_reg.h.

#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010

Definition at line 1825 of file radeon_reg.h.

#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000

Definition at line 1827 of file radeon_reg.h.

#define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)

Definition at line 2434 of file radeon_reg.h.

#define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)

Definition at line 2435 of file radeon_reg.h.

#define RADEON_VS_EYE_VECTOR_ADDR 124

Definition at line 3493 of file radeon_reg.h.

#define RADEON_VS_FOG_PARAM_ADDR 123

Definition at line 3492 of file radeon_reg.h.

#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122

Definition at line 3491 of file radeon_reg.h.

#define RADEON_VS_LIGHT_AMBIENT_ADDR 64

Definition at line 3483 of file radeon_reg.h.

#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104

Definition at line 3488 of file radeon_reg.h.

#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72

Definition at line 3484 of file radeon_reg.h.

#define RADEON_VS_LIGHT_DIRPOS_ADDR 88

Definition at line 3486 of file radeon_reg.h.

#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96

Definition at line 3487 of file radeon_reg.h.

#define RADEON_VS_LIGHT_SPECULAR_ADDR 80

Definition at line 3485 of file radeon_reg.h.

#define RADEON_VS_MATRIX_0_ADDR 0

Definition at line 3467 of file radeon_reg.h.

#define RADEON_VS_MATRIX_10_ADDR 40

Definition at line 3477 of file radeon_reg.h.

#define RADEON_VS_MATRIX_11_ADDR 44

Definition at line 3478 of file radeon_reg.h.

#define RADEON_VS_MATRIX_12_ADDR 48

Definition at line 3479 of file radeon_reg.h.

#define RADEON_VS_MATRIX_13_ADDR 52

Definition at line 3480 of file radeon_reg.h.

#define RADEON_VS_MATRIX_14_ADDR 56

Definition at line 3481 of file radeon_reg.h.

#define RADEON_VS_MATRIX_15_ADDR 60

Definition at line 3482 of file radeon_reg.h.

#define RADEON_VS_MATRIX_1_ADDR 4

Definition at line 3468 of file radeon_reg.h.

#define RADEON_VS_MATRIX_2_ADDR 8

Definition at line 3469 of file radeon_reg.h.

#define RADEON_VS_MATRIX_3_ADDR 12

Definition at line 3470 of file radeon_reg.h.

#define RADEON_VS_MATRIX_4_ADDR 16

Definition at line 3471 of file radeon_reg.h.

#define RADEON_VS_MATRIX_5_ADDR 20

Definition at line 3472 of file radeon_reg.h.

#define RADEON_VS_MATRIX_6_ADDR 24

Definition at line 3473 of file radeon_reg.h.

#define RADEON_VS_MATRIX_7_ADDR 28

Definition at line 3474 of file radeon_reg.h.

#define RADEON_VS_MATRIX_8_ADDR 32

Definition at line 3475 of file radeon_reg.h.

#define RADEON_VS_MATRIX_9_ADDR 36

Definition at line 3476 of file radeon_reg.h.

#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112

Definition at line 3489 of file radeon_reg.h.

#define RADEON_VS_UCP_ADDR 116

Definition at line 3490 of file radeon_reg.h.

#define RADEON_VTX_PIX_CENTER_D3D (0 << 27)

Definition at line 2436 of file radeon_reg.h.

#define RADEON_VTX_PIX_CENTER_OGL (1 << 27)

Definition at line 2437 of file radeon_reg.h.

#define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)

Definition at line 2467 of file radeon_reg.h.

#define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)

Definition at line 2473 of file radeon_reg.h.

#define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)

Definition at line 2468 of file radeon_reg.h.

#define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)

Definition at line 2474 of file radeon_reg.h.

#define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)

Definition at line 2469 of file radeon_reg.h.

#define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)

Definition at line 2475 of file radeon_reg.h.

#define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)

Definition at line 2470 of file radeon_reg.h.

#define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)

Definition at line 2476 of file radeon_reg.h.

#define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)

Definition at line 2472 of file radeon_reg.h.

#define RADEON_VTX_W0_NORMALIZE (1 << 12)

Definition at line 2471 of file radeon_reg.h.

#define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)

Definition at line 2465 of file radeon_reg.h.

#define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)

Definition at line 2466 of file radeon_reg.h.

#define RADEON_WAIT_2D_IDLE (1 << 14)

Definition at line 1843 of file radeon_reg.h.

#define RADEON_WAIT_2D_IDLECLEAN (1 << 16)

Definition at line 1845 of file radeon_reg.h.

#define RADEON_WAIT_3D_IDLE (1 << 15)

Definition at line 1844 of file radeon_reg.h.

#define RADEON_WAIT_3D_IDLECLEAN (1 << 17)

Definition at line 1846 of file radeon_reg.h.

#define RADEON_WAIT_AGP_FLUSH (1 << 13)

Definition at line 1842 of file radeon_reg.h.

#define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)

Definition at line 1851 of file radeon_reg.h.

#define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */

Definition at line 1840 of file radeon_reg.h.

#define RADEON_WAIT_CRTC_PFLIP (1 << 0)

Definition at line 1834 of file radeon_reg.h.

#define RADEON_WAIT_CRTC_VLINE (1 << 3)

Definition at line 1837 of file radeon_reg.h.

#define RADEON_WAIT_DMA_GUI_IDLE (1 << 9)

Definition at line 1839 of file radeon_reg.h.

#define RADEON_WAIT_DMA_VID_IDLE (1 << 8)

Definition at line 1838 of file radeon_reg.h.

#define RADEON_WAIT_FE_CRTC_VLINE (1 << 2)

Definition at line 1836 of file radeon_reg.h.

#define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)

Definition at line 1847 of file radeon_reg.h.

#define RADEON_WAIT_OV0_FLIP (1 << 11)

Definition at line 1841 of file radeon_reg.h.

#define RADEON_WAIT_RE_CRTC_VLINE (1 << 1)

Definition at line 1835 of file radeon_reg.h.

#define RADEON_WAIT_UNTIL 0x1720

Definition at line 1833 of file radeon_reg.h.

#define RADEON_WAIT_VAP_IDLE (1 << 28)

Definition at line 1850 of file radeon_reg.h.

#define RADEON_WIDELINE_ENABLE (1 << 20)

Definition at line 2433 of file radeon_reg.h.

#define RADEON_WRAPEN_S (1 << 22)

Definition at line 1961 of file radeon_reg.h.

#define RADEON_WRAPEN_T (1 << 26)

Definition at line 1971 of file radeon_reg.h.

#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */

Definition at line 1855 of file radeon_reg.h.

#define RADEON_XCLK_CNTL 0x000d /* PLL */

Definition at line 1856 of file radeon_reg.h.

#define RADEON_XCRT_CNT_EN (1 << 6)

Definition at line 424 of file radeon_reg.h.

#define RADEON_XDLL_CNTL 0x000c /* PLL */

Definition at line 1857 of file radeon_reg.h.

#define RADEON_XPLL_CNTL 0x000b /* PLL */

Definition at line 1858 of file radeon_reg.h.

#define RADEON_Y_COEF_EN (1 << 17)

Definition at line 3587 of file radeon_reg.h.

#define RADEON_Y_DEL_W_SIG_SHIFT 26

Definition at line 3572 of file radeon_reg.h.

#define RADEON_Y_FALL_PING_PONG (1 << 16)

Definition at line 3586 of file radeon_reg.h.

#define RADEON_Y_GAIN_LIMIT_SHIFT 0

Definition at line 3595 of file radeon_reg.h.

#define RADEON_Y_GAIN_SHIFT 0

Definition at line 3598 of file radeon_reg.h.

#define RADEON_Y_OUTPUT_DITHER_EN (1 << 1)

Definition at line 3582 of file radeon_reg.h.

#define RADEON_Y_RED_EN (1 << 0)

Definition at line 3520 of file radeon_reg.h.

#define RADEON_Y_RISE_PING_PONG (1 << 16)

Definition at line 3589 of file radeon_reg.h.

#define RADEON_Y_W_EN (1 << 24)

Definition at line 3570 of file radeon_reg.h.

#define RADEON_YFLT_EN (1 << 2)

Definition at line 3601 of file radeon_reg.h.

#define RADEON_YUPSAMP_EN (1 << 0)

Definition at line 3592 of file radeon_reg.h.

#define RADEON_YUV_TEMPERATURE_COOL (0 << 21)

Definition at line 1958 of file radeon_reg.h.

#define RADEON_YUV_TEMPERATURE_HOT (1 << 21)

Definition at line 1959 of file radeon_reg.h.

#define RADEON_YUV_TEMPERATURE_MASK (1 << 21)

Definition at line 1960 of file radeon_reg.h.

#define RADEON_YUV_TO_RGB (1 << 20)

Definition at line 1957 of file radeon_reg.h.

#define RADEON_Z_COMPRESSION_ENABLE (1 << 28)

Definition at line 2368 of file radeon_reg.h.

#define RADEON_Z_ENABLE (1 << 8)

Definition at line 2262 of file radeon_reg.h.

#define RADEON_Z_TEST_ALWAYS (7 << 4)

Definition at line 2336 of file radeon_reg.h.

#define RADEON_Z_TEST_EQUAL (3 << 4)

Definition at line 2332 of file radeon_reg.h.

#define RADEON_Z_TEST_GEQUAL (4 << 4)

Definition at line 2333 of file radeon_reg.h.

#define RADEON_Z_TEST_GREATER (5 << 4)

Definition at line 2334 of file radeon_reg.h.

#define RADEON_Z_TEST_LEQUAL (2 << 4)

Definition at line 2331 of file radeon_reg.h.

#define RADEON_Z_TEST_LESS (1 << 4)

Definition at line 2330 of file radeon_reg.h.

#define RADEON_Z_TEST_MASK (7 << 4)

Definition at line 2337 of file radeon_reg.h.

#define RADEON_Z_TEST_NEQUAL (6 << 4)

Definition at line 2335 of file radeon_reg.h.

#define RADEON_Z_TEST_NEVER (0 << 4)

Definition at line 2329 of file radeon_reg.h.

#define RADEON_Z_WRITE_ENABLE (1 << 30)

Definition at line 2370 of file radeon_reg.h.

#define RADEON_ZBIAS_ENABLE_LINE (1 << 17)

Definition at line 2431 of file radeon_reg.h.

#define RADEON_ZBIAS_ENABLE_POINT (1 << 16)

Definition at line 2430 of file radeon_reg.h.

#define RADEON_ZBIAS_ENABLE_TRI (1 << 18)

Definition at line 2432 of file radeon_reg.h.

#define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff

Definition at line 3678 of file radeon_reg.h.

#define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22

Definition at line 3677 of file radeon_reg.h.

#define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff

Definition at line 3669 of file radeon_reg.h.

#define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12

Definition at line 3668 of file radeon_reg.h.

#define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff

Definition at line 3671 of file radeon_reg.h.

#define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22

Definition at line 3670 of file radeon_reg.h.

#define RS400_DISP1_REQ_CNTL1 0xe3c

Definition at line 3672 of file radeon_reg.h.

#define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff

Definition at line 3674 of file radeon_reg.h.

#define RS400_DISP1_START_REQ_LEVEL_SHIFT 0

Definition at line 3673 of file radeon_reg.h.

#define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff

Definition at line 3676 of file radeon_reg.h.

#define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12

Definition at line 3675 of file radeon_reg.h.

#define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff

Definition at line 3659 of file radeon_reg.h.

#define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22

Definition at line 3658 of file radeon_reg.h.

#define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff

Definition at line 3662 of file radeon_reg.h.

#define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12

Definition at line 3661 of file radeon_reg.h.

#define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff

Definition at line 3664 of file radeon_reg.h.

#define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22

Definition at line 3663 of file radeon_reg.h.

#define RS400_DISP2_REQ_CNTL1 0xe30

Definition at line 3653 of file radeon_reg.h.

#define RS400_DISP2_REQ_CNTL2 0xe34

Definition at line 3660 of file radeon_reg.h.

#define RS400_DISP2_START_ADR_MASK 0x3ff

Definition at line 3667 of file radeon_reg.h.

#define RS400_DISP2_START_ADR_SHIFT 0

Definition at line 3666 of file radeon_reg.h.

#define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff

Definition at line 3655 of file radeon_reg.h.

#define RS400_DISP2_START_REQ_LEVEL_SHIFT 0

Definition at line 3654 of file radeon_reg.h.

#define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff

Definition at line 3657 of file radeon_reg.h.

#define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12

Definition at line 3656 of file radeon_reg.h.

#define RS400_DMIF_MEM_CNTL1 0xe38

Definition at line 3665 of file radeon_reg.h.

#define RS400_FP2_2_BLANK_EN (1 << 1)

Definition at line 998 of file radeon_reg.h.

#define RS400_FP2_2_DETECT_SENSE (1 << 8)

Definition at line 1001 of file radeon_reg.h.

#define RS400_FP2_2_DVO2_EN (1 << 25)

Definition at line 1006 of file radeon_reg.h.

#define RS400_FP2_2_GEN_CNTL 0x0388

Definition at line 997 of file radeon_reg.h.

#define RS400_FP2_2_ON (1 << 2)

Definition at line 999 of file radeon_reg.h.

#define RS400_FP2_2_PANEL_FORMAT (1 << 3)

Definition at line 1000 of file radeon_reg.h.

#define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)

Definition at line 1003 of file radeon_reg.h.

#define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)

Definition at line 1004 of file radeon_reg.h.

#define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)

Definition at line 1002 of file radeon_reg.h.

#define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)

Definition at line 1005 of file radeon_reg.h.

#define RS400_FP_2ND_BLANK_EN (1 << 1)

Definition at line 986 of file radeon_reg.h.

#define RS400_FP_2ND_DETECT_EN (1 << 12)

Definition at line 995 of file radeon_reg.h.

#define RS400_FP_2ND_DETECT_SENSE (1 << 8)

Definition at line 990 of file radeon_reg.h.

#define RS400_FP_2ND_EN_TMDS (1 << 7)

Definition at line 989 of file radeon_reg.h.

#define RS400_FP_2ND_GEN_CNTL 0x0384

Definition at line 984 of file radeon_reg.h.

#define RS400_FP_2ND_ON (1 << 0)

Definition at line 985 of file radeon_reg.h.

#define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10)

Definition at line 992 of file radeon_reg.h.

#define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10)

Definition at line 993 of file radeon_reg.h.

#define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10)

Definition at line 991 of file radeon_reg.h.

#define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10)

Definition at line 994 of file radeon_reg.h.

#define RS400_HPD_2ND_SEL (1 << 13)

Definition at line 996 of file radeon_reg.h.

#define RS400_MSI_REARM (1 << 3) /* rs400/rs480 */

Definition at line 3367 of file radeon_reg.h.

#define RS400_PANEL_FORMAT_2ND (1 << 3)

Definition at line 988 of file radeon_reg.h.

#define RS400_TMDS2_CNTL 0x0394

Definition at line 1007 of file radeon_reg.h.

#define RS400_TMDS2_PLLEN (1 << 0)

Definition at line 1009 of file radeon_reg.h.

#define RS400_TMDS2_PLLRST (1 << 1)

Definition at line 1010 of file radeon_reg.h.

#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4

Definition at line 1008 of file radeon_reg.h.

#define RS400_TMDS_2ND_EN (1 << 2)

Definition at line 987 of file radeon_reg.h.

#define RS600_BUS_MASTER_DIS (1 << 14)

Definition at line 295 of file radeon_reg.h.

#define RS600_MSI_REARM (1 << 20) /* rs600/rs690/rs740 */

Definition at line 296 of file radeon_reg.h.

#define RV100_HALF_MODE (1 << 3)

Definition at line 1204 of file radeon_reg.h.

#define RV370_BUS_BIOS_DIS_ROM (1 << 2)

Definition at line 305 of file radeon_reg.h.

#define RV370_BUS_CNTL 0x004c

Definition at line 304 of file radeon_reg.h.

#define RV370_MSI_REARM_EN (1 << 0)

Definition at line 308 of file radeon_reg.h.

#define RV530_GB_PIPE_SELECT2 0x4124

Definition at line 3707 of file radeon_reg.h.

Macros

Macro Definition Documentation