Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
radeon_ring.c
Go to the documentation of this file.
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  * Alex Deucher
26  * Jerome Glisse
27  * Christian König
28  */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <drm/drmP.h>
32 #include <drm/radeon_drm.h>
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "atom.h"
36 
37 /*
38  * IB
39  * IBs (Indirect Buffers) and areas of GPU accessible memory where
40  * commands are stored. You can put a pointer to the IB in the
41  * command ring and the hw will fetch the commands from the IB
42  * and execute them. Generally userspace acceleration drivers
43  * produce command buffers which are send to the kernel and
44  * put in IBs for execution by the requested ring.
45  */
46 static int radeon_debugfs_sa_init(struct radeon_device *rdev);
47 
61  struct radeon_ib *ib, struct radeon_vm *vm,
62  unsigned size)
63 {
64  int i, r;
65 
66  r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true);
67  if (r) {
68  dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
69  return r;
70  }
71 
72  r = radeon_semaphore_create(rdev, &ib->semaphore);
73  if (r) {
74  return r;
75  }
76 
77  ib->ring = ring;
78  ib->fence = NULL;
79  ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
80  ib->vm = vm;
81  if (vm) {
82  /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
83  * space and soffset is the offset inside the pool bo
84  */
85  ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
86  } else {
87  ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
88  }
89  ib->is_const_ib = false;
90  for (i = 0; i < RADEON_NUM_RINGS; ++i)
91  ib->sync_to[i] = NULL;
92 
93  return 0;
94 }
95 
104 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
105 {
106  radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
107  radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
109 }
110 
132  struct radeon_ib *const_ib)
133 {
134  struct radeon_ring *ring = &rdev->ring[ib->ring];
135  bool need_sync = false;
136  int i, r = 0;
137 
138  if (!ib->length_dw || !ring->ready) {
139  /* TODO: Nothings in the ib we should report. */
140  dev_err(rdev->dev, "couldn't schedule ib\n");
141  return -EINVAL;
142  }
143 
144  /* 64 dwords should be enough for fence too */
145  r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8);
146  if (r) {
147  dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
148  return r;
149  }
150  for (i = 0; i < RADEON_NUM_RINGS; ++i) {
151  struct radeon_fence *fence = ib->sync_to[i];
152  if (radeon_fence_need_sync(fence, ib->ring)) {
153  need_sync = true;
155  fence->ring, ib->ring);
156  radeon_fence_note_sync(fence, ib->ring);
157  }
158  }
159  /* immediately free semaphore when we don't need to sync */
160  if (!need_sync) {
161  radeon_semaphore_free(rdev, &ib->semaphore, NULL);
162  }
163  /* if we can't remember our last VM flush then flush now! */
164  if (ib->vm && !ib->vm->last_flush) {
165  radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
166  }
167  if (const_ib) {
168  radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
169  radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
170  }
171  radeon_ring_ib_execute(rdev, ib->ring, ib);
172  r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
173  if (r) {
174  dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
175  radeon_ring_unlock_undo(rdev, ring);
176  return r;
177  }
178  if (const_ib) {
179  const_ib->fence = radeon_fence_ref(ib->fence);
180  }
181  /* we just flushed the VM, remember that */
182  if (ib->vm && !ib->vm->last_flush) {
183  ib->vm->last_flush = radeon_fence_ref(ib->fence);
184  }
185  radeon_ring_unlock_commit(rdev, ring);
186  return 0;
187 }
188 
199 {
200  int r;
201 
202  if (rdev->ib_pool_ready) {
203  return 0;
204  }
205  r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
206  RADEON_IB_POOL_SIZE*64*1024,
208  if (r) {
209  return r;
210  }
211 
212  r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
213  if (r) {
214  return r;
215  }
216 
217  rdev->ib_pool_ready = true;
218  if (radeon_debugfs_sa_init(rdev)) {
219  dev_err(rdev->dev, "failed to register debugfs file for SA\n");
220  }
221  return 0;
222 }
223 
233 {
234  if (rdev->ib_pool_ready) {
237  rdev->ib_pool_ready = false;
238  }
239 }
240 
252 {
253  unsigned i;
254  int r;
255 
256  for (i = 0; i < RADEON_NUM_RINGS; ++i) {
257  struct radeon_ring *ring = &rdev->ring[i];
258 
259  if (!ring->ready)
260  continue;
261 
262  r = radeon_ib_test(rdev, i, ring);
263  if (r) {
264  ring->ready = false;
265 
266  if (i == RADEON_RING_TYPE_GFX_INDEX) {
267  /* oh, oh, that's really bad */
268  DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
269  rdev->accel_working = false;
270  return r;
271 
272  } else {
273  /* still not good, but we can live with it */
274  DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
275  }
276  }
277  }
278  return 0;
279 }
280 
281 /*
282  * Rings
283  * Most engines on the GPU are fed via ring buffers. Ring
284  * buffers are areas of GPU accessible memory that the host
285  * writes commands into and the GPU reads commands out of.
286  * There is a rptr (read pointer) that determines where the
287  * GPU is currently reading, and a wptr (write pointer)
288  * which determines where the host has written. When the
289  * pointers are equal, the ring is idle. When the host
290  * writes commands to the ring buffer, it increments the
291  * wptr. The GPU then starts fetching commands and executes
292  * them until the pointers are equal again.
293  */
294 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
295 
305 {
306 #if DRM_DEBUG_CODE
307  if (ring->count_dw <= 0) {
308  DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
309  }
310 #endif
311  ring->ring[ring->wptr++] = v;
312  ring->wptr &= ring->ptr_mask;
313  ring->count_dw--;
314  ring->ring_free_dw--;
315 }
316 
328  struct radeon_ring *ring)
329 {
330  switch (ring->idx) {
334  return true;
335  default:
336  return false;
337  }
338 }
339 
349 {
350  u32 rptr;
351 
352  if (rdev->wb.enabled)
353  rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
354  else
355  rptr = RREG32(ring->rptr_reg);
356  ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
357  /* This works because ring_size is a power of 2 */
358  ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
359  ring->ring_free_dw -= ring->wptr;
360  ring->ring_free_dw &= ring->ptr_mask;
361  if (!ring->ring_free_dw) {
362  ring->ring_free_dw = ring->ring_size / 4;
363  }
364 }
365 
376 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
377 {
378  int r;
379 
380  /* Align requested size with padding so unlock_commit can
381  * pad safely */
382  ndw = (ndw + ring->align_mask) & ~ring->align_mask;
383  while (ndw > (ring->ring_free_dw - 1)) {
384  radeon_ring_free_size(rdev, ring);
385  if (ndw < ring->ring_free_dw) {
386  break;
387  }
388  r = radeon_fence_wait_next_locked(rdev, ring->idx);
389  if (r)
390  return r;
391  }
392  ring->count_dw = ndw;
393  ring->wptr_old = ring->wptr;
394  return 0;
395 }
396 
408 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
409 {
410  int r;
411 
412  mutex_lock(&rdev->ring_lock);
413  r = radeon_ring_alloc(rdev, ring, ndw);
414  if (r) {
415  mutex_unlock(&rdev->ring_lock);
416  return r;
417  }
418  return 0;
419 }
420 
432 {
433  /* We pad to match fetch size */
434  while (ring->wptr & ring->align_mask) {
435  radeon_ring_write(ring, ring->nop);
436  }
438  WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
439  (void)RREG32(ring->wptr_reg);
440 }
441 
452 {
453  radeon_ring_commit(rdev, ring);
454  mutex_unlock(&rdev->ring_lock);
455 }
456 
465 {
466  ring->wptr = ring->wptr_old;
467 }
468 
477 {
478  radeon_ring_undo(ring);
479  mutex_unlock(&rdev->ring_lock);
480 }
481 
492 {
493  int r;
494 
495  radeon_ring_free_size(rdev, ring);
496  if (ring->rptr == ring->wptr) {
497  r = radeon_ring_alloc(rdev, ring, 1);
498  if (!r) {
499  radeon_ring_write(ring, ring->nop);
500  radeon_ring_commit(rdev, ring);
501  }
502  }
503 }
504 
513 {
514  ring->last_rptr = ring->rptr;
515  ring->last_activity = jiffies;
516 }
517 
539 {
540  unsigned long cjiffies, elapsed;
541  uint32_t rptr;
542 
543  cjiffies = jiffies;
544  if (!time_after(cjiffies, ring->last_activity)) {
545  /* likely a wrap around */
547  return false;
548  }
549  rptr = RREG32(ring->rptr_reg);
550  ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
551  if (ring->rptr != ring->last_rptr) {
552  /* CP is still working no lockup */
554  return false;
555  }
556  elapsed = jiffies_to_msecs(cjiffies - ring->last_activity);
557  if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
558  dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
559  return true;
560  }
561  /* give a chance to the GPU ... */
562  return false;
563 }
564 
574  uint32_t **data)
575 {
576  unsigned size, ptr, i;
577 
578  /* just in case lock the ring */
579  mutex_lock(&rdev->ring_lock);
580  *data = NULL;
581 
582  if (ring->ring_obj == NULL) {
583  mutex_unlock(&rdev->ring_lock);
584  return 0;
585  }
586 
587  /* it doesn't make sense to save anything if all fences are signaled */
588  if (!radeon_fence_count_emitted(rdev, ring->idx)) {
589  mutex_unlock(&rdev->ring_lock);
590  return 0;
591  }
592 
593  /* calculate the number of dw on the ring */
594  if (ring->rptr_save_reg)
595  ptr = RREG32(ring->rptr_save_reg);
596  else if (rdev->wb.enabled)
597  ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
598  else {
599  /* no way to read back the next rptr */
600  mutex_unlock(&rdev->ring_lock);
601  return 0;
602  }
603 
604  size = ring->wptr + (ring->ring_size / 4);
605  size -= ptr;
606  size &= ring->ptr_mask;
607  if (size == 0) {
608  mutex_unlock(&rdev->ring_lock);
609  return 0;
610  }
611 
612  /* and then save the content of the ring */
613  *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
614  if (!*data) {
615  mutex_unlock(&rdev->ring_lock);
616  return 0;
617  }
618  for (i = 0; i < size; ++i) {
619  (*data)[i] = ring->ring[ptr++];
620  ptr &= ring->ptr_mask;
621  }
622 
623  mutex_unlock(&rdev->ring_lock);
624  return size;
625 }
626 
638  unsigned size, uint32_t *data)
639 {
640  int i, r;
641 
642  if (!size || !data)
643  return 0;
644 
645  /* restore the saved ring content */
646  r = radeon_ring_lock(rdev, ring, size);
647  if (r)
648  return r;
649 
650  for (i = 0; i < size; ++i) {
651  radeon_ring_write(ring, data[i]);
652  }
653 
654  radeon_ring_unlock_commit(rdev, ring);
655  kfree(data);
656  return 0;
657 }
658 
676  unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
678 {
679  int r;
680 
681  ring->ring_size = ring_size;
682  ring->rptr_offs = rptr_offs;
683  ring->rptr_reg = rptr_reg;
684  ring->wptr_reg = wptr_reg;
686  ring->ptr_reg_mask = ptr_reg_mask;
687  ring->nop = nop;
688  /* Allocate ring buffer */
689  if (ring->ring_obj == NULL) {
690  r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
692  NULL, &ring->ring_obj);
693  if (r) {
694  dev_err(rdev->dev, "(%d) ring create failed\n", r);
695  return r;
696  }
697  r = radeon_bo_reserve(ring->ring_obj, false);
698  if (unlikely(r != 0))
699  return r;
701  &ring->gpu_addr);
702  if (r) {
703  radeon_bo_unreserve(ring->ring_obj);
704  dev_err(rdev->dev, "(%d) ring pin failed\n", r);
705  return r;
706  }
707  r = radeon_bo_kmap(ring->ring_obj,
708  (void **)&ring->ring);
709  radeon_bo_unreserve(ring->ring_obj);
710  if (r) {
711  dev_err(rdev->dev, "(%d) ring map failed\n", r);
712  return r;
713  }
714  }
715  ring->ptr_mask = (ring->ring_size / 4) - 1;
716  ring->ring_free_dw = ring->ring_size / 4;
717  if (rdev->wb.enabled) {
718  u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
719  ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
720  ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
721  }
722  if (radeon_debugfs_ring_init(rdev, ring)) {
723  DRM_ERROR("Failed to register debugfs file for rings !\n");
724  }
726  return 0;
727 }
728 
738 {
739  int r;
740  struct radeon_bo *ring_obj;
741 
742  mutex_lock(&rdev->ring_lock);
743  ring_obj = ring->ring_obj;
744  ring->ready = false;
745  ring->ring = NULL;
746  ring->ring_obj = NULL;
747  mutex_unlock(&rdev->ring_lock);
748 
749  if (ring_obj) {
750  r = radeon_bo_reserve(ring_obj, false);
751  if (likely(r == 0)) {
752  radeon_bo_kunmap(ring_obj);
753  radeon_bo_unpin(ring_obj);
754  radeon_bo_unreserve(ring_obj);
755  }
756  radeon_bo_unref(&ring_obj);
757  }
758 }
759 
760 /*
761  * Debugfs info
762  */
763 #if defined(CONFIG_DEBUG_FS)
764 
765 static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
766 {
767  struct drm_info_node *node = (struct drm_info_node *) m->private;
768  struct drm_device *dev = node->minor->dev;
769  struct radeon_device *rdev = dev->dev_private;
770  int ridx = *(int*)node->info_ent->data;
771  struct radeon_ring *ring = &rdev->ring[ridx];
772  unsigned count, i, j;
773 
775  count = (ring->ring_size / 4) - ring->ring_free_dw;
776  seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));
777  seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg));
778  if (ring->rptr_save_reg) {
779  seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg,
780  RREG32(ring->rptr_save_reg));
781  }
782  seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr);
783  seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
784  seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
785  seq_printf(m, "%u dwords in ring\n", count);
786  i = ring->rptr;
787  for (j = 0; j <= count; j++) {
788  seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
789  i = (i + 1) & ring->ptr_mask;
790  }
791  return 0;
792 }
793 
794 static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
795 static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
796 static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
797 
798 static struct drm_info_list radeon_debugfs_ring_info_list[] = {
799  {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
800  {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
801  {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
802 };
803 
804 static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
805 {
806  struct drm_info_node *node = (struct drm_info_node *) m->private;
807  struct drm_device *dev = node->minor->dev;
808  struct radeon_device *rdev = dev->dev_private;
809 
810  radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
811 
812  return 0;
813 
814 }
815 
816 static struct drm_info_list radeon_debugfs_sa_list[] = {
817  {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
818 };
819 
820 #endif
821 
822 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
823 {
824 #if defined(CONFIG_DEBUG_FS)
825  unsigned i;
826  for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
827  struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
828  int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
829  unsigned r;
830 
831  if (&rdev->ring[ridx] != ring)
832  continue;
833 
834  r = radeon_debugfs_add_files(rdev, info, 1);
835  if (r)
836  return r;
837  }
838 #endif
839  return 0;
840 }
841 
842 static int radeon_debugfs_sa_init(struct radeon_device *rdev)
843 {
844 #if defined(CONFIG_DEBUG_FS)
845  return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
846 #else
847  return 0;
848 #endif
849 }