26 #include <linux/i2c.h>
37 static int gpedge_add[] = {
42 static int irq_en_add[] = {
53 static int irq_mon_add[] = {
65 static int irq_clr_add[] = {
77 static int main_int_type[] = {
97 #define RC5T583_IRQ(_int_type, _master_bit, _grp_index, \
98 _int_bit, _mask_ind) \
100 .int_type = _int_type, \
101 .master_bit = _master_bit, \
102 .grp_index = _grp_index, \
103 .int_en_bit = _int_bit, \
104 .mask_reg_index = _mask_ind, \
162 unsigned int __irq = irq_data->
irq - rc5t583->
irq_base;
173 unsigned int __irq = irq_data->
irq - rc5t583->
irq_base;
183 static int rc5t583_irq_set_type(
struct irq_data *irq_data,
unsigned int type)
185 struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
186 unsigned int __irq = irq_data->
irq - rc5t583->
irq_base;
203 rc5t583->
gpedge_reg[gpedge_index] &= ~(3 << gpedge_bit_pos);
204 rc5t583->
gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos);
205 rc5t583_irq_unmask(irq_data);
211 static void rc5t583_irq_sync_unlock(
struct irq_data *irq_data)
213 struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
218 ret = rc5t583_write(rc5t583->
dev, gpedge_add[i],
222 "Error in writing reg 0x%02x error: %d\n",
227 ret = rc5t583_write(rc5t583->
dev, irq_en_add[i],
231 "Error in writing reg 0x%02x error: %d\n",
239 "Error in writing reg 0x%02x error: %d\n",
244 #ifdef CONFIG_PM_SLEEP
247 struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
251 #define rc5t583_irq_set_wake NULL
254 static irqreturn_t rc5t583_irq(
int irq,
void *data)
256 struct rc5t583 *rc5t583 =
data;
261 unsigned int rtc_int_sts = 0;
270 "Error in reading reg 0x%02x error: %d\n",
276 if (!(master_int & main_int_type[i]))
279 ret = rc5t583_read(rc5t583->
dev, irq_mon_add[i], &int_sts[i]);
282 "Error in reading reg 0x%02x error: %d\n",
283 irq_mon_add[i], ret);
288 if (main_int_type[i] &
RTC_INT) {
290 if (int_sts[i] & 0x1)
291 rtc_int_sts |=
BIT(6);
292 if (int_sts[i] & 0x2)
293 rtc_int_sts |=
BIT(7);
294 if (int_sts[i] & 0x4)
295 rtc_int_sts |=
BIT(0);
296 if (int_sts[i] & 0x8)
297 rtc_int_sts |=
BIT(5);
300 ret = rc5t583_write(rc5t583->
dev, irq_clr_add[i],
304 "Error in reading reg 0x%02x error: %d\n",
305 irq_clr_add[i], ret);
307 if (main_int_type[i] & RTC_INT)
308 int_sts[
i] = rtc_int_sts;
312 int_sts[7] |= int_sts[8];
326 static struct irq_chip rc5t583_irq_chip = {
327 .name =
"rc5t583-irq",
328 .irq_mask = rc5t583_irq_mask,
329 .irq_unmask = rc5t583_irq_unmask,
330 .irq_bus_lock = rc5t583_irq_lock,
331 .irq_bus_sync_unlock = rc5t583_irq_sync_unlock,
332 .irq_set_type = rc5t583_irq_set_type,
341 dev_warn(rc5t583->
dev,
"No interrupt support on IRQ base\n");
349 ret = rc5t583_write(rc5t583->
dev, irq_en_add[i],
353 "Error in writing reg 0x%02x error: %d\n",
358 ret = rc5t583_write(rc5t583->
dev, gpedge_add[i],
362 "Error in writing reg 0x%02x error: %d\n",
369 "Error in writing reg 0x%02x error: %d\n",
374 ret = rc5t583_write(rc5t583->
dev, irq_clr_add[i], 0);
377 "Error in writing reg 0x%02x error: %d\n",
378 irq_clr_add[i], ret);
387 irq_set_chip_and_handler(__irq, &rc5t583_irq_chip,
389 irq_set_nested_thread(__irq, 1);
399 "Error in registering interrupt error: %d\n", ret);