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rocket_int.h File Reference
#include <linux/mutex.h>
#include <asm/io.h>
#include <asm/byteorder.h>

Go to the source code of this file.

Data Structures

struct  CONTROLLER_T
 
struct  CHANNEL_T
 
struct  r_port
 

Macros

#define ROCKET_TYPE_NORMAL   0
 
#define ROCKET_TYPE_MODEM   1
 
#define ROCKET_TYPE_MODEMII   2
 
#define ROCKET_TYPE_MODEMIII   3
 
#define ROCKET_TYPE_PC104   4
 
#define sOutStrW(port, addr, count)   if (count) outsw(port, addr, count)
 
#define sInStrW(port, addr, count)   if (count) insw(port, addr, count)
 
#define CTL_SIZE   8
 
#define AIOP_CTL_SIZE   4
 
#define CHAN_AIOP_SIZE   8
 
#define MAX_PORTS_PER_AIOP   8
 
#define MAX_AIOPS_PER_BOARD   4
 
#define MAX_PORTS_PER_BOARD   32
 
#define isISA   0
 
#define isPCI   1
 
#define isMC   2
 
#define CTLID_NULL   -1 /* no controller exists */
 
#define CTLID_0001   0x0001 /* controller release 1 */
 
#define AIOPID_NULL   -1 /* no AIOP or channel exists */
 
#define AIOPID_0001   0x0001 /* AIOP release 1 */
 
#define _CMD_REG   0x38 /* Command Register 8 Write */
 
#define _INT_CHAN   0x39 /* Interrupt Channel Register 8 Read */
 
#define _INT_MASK   0x3A /* Interrupt Mask Register 8 Read / Write */
 
#define _UNUSED   0x3B /* Unused 8 */
 
#define _INDX_ADDR   0x3C /* Index Register Address 16 Write */
 
#define _INDX_DATA   0x3E /* Index Register Data 8/16 Read / Write */
 
#define _TD0   0x00 /* Transmit Data 16 Write */
 
#define _RD0   0x00 /* Receive Data 16 Read */
 
#define _CHN_STAT0   0x20 /* Channel Status 8/16 Read / Write */
 
#define _FIFO_CNT0   0x10 /* Transmit/Receive FIFO Count 16 Read */
 
#define _INT_ID0   0x30 /* Interrupt Identification 8 Read */
 
#define _TX_ENBLS   0x980 /* Tx Processor Enables Register 8 Read / Write */
 
#define _TXCMP1   0x988 /* Transmit Compare Value #1 8 Read / Write */
 
#define _TXCMP2   0x989 /* Transmit Compare Value #2 8 Read / Write */
 
#define _TXREP1B1   0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
 
#define _TXREP1B2   0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
 
#define _TXREP2   0x98C /* Transmit Replace Value #2 8 Read / Write */
 
#define _RX_FIFO   0x000 /* Rx FIFO */
 
#define _TX_FIFO   0x800 /* Tx FIFO */
 
#define _RXF_OUTP   0x990 /* Rx FIFO OUT pointer 16 Read / Write */
 
#define _RXF_INP   0x992 /* Rx FIFO IN pointer 16 Read / Write */
 
#define _TXF_OUTP   0x994 /* Tx FIFO OUT pointer 8 Read / Write */
 
#define _TXF_INP   0x995 /* Tx FIFO IN pointer 8 Read / Write */
 
#define _TXP_CNT   0x996 /* Tx Priority Count 8 Read / Write */
 
#define _TXP_PNTR   0x997 /* Tx Priority Pointer 8 Read / Write */
 
#define PRI_PEND   0x80 /* Priority data pending (bit7, Tx pri cnt) */
 
#define TXFIFO_SIZE   255 /* size of Tx FIFO */
 
#define RXFIFO_SIZE   1023 /* size of Rx FIFO */
 
#define _TXP_BUF   0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
 
#define TXP_SIZE   0x20 /* 32 bytes */
 
#define _TX_CTRL   0xFF0 /* Transmit Control 16 Write */
 
#define _RX_CTRL   0xFF2 /* Receive Control 8 Write */
 
#define _BAUD   0xFF4 /* Baud Rate 16 Write */
 
#define _CLK_PRE   0xFF6 /* Clock Prescaler 8 Write */
 
#define STMBREAK   0x08 /* BREAK */
 
#define STMFRAME   0x04 /* framing error */
 
#define STMRCVROVR   0x02 /* receiver over run error */
 
#define STMPARITY   0x01 /* parity error */
 
#define STMERROR   (STMBREAK | STMFRAME | STMPARITY)
 
#define STMBREAKH   0x800 /* BREAK */
 
#define STMFRAMEH   0x400 /* framing error */
 
#define STMRCVROVRH   0x200 /* receiver over run error */
 
#define STMPARITYH   0x100 /* parity error */
 
#define STMERRORH   (STMBREAKH | STMFRAMEH | STMPARITYH)
 
#define CTS_ACT   0x20 /* CTS input asserted */
 
#define DSR_ACT   0x10 /* DSR input asserted */
 
#define CD_ACT   0x08 /* CD input asserted */
 
#define TXFIFOMT   0x04 /* Tx FIFO is empty */
 
#define TXSHRMT   0x02 /* Tx shift register is empty */
 
#define RDA   0x01 /* Rx data available */
 
#define DRAINED   (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
 
#define STATMODE   0x8000 /* status mode enable bit */
 
#define RXFOVERFL   0x2000 /* receive FIFO overflow */
 
#define RX2MATCH   0x1000 /* receive compare byte 2 match */
 
#define RX1MATCH   0x0800 /* receive compare byte 1 match */
 
#define RXBREAK   0x0400 /* received BREAK */
 
#define RXFRAME   0x0200 /* received framing error */
 
#define RXPARITY   0x0100 /* received parity error */
 
#define STATERROR   (RXBREAK | RXFRAME | RXPARITY)
 
#define CTSFC_EN   0x80 /* CTS flow control enable bit */
 
#define RTSTOG_EN   0x40 /* RTS toggle enable bit */
 
#define TXINT_EN   0x10 /* transmit interrupt enable */
 
#define STOP2   0x08 /* enable 2 stop bits (0 = 1 stop) */
 
#define PARITY_EN   0x04 /* enable parity (0 = no parity) */
 
#define EVEN_PAR   0x02 /* even parity (0 = odd parity) */
 
#define DATA8BIT   0x01 /* 8 bit data (0 = 7 bit data) */
 
#define SETBREAK   0x10 /* send break condition (must clear) */
 
#define LOCALLOOP   0x08 /* local loopback set for test */
 
#define SET_DTR   0x04 /* assert DTR */
 
#define SET_RTS   0x02 /* assert RTS */
 
#define TX_ENABLE   0x01 /* enable transmitter */
 
#define RTSFC_EN   0x40 /* RTS flow control enable */
 
#define RXPROC_EN   0x20 /* receive processor enable */
 
#define TRIG_NO   0x00 /* Rx FIFO trigger level 0 (no trigger) */
 
#define TRIG_1   0x08 /* trigger level 1 char */
 
#define TRIG_1_2   0x10 /* trigger level 1/2 */
 
#define TRIG_7_8   0x18 /* trigger level 7/8 */
 
#define TRIG_MASK   0x18 /* trigger level mask */
 
#define SRCINT_EN   0x04 /* special Rx condition interrupt enable */
 
#define RXINT_EN   0x02 /* Rx interrupt enable */
 
#define MCINT_EN   0x01 /* modem change interrupt enable */
 
#define RXF_TRIG   0x20 /* Rx FIFO trigger level interrupt */
 
#define TXFIFO_MT   0x10 /* Tx FIFO empty interrupt */
 
#define SRC_INT   0x08 /* special receive condition interrupt */
 
#define DELTA_CD   0x04 /* CD change interrupt */
 
#define DELTA_CTS   0x02 /* CTS change interrupt */
 
#define DELTA_DSR   0x01 /* DSR change interrupt */
 
#define REP1W2_EN   0x10 /* replace byte 1 with 2 bytes enable */
 
#define IGN2_EN   0x08 /* ignore byte 2 enable */
 
#define IGN1_EN   0x04 /* ignore byte 1 enable */
 
#define COMP2_EN   0x02 /* compare byte 2 enable */
 
#define COMP1_EN   0x01 /* compare byte 1 enable */
 
#define RESET_ALL   0x80 /* reset AIOP (all channels) */
 
#define TXOVERIDE   0x40 /* Transmit software off override */
 
#define RESETUART   0x20 /* reset channel's UART */
 
#define RESTXFCNT   0x10 /* reset channel's Tx FIFO count register */
 
#define RESRXFCNT   0x08 /* reset channel's Rx FIFO count register */
 
#define INTSTAT0   0x01 /* AIOP 0 interrupt status */
 
#define INTSTAT1   0x02 /* AIOP 1 interrupt status */
 
#define INTSTAT2   0x04 /* AIOP 2 interrupt status */
 
#define INTSTAT3   0x08 /* AIOP 3 interrupt status */
 
#define INTR_EN   0x08 /* allow interrupts to host */
 
#define INT_STROB   0x04 /* strobe and clear interrupt line (EOI) */
 
#define _CFG_INT_PCI   0x40
 
#define _PCI_INT_FUNC   0x3A
 
#define PCI_STROB   0x2000 /* bit 13 of int aiop register */
 
#define INTR_EN_PCI   0x0010 /* allow interrupts to host */
 
#define _PCI_9030_INT_CTRL   0x4c /* Offsets from BAR1 */
 
#define _PCI_9030_GPIO_CTRL   0x54
 
#define PCI_INT_CTRL_AIOP   0x0001
 
#define PCI_GPIO_CTRL_8PORT   0x4000
 
#define _PCI_9030_RING_IND   0xc0 /* Offsets from BAR1 */
 
#define CHAN3_EN   0x08 /* enable AIOP 3 */
 
#define CHAN2_EN   0x04 /* enable AIOP 2 */
 
#define CHAN1_EN   0x02 /* enable AIOP 1 */
 
#define CHAN0_EN   0x01 /* enable AIOP 0 */
 
#define FREQ_DIS   0x00
 
#define FREQ_274HZ   0x60
 
#define FREQ_137HZ   0x50
 
#define FREQ_69HZ   0x40
 
#define FREQ_34HZ   0x30
 
#define FREQ_17HZ   0x20
 
#define FREQ_9HZ   0x10
 
#define PERIODIC_ONLY   0x80 /* only PERIODIC interrupt */
 
#define CHANINT_EN   0x0100 /* flags to enable/disable channel ints */
 
#define RDATASIZE   72
 
#define RREGDATASIZE   52
 
#define AIOP_INTR_BIT_0   0x0001
 
#define AIOP_INTR_BIT_1   0x0002
 
#define AIOP_INTR_BIT_2   0x0004
 
#define AIOP_INTR_BIT_3   0x0008
 
#define AIOP_INTR_BITS
 
#define UPCI_AIOP_INTR_BIT_0   0x0004
 
#define UPCI_AIOP_INTR_BIT_1   0x0020
 
#define UPCI_AIOP_INTR_BIT_2   0x0100
 
#define UPCI_AIOP_INTR_BIT_3   0x0800
 
#define UPCI_AIOP_INTR_BITS
 
#define InterfaceModeRS232   0x00
 
#define InterfaceModeRS422   0x08
 
#define InterfaceModeRS485   0x10
 
#define InterfaceModeRS232T   0x18
 
#define sClrBreak(ChP)
 
#define sClrDTR(ChP)
 
#define sClrRTS(ChP)
 
#define sClrTxXOFF(ChP)
 
#define sCtlNumToCtlPtr(CTLNUM)   &sController[CTLNUM]
 
#define sControllerEOI(CTLP)   sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)
 
#define sPCIControllerEOI(CTLP)
 
#define sDisAiop(CTLP, AIOPNUM)
 
#define sDisCTSFlowCtl(ChP)
 
#define sDisIXANY(ChP)
 
#define sDisParity(ChP)
 
#define sDisRTSToggle(ChP)
 
#define sDisRxFIFO(ChP)
 
#define sDisRxStatusMode(ChP)   sOutW((ChP)->ChanStat,0)
 
#define sDisTransmit(ChP)
 
#define sDisTxSoftFlowCtl(ChP)
 
#define sEnAiop(CTLP, AIOPNUM)
 
#define sEnCTSFlowCtl(ChP)
 
#define sEnIXANY(ChP)
 
#define sEnParity(ChP)
 
#define sEnRTSToggle(ChP)
 
#define sEnRxFIFO(ChP)
 
#define sEnRxProcessor(ChP)
 
#define sEnRxStatusMode(ChP)   sOutW((ChP)->ChanStat,STATMODE)
 
#define sEnTransmit(ChP)
 
#define sEnTxSoftFlowCtl(ChP)
 
#define sGetAiopIntStatus(CTLP, AIOPNUM)   sInB((CTLP)->AiopIntChanIO[AIOPNUM])
 
#define sGetAiopNumChan(CTLP, AIOPNUM)   (CTLP)->AiopNumChan[AIOPNUM]
 
#define sGetChanIntID(ChP)   (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
 
#define sGetChanNum(ChP)   (ChP)->ChanNum
 
#define sGetChanStatus(ChP)   sInW((ChP)->ChanStat)
 
#define sGetChanStatusLo(ChP)   sInB((ByteIO_t)(ChP)->ChanStat)
 
#define sGetControllerIntStatus(CTLP)   (sInB((CTLP)->MReg1IO) & 0x0f)
 
#define sPCIGetControllerIntStatus(CTLP)
 
#define sGetRxCnt(ChP)   sInW((ChP)->TxRxCount)
 
#define sGetTxCnt(ChP)   sInB((ByteIO_t)(ChP)->TxRxCount)
 
#define sGetTxRxDataIO(ChP)   (ChP)->TxRxData
 
#define sInitChanDefaults(ChP)
 
#define sResetAiopByNum(CTLP, AIOPNUM)
 
#define sSendBreak(ChP)
 
#define sSetBaud(ChP, DIVISOR)
 
#define sSetData7(ChP)
 
#define sSetData8(ChP)
 
#define sSetDTR(ChP)
 
#define sSetEvenParity(ChP)
 
#define sSetOddParity(ChP)
 
#define sSetRTS(ChP)
 
#define sSetRxTrigger(ChP, LEVEL)
 
#define sSetStop1(ChP)
 
#define sSetStop2(ChP)
 
#define sSetTxXOFFChar(ChP, CH)
 
#define sSetTxXONChar(ChP, CH)
 
#define sStartRxProcessor(ChP)   out32((ChP)->IndexAddr,&(ChP)->R[0])
 
#define sWriteTxByte(IO, DATA)   sOutB(IO,DATA)
 
#define RPORT_MAGIC   0x525001
 
#define NUM_BOARDS   8
 
#define MAX_RP_PORTS   (32*NUM_BOARDS)
 
#define XMIT_BUF_SIZE   4096
 
#define WAKEUP_CHARS   256
 
#define TTY_ROCKET_MAJOR   46
 
#define CUA_ROCKET_MAJOR   47
 
#define PCI_VENDOR_ID_RP   0x11fe
 
#define PCI_DEVICE_ID_RP32INTF   0x0001 /* Rocketport 32 port w/external I/F */
 
#define PCI_DEVICE_ID_RP8INTF   0x0002 /* Rocketport 8 port w/external I/F */
 
#define PCI_DEVICE_ID_RP16INTF   0x0003 /* Rocketport 16 port w/external I/F */
 
#define PCI_DEVICE_ID_RP4QUAD   0x0004 /* Rocketport 4 port w/quad cable */
 
#define PCI_DEVICE_ID_RP8OCTA   0x0005 /* Rocketport 8 port w/octa cable */
 
#define PCI_DEVICE_ID_RP8J   0x0006 /* Rocketport 8 port w/RJ11 connectors */
 
#define PCI_DEVICE_ID_RP4J   0x0007 /* Rocketport 4 port w/RJ11 connectors */
 
#define PCI_DEVICE_ID_RP8SNI   0x0008 /* Rocketport 8 port w/ DB78 SNI (Siemens) connector */
 
#define PCI_DEVICE_ID_RP16SNI   0x0009 /* Rocketport 16 port w/ DB78 SNI (Siemens) connector */
 
#define PCI_DEVICE_ID_RPP4   0x000A /* Rocketport Plus 4 port */
 
#define PCI_DEVICE_ID_RPP8   0x000B /* Rocketport Plus 8 port */
 
#define PCI_DEVICE_ID_RP6M   0x000C /* RocketModem 6 port */
 
#define PCI_DEVICE_ID_RP4M   0x000D /* RocketModem 4 port */
 
#define PCI_DEVICE_ID_RP2_232   0x000E /* Rocketport Plus 2 port RS232 */
 
#define PCI_DEVICE_ID_RP2_422   0x000F /* Rocketport Plus 2 port RS422 */
 
#define PCI_DEVICE_ID_URP32INTF   0x0801 /* Rocketport UPCI 32 port w/external I/F */
 
#define PCI_DEVICE_ID_URP8INTF   0x0802 /* Rocketport UPCI 8 port w/external I/F */
 
#define PCI_DEVICE_ID_URP16INTF   0x0803 /* Rocketport UPCI 16 port w/external I/F */
 
#define PCI_DEVICE_ID_URP8OCTA   0x0805 /* Rocketport UPCI 8 port w/octa cable */
 
#define PCI_DEVICE_ID_UPCI_RM3_8PORT   0x080C /* Rocketmodem III 8 port */
 
#define PCI_DEVICE_ID_UPCI_RM3_4PORT   0x080D /* Rocketmodem III 4 port */
 
#define PCI_DEVICE_ID_CRP16INTF   0x0903 /* Rocketport Compact PCI 16 port w/external I/F */
 

Typedefs

typedef unsigned char Byte_t
 
typedef unsigned int ByteIO_t
 
typedef unsigned int Word_t
 
typedef unsigned int WordIO_t
 
typedef unsigned int DWordIO_t
 
typedef CONTROLLER_T CONTROLLER_t
 
typedef CHANNEL_T CHANNEL_t
 
typedef CHANNEL_T * CHANPTR_T
 

Macro Definition Documentation

#define _BAUD   0xFF4 /* Baud Rate 16 Write */

Definition at line 157 of file rocket_int.h.

#define _CFG_INT_PCI   0x40

Definition at line 244 of file rocket_int.h.

#define _CHN_STAT0   0x20 /* Channel Status 8/16 Read / Write */

Definition at line 115 of file rocket_int.h.

#define _CLK_PRE   0xFF6 /* Clock Prescaler 8 Write */

Definition at line 158 of file rocket_int.h.

#define _CMD_REG   0x38 /* Command Register 8 Write */

Definition at line 103 of file rocket_int.h.

#define _FIFO_CNT0   0x10 /* Transmit/Receive FIFO Count 16 Read */

Definition at line 116 of file rocket_int.h.

#define _INDX_ADDR   0x3C /* Index Register Address 16 Write */

Definition at line 107 of file rocket_int.h.

#define _INDX_DATA   0x3E /* Index Register Data 8/16 Read / Write */

Definition at line 108 of file rocket_int.h.

#define _INT_CHAN   0x39 /* Interrupt Channel Register 8 Read */

Definition at line 104 of file rocket_int.h.

#define _INT_ID0   0x30 /* Interrupt Identification 8 Read */

Definition at line 117 of file rocket_int.h.

#define _INT_MASK   0x3A /* Interrupt Mask Register 8 Read / Write */

Definition at line 105 of file rocket_int.h.

#define _PCI_9030_GPIO_CTRL   0x54

Definition at line 254 of file rocket_int.h.

#define _PCI_9030_INT_CTRL   0x4c /* Offsets from BAR1 */

Definition at line 253 of file rocket_int.h.

#define _PCI_9030_RING_IND   0xc0 /* Offsets from BAR1 */

Definition at line 257 of file rocket_int.h.

#define _PCI_INT_FUNC   0x3A

Definition at line 245 of file rocket_int.h.

#define _RD0   0x00 /* Receive Data 16 Read */

Definition at line 114 of file rocket_int.h.

#define _RX_CTRL   0xFF2 /* Receive Control 8 Write */

Definition at line 156 of file rocket_int.h.

#define _RX_FIFO   0x000 /* Rx FIFO */

Definition at line 132 of file rocket_int.h.

#define _RXF_INP   0x992 /* Rx FIFO IN pointer 16 Read / Write */

Definition at line 135 of file rocket_int.h.

#define _RXF_OUTP   0x990 /* Rx FIFO OUT pointer 16 Read / Write */

Definition at line 134 of file rocket_int.h.

#define _TD0   0x00 /* Transmit Data 16 Write */

Definition at line 113 of file rocket_int.h.

#define _TX_CTRL   0xFF0 /* Transmit Control 16 Write */

Definition at line 155 of file rocket_int.h.

#define _TX_ENBLS   0x980 /* Tx Processor Enables Register 8 Read / Write */

Definition at line 122 of file rocket_int.h.

#define _TX_FIFO   0x800 /* Tx FIFO */

Definition at line 133 of file rocket_int.h.

#define _TXCMP1   0x988 /* Transmit Compare Value #1 8 Read / Write */

Definition at line 123 of file rocket_int.h.

#define _TXCMP2   0x989 /* Transmit Compare Value #2 8 Read / Write */

Definition at line 124 of file rocket_int.h.

#define _TXF_INP   0x995 /* Tx FIFO IN pointer 8 Read / Write */

Definition at line 137 of file rocket_int.h.

#define _TXF_OUTP   0x994 /* Tx FIFO OUT pointer 8 Read / Write */

Definition at line 136 of file rocket_int.h.

#define _TXP_BUF   0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */

Definition at line 148 of file rocket_int.h.

#define _TXP_CNT   0x996 /* Tx Priority Count 8 Read / Write */

Definition at line 138 of file rocket_int.h.

#define _TXP_PNTR   0x997 /* Tx Priority Pointer 8 Read / Write */

Definition at line 139 of file rocket_int.h.

#define _TXREP1B1   0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */

Definition at line 125 of file rocket_int.h.

#define _TXREP1B2   0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */

Definition at line 126 of file rocket_int.h.

#define _TXREP2   0x98C /* Transmit Replace Value #2 8 Read / Write */

Definition at line 127 of file rocket_int.h.

#define _UNUSED   0x3B /* Unused 8 */

Definition at line 106 of file rocket_int.h.

#define AIOP_CTL_SIZE   4

Definition at line 80 of file rocket_int.h.

#define AIOP_INTR_BIT_0   0x0001

Definition at line 280 of file rocket_int.h.

#define AIOP_INTR_BIT_1   0x0002

Definition at line 281 of file rocket_int.h.

#define AIOP_INTR_BIT_2   0x0004

Definition at line 282 of file rocket_int.h.

#define AIOP_INTR_BIT_3   0x0008

Definition at line 283 of file rocket_int.h.

#define AIOP_INTR_BITS
Value:
( \
AIOP_INTR_BIT_0 \
| AIOP_INTR_BIT_1 \
| AIOP_INTR_BIT_2 \
| AIOP_INTR_BIT_3)

Definition at line 285 of file rocket_int.h.

#define AIOPID_0001   0x0001 /* AIOP release 1 */

Definition at line 97 of file rocket_int.h.

#define AIOPID_NULL   -1 /* no AIOP or channel exists */

Definition at line 96 of file rocket_int.h.

#define CD_ACT   0x08 /* CD input asserted */

Definition at line 173 of file rocket_int.h.

#define CHAN0_EN   0x01 /* enable AIOP 0 */

Definition at line 262 of file rocket_int.h.

#define CHAN1_EN   0x02 /* enable AIOP 1 */

Definition at line 261 of file rocket_int.h.

#define CHAN2_EN   0x04 /* enable AIOP 2 */

Definition at line 260 of file rocket_int.h.

#define CHAN3_EN   0x08 /* enable AIOP 3 */

Definition at line 259 of file rocket_int.h.

#define CHAN_AIOP_SIZE   8

Definition at line 81 of file rocket_int.h.

#define CHANINT_EN   0x0100 /* flags to enable/disable channel ints */

Definition at line 272 of file rocket_int.h.

#define COMP1_EN   0x01 /* compare byte 1 enable */

Definition at line 224 of file rocket_int.h.

#define COMP2_EN   0x02 /* compare byte 2 enable */

Definition at line 223 of file rocket_int.h.

#define CTL_SIZE   8

Definition at line 79 of file rocket_int.h.

#define CTLID_0001   0x0001 /* controller release 1 */

Definition at line 93 of file rocket_int.h.

#define CTLID_NULL   -1 /* no controller exists */

Definition at line 92 of file rocket_int.h.

#define CTS_ACT   0x20 /* CTS input asserted */

Definition at line 171 of file rocket_int.h.

#define CTSFC_EN   0x80 /* CTS flow control enable bit */

Definition at line 188 of file rocket_int.h.

#define CUA_ROCKET_MAJOR   47

Definition at line 1169 of file rocket_int.h.

#define DATA8BIT   0x01 /* 8 bit data (0 = 7 bit data) */

Definition at line 194 of file rocket_int.h.

#define DELTA_CD   0x04 /* CD change interrupt */

Definition at line 216 of file rocket_int.h.

#define DELTA_CTS   0x02 /* CTS change interrupt */

Definition at line 217 of file rocket_int.h.

#define DELTA_DSR   0x01 /* DSR change interrupt */

Definition at line 218 of file rocket_int.h.

#define DRAINED   (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */

Definition at line 177 of file rocket_int.h.

#define DSR_ACT   0x10 /* DSR input asserted */

Definition at line 172 of file rocket_int.h.

#define EVEN_PAR   0x02 /* even parity (0 = odd parity) */

Definition at line 193 of file rocket_int.h.

#define FREQ_137HZ   0x50

Definition at line 265 of file rocket_int.h.

#define FREQ_17HZ   0x20

Definition at line 268 of file rocket_int.h.

#define FREQ_274HZ   0x60

Definition at line 264 of file rocket_int.h.

#define FREQ_34HZ   0x30

Definition at line 267 of file rocket_int.h.

#define FREQ_69HZ   0x40

Definition at line 266 of file rocket_int.h.

#define FREQ_9HZ   0x10

Definition at line 269 of file rocket_int.h.

#define FREQ_DIS   0x00

Definition at line 263 of file rocket_int.h.

#define IGN1_EN   0x04 /* ignore byte 1 enable */

Definition at line 222 of file rocket_int.h.

#define IGN2_EN   0x08 /* ignore byte 2 enable */

Definition at line 221 of file rocket_int.h.

#define INT_STROB   0x04 /* strobe and clear interrupt line (EOI) */

Definition at line 238 of file rocket_int.h.

#define InterfaceModeRS232   0x00

Definition at line 370 of file rocket_int.h.

#define InterfaceModeRS232T   0x18

Definition at line 373 of file rocket_int.h.

#define InterfaceModeRS422   0x08

Definition at line 371 of file rocket_int.h.

#define InterfaceModeRS485   0x10

Definition at line 372 of file rocket_int.h.

#define INTR_EN   0x08 /* allow interrupts to host */

Definition at line 237 of file rocket_int.h.

#define INTR_EN_PCI   0x0010 /* allow interrupts to host */

Definition at line 248 of file rocket_int.h.

#define INTSTAT0   0x01 /* AIOP 0 interrupt status */

Definition at line 232 of file rocket_int.h.

#define INTSTAT1   0x02 /* AIOP 1 interrupt status */

Definition at line 233 of file rocket_int.h.

#define INTSTAT2   0x04 /* AIOP 2 interrupt status */

Definition at line 234 of file rocket_int.h.

#define INTSTAT3   0x08 /* AIOP 3 interrupt status */

Definition at line 235 of file rocket_int.h.

#define isISA   0

Definition at line 87 of file rocket_int.h.

#define isMC   2

Definition at line 89 of file rocket_int.h.

#define isPCI   1

Definition at line 88 of file rocket_int.h.

#define LOCALLOOP   0x08 /* local loopback set for test */

Definition at line 197 of file rocket_int.h.

#define MAX_AIOPS_PER_BOARD   4

Definition at line 83 of file rocket_int.h.

#define MAX_PORTS_PER_AIOP   8

Definition at line 82 of file rocket_int.h.

#define MAX_PORTS_PER_BOARD   32

Definition at line 84 of file rocket_int.h.

#define MAX_RP_PORTS   (32*NUM_BOARDS)

Definition at line 1155 of file rocket_int.h.

#define MCINT_EN   0x01 /* modem change interrupt enable */

Definition at line 211 of file rocket_int.h.

#define NUM_BOARDS   8

Definition at line 1154 of file rocket_int.h.

#define PARITY_EN   0x04 /* enable parity (0 = no parity) */

Definition at line 192 of file rocket_int.h.

#define PCI_DEVICE_ID_CRP16INTF   0x0903 /* Rocketport Compact PCI 16 port w/external I/F */

Definition at line 1213 of file rocket_int.h.

#define PCI_DEVICE_ID_RP16INTF   0x0003 /* Rocketport 16 port w/external I/F */

Definition at line 1190 of file rocket_int.h.

#define PCI_DEVICE_ID_RP16SNI   0x0009 /* Rocketport 16 port w/ DB78 SNI (Siemens) connector */

Definition at line 1196 of file rocket_int.h.

#define PCI_DEVICE_ID_RP2_232   0x000E /* Rocketport Plus 2 port RS232 */

Definition at line 1201 of file rocket_int.h.

#define PCI_DEVICE_ID_RP2_422   0x000F /* Rocketport Plus 2 port RS422 */

Definition at line 1202 of file rocket_int.h.

#define PCI_DEVICE_ID_RP32INTF   0x0001 /* Rocketport 32 port w/external I/F */

Definition at line 1188 of file rocket_int.h.

#define PCI_DEVICE_ID_RP4J   0x0007 /* Rocketport 4 port w/RJ11 connectors */

Definition at line 1194 of file rocket_int.h.

#define PCI_DEVICE_ID_RP4M   0x000D /* RocketModem 4 port */

Definition at line 1200 of file rocket_int.h.

#define PCI_DEVICE_ID_RP4QUAD   0x0004 /* Rocketport 4 port w/quad cable */

Definition at line 1191 of file rocket_int.h.

#define PCI_DEVICE_ID_RP6M   0x000C /* RocketModem 6 port */

Definition at line 1199 of file rocket_int.h.

#define PCI_DEVICE_ID_RP8INTF   0x0002 /* Rocketport 8 port w/external I/F */

Definition at line 1189 of file rocket_int.h.

#define PCI_DEVICE_ID_RP8J   0x0006 /* Rocketport 8 port w/RJ11 connectors */

Definition at line 1193 of file rocket_int.h.

#define PCI_DEVICE_ID_RP8OCTA   0x0005 /* Rocketport 8 port w/octa cable */

Definition at line 1192 of file rocket_int.h.

#define PCI_DEVICE_ID_RP8SNI   0x0008 /* Rocketport 8 port w/ DB78 SNI (Siemens) connector */

Definition at line 1195 of file rocket_int.h.

#define PCI_DEVICE_ID_RPP4   0x000A /* Rocketport Plus 4 port */

Definition at line 1197 of file rocket_int.h.

#define PCI_DEVICE_ID_RPP8   0x000B /* Rocketport Plus 8 port */

Definition at line 1198 of file rocket_int.h.

#define PCI_DEVICE_ID_UPCI_RM3_4PORT   0x080D /* Rocketmodem III 4 port */

Definition at line 1210 of file rocket_int.h.

#define PCI_DEVICE_ID_UPCI_RM3_8PORT   0x080C /* Rocketmodem III 8 port */

Definition at line 1209 of file rocket_int.h.

#define PCI_DEVICE_ID_URP16INTF   0x0803 /* Rocketport UPCI 16 port w/external I/F */

Definition at line 1207 of file rocket_int.h.

#define PCI_DEVICE_ID_URP32INTF   0x0801 /* Rocketport UPCI 32 port w/external I/F */

Definition at line 1205 of file rocket_int.h.

#define PCI_DEVICE_ID_URP8INTF   0x0802 /* Rocketport UPCI 8 port w/external I/F */

Definition at line 1206 of file rocket_int.h.

#define PCI_DEVICE_ID_URP8OCTA   0x0805 /* Rocketport UPCI 8 port w/octa cable */

Definition at line 1208 of file rocket_int.h.

#define PCI_GPIO_CTRL_8PORT   0x4000

Definition at line 256 of file rocket_int.h.

#define PCI_INT_CTRL_AIOP   0x0001

Definition at line 255 of file rocket_int.h.

#define PCI_STROB   0x2000 /* bit 13 of int aiop register */

Definition at line 247 of file rocket_int.h.

#define PCI_VENDOR_ID_RP   0x11fe

Definition at line 1185 of file rocket_int.h.

#define PERIODIC_ONLY   0x80 /* only PERIODIC interrupt */

Definition at line 270 of file rocket_int.h.

#define PRI_PEND   0x80 /* Priority data pending (bit7, Tx pri cnt) */

Definition at line 141 of file rocket_int.h.

#define RDA   0x01 /* Rx data available */

Definition at line 176 of file rocket_int.h.

#define RDATASIZE   72

Definition at line 274 of file rocket_int.h.

#define REP1W2_EN   0x10 /* replace byte 1 with 2 bytes enable */

Definition at line 220 of file rocket_int.h.

#define RESET_ALL   0x80 /* reset AIOP (all channels) */

Definition at line 226 of file rocket_int.h.

#define RESETUART   0x20 /* reset channel's UART */

Definition at line 228 of file rocket_int.h.

#define RESRXFCNT   0x08 /* reset channel's Rx FIFO count register */

Definition at line 230 of file rocket_int.h.

#define RESTXFCNT   0x10 /* reset channel's Tx FIFO count register */

Definition at line 229 of file rocket_int.h.

#define ROCKET_TYPE_MODEM   1

Definition at line 13 of file rocket_int.h.

#define ROCKET_TYPE_MODEMII   2

Definition at line 14 of file rocket_int.h.

#define ROCKET_TYPE_MODEMIII   3

Definition at line 15 of file rocket_int.h.

#define ROCKET_TYPE_NORMAL   0

Definition at line 12 of file rocket_int.h.

#define ROCKET_TYPE_PC104   4

Definition at line 16 of file rocket_int.h.

#define RPORT_MAGIC   0x525001

Definition at line 1152 of file rocket_int.h.

#define RREGDATASIZE   52

Definition at line 275 of file rocket_int.h.

#define RTSFC_EN   0x40 /* RTS flow control enable */

Definition at line 202 of file rocket_int.h.

#define RTSTOG_EN   0x40 /* RTS toggle enable bit */

Definition at line 189 of file rocket_int.h.

#define RX1MATCH   0x0800 /* receive compare byte 1 match */

Definition at line 182 of file rocket_int.h.

#define RX2MATCH   0x1000 /* receive compare byte 2 match */

Definition at line 181 of file rocket_int.h.

#define RXBREAK   0x0400 /* received BREAK */

Definition at line 183 of file rocket_int.h.

#define RXF_TRIG   0x20 /* Rx FIFO trigger level interrupt */

Definition at line 213 of file rocket_int.h.

#define RXFIFO_SIZE   1023 /* size of Rx FIFO */

Definition at line 143 of file rocket_int.h.

#define RXFOVERFL   0x2000 /* receive FIFO overflow */

Definition at line 180 of file rocket_int.h.

#define RXFRAME   0x0200 /* received framing error */

Definition at line 184 of file rocket_int.h.

#define RXINT_EN   0x02 /* Rx interrupt enable */

Definition at line 210 of file rocket_int.h.

#define RXPARITY   0x0100 /* received parity error */

Definition at line 185 of file rocket_int.h.

#define RXPROC_EN   0x20 /* receive processor enable */

Definition at line 203 of file rocket_int.h.

#define sClrBreak (   ChP)
Value:
do { \
(ChP)->TxControl[3] &= ~SETBREAK; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 381 of file rocket_int.h.

#define sClrDTR (   ChP)
Value:
do { \
(ChP)->TxControl[3] &= ~SET_DTR; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 393 of file rocket_int.h.

#define sClrRTS (   ChP)
Value:
do { \
if ((ChP)->rtsToggle) break; \
(ChP)->TxControl[3] &= ~SET_RTS; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 405 of file rocket_int.h.

#define sClrTxXOFF (   ChP)
Value:
do { \
sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
} while (0)

Definition at line 418 of file rocket_int.h.

#define sControllerEOI (   CTLP)    sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)

Definition at line 439 of file rocket_int.h.

#define sCtlNumToCtlPtr (   CTLNUM)    &sController[CTLNUM]

Definition at line 431 of file rocket_int.h.

#define sDisAiop (   CTLP,
  AIOPNUM 
)
Value:
do { \
(CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
} while (0)

Definition at line 468 of file rocket_int.h.

#define sDisCTSFlowCtl (   ChP)
Value:
do { \
(ChP)->TxControl[2] &= ~CTSFC_EN; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 480 of file rocket_int.h.

#define sDisIXANY (   ChP)
Value:
do { \
(ChP)->R[0x0e] = 0x86; \
out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
} while (0)

Definition at line 492 of file rocket_int.h.

#define sDisParity (   ChP)
Value:
do { \
(ChP)->TxControl[2] &= ~PARITY_EN; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 506 of file rocket_int.h.

#define sDisRTSToggle (   ChP)
Value:
do { \
(ChP)->TxControl[2] &= ~RTSTOG_EN; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
(ChP)->rtsToggle = 0; \
} while (0)

Definition at line 518 of file rocket_int.h.

#define sDisRxFIFO (   ChP)
Value:
do { \
(ChP)->R[0x32] = 0x0a; \
out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
} while (0)

Definition at line 531 of file rocket_int.h.

#define sDisRxStatusMode (   ChP)    sOutW((ChP)->ChanStat,0)

Definition at line 546 of file rocket_int.h.

#define sDisTransmit (   ChP)
Value:
do { \
(ChP)->TxControl[3] &= ~TX_ENABLE; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 558 of file rocket_int.h.

#define sDisTxSoftFlowCtl (   ChP)
Value:
do { \
(ChP)->R[0x06] = 0x8a; \
out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
} while (0)

Definition at line 570 of file rocket_int.h.

#define sEnAiop (   CTLP,
  AIOPNUM 
)
Value:
do { \
(CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
} while (0)

Definition at line 583 of file rocket_int.h.

#define sEnCTSFlowCtl (   ChP)
Value:
do { \
(ChP)->TxControl[2] |= CTSFC_EN; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 595 of file rocket_int.h.

#define sEnIXANY (   ChP)
Value:
do { \
(ChP)->R[0x0e] = 0x21; \
out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
} while (0)

Definition at line 607 of file rocket_int.h.

#define sEnParity (   ChP)
Value:
do { \
(ChP)->TxControl[2] |= PARITY_EN; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 624 of file rocket_int.h.

#define sEnRTSToggle (   ChP)
Value:
do { \
(ChP)->RxControl[2] &= ~RTSFC_EN; \
out32((ChP)->IndexAddr,(ChP)->RxControl); \
(ChP)->TxControl[2] |= RTSTOG_EN; \
(ChP)->TxControl[3] &= ~SET_RTS; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
(ChP)->rtsToggle = 1; \
} while (0)

Definition at line 638 of file rocket_int.h.

#define sEnRxFIFO (   ChP)
Value:
do { \
(ChP)->R[0x32] = 0x08; \
out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
} while (0)

Definition at line 654 of file rocket_int.h.

#define sEnRxProcessor (   ChP)
Value:
do { \
(ChP)->RxControl[2] |= RXPROC_EN; \
out32((ChP)->IndexAddr,(ChP)->RxControl); \
} while (0)

Definition at line 675 of file rocket_int.h.

#define sEnRxStatusMode (   ChP)    sOutW((ChP)->ChanStat,STATMODE)

Definition at line 691 of file rocket_int.h.

#define sEnTransmit (   ChP)
Value:
do { \
(ChP)->TxControl[3] |= TX_ENABLE; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 699 of file rocket_int.h.

#define sEnTxSoftFlowCtl (   ChP)
Value:
do { \
(ChP)->R[0x06] = 0xc5; \
out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
} while (0)

Definition at line 711 of file rocket_int.h.

#define SET_DTR   0x04 /* assert DTR */

Definition at line 198 of file rocket_int.h.

#define SET_RTS   0x02 /* assert RTS */

Definition at line 199 of file rocket_int.h.

#define SETBREAK   0x10 /* send break condition (must clear) */

Definition at line 196 of file rocket_int.h.

#define sGetAiopIntStatus (   CTLP,
  AIOPNUM 
)    sInB((CTLP)->AiopIntChanIO[AIOPNUM])

Definition at line 727 of file rocket_int.h.

#define sGetAiopNumChan (   CTLP,
  AIOPNUM 
)    (CTLP)->AiopNumChan[AIOPNUM]

Definition at line 737 of file rocket_int.h.

#define sGetChanIntID (   ChP)    (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))

Definition at line 753 of file rocket_int.h.

#define sGetChanNum (   ChP)    (ChP)->ChanNum

Definition at line 763 of file rocket_int.h.

#define sGetChanStatus (   ChP)    sInW((ChP)->ChanStat)

Definition at line 791 of file rocket_int.h.

#define sGetChanStatusLo (   ChP)    sInB((ByteIO_t)(ChP)->ChanStat)

Definition at line 807 of file rocket_int.h.

#define sGetControllerIntStatus (   CTLP)    (sInB((CTLP)->MReg1IO) & 0x0f)

Definition at line 832 of file rocket_int.h.

#define sGetRxCnt (   ChP)    sInW((ChP)->TxRxCount)

Definition at line 860 of file rocket_int.h.

#define sGetTxCnt (   ChP)    sInB((ByteIO_t)(ChP)->TxRxCount)

Definition at line 871 of file rocket_int.h.

#define sGetTxRxDataIO (   ChP)    (ChP)->TxRxData

Definition at line 880 of file rocket_int.h.

#define sInitChanDefaults (   ChP)
Value:
do { \
(ChP)->CtlP = NULLCTLPTR; \
(ChP)->AiopNum = NULLAIOP; \
(ChP)->ChanID = AIOPID_NULL; \
(ChP)->ChanNum = NULLCHAN; \
} while (0)

Definition at line 891 of file rocket_int.h.

#define sInStrW (   port,
  addr,
  count 
)    if (count) insw(port, addr, count)

Definition at line 77 of file rocket_int.h.

#define sOutStrW (   port,
  addr,
  count 
)    if (count) outsw(port, addr, count)

Definition at line 76 of file rocket_int.h.

#define sPCIControllerEOI (   CTLP)
Value:
do { \
if ((CTLP)->isUPCI) { \
Word_t w = sInW((CTLP)->PCIIO); \
sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \
sOutW((CTLP)->PCIIO, w); \
} \
else { \
sOutW((CTLP)->PCIIO, PCI_STROB); \
} \
} while (0)

Definition at line 449 of file rocket_int.h.

#define sPCIGetControllerIntStatus (   CTLP)
Value:
((CTLP)->isUPCI ? \
(sInW((CTLP)->PCIIO2) & UPCI_AIOP_INTR_BITS) : \
((sInW((CTLP)->PCIIO) >> 8) & AIOP_INTR_BITS))

Definition at line 845 of file rocket_int.h.

#define SRC_INT   0x08 /* special receive condition interrupt */

Definition at line 215 of file rocket_int.h.

#define SRCINT_EN   0x04 /* special Rx condition interrupt enable */

Definition at line 209 of file rocket_int.h.

#define sResetAiopByNum (   CTLP,
  AIOPNUM 
)
Value:
do { \
sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
} while (0)

Definition at line 906 of file rocket_int.h.

#define sSendBreak (   ChP)
Value:
do { \
(ChP)->TxControl[3] |= SETBREAK; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 918 of file rocket_int.h.

#define sSetBaud (   ChP,
  DIVISOR 
)
Value:
do { \
(ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
(ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
out32((ChP)->IndexAddr,(ChP)->BaudDiv); \
} while (0)

Definition at line 931 of file rocket_int.h.

#define sSetData7 (   ChP)
Value:
do { \
(ChP)->TxControl[2] &= ~DATA8BIT; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 944 of file rocket_int.h.

#define sSetData8 (   ChP)
Value:
do { \
(ChP)->TxControl[2] |= DATA8BIT; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 956 of file rocket_int.h.

#define sSetDTR (   ChP)
Value:
do { \
(ChP)->TxControl[3] |= SET_DTR; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 968 of file rocket_int.h.

#define sSetEvenParity (   ChP)
Value:
do { \
(ChP)->TxControl[2] |= EVEN_PAR; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 985 of file rocket_int.h.

#define sSetOddParity (   ChP)
Value:
do { \
(ChP)->TxControl[2] &= ~EVEN_PAR; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 1002 of file rocket_int.h.

#define sSetRTS (   ChP)
Value:
do { \
if ((ChP)->rtsToggle) break; \
(ChP)->TxControl[3] |= SET_RTS; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 1014 of file rocket_int.h.

#define sSetRxTrigger (   ChP,
  LEVEL 
)
Value:
do { \
(ChP)->RxControl[2] &= ~TRIG_MASK; \
(ChP)->RxControl[2] |= LEVEL; \
out32((ChP)->IndexAddr,(ChP)->RxControl); \
} while (0)

Definition at line 1040 of file rocket_int.h.

#define sSetStop1 (   ChP)
Value:
do { \
(ChP)->TxControl[2] &= ~STOP2; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 1053 of file rocket_int.h.

#define sSetStop2 (   ChP)
Value:
do { \
(ChP)->TxControl[2] |= STOP2; \
out32((ChP)->IndexAddr,(ChP)->TxControl); \
} while (0)

Definition at line 1065 of file rocket_int.h.

#define sSetTxXOFFChar (   ChP,
  CH 
)
Value:
do { \
(ChP)->R[0x07] = (CH); \
out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
} while (0)

Definition at line 1078 of file rocket_int.h.

#define sSetTxXONChar (   ChP,
  CH 
)
Value:
do { \
(ChP)->R[0x0b] = (CH); \
out32((ChP)->IndexAddr,&(ChP)->R[0x08]); \
} while (0)

Definition at line 1091 of file rocket_int.h.

#define sStartRxProcessor (   ChP)    out32((ChP)->IndexAddr,&(ChP)->R[0])

Definition at line 1107 of file rocket_int.h.

#define STATERROR   (RXBREAK | RXFRAME | RXPARITY)

Definition at line 186 of file rocket_int.h.

#define STATMODE   0x8000 /* status mode enable bit */

Definition at line 179 of file rocket_int.h.

#define STMBREAK   0x08 /* BREAK */

Definition at line 160 of file rocket_int.h.

#define STMBREAKH   0x800 /* BREAK */

Definition at line 165 of file rocket_int.h.

#define STMERROR   (STMBREAK | STMFRAME | STMPARITY)

Definition at line 164 of file rocket_int.h.

#define STMERRORH   (STMBREAKH | STMFRAMEH | STMPARITYH)

Definition at line 169 of file rocket_int.h.

#define STMFRAME   0x04 /* framing error */

Definition at line 161 of file rocket_int.h.

#define STMFRAMEH   0x400 /* framing error */

Definition at line 166 of file rocket_int.h.

#define STMPARITY   0x01 /* parity error */

Definition at line 163 of file rocket_int.h.

#define STMPARITYH   0x100 /* parity error */

Definition at line 168 of file rocket_int.h.

#define STMRCVROVR   0x02 /* receiver over run error */

Definition at line 162 of file rocket_int.h.

#define STMRCVROVRH   0x200 /* receiver over run error */

Definition at line 167 of file rocket_int.h.

#define STOP2   0x08 /* enable 2 stop bits (0 = 1 stop) */

Definition at line 191 of file rocket_int.h.

#define sWriteTxByte (   IO,
  DATA 
)    sOutB(IO,DATA)

Definition at line 1118 of file rocket_int.h.

#define TRIG_1   0x08 /* trigger level 1 char */

Definition at line 205 of file rocket_int.h.

#define TRIG_1_2   0x10 /* trigger level 1/2 */

Definition at line 206 of file rocket_int.h.

#define TRIG_7_8   0x18 /* trigger level 7/8 */

Definition at line 207 of file rocket_int.h.

#define TRIG_MASK   0x18 /* trigger level mask */

Definition at line 208 of file rocket_int.h.

#define TRIG_NO   0x00 /* Rx FIFO trigger level 0 (no trigger) */

Definition at line 204 of file rocket_int.h.

#define TTY_ROCKET_MAJOR   46

Definition at line 1168 of file rocket_int.h.

#define TX_ENABLE   0x01 /* enable transmitter */

Definition at line 200 of file rocket_int.h.

#define TXFIFO_MT   0x10 /* Tx FIFO empty interrupt */

Definition at line 214 of file rocket_int.h.

#define TXFIFO_SIZE   255 /* size of Tx FIFO */

Definition at line 142 of file rocket_int.h.

#define TXFIFOMT   0x04 /* Tx FIFO is empty */

Definition at line 174 of file rocket_int.h.

#define TXINT_EN   0x10 /* transmit interrupt enable */

Definition at line 190 of file rocket_int.h.

#define TXOVERIDE   0x40 /* Transmit software off override */

Definition at line 227 of file rocket_int.h.

#define TXP_SIZE   0x20 /* 32 bytes */

Definition at line 149 of file rocket_int.h.

#define TXSHRMT   0x02 /* Tx shift register is empty */

Definition at line 175 of file rocket_int.h.

#define UPCI_AIOP_INTR_BIT_0   0x0004

Definition at line 291 of file rocket_int.h.

#define UPCI_AIOP_INTR_BIT_1   0x0020

Definition at line 292 of file rocket_int.h.

#define UPCI_AIOP_INTR_BIT_2   0x0100

Definition at line 293 of file rocket_int.h.

#define UPCI_AIOP_INTR_BIT_3   0x0800

Definition at line 294 of file rocket_int.h.

#define UPCI_AIOP_INTR_BITS
Value:
( \
UPCI_AIOP_INTR_BIT_0 \
| UPCI_AIOP_INTR_BIT_1 \
| UPCI_AIOP_INTR_BIT_2 \
| UPCI_AIOP_INTR_BIT_3)

Definition at line 296 of file rocket_int.h.

#define WAKEUP_CHARS   256

Definition at line 1163 of file rocket_int.h.

#define XMIT_BUF_SIZE   4096

Definition at line 1160 of file rocket_int.h.

Typedef Documentation

typedef unsigned char Byte_t

Definition at line 23 of file rocket_int.h.

typedef unsigned int ByteIO_t

Definition at line 24 of file rocket_int.h.

typedef CHANNEL_T CHANNEL_t

Definition at line 367 of file rocket_int.h.

typedef CHANNEL_T* CHANPTR_T

Definition at line 368 of file rocket_int.h.

typedef CONTROLLER_T CONTROLLER_t

Definition at line 327 of file rocket_int.h.

typedef unsigned int DWordIO_t

Definition at line 29 of file rocket_int.h.

typedef unsigned int Word_t

Definition at line 26 of file rocket_int.h.

typedef unsigned int WordIO_t

Definition at line 27 of file rocket_int.h.

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