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| #define CHAR_API_WHAT_BIT 0x00080000 /* Char API vs network only */ |
| #define CMD_EVT_WHAT_BIT 0x00200000 /* Command event */ |
| #define CMD_RING_ENTRIES 16 |
| #define DMA_ERROR_MASK 0xff000000 |
| #define DMA_READ_DONE 0x20000 |
| #define DMA_READ_ERR 0x80000 |
| #define DMA_WRITE_DONE 0x10000 |
| #define DMA_WRITE_ERR 0x40000 |
| #define E_CON_NC_TMOUT 0x15 /* I , Connection No Campon Timeout */ |
| #define E_DTA_CKSM_ERR 0x2E |
| #define E_FLG_SYN_ERR 0x31 |
| #define E_INTERN_ERR 0x09 |
| #define E_IP_CKSM_ERR 0x2D |
| #define E_LST_LNK_ERR 0x30 |
| #define E_NOT_IMPLEMENTED 0x40 |
| #define E_PKT_DISCARD 0x25 |
| #define E_PKT_LN_ERR 0x34 |
| #define E_RX_INV_BUF 0x36 |
| #define E_RX_INV_DSC 0x37 |
| #define E_RX_LLRC_ERR 0x2C |
| #define E_RX_PAR_ERR 0x2B |
| #define E_RX_RNG_ENER 0x21 |
| #define E_RX_RNG_OUT 0x24 |
| #define E_RX_RNG_SPC 0x23 |
| #define E_SET_CMD_CONS 0x06 |
| #define E_STATS_UPDATE 0x0B |
| #define E_TX_INV_BUF 0x1B |
| #define E_TX_INV_DSC 0x1C |
| #define E_TX_INV_RNG 0x1A |
| #define E_TX_LINK_DROP 0x19 |
| #define E_UNEXP_DATA 0x3C |
| #define EEPROM_BASE 0x80000000 |
| #define EEPROM_WORDS 8192 |
| #define ENABLE_DATA_CACHE 0x2000 |
| #define ENABLE_EEPROM_WRITE 0x1000 |
| #define ENABLE_EXTRA_DESC 0x200 |
| #define ENABLE_EXTRA_SRAM 0x100 |
| #define ENABLE_NEW_CON 0x01 |
| #define ENABLE_PARITY 0x400 |
| #define ERR_BAD_STARTUP 0x12 |
| #define ERR_DR_PEND_CMND_FULL 0x03 |
| #define ERR_DR_PEND_DATA_FULL 0x05 |
| #define ERR_DW_PEND_CMND_FULL 0x02 |
| #define ERR_DW_PEND_DATA_FULL 0x04 |
| #define ERR_EVENT_BITS 0x0C |
| #define ERR_EVENT_RING_FULL 0x01 |
| #define ERR_EXT_SERIAL 0x0103 |
| #define ERR_HALTED_ON_ERR 0x14 |
| #define ERR_ILLEGAL_JUMP 0x06 |
| #define ERR_ILLEGAL_MODE 0x0A |
| #define ERR_INTR_START 0x11 |
| #define ERR_MAIN_TIMEOUT 0x0B |
| #define ERR_MAX_RING 0x1003 |
| #define ERR_NO_PKT_END 0x13 |
| #define ERR_READ_DMA 0x0102 |
| #define ERR_RING_CLOSED 0x1004 |
| #define ERR_RING_OPEN 0x1005 |
| #define ERR_RX_INFO_FULL 0x09 |
| #define ERR_TIMER_NO_FREE 0x10 |
| #define ERR_TIMER_QUEUE_EMPTY 0x0F |
| #define ERR_TIMER_QUEUE_FULL 0x0E |
| #define ERR_TX_INFO_FULL 0x08 |
| #define ERR_TX_INT_PARITY 0x0104 |
| #define ERR_UNIMPLEMENTED 0x07 |
| #define ERR_UNKNOWN_CMD 0x1002 |
| #define ERR_UNKNOWN_MBOX 0x1001 |
| #define ERR_UNPEND_FULL 0x0D |
| #define ERR_WRITE_DMA 0x0101 |
| #define EVENT_OVFL 0x80000000 |
| #define EVT_RING_ENTRIES 64 |
| #define FAST_EEPROM_ACCESS 0x08 |
| #define FATAL_ERR 0x40000000 |
| #define FIFO_RETRY_ENABLE 0x10000 |
| #define FORCE_DMA_PARITY_ERROR 0x800 |
| #define FORCE_PCI_RESET 0x01 |
| #define HALF_DUP_RX 0x2000 |
| #define HALF_DUP_TX 0x1000 |
| #define INVALID_INST_B 0x800 |
| #define LONG_RX_WHAT_BIT 0x00800000 |
| #define LONG_TX_WHAT_BIT 0x00400000 |
| #define MASK_DMA_READ_MAX 0x1C |
| #define MASK_DMA_WRITE_MAX 0xE0 |
| #define MASK_MIN_DMA 0xFF00 |
| #define MEM_READ_MULTI 0x40 |
| #define NIC_HALT_ON_ERR 0x400 |
| #define NIC_NO_RESTART 0x800 |
| #define NO_NIC_WATCHDOG 0x80 |
| #define NO_SWAP 0x04000004 |
| #define NO_SWAP1 0x00000004 |
| #define ONEM_BUF_WHAT_BIT 0x00040000 /* 1Meg vs 256K */ |
| #define PACKET_BAD 0x01 /* Packet had link-layer error */ |
| #define PACKET_START 0x10 |
| #define PCI_RESET_NIC 0x08 |
| #define POST_WARN_EVENT 0x10 |
| #define PROVIDE_LENGTH 0x02 |
| #define PTR_WD_NOSWAP 0x00 |
| #define RBURST_DISABLE 0x00 |
| #define RR_CLEAR_INT 0x02 |
| #define RR_REV_2 0x20000000 |
| #define RR_REV_MASK 0xf0000000 |
| #define RX_RING_ENTRIES 16 |
| #define SRAM_HI_PARITY_ERR 0x8000 |
| #define SRAM_LO_PARITY_ERR 0x4000 |
| #define SWAP_CONTROL 0x200 |
| #define TRACE_ON_WHAT_BIT 0x00020000 /* Traces on */ |
| #define TX_RING_ENTRIES 16 |
| #define WBURST_DISABLE 0x00 |
| #define WHAT_BIT_MASK 0xFFFD0000 /* Feature bit mask */ |
1.8.2