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Data Structures | Macros | Variables
rt61pci.h File Reference

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Data Structures

struct  hw_key_entry
 
struct  hw_pairwise_ta_entry
 

Macros

#define RT2561s_PCI_ID   0x0301
 
#define RT2561_PCI_ID   0x0302
 
#define RT2661_PCI_ID   0x0401
 
#define RF5225   0x0001
 
#define RF5325   0x0002
 
#define RF2527   0x0003
 
#define RF2529   0x0004
 
#define DEFAULT_RSSI_OFFSET   120
 
#define CSR_REG_BASE   0x3000
 
#define CSR_REG_SIZE   0x04b0
 
#define EEPROM_BASE   0x0000
 
#define EEPROM_SIZE   0x0100
 
#define BBP_BASE   0x0000
 
#define BBP_SIZE   0x0080
 
#define RF_BASE   0x0004
 
#define RF_SIZE   0x0010
 
#define NUM_TX_QUEUES   4
 
#define HOST_CMD_CSR   0x0008
 
#define HOST_CMD_CSR_HOST_COMMAND   FIELD32(0x0000007f)
 
#define HOST_CMD_CSR_INTERRUPT_MCU   FIELD32(0x00000080)
 
#define MCU_CNTL_CSR   0x000c
 
#define MCU_CNTL_CSR_SELECT_BANK   FIELD32(0x00000001)
 
#define MCU_CNTL_CSR_RESET   FIELD32(0x00000002)
 
#define MCU_CNTL_CSR_READY   FIELD32(0x00000004)
 
#define SOFT_RESET_CSR   0x0010
 
#define SOFT_RESET_CSR_FORCE_CLOCK_ON   FIELD32(0x00000002)
 
#define MCU_INT_SOURCE_CSR   0x0014
 
#define MCU_INT_SOURCE_CSR_0   FIELD32(0x00000001)
 
#define MCU_INT_SOURCE_CSR_1   FIELD32(0x00000002)
 
#define MCU_INT_SOURCE_CSR_2   FIELD32(0x00000004)
 
#define MCU_INT_SOURCE_CSR_3   FIELD32(0x00000008)
 
#define MCU_INT_SOURCE_CSR_4   FIELD32(0x00000010)
 
#define MCU_INT_SOURCE_CSR_5   FIELD32(0x00000020)
 
#define MCU_INT_SOURCE_CSR_6   FIELD32(0x00000040)
 
#define MCU_INT_SOURCE_CSR_7   FIELD32(0x00000080)
 
#define MCU_INT_SOURCE_CSR_TWAKEUP   FIELD32(0x00000100)
 
#define MCU_INT_SOURCE_CSR_TBTT_EXPIRE   FIELD32(0x00000200)
 
#define MCU_INT_MASK_CSR   0x0018
 
#define MCU_INT_MASK_CSR_0   FIELD32(0x00000001)
 
#define MCU_INT_MASK_CSR_1   FIELD32(0x00000002)
 
#define MCU_INT_MASK_CSR_2   FIELD32(0x00000004)
 
#define MCU_INT_MASK_CSR_3   FIELD32(0x00000008)
 
#define MCU_INT_MASK_CSR_4   FIELD32(0x00000010)
 
#define MCU_INT_MASK_CSR_5   FIELD32(0x00000020)
 
#define MCU_INT_MASK_CSR_6   FIELD32(0x00000040)
 
#define MCU_INT_MASK_CSR_7   FIELD32(0x00000080)
 
#define MCU_INT_MASK_CSR_TWAKEUP   FIELD32(0x00000100)
 
#define MCU_INT_MASK_CSR_TBTT_EXPIRE   FIELD32(0x00000200)
 
#define PCI_USEC_CSR   0x001c
 
#define SHARED_KEY_TABLE_BASE   0x1000
 
#define PAIRWISE_KEY_TABLE_BASE   0x1200
 
#define PAIRWISE_TA_TABLE_BASE   0x1a00
 
#define SHARED_KEY_ENTRY(__idx)
 
#define PAIRWISE_KEY_ENTRY(__idx)
 
#define PAIRWISE_TA_ENTRY(__idx)
 
#define HW_CIS_BASE   0x2000
 
#define HW_NULL_BASE   0x2b00
 
#define HW_DEBUG_SETTING_BASE   0x2bf0
 
#define HW_BEACON_BASE0   0x2c00
 
#define HW_BEACON_BASE1   0x2d00
 
#define HW_BEACON_BASE2   0x2e00
 
#define HW_BEACON_BASE3   0x2f00
 
#define HW_BEACON_OFFSET(__index)   ( HW_BEACON_BASE0 + (__index * 0x0100) )
 
#define H2M_MAILBOX_CSR   0x2100
 
#define H2M_MAILBOX_CSR_ARG0   FIELD32(0x000000ff)
 
#define H2M_MAILBOX_CSR_ARG1   FIELD32(0x0000ff00)
 
#define H2M_MAILBOX_CSR_CMD_TOKEN   FIELD32(0x00ff0000)
 
#define H2M_MAILBOX_CSR_OWNER   FIELD32(0xff000000)
 
#define MCU_LEDCS_LED_MODE   FIELD16(0x001f)
 
#define MCU_LEDCS_RADIO_STATUS   FIELD16(0x0020)
 
#define MCU_LEDCS_LINK_BG_STATUS   FIELD16(0x0040)
 
#define MCU_LEDCS_LINK_A_STATUS   FIELD16(0x0080)
 
#define MCU_LEDCS_POLARITY_GPIO_0   FIELD16(0x0100)
 
#define MCU_LEDCS_POLARITY_GPIO_1   FIELD16(0x0200)
 
#define MCU_LEDCS_POLARITY_GPIO_2   FIELD16(0x0400)
 
#define MCU_LEDCS_POLARITY_GPIO_3   FIELD16(0x0800)
 
#define MCU_LEDCS_POLARITY_GPIO_4   FIELD16(0x1000)
 
#define MCU_LEDCS_POLARITY_ACT   FIELD16(0x2000)
 
#define MCU_LEDCS_POLARITY_READY_BG   FIELD16(0x4000)
 
#define MCU_LEDCS_POLARITY_READY_A   FIELD16(0x8000)
 
#define M2H_CMD_DONE_CSR   0x2104
 
#define MCU_TXOP_ARRAY_BASE   0x2110
 
#define MAC_CSR0   0x3000
 
#define MAC_CSR0_REVISION   FIELD32(0x0000000f)
 
#define MAC_CSR0_CHIPSET   FIELD32(0x000ffff0)
 
#define MAC_CSR1   0x3004
 
#define MAC_CSR1_SOFT_RESET   FIELD32(0x00000001)
 
#define MAC_CSR1_BBP_RESET   FIELD32(0x00000002)
 
#define MAC_CSR1_HOST_READY   FIELD32(0x00000004)
 
#define MAC_CSR2   0x3008
 
#define MAC_CSR2_BYTE0   FIELD32(0x000000ff)
 
#define MAC_CSR2_BYTE1   FIELD32(0x0000ff00)
 
#define MAC_CSR2_BYTE2   FIELD32(0x00ff0000)
 
#define MAC_CSR2_BYTE3   FIELD32(0xff000000)
 
#define MAC_CSR3   0x300c
 
#define MAC_CSR3_BYTE4   FIELD32(0x000000ff)
 
#define MAC_CSR3_BYTE5   FIELD32(0x0000ff00)
 
#define MAC_CSR3_UNICAST_TO_ME_MASK   FIELD32(0x00ff0000)
 
#define MAC_CSR4   0x3010
 
#define MAC_CSR4_BYTE0   FIELD32(0x000000ff)
 
#define MAC_CSR4_BYTE1   FIELD32(0x0000ff00)
 
#define MAC_CSR4_BYTE2   FIELD32(0x00ff0000)
 
#define MAC_CSR4_BYTE3   FIELD32(0xff000000)
 
#define MAC_CSR5   0x3014
 
#define MAC_CSR5_BYTE4   FIELD32(0x000000ff)
 
#define MAC_CSR5_BYTE5   FIELD32(0x0000ff00)
 
#define MAC_CSR5_BSS_ID_MASK   FIELD32(0x00ff0000)
 
#define MAC_CSR6   0x3018
 
#define MAC_CSR6_MAX_FRAME_UNIT   FIELD32(0x00000fff)
 
#define MAC_CSR7   0x301c
 
#define MAC_CSR8   0x3020
 
#define MAC_CSR8_SIFS   FIELD32(0x000000ff)
 
#define MAC_CSR8_SIFS_AFTER_RX_OFDM   FIELD32(0x0000ff00)
 
#define MAC_CSR8_EIFS   FIELD32(0xffff0000)
 
#define MAC_CSR9   0x3024
 
#define MAC_CSR9_SLOT_TIME   FIELD32(0x000000ff)
 
#define MAC_CSR9_CWMIN   FIELD32(0x00000f00)
 
#define MAC_CSR9_CWMAX   FIELD32(0x0000f000)
 
#define MAC_CSR9_CW_SELECT   FIELD32(0x00010000)
 
#define MAC_CSR10   0x3028
 
#define MAC_CSR11   0x302c
 
#define MAC_CSR11_DELAY_AFTER_TBCN   FIELD32(0x000000ff)
 
#define MAC_CSR11_TBCN_BEFORE_WAKEUP   FIELD32(0x00007f00)
 
#define MAC_CSR11_AUTOWAKE   FIELD32(0x00008000)
 
#define MAC_CSR11_WAKEUP_LATENCY   FIELD32(0x000f0000)
 
#define MAC_CSR12   0x3030
 
#define MAC_CSR12_CURRENT_STATE   FIELD32(0x00000001)
 
#define MAC_CSR12_PUT_TO_SLEEP   FIELD32(0x00000002)
 
#define MAC_CSR12_FORCE_WAKEUP   FIELD32(0x00000004)
 
#define MAC_CSR12_BBP_CURRENT_STATE   FIELD32(0x00000008)
 
#define MAC_CSR13   0x3034
 
#define MAC_CSR13_VAL0   FIELD32(0x00000001)
 
#define MAC_CSR13_VAL1   FIELD32(0x00000002)
 
#define MAC_CSR13_VAL2   FIELD32(0x00000004)
 
#define MAC_CSR13_VAL3   FIELD32(0x00000008)
 
#define MAC_CSR13_VAL4   FIELD32(0x00000010)
 
#define MAC_CSR13_VAL5   FIELD32(0x00000020)
 
#define MAC_CSR13_DIR0   FIELD32(0x00000100)
 
#define MAC_CSR13_DIR1   FIELD32(0x00000200)
 
#define MAC_CSR13_DIR2   FIELD32(0x00000400)
 
#define MAC_CSR13_DIR3   FIELD32(0x00000800)
 
#define MAC_CSR13_DIR4   FIELD32(0x00001000)
 
#define MAC_CSR13_DIR5   FIELD32(0x00002000)
 
#define MAC_CSR14   0x3038
 
#define MAC_CSR14_ON_PERIOD   FIELD32(0x000000ff)
 
#define MAC_CSR14_OFF_PERIOD   FIELD32(0x0000ff00)
 
#define MAC_CSR14_HW_LED   FIELD32(0x00010000)
 
#define MAC_CSR14_SW_LED   FIELD32(0x00020000)
 
#define MAC_CSR14_HW_LED_POLARITY   FIELD32(0x00040000)
 
#define MAC_CSR14_SW_LED2   FIELD32(0x00080000)
 
#define MAC_CSR15   0x303c
 
#define TXRX_CSR0   0x3040
 
#define TXRX_CSR0_RX_ACK_TIMEOUT   FIELD32(0x000001ff)
 
#define TXRX_CSR0_TSF_OFFSET   FIELD32(0x00007e00)
 
#define TXRX_CSR0_AUTO_TX_SEQ   FIELD32(0x00008000)
 
#define TXRX_CSR0_DISABLE_RX   FIELD32(0x00010000)
 
#define TXRX_CSR0_DROP_CRC   FIELD32(0x00020000)
 
#define TXRX_CSR0_DROP_PHYSICAL   FIELD32(0x00040000)
 
#define TXRX_CSR0_DROP_CONTROL   FIELD32(0x00080000)
 
#define TXRX_CSR0_DROP_NOT_TO_ME   FIELD32(0x00100000)
 
#define TXRX_CSR0_DROP_TO_DS   FIELD32(0x00200000)
 
#define TXRX_CSR0_DROP_VERSION_ERROR   FIELD32(0x00400000)
 
#define TXRX_CSR0_DROP_MULTICAST   FIELD32(0x00800000)
 
#define TXRX_CSR0_DROP_BROADCAST   FIELD32(0x01000000)
 
#define TXRX_CSR0_DROP_ACK_CTS   FIELD32(0x02000000)
 
#define TXRX_CSR0_TX_WITHOUT_WAITING   FIELD32(0x04000000)
 
#define TXRX_CSR1   0x3044
 
#define TXRX_CSR1_BBP_ID0   FIELD32(0x0000007f)
 
#define TXRX_CSR1_BBP_ID0_VALID   FIELD32(0x00000080)
 
#define TXRX_CSR1_BBP_ID1   FIELD32(0x00007f00)
 
#define TXRX_CSR1_BBP_ID1_VALID   FIELD32(0x00008000)
 
#define TXRX_CSR1_BBP_ID2   FIELD32(0x007f0000)
 
#define TXRX_CSR1_BBP_ID2_VALID   FIELD32(0x00800000)
 
#define TXRX_CSR1_BBP_ID3   FIELD32(0x7f000000)
 
#define TXRX_CSR1_BBP_ID3_VALID   FIELD32(0x80000000)
 
#define TXRX_CSR2   0x3048
 
#define TXRX_CSR2_BBP_ID0   FIELD32(0x0000007f)
 
#define TXRX_CSR2_BBP_ID0_VALID   FIELD32(0x00000080)
 
#define TXRX_CSR2_BBP_ID1   FIELD32(0x00007f00)
 
#define TXRX_CSR2_BBP_ID1_VALID   FIELD32(0x00008000)
 
#define TXRX_CSR2_BBP_ID2   FIELD32(0x007f0000)
 
#define TXRX_CSR2_BBP_ID2_VALID   FIELD32(0x00800000)
 
#define TXRX_CSR2_BBP_ID3   FIELD32(0x7f000000)
 
#define TXRX_CSR2_BBP_ID3_VALID   FIELD32(0x80000000)
 
#define TXRX_CSR3   0x304c
 
#define TXRX_CSR3_BBP_ID0   FIELD32(0x0000007f)
 
#define TXRX_CSR3_BBP_ID0_VALID   FIELD32(0x00000080)
 
#define TXRX_CSR3_BBP_ID1   FIELD32(0x00007f00)
 
#define TXRX_CSR3_BBP_ID1_VALID   FIELD32(0x00008000)
 
#define TXRX_CSR3_BBP_ID2   FIELD32(0x007f0000)
 
#define TXRX_CSR3_BBP_ID2_VALID   FIELD32(0x00800000)
 
#define TXRX_CSR3_BBP_ID3   FIELD32(0x7f000000)
 
#define TXRX_CSR3_BBP_ID3_VALID   FIELD32(0x80000000)
 
#define TXRX_CSR4   0x3050
 
#define TXRX_CSR4_TX_ACK_TIMEOUT   FIELD32(0x000000ff)
 
#define TXRX_CSR4_CNTL_ACK_POLICY   FIELD32(0x00000700)
 
#define TXRX_CSR4_ACK_CTS_PSM   FIELD32(0x00010000)
 
#define TXRX_CSR4_AUTORESPOND_ENABLE   FIELD32(0x00020000)
 
#define TXRX_CSR4_AUTORESPOND_PREAMBLE   FIELD32(0x00040000)
 
#define TXRX_CSR4_OFDM_TX_RATE_DOWN   FIELD32(0x00080000)
 
#define TXRX_CSR4_OFDM_TX_RATE_STEP   FIELD32(0x00300000)
 
#define TXRX_CSR4_OFDM_TX_FALLBACK_CCK   FIELD32(0x00400000)
 
#define TXRX_CSR4_LONG_RETRY_LIMIT   FIELD32(0x0f000000)
 
#define TXRX_CSR4_SHORT_RETRY_LIMIT   FIELD32(0xf0000000)
 
#define TXRX_CSR5   0x3054
 
#define TXRX_CSR6   0x3058
 
#define TXRX_CSR7   0x305c
 
#define TXRX_CSR7_ACK_CTS_6MBS   FIELD32(0x000000ff)
 
#define TXRX_CSR7_ACK_CTS_9MBS   FIELD32(0x0000ff00)
 
#define TXRX_CSR7_ACK_CTS_12MBS   FIELD32(0x00ff0000)
 
#define TXRX_CSR7_ACK_CTS_18MBS   FIELD32(0xff000000)
 
#define TXRX_CSR8   0x3060
 
#define TXRX_CSR8_ACK_CTS_24MBS   FIELD32(0x000000ff)
 
#define TXRX_CSR8_ACK_CTS_36MBS   FIELD32(0x0000ff00)
 
#define TXRX_CSR8_ACK_CTS_48MBS   FIELD32(0x00ff0000)
 
#define TXRX_CSR8_ACK_CTS_54MBS   FIELD32(0xff000000)
 
#define TXRX_CSR9   0x3064
 
#define TXRX_CSR9_BEACON_INTERVAL   FIELD32(0x0000ffff)
 
#define TXRX_CSR9_TSF_TICKING   FIELD32(0x00010000)
 
#define TXRX_CSR9_TSF_SYNC   FIELD32(0x00060000)
 
#define TXRX_CSR9_TBTT_ENABLE   FIELD32(0x00080000)
 
#define TXRX_CSR9_BEACON_GEN   FIELD32(0x00100000)
 
#define TXRX_CSR9_TIMESTAMP_COMPENSATE   FIELD32(0xff000000)
 
#define TXRX_CSR10   0x3068
 
#define TXRX_CSR11   0x306c
 
#define TXRX_CSR12   0x3070
 
#define TXRX_CSR12_LOW_TSFTIMER   FIELD32(0xffffffff)
 
#define TXRX_CSR13   0x3074
 
#define TXRX_CSR13_HIGH_TSFTIMER   FIELD32(0xffffffff)
 
#define TXRX_CSR14   0x3078
 
#define TXRX_CSR15   0x307c
 
#define PHY_CSR0   0x3080
 
#define PHY_CSR0_PA_PE_BG   FIELD32(0x00010000)
 
#define PHY_CSR0_PA_PE_A   FIELD32(0x00020000)
 
#define PHY_CSR1   0x3084
 
#define PHY_CSR2   0x3088
 
#define PHY_CSR3   0x308c
 
#define PHY_CSR3_VALUE   FIELD32(0x000000ff)
 
#define PHY_CSR3_REGNUM   FIELD32(0x00007f00)
 
#define PHY_CSR3_READ_CONTROL   FIELD32(0x00008000)
 
#define PHY_CSR3_BUSY   FIELD32(0x00010000)
 
#define PHY_CSR4   0x3090
 
#define PHY_CSR4_VALUE   FIELD32(0x00ffffff)
 
#define PHY_CSR4_NUMBER_OF_BITS   FIELD32(0x1f000000)
 
#define PHY_CSR4_IF_SELECT   FIELD32(0x20000000)
 
#define PHY_CSR4_PLL_LD   FIELD32(0x40000000)
 
#define PHY_CSR4_BUSY   FIELD32(0x80000000)
 
#define PHY_CSR5   0x3094
 
#define PHY_CSR5_IQ_FLIP   FIELD32(0x00000004)
 
#define PHY_CSR6   0x3098
 
#define PHY_CSR6_IQ_FLIP   FIELD32(0x00000004)
 
#define PHY_CSR7   0x309c
 
#define SEC_CSR0   0x30a0
 
#define SEC_CSR0_BSS0_KEY0_VALID   FIELD32(0x00000001)
 
#define SEC_CSR0_BSS0_KEY1_VALID   FIELD32(0x00000002)
 
#define SEC_CSR0_BSS0_KEY2_VALID   FIELD32(0x00000004)
 
#define SEC_CSR0_BSS0_KEY3_VALID   FIELD32(0x00000008)
 
#define SEC_CSR0_BSS1_KEY0_VALID   FIELD32(0x00000010)
 
#define SEC_CSR0_BSS1_KEY1_VALID   FIELD32(0x00000020)
 
#define SEC_CSR0_BSS1_KEY2_VALID   FIELD32(0x00000040)
 
#define SEC_CSR0_BSS1_KEY3_VALID   FIELD32(0x00000080)
 
#define SEC_CSR0_BSS2_KEY0_VALID   FIELD32(0x00000100)
 
#define SEC_CSR0_BSS2_KEY1_VALID   FIELD32(0x00000200)
 
#define SEC_CSR0_BSS2_KEY2_VALID   FIELD32(0x00000400)
 
#define SEC_CSR0_BSS2_KEY3_VALID   FIELD32(0x00000800)
 
#define SEC_CSR0_BSS3_KEY0_VALID   FIELD32(0x00001000)
 
#define SEC_CSR0_BSS3_KEY1_VALID   FIELD32(0x00002000)
 
#define SEC_CSR0_BSS3_KEY2_VALID   FIELD32(0x00004000)
 
#define SEC_CSR0_BSS3_KEY3_VALID   FIELD32(0x00008000)
 
#define SEC_CSR1   0x30a4
 
#define SEC_CSR1_BSS0_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 
#define SEC_CSR1_BSS0_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 
#define SEC_CSR1_BSS0_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 
#define SEC_CSR1_BSS0_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 
#define SEC_CSR1_BSS1_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 
#define SEC_CSR1_BSS1_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 
#define SEC_CSR1_BSS1_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 
#define SEC_CSR1_BSS1_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 
#define SEC_CSR2   0x30a8
 
#define SEC_CSR3   0x30ac
 
#define SEC_CSR4   0x30b0
 
#define SEC_CSR4_ENABLE_BSS0   FIELD32(0x00000001)
 
#define SEC_CSR4_ENABLE_BSS1   FIELD32(0x00000002)
 
#define SEC_CSR4_ENABLE_BSS2   FIELD32(0x00000004)
 
#define SEC_CSR4_ENABLE_BSS3   FIELD32(0x00000008)
 
#define SEC_CSR5   0x30b4
 
#define SEC_CSR5_BSS2_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 
#define SEC_CSR5_BSS2_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 
#define SEC_CSR5_BSS2_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 
#define SEC_CSR5_BSS2_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 
#define SEC_CSR5_BSS3_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 
#define SEC_CSR5_BSS3_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 
#define SEC_CSR5_BSS3_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 
#define SEC_CSR5_BSS3_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 
#define STA_CSR0   0x30c0
 
#define STA_CSR0_FCS_ERROR   FIELD32(0x0000ffff)
 
#define STA_CSR0_PLCP_ERROR   FIELD32(0xffff0000)
 
#define STA_CSR1   0x30c4
 
#define STA_CSR1_PHYSICAL_ERROR   FIELD32(0x0000ffff)
 
#define STA_CSR1_FALSE_CCA_ERROR   FIELD32(0xffff0000)
 
#define STA_CSR2   0x30c8
 
#define STA_CSR2_RX_FIFO_OVERFLOW_COUNT   FIELD32(0x0000ffff)
 
#define STA_CSR2_RX_OVERFLOW_COUNT   FIELD32(0xffff0000)
 
#define STA_CSR3   0x30cc
 
#define STA_CSR3_TX_BEACON_COUNT   FIELD32(0x0000ffff)
 
#define STA_CSR4   0x30d0
 
#define STA_CSR4_VALID   FIELD32(0x00000001)
 
#define STA_CSR4_TX_RESULT   FIELD32(0x0000000e)
 
#define STA_CSR4_RETRY_COUNT   FIELD32(0x000000f0)
 
#define STA_CSR4_PID_SUBTYPE   FIELD32(0x00001f00)
 
#define STA_CSR4_PID_TYPE   FIELD32(0x0000e000)
 
#define STA_CSR4_TXRATE   FIELD32(0x000f0000)
 
#define QOS_CSR0   0x30e0
 
#define QOS_CSR0_BYTE0   FIELD32(0x000000ff)
 
#define QOS_CSR0_BYTE1   FIELD32(0x0000ff00)
 
#define QOS_CSR0_BYTE2   FIELD32(0x00ff0000)
 
#define QOS_CSR0_BYTE3   FIELD32(0xff000000)
 
#define QOS_CSR1   0x30e4
 
#define QOS_CSR1_BYTE4   FIELD32(0x000000ff)
 
#define QOS_CSR1_BYTE5   FIELD32(0x0000ff00)
 
#define QOS_CSR2   0x30e8
 
#define QOS_CSR3   0x30ec
 
#define QOS_CSR4   0x30f0
 
#define QOS_CSR5   0x30f4
 
#define AC0_BASE_CSR   0x3400
 
#define AC0_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)
 
#define AC1_BASE_CSR   0x3404
 
#define AC1_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)
 
#define AC2_BASE_CSR   0x3408
 
#define AC2_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)
 
#define AC3_BASE_CSR   0x340c
 
#define AC3_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)
 
#define MGMT_BASE_CSR   0x3410
 
#define MGMT_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)
 
#define TX_RING_CSR0   0x3418
 
#define TX_RING_CSR0_AC0_RING_SIZE   FIELD32(0x000000ff)
 
#define TX_RING_CSR0_AC1_RING_SIZE   FIELD32(0x0000ff00)
 
#define TX_RING_CSR0_AC2_RING_SIZE   FIELD32(0x00ff0000)
 
#define TX_RING_CSR0_AC3_RING_SIZE   FIELD32(0xff000000)
 
#define TX_RING_CSR1   0x341c
 
#define TX_RING_CSR1_MGMT_RING_SIZE   FIELD32(0x000000ff)
 
#define TX_RING_CSR1_HCCA_RING_SIZE   FIELD32(0x0000ff00)
 
#define TX_RING_CSR1_TXD_SIZE   FIELD32(0x003f0000)
 
#define AIFSN_CSR   0x3420
 
#define AIFSN_CSR_AIFSN0   FIELD32(0x0000000f)
 
#define AIFSN_CSR_AIFSN1   FIELD32(0x000000f0)
 
#define AIFSN_CSR_AIFSN2   FIELD32(0x00000f00)
 
#define AIFSN_CSR_AIFSN3   FIELD32(0x0000f000)
 
#define CWMIN_CSR   0x3424
 
#define CWMIN_CSR_CWMIN0   FIELD32(0x0000000f)
 
#define CWMIN_CSR_CWMIN1   FIELD32(0x000000f0)
 
#define CWMIN_CSR_CWMIN2   FIELD32(0x00000f00)
 
#define CWMIN_CSR_CWMIN3   FIELD32(0x0000f000)
 
#define CWMAX_CSR   0x3428
 
#define CWMAX_CSR_CWMAX0   FIELD32(0x0000000f)
 
#define CWMAX_CSR_CWMAX1   FIELD32(0x000000f0)
 
#define CWMAX_CSR_CWMAX2   FIELD32(0x00000f00)
 
#define CWMAX_CSR_CWMAX3   FIELD32(0x0000f000)
 
#define TX_DMA_DST_CSR   0x342c
 
#define TX_DMA_DST_CSR_DEST_AC0   FIELD32(0x00000003)
 
#define TX_DMA_DST_CSR_DEST_AC1   FIELD32(0x0000000c)
 
#define TX_DMA_DST_CSR_DEST_AC2   FIELD32(0x00000030)
 
#define TX_DMA_DST_CSR_DEST_AC3   FIELD32(0x000000c0)
 
#define TX_DMA_DST_CSR_DEST_MGMT   FIELD32(0x00000300)
 
#define TX_CNTL_CSR   0x3430
 
#define TX_CNTL_CSR_KICK_TX_AC0   FIELD32(0x00000001)
 
#define TX_CNTL_CSR_KICK_TX_AC1   FIELD32(0x00000002)
 
#define TX_CNTL_CSR_KICK_TX_AC2   FIELD32(0x00000004)
 
#define TX_CNTL_CSR_KICK_TX_AC3   FIELD32(0x00000008)
 
#define TX_CNTL_CSR_KICK_TX_MGMT   FIELD32(0x00000010)
 
#define TX_CNTL_CSR_ABORT_TX_AC0   FIELD32(0x00010000)
 
#define TX_CNTL_CSR_ABORT_TX_AC1   FIELD32(0x00020000)
 
#define TX_CNTL_CSR_ABORT_TX_AC2   FIELD32(0x00040000)
 
#define TX_CNTL_CSR_ABORT_TX_AC3   FIELD32(0x00080000)
 
#define TX_CNTL_CSR_ABORT_TX_MGMT   FIELD32(0x00100000)
 
#define LOAD_TX_RING_CSR   0x3434
 
#define LOAD_TX_RING_CSR_LOAD_TXD_AC0   FIELD32(0x00000001)
 
#define LOAD_TX_RING_CSR_LOAD_TXD_AC1   FIELD32(0x00000002)
 
#define LOAD_TX_RING_CSR_LOAD_TXD_AC2   FIELD32(0x00000004)
 
#define LOAD_TX_RING_CSR_LOAD_TXD_AC3   FIELD32(0x00000008)
 
#define LOAD_TX_RING_CSR_LOAD_TXD_MGMT   FIELD32(0x00000010)
 
#define AC0_TXPTR_CSR   0x3438
 
#define AC1_TXPTR_CSR   0x343c
 
#define AC2_TXPTR_CSR   0x3440
 
#define AC3_TXPTR_CSR   0x3444
 
#define MGMT_TXPTR_CSR   0x3448
 
#define RX_BASE_CSR   0x3450
 
#define RX_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)
 
#define RX_RING_CSR   0x3454
 
#define RX_RING_CSR_RING_SIZE   FIELD32(0x000000ff)
 
#define RX_RING_CSR_RXD_SIZE   FIELD32(0x00003f00)
 
#define RX_RING_CSR_RXD_WRITEBACK_SIZE   FIELD32(0x00070000)
 
#define RX_CNTL_CSR   0x3458
 
#define RX_CNTL_CSR_ENABLE_RX_DMA   FIELD32(0x00000001)
 
#define RX_CNTL_CSR_LOAD_RXD   FIELD32(0x00000002)
 
#define RXPTR_CSR   0x345c
 
#define PCI_CFG_CSR   0x3460
 
#define BUF_FORMAT_CSR   0x3464
 
#define INT_SOURCE_CSR   0x3468
 
#define INT_SOURCE_CSR_TXDONE   FIELD32(0x00000001)
 
#define INT_SOURCE_CSR_RXDONE   FIELD32(0x00000002)
 
#define INT_SOURCE_CSR_BEACON_DONE   FIELD32(0x00000004)
 
#define INT_SOURCE_CSR_TX_ABORT_DONE   FIELD32(0x00000010)
 
#define INT_SOURCE_CSR_AC0_DMA_DONE   FIELD32(0x00010000)
 
#define INT_SOURCE_CSR_AC1_DMA_DONE   FIELD32(0x00020000)
 
#define INT_SOURCE_CSR_AC2_DMA_DONE   FIELD32(0x00040000)
 
#define INT_SOURCE_CSR_AC3_DMA_DONE   FIELD32(0x00080000)
 
#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00100000)
 
#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00200000)
 
#define INT_MASK_CSR   0x346c
 
#define INT_MASK_CSR_TXDONE   FIELD32(0x00000001)
 
#define INT_MASK_CSR_RXDONE   FIELD32(0x00000002)
 
#define INT_MASK_CSR_BEACON_DONE   FIELD32(0x00000004)
 
#define INT_MASK_CSR_TX_ABORT_DONE   FIELD32(0x00000010)
 
#define INT_MASK_CSR_ENABLE_MITIGATION   FIELD32(0x00000080)
 
#define INT_MASK_CSR_MITIGATION_PERIOD   FIELD32(0x0000ff00)
 
#define INT_MASK_CSR_AC0_DMA_DONE   FIELD32(0x00010000)
 
#define INT_MASK_CSR_AC1_DMA_DONE   FIELD32(0x00020000)
 
#define INT_MASK_CSR_AC2_DMA_DONE   FIELD32(0x00040000)
 
#define INT_MASK_CSR_AC3_DMA_DONE   FIELD32(0x00080000)
 
#define INT_MASK_CSR_MGMT_DMA_DONE   FIELD32(0x00100000)
 
#define INT_MASK_CSR_HCCA_DMA_DONE   FIELD32(0x00200000)
 
#define E2PROM_CSR   0x3470
 
#define E2PROM_CSR_RELOAD   FIELD32(0x00000001)
 
#define E2PROM_CSR_DATA_CLOCK   FIELD32(0x00000002)
 
#define E2PROM_CSR_CHIP_SELECT   FIELD32(0x00000004)
 
#define E2PROM_CSR_DATA_IN   FIELD32(0x00000008)
 
#define E2PROM_CSR_DATA_OUT   FIELD32(0x00000010)
 
#define E2PROM_CSR_TYPE_93C46   FIELD32(0x00000020)
 
#define E2PROM_CSR_LOAD_STATUS   FIELD32(0x00000040)
 
#define AC_TXOP_CSR0   0x3474
 
#define AC_TXOP_CSR0_AC0_TX_OP   FIELD32(0x0000ffff)
 
#define AC_TXOP_CSR0_AC1_TX_OP   FIELD32(0xffff0000)
 
#define AC_TXOP_CSR1   0x3478
 
#define AC_TXOP_CSR1_AC2_TX_OP   FIELD32(0x0000ffff)
 
#define AC_TXOP_CSR1_AC3_TX_OP   FIELD32(0xffff0000)
 
#define DMA_STATUS_CSR   0x3480
 
#define TEST_MODE_CSR   0x3484
 
#define UART0_TX_CSR   0x3488
 
#define UART0_RX_CSR   0x348c
 
#define UART0_FRAME_CSR   0x3490
 
#define UART0_BUFFER_CSR   0x3494
 
#define IO_CNTL_CSR   0x3498
 
#define IO_CNTL_CSR_RF_PS   FIELD32(0x00000004)
 
#define UART_INT_SOURCE_CSR   0x34a8
 
#define UART_INT_MASK_CSR   0x34ac
 
#define PBF_QUEUE_CSR   0x34b0
 
#define FW_TX_BASE_CSR   0x34c0
 
#define FW_TX_START_CSR   0x34c4
 
#define FW_TX_LAST_CSR   0x34c8
 
#define FW_MODE_CNTL_CSR   0x34cc
 
#define FW_TXPTR_CSR   0x34d0
 
#define FIRMWARE_RT2561   "rt2561.bin"
 
#define FIRMWARE_RT2561s   "rt2561s.bin"
 
#define FIRMWARE_RT2661   "rt2661.bin"
 
#define FIRMWARE_IMAGE_BASE   0x4000
 
#define BBP_R2_BG_MODE   FIELD8(0x20)
 
#define BBP_R3_SMART_MODE   FIELD8(0x01)
 
#define BBP_R4_RX_ANTENNA_CONTROL   FIELD8(0x03)
 
#define BBP_R4_RX_FRAME_END   FIELD8(0x20)
 
#define BBP_R77_RX_ANTENNA   FIELD8(0x03)
 
#define RF3_TXPOWER   FIELD32(0x00003e00)
 
#define RF4_FREQ_OFFSET   FIELD32(0x0003f000)
 
#define EEPROM_MAC_ADDR_0   0x0002
 
#define EEPROM_MAC_ADDR_BYTE0   FIELD16(0x00ff)
 
#define EEPROM_MAC_ADDR_BYTE1   FIELD16(0xff00)
 
#define EEPROM_MAC_ADDR1   0x0003
 
#define EEPROM_MAC_ADDR_BYTE2   FIELD16(0x00ff)
 
#define EEPROM_MAC_ADDR_BYTE3   FIELD16(0xff00)
 
#define EEPROM_MAC_ADDR_2   0x0004
 
#define EEPROM_MAC_ADDR_BYTE4   FIELD16(0x00ff)
 
#define EEPROM_MAC_ADDR_BYTE5   FIELD16(0xff00)
 
#define EEPROM_ANTENNA   0x0010
 
#define EEPROM_ANTENNA_NUM   FIELD16(0x0003)
 
#define EEPROM_ANTENNA_TX_DEFAULT   FIELD16(0x000c)
 
#define EEPROM_ANTENNA_RX_DEFAULT   FIELD16(0x0030)
 
#define EEPROM_ANTENNA_FRAME_TYPE   FIELD16(0x0040)
 
#define EEPROM_ANTENNA_DYN_TXAGC   FIELD16(0x0200)
 
#define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
 
#define EEPROM_ANTENNA_RF_TYPE   FIELD16(0xf800)
 
#define EEPROM_NIC   0x0011
 
#define EEPROM_NIC_ENABLE_DIVERSITY   FIELD16(0x0001)
 
#define EEPROM_NIC_TX_DIVERSITY   FIELD16(0x0002)
 
#define EEPROM_NIC_RX_FIXED   FIELD16(0x0004)
 
#define EEPROM_NIC_TX_FIXED   FIELD16(0x0008)
 
#define EEPROM_NIC_EXTERNAL_LNA_BG   FIELD16(0x0010)
 
#define EEPROM_NIC_CARDBUS_ACCEL   FIELD16(0x0020)
 
#define EEPROM_NIC_EXTERNAL_LNA_A   FIELD16(0x0040)
 
#define EEPROM_GEOGRAPHY   0x0012
 
#define EEPROM_GEOGRAPHY_GEO_A   FIELD16(0x00ff)
 
#define EEPROM_GEOGRAPHY_GEO   FIELD16(0xff00)
 
#define EEPROM_BBP_START   0x0013
 
#define EEPROM_BBP_SIZE   16
 
#define EEPROM_BBP_VALUE   FIELD16(0x00ff)
 
#define EEPROM_BBP_REG_ID   FIELD16(0xff00)
 
#define EEPROM_TXPOWER_G_START   0x0023
 
#define EEPROM_TXPOWER_G_SIZE   7
 
#define EEPROM_TXPOWER_G_1   FIELD16(0x00ff)
 
#define EEPROM_TXPOWER_G_2   FIELD16(0xff00)
 
#define EEPROM_FREQ   0x002f
 
#define EEPROM_FREQ_OFFSET   FIELD16(0x00ff)
 
#define EEPROM_FREQ_SEQ_MASK   FIELD16(0xff00)
 
#define EEPROM_FREQ_SEQ   FIELD16(0x0300)
 
#define EEPROM_LED   0x0030
 
#define EEPROM_LED_POLARITY_RDY_G   FIELD16(0x0001)
 
#define EEPROM_LED_POLARITY_RDY_A   FIELD16(0x0002)
 
#define EEPROM_LED_POLARITY_ACT   FIELD16(0x0004)
 
#define EEPROM_LED_POLARITY_GPIO_0   FIELD16(0x0008)
 
#define EEPROM_LED_POLARITY_GPIO_1   FIELD16(0x0010)
 
#define EEPROM_LED_POLARITY_GPIO_2   FIELD16(0x0020)
 
#define EEPROM_LED_POLARITY_GPIO_3   FIELD16(0x0040)
 
#define EEPROM_LED_POLARITY_GPIO_4   FIELD16(0x0080)
 
#define EEPROM_LED_LED_MODE   FIELD16(0x1f00)
 
#define EEPROM_TXPOWER_A_START   0x0031
 
#define EEPROM_TXPOWER_A_SIZE   12
 
#define EEPROM_TXPOWER_A_1   FIELD16(0x00ff)
 
#define EEPROM_TXPOWER_A_2   FIELD16(0xff00)
 
#define EEPROM_RSSI_OFFSET_BG   0x004d
 
#define EEPROM_RSSI_OFFSET_BG_1   FIELD16(0x00ff)
 
#define EEPROM_RSSI_OFFSET_BG_2   FIELD16(0xff00)
 
#define EEPROM_RSSI_OFFSET_A   0x004e
 
#define EEPROM_RSSI_OFFSET_A_1   FIELD16(0x00ff)
 
#define EEPROM_RSSI_OFFSET_A_2   FIELD16(0xff00)
 
#define MCU_SLEEP   0x30
 
#define MCU_WAKEUP   0x31
 
#define MCU_LED   0x50
 
#define MCU_LED_STRENGTH   0x52
 
#define TXD_DESC_SIZE   ( 16 * sizeof(__le32) )
 
#define TXINFO_SIZE   ( 6 * sizeof(__le32) )
 
#define RXD_DESC_SIZE   ( 16 * sizeof(__le32) )
 
#define TXD_W0_OWNER_NIC   FIELD32(0x00000001)
 
#define TXD_W0_VALID   FIELD32(0x00000002)
 
#define TXD_W0_MORE_FRAG   FIELD32(0x00000004)
 
#define TXD_W0_ACK   FIELD32(0x00000008)
 
#define TXD_W0_TIMESTAMP   FIELD32(0x00000010)
 
#define TXD_W0_OFDM   FIELD32(0x00000020)
 
#define TXD_W0_IFS   FIELD32(0x00000040)
 
#define TXD_W0_RETRY_MODE   FIELD32(0x00000080)
 
#define TXD_W0_TKIP_MIC   FIELD32(0x00000100)
 
#define TXD_W0_KEY_TABLE   FIELD32(0x00000200)
 
#define TXD_W0_KEY_INDEX   FIELD32(0x0000fc00)
 
#define TXD_W0_DATABYTE_COUNT   FIELD32(0x0fff0000)
 
#define TXD_W0_BURST   FIELD32(0x10000000)
 
#define TXD_W0_CIPHER_ALG   FIELD32(0xe0000000)
 
#define TXD_W1_HOST_Q_ID   FIELD32(0x0000000f)
 
#define TXD_W1_AIFSN   FIELD32(0x000000f0)
 
#define TXD_W1_CWMIN   FIELD32(0x00000f00)
 
#define TXD_W1_CWMAX   FIELD32(0x0000f000)
 
#define TXD_W1_IV_OFFSET   FIELD32(0x003f0000)
 
#define TXD_W1_PIGGY_BACK   FIELD32(0x01000000)
 
#define TXD_W1_HW_SEQUENCE   FIELD32(0x10000000)
 
#define TXD_W1_BUFFER_COUNT   FIELD32(0xe0000000)
 
#define TXD_W2_PLCP_SIGNAL   FIELD32(0x000000ff)
 
#define TXD_W2_PLCP_SERVICE   FIELD32(0x0000ff00)
 
#define TXD_W2_PLCP_LENGTH_LOW   FIELD32(0x00ff0000)
 
#define TXD_W2_PLCP_LENGTH_HIGH   FIELD32(0xff000000)
 
#define TXD_W3_IV   FIELD32(0xffffffff)
 
#define TXD_W4_EIV   FIELD32(0xffffffff)
 
#define TXD_W5_FRAME_OFFSET   FIELD32(0x000000ff)
 
#define TXD_W5_PID_SUBTYPE   FIELD32(0x00001f00)
 
#define TXD_W5_PID_TYPE   FIELD32(0x0000e000)
 
#define TXD_W5_TX_POWER   FIELD32(0x00ff0000)
 
#define TXD_W5_WAITING_DMA_DONE_INT   FIELD32(0x01000000)
 
#define TXD_W6_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)
 
#define TXD_W7_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)
 
#define TXD_W8_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)
 
#define TXD_W9_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)
 
#define TXD_W10_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)
 
#define TXD_W11_BUFFER_LENGTH0   FIELD32(0x00000fff)
 
#define TXD_W11_BUFFER_LENGTH1   FIELD32(0x0fff0000)
 
#define TXD_W12_BUFFER_LENGTH2   FIELD32(0x00000fff)
 
#define TXD_W12_BUFFER_LENGTH3   FIELD32(0x0fff0000)
 
#define TXD_W13_BUFFER_LENGTH4   FIELD32(0x00000fff)
 
#define TXD_W14_SK_BUFFER   FIELD32(0xffffffff)
 
#define TXD_W15_NEXT_SK_BUFFER   FIELD32(0xffffffff)
 
#define RXD_W0_OWNER_NIC   FIELD32(0x00000001)
 
#define RXD_W0_DROP   FIELD32(0x00000002)
 
#define RXD_W0_UNICAST_TO_ME   FIELD32(0x00000004)
 
#define RXD_W0_MULTICAST   FIELD32(0x00000008)
 
#define RXD_W0_BROADCAST   FIELD32(0x00000010)
 
#define RXD_W0_MY_BSS   FIELD32(0x00000020)
 
#define RXD_W0_CRC_ERROR   FIELD32(0x00000040)
 
#define RXD_W0_OFDM   FIELD32(0x00000080)
 
#define RXD_W0_CIPHER_ERROR   FIELD32(0x00000300)
 
#define RXD_W0_KEY_INDEX   FIELD32(0x0000fc00)
 
#define RXD_W0_DATABYTE_COUNT   FIELD32(0x0fff0000)
 
#define RXD_W0_CIPHER_ALG   FIELD32(0xe0000000)
 
#define RXD_W1_SIGNAL   FIELD32(0x000000ff)
 
#define RXD_W1_RSSI_AGC   FIELD32(0x00001f00)
 
#define RXD_W1_RSSI_LNA   FIELD32(0x00006000)
 
#define RXD_W1_FRAME_OFFSET   FIELD32(0x7f000000)
 
#define RXD_W2_IV   FIELD32(0xffffffff)
 
#define RXD_W3_EIV   FIELD32(0xffffffff)
 
#define RXD_W4_ICV   FIELD32(0xffffffff)
 
#define RXD_W5_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)
 
#define RXD_W6_RESERVED   FIELD32(0xffffffff)
 
#define RXD_W7_RESERVED   FIELD32(0xffffffff)
 
#define RXD_W8_RESERVED   FIELD32(0xffffffff)
 
#define RXD_W9_RESERVED   FIELD32(0xffffffff)
 
#define RXD_W10_RESERVED   FIELD32(0xffffffff)
 
#define RXD_W11_RESERVED   FIELD32(0xffffffff)
 
#define RXD_W12_RESERVED   FIELD32(0xffffffff)
 
#define RXD_W13_RESERVED   FIELD32(0xffffffff)
 
#define RXD_W14_RESERVED   FIELD32(0xffffffff)
 
#define RXD_W15_RESERVED   FIELD32(0xffffffff)
 
#define MIN_TXPOWER   0
 
#define MAX_TXPOWER   31
 
#define DEFAULT_TXPOWER   24
 
#define TXPOWER_FROM_DEV(__txpower)   (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
 
#define TXPOWER_TO_DEV(__txpower)   clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
 

Variables

struct hw_key_entry __packed
 

Macro Definition Documentation

#define AC0_BASE_CSR   0x3400

Definition at line 790 of file rt61pci.h.

#define AC0_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)

Definition at line 791 of file rt61pci.h.

#define AC0_TXPTR_CSR   0x3438

Definition at line 921 of file rt61pci.h.

#define AC1_BASE_CSR   0x3404

Definition at line 796 of file rt61pci.h.

#define AC1_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)

Definition at line 797 of file rt61pci.h.

#define AC1_TXPTR_CSR   0x343c

Definition at line 922 of file rt61pci.h.

#define AC2_BASE_CSR   0x3408

Definition at line 802 of file rt61pci.h.

#define AC2_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)

Definition at line 803 of file rt61pci.h.

#define AC2_TXPTR_CSR   0x3440

Definition at line 923 of file rt61pci.h.

#define AC3_BASE_CSR   0x340c

Definition at line 808 of file rt61pci.h.

#define AC3_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)

Definition at line 809 of file rt61pci.h.

#define AC3_TXPTR_CSR   0x3444

Definition at line 924 of file rt61pci.h.

#define AC_TXOP_CSR0   0x3474

Definition at line 1018 of file rt61pci.h.

#define AC_TXOP_CSR0_AC0_TX_OP   FIELD32(0x0000ffff)

Definition at line 1019 of file rt61pci.h.

#define AC_TXOP_CSR0_AC1_TX_OP   FIELD32(0xffff0000)

Definition at line 1020 of file rt61pci.h.

#define AC_TXOP_CSR1   0x3478

Definition at line 1027 of file rt61pci.h.

#define AC_TXOP_CSR1_AC2_TX_OP   FIELD32(0x0000ffff)

Definition at line 1028 of file rt61pci.h.

#define AC_TXOP_CSR1_AC3_TX_OP   FIELD32(0xffff0000)

Definition at line 1029 of file rt61pci.h.

#define AIFSN_CSR   0x3420

Definition at line 842 of file rt61pci.h.

#define AIFSN_CSR_AIFSN0   FIELD32(0x0000000f)

Definition at line 843 of file rt61pci.h.

#define AIFSN_CSR_AIFSN1   FIELD32(0x000000f0)

Definition at line 844 of file rt61pci.h.

#define AIFSN_CSR_AIFSN2   FIELD32(0x00000f00)

Definition at line 845 of file rt61pci.h.

#define AIFSN_CSR_AIFSN3   FIELD32(0x0000f000)

Definition at line 846 of file rt61pci.h.

#define BBP_BASE   0x0000

Definition at line 58 of file rt61pci.h.

#define BBP_R2_BG_MODE   FIELD8(0x20)

Definition at line 1111 of file rt61pci.h.

#define BBP_R3_SMART_MODE   FIELD8(0x01)

Definition at line 1116 of file rt61pci.h.

#define BBP_R4_RX_ANTENNA_CONTROL   FIELD8(0x03)

Definition at line 1128 of file rt61pci.h.

#define BBP_R4_RX_FRAME_END   FIELD8(0x20)

Definition at line 1129 of file rt61pci.h.

#define BBP_R77_RX_ANTENNA   FIELD8(0x03)

Definition at line 1134 of file rt61pci.h.

#define BBP_SIZE   0x0080

Definition at line 59 of file rt61pci.h.

#define BUF_FORMAT_CSR   0x3464

Definition at line 962 of file rt61pci.h.

#define CSR_REG_BASE   0x3000

Definition at line 54 of file rt61pci.h.

#define CSR_REG_SIZE   0x04b0

Definition at line 55 of file rt61pci.h.

#define CWMAX_CSR   0x3428

Definition at line 868 of file rt61pci.h.

#define CWMAX_CSR_CWMAX0   FIELD32(0x0000000f)

Definition at line 869 of file rt61pci.h.

#define CWMAX_CSR_CWMAX1   FIELD32(0x000000f0)

Definition at line 870 of file rt61pci.h.

#define CWMAX_CSR_CWMAX2   FIELD32(0x00000f00)

Definition at line 871 of file rt61pci.h.

#define CWMAX_CSR_CWMAX3   FIELD32(0x0000f000)

Definition at line 872 of file rt61pci.h.

#define CWMIN_CSR   0x3424

Definition at line 855 of file rt61pci.h.

#define CWMIN_CSR_CWMIN0   FIELD32(0x0000000f)

Definition at line 856 of file rt61pci.h.

#define CWMIN_CSR_CWMIN1   FIELD32(0x000000f0)

Definition at line 857 of file rt61pci.h.

#define CWMIN_CSR_CWMIN2   FIELD32(0x00000f00)

Definition at line 858 of file rt61pci.h.

#define CWMIN_CSR_CWMIN3   FIELD32(0x0000f000)

Definition at line 859 of file rt61pci.h.

#define DEFAULT_RSSI_OFFSET   120

Definition at line 49 of file rt61pci.h.

#define DEFAULT_TXPOWER   24

Definition at line 1494 of file rt61pci.h.

#define DMA_STATUS_CSR   0x3480

Definition at line 1034 of file rt61pci.h.

#define E2PROM_CSR   0x3470

Definition at line 1004 of file rt61pci.h.

#define E2PROM_CSR_CHIP_SELECT   FIELD32(0x00000004)

Definition at line 1007 of file rt61pci.h.

#define E2PROM_CSR_DATA_CLOCK   FIELD32(0x00000002)

Definition at line 1006 of file rt61pci.h.

#define E2PROM_CSR_DATA_IN   FIELD32(0x00000008)

Definition at line 1008 of file rt61pci.h.

#define E2PROM_CSR_DATA_OUT   FIELD32(0x00000010)

Definition at line 1009 of file rt61pci.h.

#define E2PROM_CSR_LOAD_STATUS   FIELD32(0x00000040)

Definition at line 1011 of file rt61pci.h.

#define E2PROM_CSR_RELOAD   FIELD32(0x00000001)

Definition at line 1005 of file rt61pci.h.

#define E2PROM_CSR_TYPE_93C46   FIELD32(0x00000020)

Definition at line 1010 of file rt61pci.h.

#define EEPROM_ANTENNA   0x0010

Definition at line 1178 of file rt61pci.h.

#define EEPROM_ANTENNA_DYN_TXAGC   FIELD16(0x0200)

Definition at line 1183 of file rt61pci.h.

#define EEPROM_ANTENNA_FRAME_TYPE   FIELD16(0x0040)

Definition at line 1182 of file rt61pci.h.

#define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)

Definition at line 1184 of file rt61pci.h.

#define EEPROM_ANTENNA_NUM   FIELD16(0x0003)

Definition at line 1179 of file rt61pci.h.

#define EEPROM_ANTENNA_RF_TYPE   FIELD16(0xf800)

Definition at line 1185 of file rt61pci.h.

#define EEPROM_ANTENNA_RX_DEFAULT   FIELD16(0x0030)

Definition at line 1181 of file rt61pci.h.

#define EEPROM_ANTENNA_TX_DEFAULT   FIELD16(0x000c)

Definition at line 1180 of file rt61pci.h.

#define EEPROM_BASE   0x0000

Definition at line 56 of file rt61pci.h.

#define EEPROM_BBP_REG_ID   FIELD16(0xff00)

Definition at line 1218 of file rt61pci.h.

#define EEPROM_BBP_SIZE   16

Definition at line 1216 of file rt61pci.h.

#define EEPROM_BBP_START   0x0013

Definition at line 1215 of file rt61pci.h.

#define EEPROM_BBP_VALUE   FIELD16(0x00ff)

Definition at line 1217 of file rt61pci.h.

#define EEPROM_FREQ   0x002f

Definition at line 1231 of file rt61pci.h.

#define EEPROM_FREQ_OFFSET   FIELD16(0x00ff)

Definition at line 1232 of file rt61pci.h.

#define EEPROM_FREQ_SEQ   FIELD16(0x0300)

Definition at line 1234 of file rt61pci.h.

#define EEPROM_FREQ_SEQ_MASK   FIELD16(0xff00)

Definition at line 1233 of file rt61pci.h.

#define EEPROM_GEOGRAPHY   0x0012

Definition at line 1208 of file rt61pci.h.

#define EEPROM_GEOGRAPHY_GEO   FIELD16(0xff00)

Definition at line 1210 of file rt61pci.h.

#define EEPROM_GEOGRAPHY_GEO_A   FIELD16(0x00ff)

Definition at line 1209 of file rt61pci.h.

#define EEPROM_LED   0x0030

Definition at line 1248 of file rt61pci.h.

#define EEPROM_LED_LED_MODE   FIELD16(0x1f00)

Definition at line 1257 of file rt61pci.h.

#define EEPROM_LED_POLARITY_ACT   FIELD16(0x0004)

Definition at line 1251 of file rt61pci.h.

#define EEPROM_LED_POLARITY_GPIO_0   FIELD16(0x0008)

Definition at line 1252 of file rt61pci.h.

#define EEPROM_LED_POLARITY_GPIO_1   FIELD16(0x0010)

Definition at line 1253 of file rt61pci.h.

#define EEPROM_LED_POLARITY_GPIO_2   FIELD16(0x0020)

Definition at line 1254 of file rt61pci.h.

#define EEPROM_LED_POLARITY_GPIO_3   FIELD16(0x0040)

Definition at line 1255 of file rt61pci.h.

#define EEPROM_LED_POLARITY_GPIO_4   FIELD16(0x0080)

Definition at line 1256 of file rt61pci.h.

#define EEPROM_LED_POLARITY_RDY_A   FIELD16(0x0002)

Definition at line 1250 of file rt61pci.h.

#define EEPROM_LED_POLARITY_RDY_G   FIELD16(0x0001)

Definition at line 1249 of file rt61pci.h.

#define EEPROM_MAC_ADDR1   0x0003

Definition at line 1161 of file rt61pci.h.

#define EEPROM_MAC_ADDR_0   0x0002

Definition at line 1158 of file rt61pci.h.

#define EEPROM_MAC_ADDR_2   0x0004

Definition at line 1164 of file rt61pci.h.

#define EEPROM_MAC_ADDR_BYTE0   FIELD16(0x00ff)

Definition at line 1159 of file rt61pci.h.

#define EEPROM_MAC_ADDR_BYTE1   FIELD16(0xff00)

Definition at line 1160 of file rt61pci.h.

#define EEPROM_MAC_ADDR_BYTE2   FIELD16(0x00ff)

Definition at line 1162 of file rt61pci.h.

#define EEPROM_MAC_ADDR_BYTE3   FIELD16(0xff00)

Definition at line 1163 of file rt61pci.h.

#define EEPROM_MAC_ADDR_BYTE4   FIELD16(0x00ff)

Definition at line 1165 of file rt61pci.h.

#define EEPROM_MAC_ADDR_BYTE5   FIELD16(0xff00)

Definition at line 1166 of file rt61pci.h.

#define EEPROM_NIC   0x0011

Definition at line 1194 of file rt61pci.h.

#define EEPROM_NIC_CARDBUS_ACCEL   FIELD16(0x0020)

Definition at line 1200 of file rt61pci.h.

#define EEPROM_NIC_ENABLE_DIVERSITY   FIELD16(0x0001)

Definition at line 1195 of file rt61pci.h.

#define EEPROM_NIC_EXTERNAL_LNA_A   FIELD16(0x0040)

Definition at line 1201 of file rt61pci.h.

#define EEPROM_NIC_EXTERNAL_LNA_BG   FIELD16(0x0010)

Definition at line 1199 of file rt61pci.h.

#define EEPROM_NIC_RX_FIXED   FIELD16(0x0004)

Definition at line 1197 of file rt61pci.h.

#define EEPROM_NIC_TX_DIVERSITY   FIELD16(0x0002)

Definition at line 1196 of file rt61pci.h.

#define EEPROM_NIC_TX_FIXED   FIELD16(0x0008)

Definition at line 1198 of file rt61pci.h.

#define EEPROM_RSSI_OFFSET_A   0x004e

Definition at line 1277 of file rt61pci.h.

#define EEPROM_RSSI_OFFSET_A_1   FIELD16(0x00ff)

Definition at line 1278 of file rt61pci.h.

#define EEPROM_RSSI_OFFSET_A_2   FIELD16(0xff00)

Definition at line 1279 of file rt61pci.h.

#define EEPROM_RSSI_OFFSET_BG   0x004d

Definition at line 1270 of file rt61pci.h.

#define EEPROM_RSSI_OFFSET_BG_1   FIELD16(0x00ff)

Definition at line 1271 of file rt61pci.h.

#define EEPROM_RSSI_OFFSET_BG_2   FIELD16(0xff00)

Definition at line 1272 of file rt61pci.h.

#define EEPROM_SIZE   0x0100

Definition at line 57 of file rt61pci.h.

#define EEPROM_TXPOWER_A_1   FIELD16(0x00ff)

Definition at line 1264 of file rt61pci.h.

#define EEPROM_TXPOWER_A_2   FIELD16(0xff00)

Definition at line 1265 of file rt61pci.h.

#define EEPROM_TXPOWER_A_SIZE   12

Definition at line 1263 of file rt61pci.h.

#define EEPROM_TXPOWER_A_START   0x0031

Definition at line 1262 of file rt61pci.h.

#define EEPROM_TXPOWER_G_1   FIELD16(0x00ff)

Definition at line 1225 of file rt61pci.h.

#define EEPROM_TXPOWER_G_2   FIELD16(0xff00)

Definition at line 1226 of file rt61pci.h.

#define EEPROM_TXPOWER_G_SIZE   7

Definition at line 1224 of file rt61pci.h.

#define EEPROM_TXPOWER_G_START   0x0023

Definition at line 1223 of file rt61pci.h.

#define FIRMWARE_IMAGE_BASE   0x4000

Definition at line 1101 of file rt61pci.h.

#define FIRMWARE_RT2561   "rt2561.bin"

Definition at line 1098 of file rt61pci.h.

#define FIRMWARE_RT2561s   "rt2561s.bin"

Definition at line 1099 of file rt61pci.h.

#define FIRMWARE_RT2661   "rt2661.bin"

Definition at line 1100 of file rt61pci.h.

#define FW_MODE_CNTL_CSR   0x34cc

Definition at line 1092 of file rt61pci.h.

#define FW_TX_BASE_CSR   0x34c0

Definition at line 1089 of file rt61pci.h.

#define FW_TX_LAST_CSR   0x34c8

Definition at line 1091 of file rt61pci.h.

#define FW_TX_START_CSR   0x34c4

Definition at line 1090 of file rt61pci.h.

#define FW_TXPTR_CSR   0x34d0

Definition at line 1093 of file rt61pci.h.

#define H2M_MAILBOX_CSR   0x2100

Definition at line 194 of file rt61pci.h.

#define H2M_MAILBOX_CSR_ARG0   FIELD32(0x000000ff)

Definition at line 195 of file rt61pci.h.

#define H2M_MAILBOX_CSR_ARG1   FIELD32(0x0000ff00)

Definition at line 196 of file rt61pci.h.

#define H2M_MAILBOX_CSR_CMD_TOKEN   FIELD32(0x00ff0000)

Definition at line 197 of file rt61pci.h.

#define H2M_MAILBOX_CSR_OWNER   FIELD32(0xff000000)

Definition at line 198 of file rt61pci.h.

#define HOST_CMD_CSR   0x0008

Definition at line 75 of file rt61pci.h.

#define HOST_CMD_CSR_HOST_COMMAND   FIELD32(0x0000007f)

Definition at line 76 of file rt61pci.h.

#define HOST_CMD_CSR_INTERRUPT_MCU   FIELD32(0x00000080)

Definition at line 77 of file rt61pci.h.

#define HW_BEACON_BASE0   0x2c00

Definition at line 179 of file rt61pci.h.

#define HW_BEACON_BASE1   0x2d00

Definition at line 180 of file rt61pci.h.

#define HW_BEACON_BASE2   0x2e00

Definition at line 181 of file rt61pci.h.

#define HW_BEACON_BASE3   0x2f00

Definition at line 182 of file rt61pci.h.

#define HW_BEACON_OFFSET (   __index)    ( HW_BEACON_BASE0 + (__index * 0x0100) )

Definition at line 184 of file rt61pci.h.

#define HW_CIS_BASE   0x2000

Definition at line 167 of file rt61pci.h.

#define HW_DEBUG_SETTING_BASE   0x2bf0

Definition at line 174 of file rt61pci.h.

#define HW_NULL_BASE   0x2b00

Definition at line 168 of file rt61pci.h.

#define INT_MASK_CSR   0x346c

Definition at line 984 of file rt61pci.h.

#define INT_MASK_CSR_AC0_DMA_DONE   FIELD32(0x00010000)

Definition at line 991 of file rt61pci.h.

#define INT_MASK_CSR_AC1_DMA_DONE   FIELD32(0x00020000)

Definition at line 992 of file rt61pci.h.

#define INT_MASK_CSR_AC2_DMA_DONE   FIELD32(0x00040000)

Definition at line 993 of file rt61pci.h.

#define INT_MASK_CSR_AC3_DMA_DONE   FIELD32(0x00080000)

Definition at line 994 of file rt61pci.h.

#define INT_MASK_CSR_BEACON_DONE   FIELD32(0x00000004)

Definition at line 987 of file rt61pci.h.

#define INT_MASK_CSR_ENABLE_MITIGATION   FIELD32(0x00000080)

Definition at line 989 of file rt61pci.h.

#define INT_MASK_CSR_HCCA_DMA_DONE   FIELD32(0x00200000)

Definition at line 996 of file rt61pci.h.

#define INT_MASK_CSR_MGMT_DMA_DONE   FIELD32(0x00100000)

Definition at line 995 of file rt61pci.h.

#define INT_MASK_CSR_MITIGATION_PERIOD   FIELD32(0x0000ff00)

Definition at line 990 of file rt61pci.h.

#define INT_MASK_CSR_RXDONE   FIELD32(0x00000002)

Definition at line 986 of file rt61pci.h.

#define INT_MASK_CSR_TX_ABORT_DONE   FIELD32(0x00000010)

Definition at line 988 of file rt61pci.h.

#define INT_MASK_CSR_TXDONE   FIELD32(0x00000001)

Definition at line 985 of file rt61pci.h.

#define INT_SOURCE_CSR   0x3468

Definition at line 968 of file rt61pci.h.

#define INT_SOURCE_CSR_AC0_DMA_DONE   FIELD32(0x00010000)

Definition at line 973 of file rt61pci.h.

#define INT_SOURCE_CSR_AC1_DMA_DONE   FIELD32(0x00020000)

Definition at line 974 of file rt61pci.h.

#define INT_SOURCE_CSR_AC2_DMA_DONE   FIELD32(0x00040000)

Definition at line 975 of file rt61pci.h.

#define INT_SOURCE_CSR_AC3_DMA_DONE   FIELD32(0x00080000)

Definition at line 976 of file rt61pci.h.

#define INT_SOURCE_CSR_BEACON_DONE   FIELD32(0x00000004)

Definition at line 971 of file rt61pci.h.

#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00200000)

Definition at line 978 of file rt61pci.h.

#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00100000)

Definition at line 977 of file rt61pci.h.

#define INT_SOURCE_CSR_RXDONE   FIELD32(0x00000002)

Definition at line 970 of file rt61pci.h.

#define INT_SOURCE_CSR_TX_ABORT_DONE   FIELD32(0x00000010)

Definition at line 972 of file rt61pci.h.

#define INT_SOURCE_CSR_TXDONE   FIELD32(0x00000001)

Definition at line 969 of file rt61pci.h.

#define IO_CNTL_CSR   0x3498

Definition at line 1065 of file rt61pci.h.

#define IO_CNTL_CSR_RF_PS   FIELD32(0x00000004)

Definition at line 1066 of file rt61pci.h.

#define LOAD_TX_RING_CSR   0x3434

Definition at line 911 of file rt61pci.h.

#define LOAD_TX_RING_CSR_LOAD_TXD_AC0   FIELD32(0x00000001)

Definition at line 912 of file rt61pci.h.

#define LOAD_TX_RING_CSR_LOAD_TXD_AC1   FIELD32(0x00000002)

Definition at line 913 of file rt61pci.h.

#define LOAD_TX_RING_CSR_LOAD_TXD_AC2   FIELD32(0x00000004)

Definition at line 914 of file rt61pci.h.

#define LOAD_TX_RING_CSR_LOAD_TXD_AC3   FIELD32(0x00000008)

Definition at line 915 of file rt61pci.h.

#define LOAD_TX_RING_CSR_LOAD_TXD_MGMT   FIELD32(0x00000010)

Definition at line 916 of file rt61pci.h.

#define M2H_CMD_DONE_CSR   0x2104

Definition at line 219 of file rt61pci.h.

#define MAC_CSR0   0x3000

Definition at line 234 of file rt61pci.h.

#define MAC_CSR0_CHIPSET   FIELD32(0x000ffff0)

Definition at line 236 of file rt61pci.h.

#define MAC_CSR0_REVISION   FIELD32(0x0000000f)

Definition at line 235 of file rt61pci.h.

#define MAC_CSR1   0x3004

Definition at line 244 of file rt61pci.h.

#define MAC_CSR10   0x3028

Definition at line 332 of file rt61pci.h.

#define MAC_CSR11   0x302c

Definition at line 340 of file rt61pci.h.

#define MAC_CSR11_AUTOWAKE   FIELD32(0x00008000)

Definition at line 343 of file rt61pci.h.

#define MAC_CSR11_DELAY_AFTER_TBCN   FIELD32(0x000000ff)

Definition at line 341 of file rt61pci.h.

#define MAC_CSR11_TBCN_BEFORE_WAKEUP   FIELD32(0x00007f00)

Definition at line 342 of file rt61pci.h.

#define MAC_CSR11_WAKEUP_LATENCY   FIELD32(0x000f0000)

Definition at line 344 of file rt61pci.h.

#define MAC_CSR12   0x3030

Definition at line 352 of file rt61pci.h.

#define MAC_CSR12_BBP_CURRENT_STATE   FIELD32(0x00000008)

Definition at line 356 of file rt61pci.h.

#define MAC_CSR12_CURRENT_STATE   FIELD32(0x00000001)

Definition at line 353 of file rt61pci.h.

#define MAC_CSR12_FORCE_WAKEUP   FIELD32(0x00000004)

Definition at line 355 of file rt61pci.h.

#define MAC_CSR12_PUT_TO_SLEEP   FIELD32(0x00000002)

Definition at line 354 of file rt61pci.h.

#define MAC_CSR13   0x3034

Definition at line 363 of file rt61pci.h.

#define MAC_CSR13_DIR0   FIELD32(0x00000100)

Definition at line 370 of file rt61pci.h.

#define MAC_CSR13_DIR1   FIELD32(0x00000200)

Definition at line 371 of file rt61pci.h.

#define MAC_CSR13_DIR2   FIELD32(0x00000400)

Definition at line 372 of file rt61pci.h.

#define MAC_CSR13_DIR3   FIELD32(0x00000800)

Definition at line 373 of file rt61pci.h.

#define MAC_CSR13_DIR4   FIELD32(0x00001000)

Definition at line 374 of file rt61pci.h.

#define MAC_CSR13_DIR5   FIELD32(0x00002000)

Definition at line 375 of file rt61pci.h.

#define MAC_CSR13_VAL0   FIELD32(0x00000001)

Definition at line 364 of file rt61pci.h.

#define MAC_CSR13_VAL1   FIELD32(0x00000002)

Definition at line 365 of file rt61pci.h.

#define MAC_CSR13_VAL2   FIELD32(0x00000004)

Definition at line 366 of file rt61pci.h.

#define MAC_CSR13_VAL3   FIELD32(0x00000008)

Definition at line 367 of file rt61pci.h.

#define MAC_CSR13_VAL4   FIELD32(0x00000010)

Definition at line 368 of file rt61pci.h.

#define MAC_CSR13_VAL5   FIELD32(0x00000020)

Definition at line 369 of file rt61pci.h.

#define MAC_CSR14   0x3038

Definition at line 385 of file rt61pci.h.

#define MAC_CSR14_HW_LED   FIELD32(0x00010000)

Definition at line 388 of file rt61pci.h.

#define MAC_CSR14_HW_LED_POLARITY   FIELD32(0x00040000)

Definition at line 390 of file rt61pci.h.

#define MAC_CSR14_OFF_PERIOD   FIELD32(0x0000ff00)

Definition at line 387 of file rt61pci.h.

#define MAC_CSR14_ON_PERIOD   FIELD32(0x000000ff)

Definition at line 386 of file rt61pci.h.

#define MAC_CSR14_SW_LED   FIELD32(0x00020000)

Definition at line 389 of file rt61pci.h.

#define MAC_CSR14_SW_LED2   FIELD32(0x00080000)

Definition at line 391 of file rt61pci.h.

#define MAC_CSR15   0x303c

Definition at line 396 of file rt61pci.h.

#define MAC_CSR1_BBP_RESET   FIELD32(0x00000002)

Definition at line 246 of file rt61pci.h.

#define MAC_CSR1_HOST_READY   FIELD32(0x00000004)

Definition at line 247 of file rt61pci.h.

#define MAC_CSR1_SOFT_RESET   FIELD32(0x00000001)

Definition at line 245 of file rt61pci.h.

#define MAC_CSR2   0x3008

Definition at line 252 of file rt61pci.h.

#define MAC_CSR2_BYTE0   FIELD32(0x000000ff)

Definition at line 253 of file rt61pci.h.

#define MAC_CSR2_BYTE1   FIELD32(0x0000ff00)

Definition at line 254 of file rt61pci.h.

#define MAC_CSR2_BYTE2   FIELD32(0x00ff0000)

Definition at line 255 of file rt61pci.h.

#define MAC_CSR2_BYTE3   FIELD32(0xff000000)

Definition at line 256 of file rt61pci.h.

#define MAC_CSR3   0x300c

Definition at line 266 of file rt61pci.h.

#define MAC_CSR3_BYTE4   FIELD32(0x000000ff)

Definition at line 267 of file rt61pci.h.

#define MAC_CSR3_BYTE5   FIELD32(0x0000ff00)

Definition at line 268 of file rt61pci.h.

#define MAC_CSR3_UNICAST_TO_ME_MASK   FIELD32(0x00ff0000)

Definition at line 269 of file rt61pci.h.

#define MAC_CSR4   0x3010

Definition at line 274 of file rt61pci.h.

#define MAC_CSR4_BYTE0   FIELD32(0x000000ff)

Definition at line 275 of file rt61pci.h.

#define MAC_CSR4_BYTE1   FIELD32(0x0000ff00)

Definition at line 276 of file rt61pci.h.

#define MAC_CSR4_BYTE2   FIELD32(0x00ff0000)

Definition at line 277 of file rt61pci.h.

#define MAC_CSR4_BYTE3   FIELD32(0xff000000)

Definition at line 278 of file rt61pci.h.

#define MAC_CSR5   0x3014

Definition at line 291 of file rt61pci.h.

#define MAC_CSR5_BSS_ID_MASK   FIELD32(0x00ff0000)

Definition at line 294 of file rt61pci.h.

#define MAC_CSR5_BYTE4   FIELD32(0x000000ff)

Definition at line 292 of file rt61pci.h.

#define MAC_CSR5_BYTE5   FIELD32(0x0000ff00)

Definition at line 293 of file rt61pci.h.

#define MAC_CSR6   0x3018

Definition at line 299 of file rt61pci.h.

#define MAC_CSR6_MAX_FRAME_UNIT   FIELD32(0x00000fff)

Definition at line 300 of file rt61pci.h.

#define MAC_CSR7   0x301c

Definition at line 305 of file rt61pci.h.

#define MAC_CSR8   0x3020

Definition at line 311 of file rt61pci.h.

#define MAC_CSR8_EIFS   FIELD32(0xffff0000)

Definition at line 314 of file rt61pci.h.

#define MAC_CSR8_SIFS   FIELD32(0x000000ff)

Definition at line 312 of file rt61pci.h.

#define MAC_CSR8_SIFS_AFTER_RX_OFDM   FIELD32(0x0000ff00)

Definition at line 313 of file rt61pci.h.

#define MAC_CSR9   0x3024

Definition at line 323 of file rt61pci.h.

#define MAC_CSR9_CW_SELECT   FIELD32(0x00010000)

Definition at line 327 of file rt61pci.h.

#define MAC_CSR9_CWMAX   FIELD32(0x0000f000)

Definition at line 326 of file rt61pci.h.

#define MAC_CSR9_CWMIN   FIELD32(0x00000f00)

Definition at line 325 of file rt61pci.h.

#define MAC_CSR9_SLOT_TIME   FIELD32(0x000000ff)

Definition at line 324 of file rt61pci.h.

#define MAX_TXPOWER   31

Definition at line 1493 of file rt61pci.h.

#define MCU_CNTL_CSR   0x000c

Definition at line 85 of file rt61pci.h.

#define MCU_CNTL_CSR_READY   FIELD32(0x00000004)

Definition at line 88 of file rt61pci.h.

#define MCU_CNTL_CSR_RESET   FIELD32(0x00000002)

Definition at line 87 of file rt61pci.h.

#define MCU_CNTL_CSR_SELECT_BANK   FIELD32(0x00000001)

Definition at line 86 of file rt61pci.h.

#define MCU_INT_MASK_CSR   0x0018

Definition at line 115 of file rt61pci.h.

#define MCU_INT_MASK_CSR_0   FIELD32(0x00000001)

Definition at line 116 of file rt61pci.h.

#define MCU_INT_MASK_CSR_1   FIELD32(0x00000002)

Definition at line 117 of file rt61pci.h.

#define MCU_INT_MASK_CSR_2   FIELD32(0x00000004)

Definition at line 118 of file rt61pci.h.

#define MCU_INT_MASK_CSR_3   FIELD32(0x00000008)

Definition at line 119 of file rt61pci.h.

#define MCU_INT_MASK_CSR_4   FIELD32(0x00000010)

Definition at line 120 of file rt61pci.h.

#define MCU_INT_MASK_CSR_5   FIELD32(0x00000020)

Definition at line 121 of file rt61pci.h.

#define MCU_INT_MASK_CSR_6   FIELD32(0x00000040)

Definition at line 122 of file rt61pci.h.

#define MCU_INT_MASK_CSR_7   FIELD32(0x00000080)

Definition at line 123 of file rt61pci.h.

#define MCU_INT_MASK_CSR_TBTT_EXPIRE   FIELD32(0x00000200)

Definition at line 125 of file rt61pci.h.

#define MCU_INT_MASK_CSR_TWAKEUP   FIELD32(0x00000100)

Definition at line 124 of file rt61pci.h.

#define MCU_INT_SOURCE_CSR   0x0014

Definition at line 100 of file rt61pci.h.

#define MCU_INT_SOURCE_CSR_0   FIELD32(0x00000001)

Definition at line 101 of file rt61pci.h.

#define MCU_INT_SOURCE_CSR_1   FIELD32(0x00000002)

Definition at line 102 of file rt61pci.h.

#define MCU_INT_SOURCE_CSR_2   FIELD32(0x00000004)

Definition at line 103 of file rt61pci.h.

#define MCU_INT_SOURCE_CSR_3   FIELD32(0x00000008)

Definition at line 104 of file rt61pci.h.

#define MCU_INT_SOURCE_CSR_4   FIELD32(0x00000010)

Definition at line 105 of file rt61pci.h.

#define MCU_INT_SOURCE_CSR_5   FIELD32(0x00000020)

Definition at line 106 of file rt61pci.h.

#define MCU_INT_SOURCE_CSR_6   FIELD32(0x00000040)

Definition at line 107 of file rt61pci.h.

#define MCU_INT_SOURCE_CSR_7   FIELD32(0x00000080)

Definition at line 108 of file rt61pci.h.

#define MCU_INT_SOURCE_CSR_TBTT_EXPIRE   FIELD32(0x00000200)

Definition at line 110 of file rt61pci.h.

#define MCU_INT_SOURCE_CSR_TWAKEUP   FIELD32(0x00000100)

Definition at line 109 of file rt61pci.h.

#define MCU_LED   0x50

Definition at line 1286 of file rt61pci.h.

#define MCU_LED_STRENGTH   0x52

Definition at line 1287 of file rt61pci.h.

#define MCU_LEDCS_LED_MODE   FIELD16(0x001f)

Definition at line 203 of file rt61pci.h.

#define MCU_LEDCS_LINK_A_STATUS   FIELD16(0x0080)

Definition at line 206 of file rt61pci.h.

#define MCU_LEDCS_LINK_BG_STATUS   FIELD16(0x0040)

Definition at line 205 of file rt61pci.h.

#define MCU_LEDCS_POLARITY_ACT   FIELD16(0x2000)

Definition at line 212 of file rt61pci.h.

#define MCU_LEDCS_POLARITY_GPIO_0   FIELD16(0x0100)

Definition at line 207 of file rt61pci.h.

#define MCU_LEDCS_POLARITY_GPIO_1   FIELD16(0x0200)

Definition at line 208 of file rt61pci.h.

#define MCU_LEDCS_POLARITY_GPIO_2   FIELD16(0x0400)

Definition at line 209 of file rt61pci.h.

#define MCU_LEDCS_POLARITY_GPIO_3   FIELD16(0x0800)

Definition at line 210 of file rt61pci.h.

#define MCU_LEDCS_POLARITY_GPIO_4   FIELD16(0x1000)

Definition at line 211 of file rt61pci.h.

#define MCU_LEDCS_POLARITY_READY_A   FIELD16(0x8000)

Definition at line 214 of file rt61pci.h.

#define MCU_LEDCS_POLARITY_READY_BG   FIELD16(0x4000)

Definition at line 213 of file rt61pci.h.

#define MCU_LEDCS_RADIO_STATUS   FIELD16(0x0020)

Definition at line 204 of file rt61pci.h.

#define MCU_SLEEP   0x30

Definition at line 1284 of file rt61pci.h.

#define MCU_TXOP_ARRAY_BASE   0x2110

Definition at line 224 of file rt61pci.h.

#define MCU_WAKEUP   0x31

Definition at line 1285 of file rt61pci.h.

#define MGMT_BASE_CSR   0x3410

Definition at line 814 of file rt61pci.h.

#define MGMT_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)

Definition at line 815 of file rt61pci.h.

#define MGMT_TXPTR_CSR   0x3448

Definition at line 925 of file rt61pci.h.

#define MIN_TXPOWER   0

Definition at line 1492 of file rt61pci.h.

#define NUM_TX_QUEUES   4

Definition at line 66 of file rt61pci.h.

#define PAIRWISE_KEY_ENTRY (   __idx)
Value:
( PAIRWISE_KEY_TABLE_BASE + \
((__idx) * sizeof(struct hw_key_entry)) )

Definition at line 145 of file rt61pci.h.

#define PAIRWISE_KEY_TABLE_BASE   0x1200

Definition at line 139 of file rt61pci.h.

#define PAIRWISE_TA_ENTRY (   __idx)
Value:
( PAIRWISE_TA_TABLE_BASE + \
((__idx) * sizeof(struct hw_pairwise_ta_entry)) )

Definition at line 148 of file rt61pci.h.

#define PAIRWISE_TA_TABLE_BASE   0x1a00

Definition at line 140 of file rt61pci.h.

#define PBF_QUEUE_CSR   0x34b0

Definition at line 1081 of file rt61pci.h.

#define PCI_CFG_CSR   0x3460

Definition at line 957 of file rt61pci.h.

#define PCI_USEC_CSR   0x001c

Definition at line 130 of file rt61pci.h.

#define PHY_CSR0   0x3080

Definition at line 575 of file rt61pci.h.

#define PHY_CSR0_PA_PE_A   FIELD32(0x00020000)

Definition at line 577 of file rt61pci.h.

#define PHY_CSR0_PA_PE_BG   FIELD32(0x00010000)

Definition at line 576 of file rt61pci.h.

#define PHY_CSR1   0x3084

Definition at line 582 of file rt61pci.h.

#define PHY_CSR2   0x3088

Definition at line 587 of file rt61pci.h.

#define PHY_CSR3   0x308c

Definition at line 596 of file rt61pci.h.

#define PHY_CSR3_BUSY   FIELD32(0x00010000)

Definition at line 600 of file rt61pci.h.

#define PHY_CSR3_READ_CONTROL   FIELD32(0x00008000)

Definition at line 599 of file rt61pci.h.

#define PHY_CSR3_REGNUM   FIELD32(0x00007f00)

Definition at line 598 of file rt61pci.h.

#define PHY_CSR3_VALUE   FIELD32(0x000000ff)

Definition at line 597 of file rt61pci.h.

#define PHY_CSR4   0x3090

Definition at line 610 of file rt61pci.h.

#define PHY_CSR4_BUSY   FIELD32(0x80000000)

Definition at line 615 of file rt61pci.h.

#define PHY_CSR4_IF_SELECT   FIELD32(0x20000000)

Definition at line 613 of file rt61pci.h.

#define PHY_CSR4_NUMBER_OF_BITS   FIELD32(0x1f000000)

Definition at line 612 of file rt61pci.h.

#define PHY_CSR4_PLL_LD   FIELD32(0x40000000)

Definition at line 614 of file rt61pci.h.

#define PHY_CSR4_VALUE   FIELD32(0x00ffffff)

Definition at line 611 of file rt61pci.h.

#define PHY_CSR5   0x3094

Definition at line 620 of file rt61pci.h.

#define PHY_CSR5_IQ_FLIP   FIELD32(0x00000004)

Definition at line 621 of file rt61pci.h.

#define PHY_CSR6   0x3098

Definition at line 626 of file rt61pci.h.

#define PHY_CSR6_IQ_FLIP   FIELD32(0x00000004)

Definition at line 627 of file rt61pci.h.

#define PHY_CSR7   0x309c

Definition at line 632 of file rt61pci.h.

#define QOS_CSR0   0x30e0

Definition at line 752 of file rt61pci.h.

#define QOS_CSR0_BYTE0   FIELD32(0x000000ff)

Definition at line 753 of file rt61pci.h.

#define QOS_CSR0_BYTE1   FIELD32(0x0000ff00)

Definition at line 754 of file rt61pci.h.

#define QOS_CSR0_BYTE2   FIELD32(0x00ff0000)

Definition at line 755 of file rt61pci.h.

#define QOS_CSR0_BYTE3   FIELD32(0xff000000)

Definition at line 756 of file rt61pci.h.

#define QOS_CSR1   0x30e4

Definition at line 761 of file rt61pci.h.

#define QOS_CSR1_BYTE4   FIELD32(0x000000ff)

Definition at line 762 of file rt61pci.h.

#define QOS_CSR1_BYTE5   FIELD32(0x0000ff00)

Definition at line 763 of file rt61pci.h.

#define QOS_CSR2   0x30e8

Definition at line 768 of file rt61pci.h.

#define QOS_CSR3   0x30ec

Definition at line 775 of file rt61pci.h.

#define QOS_CSR4   0x30f0

Definition at line 776 of file rt61pci.h.

#define QOS_CSR5   0x30f4

Definition at line 781 of file rt61pci.h.

#define RF2527   0x0003

Definition at line 42 of file rt61pci.h.

#define RF2529   0x0004

Definition at line 43 of file rt61pci.h.

#define RF3_TXPOWER   FIELD32(0x00003e00)

Definition at line 1143 of file rt61pci.h.

#define RF4_FREQ_OFFSET   FIELD32(0x0003f000)

Definition at line 1148 of file rt61pci.h.

#define RF5225   0x0001

Definition at line 40 of file rt61pci.h.

#define RF5325   0x0002

Definition at line 41 of file rt61pci.h.

#define RF_BASE   0x0004

Definition at line 60 of file rt61pci.h.

#define RF_SIZE   0x0010

Definition at line 61 of file rt61pci.h.

#define RT2561_PCI_ID   0x0302

Definition at line 34 of file rt61pci.h.

#define RT2561s_PCI_ID   0x0301

Definition at line 33 of file rt61pci.h.

#define RT2661_PCI_ID   0x0401

Definition at line 35 of file rt61pci.h.

#define RX_BASE_CSR   0x3450

Definition at line 930 of file rt61pci.h.

#define RX_BASE_CSR_RING_REGISTER   FIELD32(0xffffffff)

Definition at line 931 of file rt61pci.h.

#define RX_CNTL_CSR   0x3458

Definition at line 945 of file rt61pci.h.

#define RX_CNTL_CSR_ENABLE_RX_DMA   FIELD32(0x00000001)

Definition at line 946 of file rt61pci.h.

#define RX_CNTL_CSR_LOAD_RXD   FIELD32(0x00000002)

Definition at line 947 of file rt61pci.h.

#define RX_RING_CSR   0x3454

Definition at line 937 of file rt61pci.h.

#define RX_RING_CSR_RING_SIZE   FIELD32(0x000000ff)

Definition at line 938 of file rt61pci.h.

#define RX_RING_CSR_RXD_SIZE   FIELD32(0x00003f00)

Definition at line 939 of file rt61pci.h.

#define RX_RING_CSR_RXD_WRITEBACK_SIZE   FIELD32(0x00070000)

Definition at line 940 of file rt61pci.h.

#define RXD_DESC_SIZE   ( 16 * sizeof(__le32) )

Definition at line 1294 of file rt61pci.h.

#define RXD_W0_BROADCAST   FIELD32(0x00000010)

Definition at line 1425 of file rt61pci.h.

#define RXD_W0_CIPHER_ALG   FIELD32(0xe0000000)

Definition at line 1432 of file rt61pci.h.

#define RXD_W0_CIPHER_ERROR   FIELD32(0x00000300)

Definition at line 1429 of file rt61pci.h.

#define RXD_W0_CRC_ERROR   FIELD32(0x00000040)

Definition at line 1427 of file rt61pci.h.

#define RXD_W0_DATABYTE_COUNT   FIELD32(0x0fff0000)

Definition at line 1431 of file rt61pci.h.

#define RXD_W0_DROP   FIELD32(0x00000002)

Definition at line 1422 of file rt61pci.h.

#define RXD_W0_KEY_INDEX   FIELD32(0x0000fc00)

Definition at line 1430 of file rt61pci.h.

#define RXD_W0_MULTICAST   FIELD32(0x00000008)

Definition at line 1424 of file rt61pci.h.

#define RXD_W0_MY_BSS   FIELD32(0x00000020)

Definition at line 1426 of file rt61pci.h.

#define RXD_W0_OFDM   FIELD32(0x00000080)

Definition at line 1428 of file rt61pci.h.

#define RXD_W0_OWNER_NIC   FIELD32(0x00000001)

Definition at line 1421 of file rt61pci.h.

#define RXD_W0_UNICAST_TO_ME   FIELD32(0x00000004)

Definition at line 1423 of file rt61pci.h.

#define RXD_W10_RESERVED   FIELD32(0xffffffff)

Definition at line 1481 of file rt61pci.h.

#define RXD_W11_RESERVED   FIELD32(0xffffffff)

Definition at line 1482 of file rt61pci.h.

#define RXD_W12_RESERVED   FIELD32(0xffffffff)

Definition at line 1483 of file rt61pci.h.

#define RXD_W13_RESERVED   FIELD32(0xffffffff)

Definition at line 1484 of file rt61pci.h.

#define RXD_W14_RESERVED   FIELD32(0xffffffff)

Definition at line 1485 of file rt61pci.h.

#define RXD_W15_RESERVED   FIELD32(0xffffffff)

Definition at line 1486 of file rt61pci.h.

#define RXD_W1_FRAME_OFFSET   FIELD32(0x7f000000)

Definition at line 1441 of file rt61pci.h.

#define RXD_W1_RSSI_AGC   FIELD32(0x00001f00)

Definition at line 1439 of file rt61pci.h.

#define RXD_W1_RSSI_LNA   FIELD32(0x00006000)

Definition at line 1440 of file rt61pci.h.

#define RXD_W1_SIGNAL   FIELD32(0x000000ff)

Definition at line 1438 of file rt61pci.h.

#define RXD_W2_IV   FIELD32(0xffffffff)

Definition at line 1447 of file rt61pci.h.

#define RXD_W3_EIV   FIELD32(0xffffffff)

Definition at line 1453 of file rt61pci.h.

#define RXD_W4_ICV   FIELD32(0xffffffff)

Definition at line 1460 of file rt61pci.h.

#define RXD_W5_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)

Definition at line 1472 of file rt61pci.h.

#define RXD_W6_RESERVED   FIELD32(0xffffffff)

Definition at line 1477 of file rt61pci.h.

#define RXD_W7_RESERVED   FIELD32(0xffffffff)

Definition at line 1478 of file rt61pci.h.

#define RXD_W8_RESERVED   FIELD32(0xffffffff)

Definition at line 1479 of file rt61pci.h.

#define RXD_W9_RESERVED   FIELD32(0xffffffff)

Definition at line 1480 of file rt61pci.h.

#define RXPTR_CSR   0x345c

Definition at line 952 of file rt61pci.h.

#define SEC_CSR0   0x30a0

Definition at line 641 of file rt61pci.h.

#define SEC_CSR0_BSS0_KEY0_VALID   FIELD32(0x00000001)

Definition at line 642 of file rt61pci.h.

#define SEC_CSR0_BSS0_KEY1_VALID   FIELD32(0x00000002)

Definition at line 643 of file rt61pci.h.

#define SEC_CSR0_BSS0_KEY2_VALID   FIELD32(0x00000004)

Definition at line 644 of file rt61pci.h.

#define SEC_CSR0_BSS0_KEY3_VALID   FIELD32(0x00000008)

Definition at line 645 of file rt61pci.h.

#define SEC_CSR0_BSS1_KEY0_VALID   FIELD32(0x00000010)

Definition at line 646 of file rt61pci.h.

#define SEC_CSR0_BSS1_KEY1_VALID   FIELD32(0x00000020)

Definition at line 647 of file rt61pci.h.

#define SEC_CSR0_BSS1_KEY2_VALID   FIELD32(0x00000040)

Definition at line 648 of file rt61pci.h.

#define SEC_CSR0_BSS1_KEY3_VALID   FIELD32(0x00000080)

Definition at line 649 of file rt61pci.h.

#define SEC_CSR0_BSS2_KEY0_VALID   FIELD32(0x00000100)

Definition at line 650 of file rt61pci.h.

#define SEC_CSR0_BSS2_KEY1_VALID   FIELD32(0x00000200)

Definition at line 651 of file rt61pci.h.

#define SEC_CSR0_BSS2_KEY2_VALID   FIELD32(0x00000400)

Definition at line 652 of file rt61pci.h.

#define SEC_CSR0_BSS2_KEY3_VALID   FIELD32(0x00000800)

Definition at line 653 of file rt61pci.h.

#define SEC_CSR0_BSS3_KEY0_VALID   FIELD32(0x00001000)

Definition at line 654 of file rt61pci.h.

#define SEC_CSR0_BSS3_KEY1_VALID   FIELD32(0x00002000)

Definition at line 655 of file rt61pci.h.

#define SEC_CSR0_BSS3_KEY2_VALID   FIELD32(0x00004000)

Definition at line 656 of file rt61pci.h.

#define SEC_CSR0_BSS3_KEY3_VALID   FIELD32(0x00008000)

Definition at line 657 of file rt61pci.h.

#define SEC_CSR1   0x30a4

Definition at line 662 of file rt61pci.h.

#define SEC_CSR1_BSS0_KEY0_CIPHER_ALG   FIELD32(0x00000007)

Definition at line 663 of file rt61pci.h.

#define SEC_CSR1_BSS0_KEY1_CIPHER_ALG   FIELD32(0x00000070)

Definition at line 664 of file rt61pci.h.

#define SEC_CSR1_BSS0_KEY2_CIPHER_ALG   FIELD32(0x00000700)

Definition at line 665 of file rt61pci.h.

#define SEC_CSR1_BSS0_KEY3_CIPHER_ALG   FIELD32(0x00007000)

Definition at line 666 of file rt61pci.h.

#define SEC_CSR1_BSS1_KEY0_CIPHER_ALG   FIELD32(0x00070000)

Definition at line 667 of file rt61pci.h.

#define SEC_CSR1_BSS1_KEY1_CIPHER_ALG   FIELD32(0x00700000)

Definition at line 668 of file rt61pci.h.

#define SEC_CSR1_BSS1_KEY2_CIPHER_ALG   FIELD32(0x07000000)

Definition at line 669 of file rt61pci.h.

#define SEC_CSR1_BSS1_KEY3_CIPHER_ALG   FIELD32(0x70000000)

Definition at line 670 of file rt61pci.h.

#define SEC_CSR2   0x30a8

Definition at line 677 of file rt61pci.h.

#define SEC_CSR3   0x30ac

Definition at line 678 of file rt61pci.h.

#define SEC_CSR4   0x30b0

Definition at line 683 of file rt61pci.h.

#define SEC_CSR4_ENABLE_BSS0   FIELD32(0x00000001)

Definition at line 684 of file rt61pci.h.

#define SEC_CSR4_ENABLE_BSS1   FIELD32(0x00000002)

Definition at line 685 of file rt61pci.h.

#define SEC_CSR4_ENABLE_BSS2   FIELD32(0x00000004)

Definition at line 686 of file rt61pci.h.

#define SEC_CSR4_ENABLE_BSS3   FIELD32(0x00000008)

Definition at line 687 of file rt61pci.h.

#define SEC_CSR5   0x30b4

Definition at line 692 of file rt61pci.h.

#define SEC_CSR5_BSS2_KEY0_CIPHER_ALG   FIELD32(0x00000007)

Definition at line 693 of file rt61pci.h.

#define SEC_CSR5_BSS2_KEY1_CIPHER_ALG   FIELD32(0x00000070)

Definition at line 694 of file rt61pci.h.

#define SEC_CSR5_BSS2_KEY2_CIPHER_ALG   FIELD32(0x00000700)

Definition at line 695 of file rt61pci.h.

#define SEC_CSR5_BSS2_KEY3_CIPHER_ALG   FIELD32(0x00007000)

Definition at line 696 of file rt61pci.h.

#define SEC_CSR5_BSS3_KEY0_CIPHER_ALG   FIELD32(0x00070000)

Definition at line 697 of file rt61pci.h.

#define SEC_CSR5_BSS3_KEY1_CIPHER_ALG   FIELD32(0x00700000)

Definition at line 698 of file rt61pci.h.

#define SEC_CSR5_BSS3_KEY2_CIPHER_ALG   FIELD32(0x07000000)

Definition at line 699 of file rt61pci.h.

#define SEC_CSR5_BSS3_KEY3_CIPHER_ALG   FIELD32(0x70000000)

Definition at line 700 of file rt61pci.h.

#define SHARED_KEY_ENTRY (   __idx)
Value:
( SHARED_KEY_TABLE_BASE + \
((__idx) * sizeof(struct hw_key_entry)) )

Definition at line 142 of file rt61pci.h.

#define SHARED_KEY_TABLE_BASE   0x1000

Definition at line 138 of file rt61pci.h.

#define SOFT_RESET_CSR   0x0010

Definition at line 94 of file rt61pci.h.

#define SOFT_RESET_CSR_FORCE_CLOCK_ON   FIELD32(0x00000002)

Definition at line 95 of file rt61pci.h.

#define STA_CSR0   0x30c0

Definition at line 709 of file rt61pci.h.

#define STA_CSR0_FCS_ERROR   FIELD32(0x0000ffff)

Definition at line 710 of file rt61pci.h.

#define STA_CSR0_PLCP_ERROR   FIELD32(0xffff0000)

Definition at line 711 of file rt61pci.h.

#define STA_CSR1   0x30c4

Definition at line 716 of file rt61pci.h.

#define STA_CSR1_FALSE_CCA_ERROR   FIELD32(0xffff0000)

Definition at line 718 of file rt61pci.h.

#define STA_CSR1_PHYSICAL_ERROR   FIELD32(0x0000ffff)

Definition at line 717 of file rt61pci.h.

#define STA_CSR2   0x30c8

Definition at line 723 of file rt61pci.h.

#define STA_CSR2_RX_FIFO_OVERFLOW_COUNT   FIELD32(0x0000ffff)

Definition at line 724 of file rt61pci.h.

#define STA_CSR2_RX_OVERFLOW_COUNT   FIELD32(0xffff0000)

Definition at line 725 of file rt61pci.h.

#define STA_CSR3   0x30cc

Definition at line 730 of file rt61pci.h.

#define STA_CSR3_TX_BEACON_COUNT   FIELD32(0x0000ffff)

Definition at line 731 of file rt61pci.h.

#define STA_CSR4   0x30d0

Definition at line 737 of file rt61pci.h.

#define STA_CSR4_PID_SUBTYPE   FIELD32(0x00001f00)

Definition at line 741 of file rt61pci.h.

#define STA_CSR4_PID_TYPE   FIELD32(0x0000e000)

Definition at line 742 of file rt61pci.h.

#define STA_CSR4_RETRY_COUNT   FIELD32(0x000000f0)

Definition at line 740 of file rt61pci.h.

#define STA_CSR4_TX_RESULT   FIELD32(0x0000000e)

Definition at line 739 of file rt61pci.h.

#define STA_CSR4_TXRATE   FIELD32(0x000f0000)

Definition at line 743 of file rt61pci.h.

#define STA_CSR4_VALID   FIELD32(0x00000001)

Definition at line 738 of file rt61pci.h.

#define TEST_MODE_CSR   0x3484

Definition at line 1039 of file rt61pci.h.

#define TX_CNTL_CSR   0x3430

Definition at line 896 of file rt61pci.h.

#define TX_CNTL_CSR_ABORT_TX_AC0   FIELD32(0x00010000)

Definition at line 902 of file rt61pci.h.

#define TX_CNTL_CSR_ABORT_TX_AC1   FIELD32(0x00020000)

Definition at line 903 of file rt61pci.h.

#define TX_CNTL_CSR_ABORT_TX_AC2   FIELD32(0x00040000)

Definition at line 904 of file rt61pci.h.

#define TX_CNTL_CSR_ABORT_TX_AC3   FIELD32(0x00080000)

Definition at line 905 of file rt61pci.h.

#define TX_CNTL_CSR_ABORT_TX_MGMT   FIELD32(0x00100000)

Definition at line 906 of file rt61pci.h.

#define TX_CNTL_CSR_KICK_TX_AC0   FIELD32(0x00000001)

Definition at line 897 of file rt61pci.h.

#define TX_CNTL_CSR_KICK_TX_AC1   FIELD32(0x00000002)

Definition at line 898 of file rt61pci.h.

#define TX_CNTL_CSR_KICK_TX_AC2   FIELD32(0x00000004)

Definition at line 899 of file rt61pci.h.

#define TX_CNTL_CSR_KICK_TX_AC3   FIELD32(0x00000008)

Definition at line 900 of file rt61pci.h.

#define TX_CNTL_CSR_KICK_TX_MGMT   FIELD32(0x00000010)

Definition at line 901 of file rt61pci.h.

#define TX_DMA_DST_CSR   0x342c

Definition at line 878 of file rt61pci.h.

#define TX_DMA_DST_CSR_DEST_AC0   FIELD32(0x00000003)

Definition at line 879 of file rt61pci.h.

#define TX_DMA_DST_CSR_DEST_AC1   FIELD32(0x0000000c)

Definition at line 880 of file rt61pci.h.

#define TX_DMA_DST_CSR_DEST_AC2   FIELD32(0x00000030)

Definition at line 881 of file rt61pci.h.

#define TX_DMA_DST_CSR_DEST_AC3   FIELD32(0x000000c0)

Definition at line 882 of file rt61pci.h.

#define TX_DMA_DST_CSR_DEST_MGMT   FIELD32(0x00000300)

Definition at line 883 of file rt61pci.h.

#define TX_RING_CSR0   0x3418

Definition at line 820 of file rt61pci.h.

#define TX_RING_CSR0_AC0_RING_SIZE   FIELD32(0x000000ff)

Definition at line 821 of file rt61pci.h.

#define TX_RING_CSR0_AC1_RING_SIZE   FIELD32(0x0000ff00)

Definition at line 822 of file rt61pci.h.

#define TX_RING_CSR0_AC2_RING_SIZE   FIELD32(0x00ff0000)

Definition at line 823 of file rt61pci.h.

#define TX_RING_CSR0_AC3_RING_SIZE   FIELD32(0xff000000)

Definition at line 824 of file rt61pci.h.

#define TX_RING_CSR1   0x341c

Definition at line 830 of file rt61pci.h.

#define TX_RING_CSR1_HCCA_RING_SIZE   FIELD32(0x0000ff00)

Definition at line 832 of file rt61pci.h.

#define TX_RING_CSR1_MGMT_RING_SIZE   FIELD32(0x000000ff)

Definition at line 831 of file rt61pci.h.

#define TX_RING_CSR1_TXD_SIZE   FIELD32(0x003f0000)

Definition at line 833 of file rt61pci.h.

#define TXD_DESC_SIZE   ( 16 * sizeof(__le32) )

Definition at line 1292 of file rt61pci.h.

#define TXD_W0_ACK   FIELD32(0x00000008)

Definition at line 1315 of file rt61pci.h.

#define TXD_W0_BURST   FIELD32(0x10000000)

Definition at line 1324 of file rt61pci.h.

#define TXD_W0_CIPHER_ALG   FIELD32(0xe0000000)

Definition at line 1325 of file rt61pci.h.

#define TXD_W0_DATABYTE_COUNT   FIELD32(0x0fff0000)

Definition at line 1323 of file rt61pci.h.

#define TXD_W0_IFS   FIELD32(0x00000040)

Definition at line 1318 of file rt61pci.h.

#define TXD_W0_KEY_INDEX   FIELD32(0x0000fc00)

Definition at line 1322 of file rt61pci.h.

#define TXD_W0_KEY_TABLE   FIELD32(0x00000200)

Definition at line 1321 of file rt61pci.h.

#define TXD_W0_MORE_FRAG   FIELD32(0x00000004)

Definition at line 1314 of file rt61pci.h.

#define TXD_W0_OFDM   FIELD32(0x00000020)

Definition at line 1317 of file rt61pci.h.

#define TXD_W0_OWNER_NIC   FIELD32(0x00000001)

Definition at line 1312 of file rt61pci.h.

#define TXD_W0_RETRY_MODE   FIELD32(0x00000080)

Definition at line 1319 of file rt61pci.h.

#define TXD_W0_TIMESTAMP   FIELD32(0x00000010)

Definition at line 1316 of file rt61pci.h.

#define TXD_W0_TKIP_MIC   FIELD32(0x00000100)

Definition at line 1320 of file rt61pci.h.

#define TXD_W0_VALID   FIELD32(0x00000002)

Definition at line 1313 of file rt61pci.h.

#define TXD_W10_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)

Definition at line 1391 of file rt61pci.h.

#define TXD_W11_BUFFER_LENGTH0   FIELD32(0x00000fff)

Definition at line 1396 of file rt61pci.h.

#define TXD_W11_BUFFER_LENGTH1   FIELD32(0x0fff0000)

Definition at line 1397 of file rt61pci.h.

#define TXD_W12_BUFFER_LENGTH2   FIELD32(0x00000fff)

Definition at line 1398 of file rt61pci.h.

#define TXD_W12_BUFFER_LENGTH3   FIELD32(0x0fff0000)

Definition at line 1399 of file rt61pci.h.

#define TXD_W13_BUFFER_LENGTH4   FIELD32(0x00000fff)

Definition at line 1400 of file rt61pci.h.

#define TXD_W14_SK_BUFFER   FIELD32(0xffffffff)

Definition at line 1405 of file rt61pci.h.

#define TXD_W15_NEXT_SK_BUFFER   FIELD32(0xffffffff)

Definition at line 1410 of file rt61pci.h.

#define TXD_W1_AIFSN   FIELD32(0x000000f0)

Definition at line 1334 of file rt61pci.h.

#define TXD_W1_BUFFER_COUNT   FIELD32(0xe0000000)

Definition at line 1340 of file rt61pci.h.

#define TXD_W1_CWMAX   FIELD32(0x0000f000)

Definition at line 1336 of file rt61pci.h.

#define TXD_W1_CWMIN   FIELD32(0x00000f00)

Definition at line 1335 of file rt61pci.h.

#define TXD_W1_HOST_Q_ID   FIELD32(0x0000000f)

Definition at line 1333 of file rt61pci.h.

#define TXD_W1_HW_SEQUENCE   FIELD32(0x10000000)

Definition at line 1339 of file rt61pci.h.

#define TXD_W1_IV_OFFSET   FIELD32(0x003f0000)

Definition at line 1337 of file rt61pci.h.

#define TXD_W1_PIGGY_BACK   FIELD32(0x01000000)

Definition at line 1338 of file rt61pci.h.

#define TXD_W2_PLCP_LENGTH_HIGH   FIELD32(0xff000000)

Definition at line 1348 of file rt61pci.h.

#define TXD_W2_PLCP_LENGTH_LOW   FIELD32(0x00ff0000)

Definition at line 1347 of file rt61pci.h.

#define TXD_W2_PLCP_SERVICE   FIELD32(0x0000ff00)

Definition at line 1346 of file rt61pci.h.

#define TXD_W2_PLCP_SIGNAL   FIELD32(0x000000ff)

Definition at line 1345 of file rt61pci.h.

#define TXD_W3_IV   FIELD32(0xffffffff)

Definition at line 1353 of file rt61pci.h.

#define TXD_W4_EIV   FIELD32(0xffffffff)

Definition at line 1358 of file rt61pci.h.

#define TXD_W5_FRAME_OFFSET   FIELD32(0x000000ff)

Definition at line 1368 of file rt61pci.h.

#define TXD_W5_PID_SUBTYPE   FIELD32(0x00001f00)

Definition at line 1369 of file rt61pci.h.

#define TXD_W5_PID_TYPE   FIELD32(0x0000e000)

Definition at line 1370 of file rt61pci.h.

#define TXD_W5_TX_POWER   FIELD32(0x00ff0000)

Definition at line 1371 of file rt61pci.h.

#define TXD_W5_WAITING_DMA_DONE_INT   FIELD32(0x01000000)

Definition at line 1372 of file rt61pci.h.

#define TXD_W6_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)

Definition at line 1387 of file rt61pci.h.

#define TXD_W7_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)

Definition at line 1388 of file rt61pci.h.

#define TXD_W8_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)

Definition at line 1389 of file rt61pci.h.

#define TXD_W9_BUFFER_PHYSICAL_ADDRESS   FIELD32(0xffffffff)

Definition at line 1390 of file rt61pci.h.

#define TXINFO_SIZE   ( 6 * sizeof(__le32) )

Definition at line 1293 of file rt61pci.h.

#define TXPOWER_FROM_DEV (   __txpower)    (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)

Definition at line 1496 of file rt61pci.h.

#define TXPOWER_TO_DEV (   __txpower)    clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)

Definition at line 1499 of file rt61pci.h.

#define TXRX_CSR0   0x3040

Definition at line 418 of file rt61pci.h.

#define TXRX_CSR0_AUTO_TX_SEQ   FIELD32(0x00008000)

Definition at line 421 of file rt61pci.h.

#define TXRX_CSR0_DISABLE_RX   FIELD32(0x00010000)

Definition at line 422 of file rt61pci.h.

#define TXRX_CSR0_DROP_ACK_CTS   FIELD32(0x02000000)

Definition at line 431 of file rt61pci.h.

#define TXRX_CSR0_DROP_BROADCAST   FIELD32(0x01000000)

Definition at line 430 of file rt61pci.h.

#define TXRX_CSR0_DROP_CONTROL   FIELD32(0x00080000)

Definition at line 425 of file rt61pci.h.

#define TXRX_CSR0_DROP_CRC   FIELD32(0x00020000)

Definition at line 423 of file rt61pci.h.

#define TXRX_CSR0_DROP_MULTICAST   FIELD32(0x00800000)

Definition at line 429 of file rt61pci.h.

#define TXRX_CSR0_DROP_NOT_TO_ME   FIELD32(0x00100000)

Definition at line 426 of file rt61pci.h.

#define TXRX_CSR0_DROP_PHYSICAL   FIELD32(0x00040000)

Definition at line 424 of file rt61pci.h.

#define TXRX_CSR0_DROP_TO_DS   FIELD32(0x00200000)

Definition at line 427 of file rt61pci.h.

#define TXRX_CSR0_DROP_VERSION_ERROR   FIELD32(0x00400000)

Definition at line 428 of file rt61pci.h.

#define TXRX_CSR0_RX_ACK_TIMEOUT   FIELD32(0x000001ff)

Definition at line 419 of file rt61pci.h.

#define TXRX_CSR0_TSF_OFFSET   FIELD32(0x00007e00)

Definition at line 420 of file rt61pci.h.

#define TXRX_CSR0_TX_WITHOUT_WAITING   FIELD32(0x04000000)

Definition at line 432 of file rt61pci.h.

#define TXRX_CSR1   0x3044

Definition at line 437 of file rt61pci.h.

#define TXRX_CSR10   0x3068

Definition at line 538 of file rt61pci.h.

#define TXRX_CSR11   0x306c

Definition at line 543 of file rt61pci.h.

#define TXRX_CSR12   0x3070

Definition at line 548 of file rt61pci.h.

#define TXRX_CSR12_LOW_TSFTIMER   FIELD32(0xffffffff)

Definition at line 549 of file rt61pci.h.

#define TXRX_CSR13   0x3074

Definition at line 554 of file rt61pci.h.

#define TXRX_CSR13_HIGH_TSFTIMER   FIELD32(0xffffffff)

Definition at line 555 of file rt61pci.h.

#define TXRX_CSR14   0x3078

Definition at line 560 of file rt61pci.h.

#define TXRX_CSR15   0x307c

Definition at line 565 of file rt61pci.h.

#define TXRX_CSR1_BBP_ID0   FIELD32(0x0000007f)

Definition at line 438 of file rt61pci.h.

#define TXRX_CSR1_BBP_ID0_VALID   FIELD32(0x00000080)

Definition at line 439 of file rt61pci.h.

#define TXRX_CSR1_BBP_ID1   FIELD32(0x00007f00)

Definition at line 440 of file rt61pci.h.

#define TXRX_CSR1_BBP_ID1_VALID   FIELD32(0x00008000)

Definition at line 441 of file rt61pci.h.

#define TXRX_CSR1_BBP_ID2   FIELD32(0x007f0000)

Definition at line 442 of file rt61pci.h.

#define TXRX_CSR1_BBP_ID2_VALID   FIELD32(0x00800000)

Definition at line 443 of file rt61pci.h.

#define TXRX_CSR1_BBP_ID3   FIELD32(0x7f000000)

Definition at line 444 of file rt61pci.h.

#define TXRX_CSR1_BBP_ID3_VALID   FIELD32(0x80000000)

Definition at line 445 of file rt61pci.h.

#define TXRX_CSR2   0x3048

Definition at line 450 of file rt61pci.h.

#define TXRX_CSR2_BBP_ID0   FIELD32(0x0000007f)

Definition at line 451 of file rt61pci.h.

#define TXRX_CSR2_BBP_ID0_VALID   FIELD32(0x00000080)

Definition at line 452 of file rt61pci.h.

#define TXRX_CSR2_BBP_ID1   FIELD32(0x00007f00)

Definition at line 453 of file rt61pci.h.

#define TXRX_CSR2_BBP_ID1_VALID   FIELD32(0x00008000)

Definition at line 454 of file rt61pci.h.

#define TXRX_CSR2_BBP_ID2   FIELD32(0x007f0000)

Definition at line 455 of file rt61pci.h.

#define TXRX_CSR2_BBP_ID2_VALID   FIELD32(0x00800000)

Definition at line 456 of file rt61pci.h.

#define TXRX_CSR2_BBP_ID3   FIELD32(0x7f000000)

Definition at line 457 of file rt61pci.h.

#define TXRX_CSR2_BBP_ID3_VALID   FIELD32(0x80000000)

Definition at line 458 of file rt61pci.h.

#define TXRX_CSR3   0x304c

Definition at line 463 of file rt61pci.h.

#define TXRX_CSR3_BBP_ID0   FIELD32(0x0000007f)

Definition at line 464 of file rt61pci.h.

#define TXRX_CSR3_BBP_ID0_VALID   FIELD32(0x00000080)

Definition at line 465 of file rt61pci.h.

#define TXRX_CSR3_BBP_ID1   FIELD32(0x00007f00)

Definition at line 466 of file rt61pci.h.

#define TXRX_CSR3_BBP_ID1_VALID   FIELD32(0x00008000)

Definition at line 467 of file rt61pci.h.

#define TXRX_CSR3_BBP_ID2   FIELD32(0x007f0000)

Definition at line 468 of file rt61pci.h.

#define TXRX_CSR3_BBP_ID2_VALID   FIELD32(0x00800000)

Definition at line 469 of file rt61pci.h.

#define TXRX_CSR3_BBP_ID3   FIELD32(0x7f000000)

Definition at line 470 of file rt61pci.h.

#define TXRX_CSR3_BBP_ID3_VALID   FIELD32(0x80000000)

Definition at line 471 of file rt61pci.h.

#define TXRX_CSR4   0x3050

Definition at line 480 of file rt61pci.h.

#define TXRX_CSR4_ACK_CTS_PSM   FIELD32(0x00010000)

Definition at line 483 of file rt61pci.h.

#define TXRX_CSR4_AUTORESPOND_ENABLE   FIELD32(0x00020000)

Definition at line 484 of file rt61pci.h.

#define TXRX_CSR4_AUTORESPOND_PREAMBLE   FIELD32(0x00040000)

Definition at line 485 of file rt61pci.h.

#define TXRX_CSR4_CNTL_ACK_POLICY   FIELD32(0x00000700)

Definition at line 482 of file rt61pci.h.

#define TXRX_CSR4_LONG_RETRY_LIMIT   FIELD32(0x0f000000)

Definition at line 489 of file rt61pci.h.

#define TXRX_CSR4_OFDM_TX_FALLBACK_CCK   FIELD32(0x00400000)

Definition at line 488 of file rt61pci.h.

#define TXRX_CSR4_OFDM_TX_RATE_DOWN   FIELD32(0x00080000)

Definition at line 486 of file rt61pci.h.

#define TXRX_CSR4_OFDM_TX_RATE_STEP   FIELD32(0x00300000)

Definition at line 487 of file rt61pci.h.

#define TXRX_CSR4_SHORT_RETRY_LIMIT   FIELD32(0xf0000000)

Definition at line 490 of file rt61pci.h.

#define TXRX_CSR4_TX_ACK_TIMEOUT   FIELD32(0x000000ff)

Definition at line 481 of file rt61pci.h.

#define TXRX_CSR5   0x3054

Definition at line 495 of file rt61pci.h.

#define TXRX_CSR6   0x3058

Definition at line 500 of file rt61pci.h.

#define TXRX_CSR7   0x305c

Definition at line 505 of file rt61pci.h.

#define TXRX_CSR7_ACK_CTS_12MBS   FIELD32(0x00ff0000)

Definition at line 508 of file rt61pci.h.

#define TXRX_CSR7_ACK_CTS_18MBS   FIELD32(0xff000000)

Definition at line 509 of file rt61pci.h.

#define TXRX_CSR7_ACK_CTS_6MBS   FIELD32(0x000000ff)

Definition at line 506 of file rt61pci.h.

#define TXRX_CSR7_ACK_CTS_9MBS   FIELD32(0x0000ff00)

Definition at line 507 of file rt61pci.h.

#define TXRX_CSR8   0x3060

Definition at line 514 of file rt61pci.h.

#define TXRX_CSR8_ACK_CTS_24MBS   FIELD32(0x000000ff)

Definition at line 515 of file rt61pci.h.

#define TXRX_CSR8_ACK_CTS_36MBS   FIELD32(0x0000ff00)

Definition at line 516 of file rt61pci.h.

#define TXRX_CSR8_ACK_CTS_48MBS   FIELD32(0x00ff0000)

Definition at line 517 of file rt61pci.h.

#define TXRX_CSR8_ACK_CTS_54MBS   FIELD32(0xff000000)

Definition at line 518 of file rt61pci.h.

#define TXRX_CSR9   0x3064

Definition at line 527 of file rt61pci.h.

#define TXRX_CSR9_BEACON_GEN   FIELD32(0x00100000)

Definition at line 532 of file rt61pci.h.

#define TXRX_CSR9_BEACON_INTERVAL   FIELD32(0x0000ffff)

Definition at line 528 of file rt61pci.h.

#define TXRX_CSR9_TBTT_ENABLE   FIELD32(0x00080000)

Definition at line 531 of file rt61pci.h.

#define TXRX_CSR9_TIMESTAMP_COMPENSATE   FIELD32(0xff000000)

Definition at line 533 of file rt61pci.h.

#define TXRX_CSR9_TSF_SYNC   FIELD32(0x00060000)

Definition at line 530 of file rt61pci.h.

#define TXRX_CSR9_TSF_TICKING   FIELD32(0x00010000)

Definition at line 529 of file rt61pci.h.

#define UART0_BUFFER_CSR   0x3494

Definition at line 1059 of file rt61pci.h.

#define UART0_FRAME_CSR   0x3490

Definition at line 1054 of file rt61pci.h.

#define UART0_RX_CSR   0x348c

Definition at line 1049 of file rt61pci.h.

#define UART0_TX_CSR   0x3488

Definition at line 1044 of file rt61pci.h.

#define UART_INT_MASK_CSR   0x34ac

Definition at line 1076 of file rt61pci.h.

#define UART_INT_SOURCE_CSR   0x34a8

Definition at line 1071 of file rt61pci.h.

Variable Documentation

struct hw_pairwise_ta_entry __packed
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