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rtl818x.h
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1 /*
2  * Definitions for RTL818x hardware
3  *
4  * Copyright 2007 Michael Wu <[email protected]>
5  * Copyright 2007 Andrea Merello <[email protected]>
6  *
7  * Based on the r8187 driver, which is:
8  * Copyright 2005 Andrea Merello <[email protected]>, et al.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 
15 #ifndef RTL818X_H
16 #define RTL818X_H
17 
18 struct rtl818x_csr {
19  u8 MAC[6];
20  u8 reserved_0[2];
21  __le32 MAR[2];
22  u8 RX_FIFO_COUNT;
23  u8 reserved_1;
24  u8 TX_FIFO_COUNT;
25  u8 BQREQ;
26  u8 reserved_2[4];
27  __le32 TSFT[2];
28  __le32 TLPDA;
29  __le32 TNPDA;
30  __le32 THPDA;
31  __le16 BRSR;
32  u8 BSSID[6];
33  u8 RESP_RATE;
34  u8 EIFS;
35  u8 reserved_3[1];
36  u8 CMD;
37 #define RTL818X_CMD_TX_ENABLE (1 << 2)
38 #define RTL818X_CMD_RX_ENABLE (1 << 3)
39 #define RTL818X_CMD_RESET (1 << 4)
40  u8 reserved_4[4];
41  __le16 INT_MASK;
42  __le16 INT_STATUS;
43 #define RTL818X_INT_RX_OK (1 << 0)
44 #define RTL818X_INT_RX_ERR (1 << 1)
45 #define RTL818X_INT_TXL_OK (1 << 2)
46 #define RTL818X_INT_TXL_ERR (1 << 3)
47 #define RTL818X_INT_RX_DU (1 << 4)
48 #define RTL818X_INT_RX_FO (1 << 5)
49 #define RTL818X_INT_TXN_OK (1 << 6)
50 #define RTL818X_INT_TXN_ERR (1 << 7)
51 #define RTL818X_INT_TXH_OK (1 << 8)
52 #define RTL818X_INT_TXH_ERR (1 << 9)
53 #define RTL818X_INT_TXB_OK (1 << 10)
54 #define RTL818X_INT_TXB_ERR (1 << 11)
55 #define RTL818X_INT_ATIM (1 << 12)
56 #define RTL818X_INT_BEACON (1 << 13)
57 #define RTL818X_INT_TIME_OUT (1 << 14)
58 #define RTL818X_INT_TX_FO (1 << 15)
59  __le32 TX_CONF;
60 #define RTL818X_TX_CONF_LOOPBACK_MAC (1 << 17)
61 #define RTL818X_TX_CONF_LOOPBACK_CONT (3 << 17)
62 #define RTL818X_TX_CONF_NO_ICV (1 << 19)
63 #define RTL818X_TX_CONF_DISCW (1 << 20)
64 #define RTL818X_TX_CONF_SAT_HWPLCP (1 << 24)
65 #define RTL818X_TX_CONF_R8180_ABCD (2 << 25)
66 #define RTL818X_TX_CONF_R8180_F (3 << 25)
67 #define RTL818X_TX_CONF_R8185_ABC (4 << 25)
68 #define RTL818X_TX_CONF_R8185_D (5 << 25)
69 #define RTL818X_TX_CONF_R8187vD (5 << 25)
70 #define RTL818X_TX_CONF_R8187vD_B (6 << 25)
71 #define RTL818X_TX_CONF_HWVER_MASK (7 << 25)
72 #define RTL818X_TX_CONF_DISREQQSIZE (1 << 28)
73 #define RTL818X_TX_CONF_PROBE_DTS (1 << 29)
74 #define RTL818X_TX_CONF_HW_SEQNUM (1 << 30)
75 #define RTL818X_TX_CONF_CW_MIN (1 << 31)
76  __le32 RX_CONF;
77 #define RTL818X_RX_CONF_MONITOR (1 << 0)
78 #define RTL818X_RX_CONF_NICMAC (1 << 1)
79 #define RTL818X_RX_CONF_MULTICAST (1 << 2)
80 #define RTL818X_RX_CONF_BROADCAST (1 << 3)
81 #define RTL818X_RX_CONF_FCS (1 << 5)
82 #define RTL818X_RX_CONF_DATA (1 << 18)
83 #define RTL818X_RX_CONF_CTRL (1 << 19)
84 #define RTL818X_RX_CONF_MGMT (1 << 20)
85 #define RTL818X_RX_CONF_ADDR3 (1 << 21)
86 #define RTL818X_RX_CONF_PM (1 << 22)
87 #define RTL818X_RX_CONF_BSSID (1 << 23)
88 #define RTL818X_RX_CONF_RX_AUTORESETPHY (1 << 28)
89 #define RTL818X_RX_CONF_CSDM1 (1 << 29)
90 #define RTL818X_RX_CONF_CSDM2 (1 << 30)
91 #define RTL818X_RX_CONF_ONLYERLPKT (1 << 31)
92  __le32 INT_TIMEOUT;
93  __le32 TBDA;
94  u8 EEPROM_CMD;
95 #define RTL818X_EEPROM_CMD_READ (1 << 0)
96 #define RTL818X_EEPROM_CMD_WRITE (1 << 1)
97 #define RTL818X_EEPROM_CMD_CK (1 << 2)
98 #define RTL818X_EEPROM_CMD_CS (1 << 3)
99 #define RTL818X_EEPROM_CMD_NORMAL (0 << 6)
100 #define RTL818X_EEPROM_CMD_LOAD (1 << 6)
101 #define RTL818X_EEPROM_CMD_PROGRAM (2 << 6)
102 #define RTL818X_EEPROM_CMD_CONFIG (3 << 6)
103  u8 CONFIG0;
104  u8 CONFIG1;
105  u8 CONFIG2;
106 #define RTL818X_CONFIG2_ANTENNA_DIV (1 << 6)
107  __le32 ANAPARAM;
108  u8 MSR;
109 #define RTL818X_MSR_NO_LINK (0 << 2)
110 #define RTL818X_MSR_ADHOC (1 << 2)
111 #define RTL818X_MSR_INFRA (2 << 2)
112 #define RTL818X_MSR_MASTER (3 << 2)
113 #define RTL818X_MSR_ENEDCA (4 << 2)
114  u8 CONFIG3;
115 #define RTL818X_CONFIG3_ANAPARAM_WRITE (1 << 6)
116 #define RTL818X_CONFIG3_GNT_SELECT (1 << 7)
117  u8 CONFIG4;
118 #define RTL818X_CONFIG4_POWEROFF (1 << 6)
119 #define RTL818X_CONFIG4_VCOOFF (1 << 7)
120  u8 TESTR;
121  u8 reserved_9[2];
122  u8 PGSELECT;
123  u8 SECURITY;
124  __le32 ANAPARAM2;
125  u8 reserved_10[12];
126  __le16 BEACON_INTERVAL;
127  __le16 ATIM_WND;
128  __le16 BEACON_INTERVAL_TIME;
129  __le16 ATIMTR_INTERVAL;
130  u8 PHY_DELAY;
131  u8 CARRIER_SENSE_COUNTER;
132  u8 reserved_11[2];
133  u8 PHY[4];
134  __le16 RFPinsOutput;
135  __le16 RFPinsEnable;
136  __le16 RFPinsSelect;
137  __le16 RFPinsInput;
138  __le32 RF_PARA;
139  __le32 RF_TIMING;
140  u8 GP_ENABLE;
141  u8 GPIO0;
142  u8 GPIO1;
143  u8 reserved_12;
144  __le32 HSSI_PARA;
145  u8 reserved_13[4];
146  u8 TX_AGC_CTL;
147 #define RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT (1 << 0)
148 #define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT (1 << 1)
149 #define RTL818X_TX_AGC_CTL_FEEDBACK_ANT (1 << 2)
150  u8 TX_GAIN_CCK;
151  u8 TX_GAIN_OFDM;
152  u8 TX_ANTENNA;
153  u8 reserved_14[16];
154  u8 WPA_CONF;
155  u8 reserved_15[3];
156  u8 SIFS;
157  u8 DIFS;
158  u8 SLOT;
159  u8 reserved_16[5];
160  u8 CW_CONF;
161 #define RTL818X_CW_CONF_PERPACKET_CW_SHIFT (1 << 0)
162 #define RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT (1 << 1)
163  u8 CW_VAL;
164  u8 RATE_FALLBACK;
165 #define RTL818X_RATE_FALLBACK_ENABLE (1 << 7)
166  u8 ACM_CONTROL;
167  u8 reserved_17[24];
168  u8 CONFIG5;
169  u8 TX_DMA_POLLING;
170  u8 reserved_18[2];
171  __le16 CWR;
172  u8 RETRY_CTR;
173  u8 reserved_19[3];
174  __le16 INT_MIG;
175 /* RTL818X_R8187B_*: magic numbers from ioregisters */
176 #define RTL818X_R8187B_B 0
177 #define RTL818X_R8187B_D 1
178 #define RTL818X_R8187B_E 2
179  __le32 RDSAR;
180  __le16 TID_AC_MAP;
181  u8 reserved_20[4];
182  u8 ANAPARAM3;
183  u8 reserved_21[5];
184  __le16 FEMR;
185  u8 reserved_22[4];
186  __le16 TALLY_CNT;
187  u8 TALLY_SEL;
188 } __packed;
189 
190 struct rtl818x_rf_ops {
191  char *name;
192  void (*init)(struct ieee80211_hw *);
193  void (*stop)(struct ieee80211_hw *);
194  void (*set_chan)(struct ieee80211_hw *, struct ieee80211_conf *);
195  void (*conf_erp)(struct ieee80211_hw *, struct ieee80211_bss_conf *);
196  u8 (*calc_rssi)(u8 agc, u8 sq);
197 };
198 
211 enum rtl818x_tx_desc_flags {
212  RTL818X_TX_DESC_FLAG_NO_ENC = (1 << 15),
213  RTL818X_TX_DESC_FLAG_TX_OK = (1 << 15),
214  RTL818X_TX_DESC_FLAG_SPLCP = (1 << 16),
215  RTL818X_TX_DESC_FLAG_RX_UNDER = (1 << 16),
216  RTL818X_TX_DESC_FLAG_MOREFRAG = (1 << 17),
217  RTL818X_TX_DESC_FLAG_CTS = (1 << 18),
218  RTL818X_TX_DESC_FLAG_RTS = (1 << 23),
219  RTL818X_TX_DESC_FLAG_LS = (1 << 28),
220  RTL818X_TX_DESC_FLAG_FS = (1 << 29),
221  RTL818X_TX_DESC_FLAG_DMA = (1 << 30),
222  RTL818X_TX_DESC_FLAG_OWN = (1 << 31)
223 };
224 
225 enum rtl818x_rx_desc_flags {
226  RTL818X_RX_DESC_FLAG_ICV_ERR = (1 << 12),
227  RTL818X_RX_DESC_FLAG_CRC32_ERR = (1 << 13),
228  RTL818X_RX_DESC_FLAG_PM = (1 << 14),
229  RTL818X_RX_DESC_FLAG_RX_ERR = (1 << 15),
230  RTL818X_RX_DESC_FLAG_BCAST = (1 << 16),
231  RTL818X_RX_DESC_FLAG_PAM = (1 << 17),
232  RTL818X_RX_DESC_FLAG_MCAST = (1 << 18),
233  RTL818X_RX_DESC_FLAG_QOS = (1 << 19), /* RTL8187(B) only */
234  RTL818X_RX_DESC_FLAG_TRSW = (1 << 24), /* RTL8187(B) only */
235  RTL818X_RX_DESC_FLAG_SPLCP = (1 << 25),
236  RTL818X_RX_DESC_FLAG_FOF = (1 << 26),
237  RTL818X_RX_DESC_FLAG_DMA_FAIL = (1 << 27),
238  RTL818X_RX_DESC_FLAG_LS = (1 << 28),
239  RTL818X_RX_DESC_FLAG_FS = (1 << 29),
240  RTL818X_RX_DESC_FLAG_EOR = (1 << 30),
241  RTL818X_RX_DESC_FLAG_OWN = (1 << 31)
242 };
243 
244 #endif /* RTL818X_H */
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