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def.h
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1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2012 Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * wlanfae <[email protected]>
23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24  * Hsinchu 300, Taiwan.
25  *
26  * Larry Finger <[email protected]>
27  *
28  *****************************************************************************/
29 
30 #ifndef __RTL92D_DEF_H__
31 #define __RTL92D_DEF_H__
32 
33 /* Min Spacing related settings. */
34 #define MAX_MSS_DENSITY_2T 0x13
35 #define MAX_MSS_DENSITY_1T 0x0A
36 
37 #define RF6052_MAX_TX_PWR 0x3F
38 #define RF6052_MAX_REG 0x3F
39 #define RF6052_MAX_PATH 2
40 
41 #define HAL_RETRY_LIMIT_INFRA 48
42 #define HAL_RETRY_LIMIT_AP_ADHOC 7
43 
44 #define PHY_RSSI_SLID_WIN_MAX 100
45 #define PHY_LINKQUALITY_SLID_WIN_MAX 20
46 #define PHY_BEACON_RSSI_SLID_WIN_MAX 10
47 
48 #define RESET_DELAY_8185 20
49 
50 #define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
51 #define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
52 
53 #define NUM_OF_FIRMWARE_QUEUE 10
54 #define NUM_OF_PAGES_IN_FW 0x100
55 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
56 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
57 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
58 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
59 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
60 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
61 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
62 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
63 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
64 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
65 
66 #define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
67 #define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
68 #define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
69 #define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
70 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
71 
72 #define MAX_LINES_HWCONFIG_TXT 1000
73 #define MAX_BYTES_LINE_HWCONFIG_TXT 256
74 
75 #define SW_THREE_WIRE 0
76 #define HW_THREE_WIRE 2
77 
78 #define BT_DEMO_BOARD 0
79 #define BT_QA_BOARD 1
80 #define BT_FPGA 2
81 
82 #define RX_SMOOTH_FACTOR 20
83 
84 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
85 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
86 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
87 
88 #define MAX_H2C_QUEUE_NUM 10
89 
90 #define RX_MPDU_QUEUE 0
91 #define RX_CMD_QUEUE 1
92 #define RX_MAX_QUEUE 2
93 
94 #define C2H_RX_CMD_HDR_LEN 8
95 #define GET_C2H_CMD_CMD_LEN(__prxhdr) \
96  LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
97 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
98  LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
99 #define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
100  LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
101 #define GET_C2H_CMD_CONTINUE(__prxhdr) \
102  LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
103 #define GET_C2H_CMD_CONTENT(__prxhdr) \
104  ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
105 
106 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
107  LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
108 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
109  LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
110 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
111  LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
112 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
113  LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
114 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
115  LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
116 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
117  LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
118 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
119  LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
120 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
121  LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
122 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
123  LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
124 
125 enum version_8192d {
126  VERSION_TEST_CHIP_88C = 0x0000,
127  VERSION_TEST_CHIP_92C = 0x0020,
128  VERSION_TEST_UMC_CHIP_8723 = 0x0081,
129  VERSION_NORMAL_TSMC_CHIP_88C = 0x0008,
130  VERSION_NORMAL_TSMC_CHIP_92C = 0x0028,
131  VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018,
132  VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088,
133  VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8,
134  VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098,
135  VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089,
136  VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089,
137  VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088,
138  VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8,
139  VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090,
140  VERSION_TEST_CHIP_92D_SINGLEPHY = 0x0022,
141  VERSION_TEST_CHIP_92D_DUALPHY = 0x0002,
142  VERSION_NORMAL_CHIP_92D_SINGLEPHY = 0x002a,
143  VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a,
144  VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a,
145  VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a,
146  VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a,
147  VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a,
148  VERSION_NORMAL_CHIP_92D_E_CUT_SINGLEPHY = 0x402a,
149  VERSION_NORMAL_CHIP_92D_E_CUT_DUALPHY = 0x400a,
150 };
151 
152 /* for 92D */
153 #define CHIP_92D_SINGLEPHY BIT(9)
154 
155 /* Chip specific */
156 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
157 #define CHIP_BONDING_92C_1T2R 0x1
158 #define CHIP_BONDING_88C_USB_MCARD 0x2
159 #define CHIP_BONDING_88C_USB_HP 0x1
160 
161 /* [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3 */
162 /* [7] Manufacturer: TSMC=0, UMC=1 */
163 /* [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2 */
164 /* [3] Chip type: TEST=0, NORMAL=1 */
165 /* [2:0] IC type: 81xxC=0, 8723=1, 92D=2 */
166 #define CHIP_8723 BIT(0)
167 #define CHIP_92D BIT(1)
168 #define NORMAL_CHIP BIT(3)
169 #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
170 #define RF_TYPE_1T2R BIT(4)
171 #define RF_TYPE_2T2R BIT(5)
172 #define CHIP_VENDOR_UMC BIT(7)
173 #define CHIP_92D_B_CUT BIT(12)
174 #define CHIP_92D_C_CUT BIT(13)
175 #define CHIP_92D_D_CUT (BIT(13)|BIT(12))
176 #define CHIP_92D_E_CUT BIT(14)
177 
178 /* MASK */
179 #define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
180 #define CHIP_TYPE_MASK BIT(3)
181 #define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
182 #define MANUFACTUER_MASK BIT(7)
183 #define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
184 #define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
185 
186 
187 /* Get element */
188 #define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
189 #define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
190 #define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
191 #define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
192 #define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
193 #define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
194 
195 #define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? \
196  false : true)
197 #define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == \
198  RF_TYPE_1T2R) ? true : false)
199 #define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == \
200  RF_TYPE_2T2R) ? true : false)
201 
202 #define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? \
203  (IS_2T2R(version) ? true : false) : false)
204 #define IS_92D(version) ((GET_CVID_IC_TYPE(version) == \
205  CHIP_92D) ? true : false)
206 #define IS_92D_C_CUT(version) ((IS_92D(version)) ? \
207  ((GET_CVID_CUT_VERSION(version) == \
208  CHIP_92D_C_CUT) ? true : false) : false)
209 #define IS_92D_D_CUT(version) ((IS_92D(version)) ? \
210  ((GET_CVID_CUT_VERSION(version) == \
211  CHIP_92D_D_CUT) ? true : false) : false)
212 #define IS_92D_E_CUT(version) ((IS_92D(version)) ? \
213  ((GET_CVID_CUT_VERSION(version) == \
214  CHIP_92D_E_CUT) ? true : false) : false)
215 
216 enum rf_optype {
217  RF_OP_BY_SW_3WIRE = 0,
218  RF_OP_BY_FW,
219  RF_OP_MAX
220 };
221 
222 enum rtl_desc_qsel {
223  QSLT_BK = 0x2,
224  QSLT_BE = 0x0,
225  QSLT_VI = 0x5,
226  QSLT_VO = 0x7,
227  QSLT_BEACON = 0x10,
228  QSLT_HIGH = 0x11,
229  QSLT_MGNT = 0x12,
230  QSLT_CMD = 0x13,
231 };
232 
233 enum channel_plan {
234  CHPL_FCC = 0,
235  CHPL_IC = 1,
236  CHPL_ETSI = 2,
237  CHPL_SPAIN = 3,
238  CHPL_FRANCE = 4,
239  CHPL_MKK = 5,
240  CHPL_MKK1 = 6,
241  CHPL_ISRAEL = 7,
242  CHPL_TELEC = 8,
243  CHPL_GLOBAL = 9,
244  CHPL_WORLD = 10,
245 };
246 
247 struct phy_sts_cck_8192d {
248  u8 adc_pwdb_X[4];
249  u8 sq_rpt;
250  u8 cck_agc_rpt;
251 };
252 
253 struct h2c_cmd_8192c {
254  u8 element_id;
255  u32 cmd_len;
256  u8 *p_cmdbuffer;
257 };
258 
259 struct txpower_info {
260  u8 cck_index[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
261  u8 ht40_1sindex[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
262  u8 ht40_2sindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
263  u8 ht20indexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
264  u8 ofdmindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
265  u8 ht40maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
266  u8 ht20maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
267  u8 tssi_a[3]; /* 5GL/5GM/5GH */
268  u8 tssi_b[3];
269 };
270 
271 #endif
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